Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body, a common electrode layer and a plurality of sub-pixels, wherein the common electrode layer and the sub-pixels are arranged on the substrate body. Each sub-pixel comprises a transistor structure and a pixel electrode, the pixel electrode comprises a bottom edge structure, the bottom edge structure is connected with the transistor structure, and the orthographic projection of the bottom edge structure on the substrate is located in the orthographic projection of the common electrode layer on the substrate.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, the application fields of display products are becoming increasingly broad, and people's requirements for display quality of display products are also becoming increasingly higher. Currently, commonly used display products include liquid crystal display products. Liquid crystal display products generally include an array substrate and a color filter substrate arranged opposite each other, and a liquid crystal layer located between the array substrate and the color filter substrate. The liquid crystal layer is deflected by the electric field formed between the array substrate and the color filter substrate, thereby realizing the display function of the liquid crystal display product.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a common electrode layer and a plurality of sub-pixels all arranged on the base substrate; the sub-pixels include a transistor structure and a pixel electrode, the pixel electrode includes a bottom edge structure, the bottom edge structure is connected to the transistor structure, and the orthographic projection of the bottom edge structure on the base substrate is located inside the orthographic projection of the common electrode layer on the base substrate.

[0007] Optionally, the common electrode layer includes a first opening, and an orthographic projection of the first opening on the base substrate at least partially overlaps with an orthographic projection of the transistor structure on the base substrate.

[0008] Optionally, the transistor structure includes an active layer, and the orthographic projection of the boundary of the first opening on the substrate surrounds the orthographic projection of the active layer on the substrate.

[0009] Optionally, a distance d1 between the orthographic projection of the boundary of the first opening on the substrate and the orthographic projection of the channel portion included in the active layer on the substrate satisfies: d1 ≥ (a^2+b^2+c^2+e^2)^0.5; a represents the line width fluctuation parameter of the common electrode layer, b represents the alignment fluctuation parameter of the common electrode layer, c represents the line width fluctuation parameter of the source and drain metal layer included in the display substrate, and e represents the alignment fluctuation parameter of the source and drain metal layer.

[0010] Optionally, the orthographic projection of the first opening on the substrate is located inside the orthographic projection of the gate of the transistor structure on the substrate.

[0011] Optionally, the display substrate further includes data lines; the common electrode layer includes a plurality of slits distributed in an array, and an extending direction of the slits is the same as an extending direction of at least part of the data lines.

[0012] Optionally, the bottom edge structure includes a first bottom edge portion and a second bottom edge portion coupled to each other, the first bottom edge portion extends along a second direction, the second bottom edge portion extends along a first direction, and the second direction intersects with the first direction; the second bottom edge portion is coupled to the transistor structure.

[0013] Optionally, the data line includes a first data portion and a second data portion that are alternately arranged, adjacent first data portions and second data portions are coupled, an extension direction of the first data portion is the same as an extension direction of the slit, and the second data portion is coupled to the transistor structure; the orthographic projection of the first data line portion on the base substrate at least partially overlaps with the orthographic projection of the common electrode layer on the base substrate.

[0014] Optionally, the orthographic projection of the first data line portion on the base substrate is located inside the orthographic projection of the common electrode layer on the base substrate.

[0015] Optionally, the display substrate further includes a plurality of first common electrode lines and a plurality of data lines, the extension direction of at least part of the first common electrode lines is the same as the extension direction of the first data part, the orthographic projection of the first common electrode line on the base substrate at least partially overlaps with the orthographic projection of the corresponding first data part on the base substrate, and the plurality of first common electrode lines are respectively coupled to the common electrode layer.

[0016] Optionally, the first common electrode line includes a first common electrode portion and a second common electrode portion alternately arranged along a first direction, adjacent first common electrode portions are coupled to the second common electrode portions, an extension direction of the first common electrode portion is the same as an extension direction of the first data portion, and an orthographic projection of the first common electrode portion on the base substrate at least partially overlaps with an orthographic projection of a corresponding first data portion on the base substrate;

[0017] An orthographic projection of the second common electrode portion on the base substrate and an orthographic projection of the active layer of the transistor structure on the base substrate are arranged along a second direction.

[0018] Optionally, the distance d2 between the orthographic projection of the second common electrode part on the base substrate and the orthographic projection of the active layer on the base substrate satisfies: d2≥ (g^2+h^2+j^2+k^2)^0.5; g represents the line width fluctuation parameter of the first common electrode line, h represents the alignment fluctuation parameter of the first common electrode line, j represents the line width fluctuation parameter of the active layer, and k represents the alignment fluctuation parameter of the active layer.

[0019] Optionally, the display substrate also includes a plurality of second common electrode lines arranged along the first direction, the second common electrode lines include at least a portion extending along the second direction, the second direction intersects with the first direction, and the plurality of second common electrode lines are respectively coupled to the common electrode layer; the plurality of first common electrode lines and the plurality of second common electrode lines intersect to form a grid structure.

[0020] Optionally, the display substrate further includes a plurality of gate lines, the plurality of sub-pixels are divided into a plurality of sub-pixel rows, the gate lines are respectively coupled to the sub-pixels in a corresponding row of sub-pixel rows, the sub-pixel rows and the gate lines are alternately arranged along a first direction, the gate lines include first gate portions and second gate portions alternately arranged along a second direction, the second direction intersecting the first direction; adjacent first gate portions are coupled to second gate portions, a width of the first gate portion is greater than a width of the second gate portion along the first direction, and the first gate portion is reused as a gate of the transistor structure;

[0021] The transistor structure includes a first electrode and a second electrode, the first electrode is coupled to the corresponding data line, the second electrode includes a first part, a second part and a third part coupled in sequence, the orthographic projection of the first part on the substrate is located inside the orthographic projection of the gate of the transistor structure to which it belongs on the substrate, the orthographic projection of the third part on the substrate is located inside the orthographic projection of the gate of the adjacent transistor structure on the substrate, and the orthographic projection of the second part on the substrate and the orthographic projection of the second gate part on the substrate are arranged along the first direction.

[0022] Optionally, the second gate portion includes a first boundary close to the second portion, the first boundary includes a first corner portion; the second portion includes a second corner portion; and an extension direction of the first corner portion is the same as an extension direction of the second corner portion.

[0023] Based on the technical solution of the above-mentioned display substrate, the second aspect of the present disclosure provides a display device, including the above-mentioned display substrate, and the display device also includes a color filter substrate and a liquid crystal layer; the color filter substrate is arranged opposite to the display substrate, and the liquid crystal layer is located between the color filter substrate and the display substrate.

[0024] Optionally, the color filter substrate includes a base, and a black matrix layer and a color filter layer both arranged on the base, the black matrix layer and the color filter layer are arranged in the same layer, and the thickness of the black matrix layer is greater than or equal to 1.3 microns.

[0025] Optionally, the color filter substrate further includes a flat layer, which is located on a side of the black matrix layer and the color filter layer facing away from the substrate, and has a thickness greater than or equal to 1.8 microns. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0027] FIG1 is a schematic diagram of a gate line layout according to an embodiment of the present disclosure;

[0028] FIG2 is a schematic diagram of the layout of gate lines and active layers provided in an embodiment of the present disclosure;

[0029] FIG3 is a schematic diagram of the layout of the source and drain metal layers provided in an embodiment of the present disclosure;

[0030] FIG4 is a schematic diagram of a layout with source and drain metal layers added on the basis of FIG2 ;

[0031] FIG5 is a schematic diagram of forming a via hole in the insulating layer based on FIG4;

[0032] FIG6 is a schematic diagram of the layout of a pixel electrode layer provided in an embodiment of the present disclosure;

[0033] FIG7 is a schematic diagram of a layout in which a pixel electrode layer is added based on FIG5 ;

[0034] FIG8 is a schematic diagram of the layout of common electrode lines provided in an embodiment of the present disclosure;

[0035] FIG9 is a schematic diagram of a layout in which common electrode lines are added based on FIG7 ;

[0036] FIG10 is a schematic diagram of the layout of the common electrode layer provided in an embodiment of the present disclosure;

[0037] FIG11 is a schematic diagram of a layout in which a common electrode layer is added on the basis of FIG9 ;

[0038] FIG12 is a schematic diagram of the distance between the boundary of the first opening and the channel portion provided by an embodiment of the present disclosure;

[0039] FIG13 is a schematic diagram of the distance between the second common electrode portion and the active layer provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0041] In the related art, display products generally have a dark-state light leakage problem, which causes the brightness of the display product to be too high in the dark state, reduces the display contrast of the display product, and affects the display quality of the display product.

[0042] Referring to Figures 6, 7, 10 and 11, an embodiment of the present disclosure provides a display substrate, including: a base substrate, and a common electrode layer 10 and multiple sub-pixels all arranged on the base substrate; the sub-pixels include a transistor structure TFT and a pixel electrode 20, the pixel electrode 20 includes a bottom edge structure 201, the bottom edge structure 201 is connected to the transistor structure TFT, and the orthographic projection of the bottom edge structure 201 on the base substrate is located inside the orthographic projection of the common electrode layer 10 on the base substrate.

[0043] Exemplarily, the plurality of sub-pixels are distributed in an array on the substrate, the plurality of sub-pixels are divided into a plurality of sub-pixel rows, the plurality of sub-pixel rows are arranged along a first direction, and each sub-pixel row includes a plurality of sub-pixels arranged along a second direction. The second direction intersects the first direction, for example, the first direction includes a longitudinal direction, and the second direction includes a transverse direction, but is not limited thereto.

[0044] Exemplarily, the display substrate further includes a plurality of gate lines GA, the plurality of gate lines GA being arranged along the first direction, and the gate lines GA including at least a portion extending along the second direction. The gate lines GA may correspond to at least one row of sub-pixels. For example, the gate 50 may correspond to a row of sub-pixels, and the gate lines GA may be coupled to transistor structures TFT included in each sub-pixel in the corresponding row of sub-pixels.

[0045] Exemplarily, the plurality of sub-pixels are divided into a plurality of sub-pixel columns, the plurality of sub-pixel columns are arranged along the second direction, and each sub-pixel column includes a plurality of sub-pixels arranged along the first direction. The display substrate further includes a plurality of data lines DA, the data lines DA being coupled to transistor structures TFT included in each sub-pixel in a corresponding sub-pixel column.

[0046] As shown in Figures 1 to 11, the sub-pixel exemplarily includes a transistor structure TFT and a pixel electrode 20, wherein the pixel electrode 20 includes a bottom edge structure 201. The gate electrode 50 of the transistor structure TFT is coupled to the corresponding gate line GA, the first electrode 51 of the transistor structure TFT is coupled to the corresponding data line DA, and the second electrode 52 of the transistor structure TFT is coupled to the bottom edge structure 201. The transistor structure TFT is turned on under the control of a scan line signal transmitted by the gate line GA, thereby transmitting the data signal transmitted by the data line DA to the pixel electrode 20.

[0047] Exemplarily, the display substrate further includes a common electrode layer 10, which is used to transmit common electrode signals. The common electrode layer 10 and the pixel electrode 20 are arranged opposite each other in a direction perpendicular to the base substrate, and an electric field is formed between the common electrode layer 10 and the pixel electrode 20, but the present invention is not limited thereto. When the display substrate is used in a liquid crystal display device, the liquid crystal display device further includes a color filter substrate arranged opposite the display substrate, a liquid crystal layer located between the color filter substrate and the display substrate, and a backlight source located on the side of the array substrate facing away from the liquid crystal layer. The liquid crystal molecules in the liquid crystal layer are configured to be deflected by the electric field formed between the common electrode layer 10 and the pixel electrode 20, thereby realizing the display function of the display device.

[0048] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, the bottom edge structure 201 of the pixel electrode 20 is connected to the transistor structure TFT, and the orthographic projection of the bottom edge structure 201 on the base substrate is located within the orthographic projection of the common electrode layer 10 on the base substrate. This arrangement enables the common electrode layer 10 to completely cover the bottom edge structure 201 of the pixel electrode 20. Therefore, when the display substrate is used in a display product, the degree of light leakage near the bottom edge structure 201 of the pixel electrode 20 in the dark state of the display product can be effectively reduced, thereby improving the problem of high brightness of the display product in the dark state, effectively improving the display contrast of the display product, and ensuring the display quality of the display product.

[0049] As shown in FIG. 10 and FIG. 11 , in some embodiments, the common electrode layer 10 includes a first opening 101 , and an orthographic projection of the first opening 101 on the base substrate at least partially overlaps with an orthographic projection of the transistor structure TFT on the base substrate.

[0050] As shown in FIG12 , illustratively, the active layer ACT of the transistor structure TFT can form a channel portion gd, and the orthographic projection of the first opening 101 on the substrate at least partially overlaps with the orthographic projection of the channel portion gd on the substrate. For example, the orthographic projection of the first opening 101 on the substrate completely covers the orthographic projection of the channel portion gd on the substrate, that is, the orthographic projection of the boundary of the first opening 101 on the substrate surrounds the orthographic projection of the channel portion gd on the substrate.

[0051] In the display substrate provided in the above embodiment, by setting the orthographic projection of the first opening 101 on the base substrate to at least partially overlap with the orthographic projection of the transistor structure TFT on the base substrate, the common electrode layer 10 avoids the transistor structure TFT while ensuring that the common electrode layer 10 covers the bottom edge structure 201 of the pixel electrode 20, thereby avoiding the common electrode layer 10 from affecting the characteristics of the transistor structure TFT and ensuring the stability of the characteristics of the transistor structure TFT.

[0052] Moreover, the above-mentioned setting method reduces the overlapping area between the common electrode layer 10 and the transistor structure TFT, effectively reducing the parasitic capacitance between the common electrode layer 10 and the transistor structure TFT. When the display substrate is applied to a display product, a high charging rate and a high refresh rate of the display product are achieved.

[0053] As shown in FIG. 2 to FIG. 11 , in some embodiments, the transistor structure TFT includes an active layer ACT, and the orthographic projection of the boundary of the first opening 101 on the base substrate surrounds the orthographic projection of the active layer ACT on the base substrate.

[0054] Illustratively, the orthographic projection of the first opening 101 on the substrate at least partially overlaps with the orthographic projection of the first electrode 51 of the transistor structure TFT on the substrate. The orthographic projection of the first opening 101 on the substrate at least partially overlaps with the orthographic projection of the second electrode 52 of the transistor structure TFT on the substrate.

[0055] Exemplarily, at least a portion of the first electrode 51 of the transistor structure TFT includes a U-shaped structure, the first electrode 51 of the transistor structure TFT and the data line DA coupled thereto form an integral structure, and the second electrode 52 of the transistor structure TFT extends into the opening of the U-shaped structure.

[0056] For example, the active layer ACT may be designed to have a hexagonal shape, but is not limited thereto.

[0057] In the display substrate provided by the above embodiment, the orthographic projection of the boundary of the first opening 101 on the base substrate is set to surround the orthographic projection of the active layer ACT on the base substrate, so that the orthographic projection of the active layer ACT on the base substrate is completely located inside the orthographic projection of the first opening 101 on the base substrate. While ensuring that the common electrode layer 10 covers the bottom edge structure 201 of the pixel electrode 20, the common electrode layer 10 avoids the transistor structure TFT, thereby avoiding the common electrode layer 10 from affecting the characteristics of the transistor structure TFT and ensuring the stability of the characteristics of the transistor structure TFT.

[0058] As shown in Figure 12, in some embodiments, the distance d1 between the orthographic projection of the boundary of the first opening 101 on the substrate and the orthographic projection of the channel portion gd included in the active layer ACT on the substrate satisfies: d1≥(a^2+b^2+c^2+e^2)^0.5; a represents the line width fluctuation parameter of the common electrode layer 10, b represents the alignment fluctuation parameter of the common electrode layer 10, c represents the line width fluctuation parameter of the source and drain metal layer included in the display substrate, and e represents the alignment fluctuation parameter of the source and drain metal layer.

[0059] It should be noted that in the above formula, "^2" represents the square power, and "^0.5" represents the square root of the content in the previous brackets.

[0060] Exemplarily, a and c are both in the range of -1 micron to +1 micron, inclusive. b and e are both in the range of -2 micron to +2 micron, inclusive. Distance d1 is less than 3.5 microns.

[0061] Exemplarily, there is a minimum distance d1 between an orthographic projection of a boundary of the first opening 101 on the base substrate and an orthographic projection of a channel portion gd included in the active layer ACT on the base substrate.

[0062] It should be noted that the line width fluctuation parameter of the common electrode layer 10 refers to the dimensional accuracy of the common electrode layer 10. The alignment fluctuation parameter of the common electrode layer 10 refers to the alignment accuracy of the common electrode layer 10 formed at a specified position. The line width fluctuation parameter of the source / drain metal layer refers to the dimensional accuracy of the source / drain metal layer. The alignment fluctuation parameter of the source / drain metal layer refers to the alignment accuracy of the source / drain metal layer formed at a specified position. The source / drain metal layer is used to form the data line DA in the display substrate, the first electrode 51 and the second electrode 52 of the transistor structure TFT, but is not limited thereto.

[0063] In the display substrate provided in the above embodiment, by setting the distance d1 to meet the above conditions, the common electrode layer 10 can avoid the transistor structure TFT while maximizing the coverage area of ​​the common electrode layer 10, thereby better improving the dark state display light leakage problem of the display product.

[0064] As shown in FIG. 2 to FIG. 12 , in some embodiments, the orthographic projection of the first opening 101 on the substrate is located inside the orthographic projection of the gate 50 of the transistor structure TFT on the substrate.

[0065] Illustratively, the orthographic projection of the boundary of the gate 50 of the transistor structure TFT on the substrate surrounds the orthographic projection of the first opening 101 on the substrate.

[0066] The above arrangement can maximize the coverage area of ​​the common electrode layer 10 while achieving the avoidance of the common electrode layer 10 from the transistor structure TFT, thereby better improving the dark state display light leakage problem of the display product.

[0067] As shown in FIG11 , in some embodiments, the display substrate further includes a data line DA; the common electrode layer 10 includes a plurality of slits 30 distributed in an array, and the extending direction of the slits 30 is the same as the extending direction of at least part of the data line DA.

[0068] Exemplarily, the plurality of slits 30 are divided into a plurality of slit groups, which are distributed in an array, and each slit group includes a plurality of slits 30 arranged sequentially along the second direction. For example, the plurality of slit groups correspond one-to-one to a plurality of sub-pixels in the display substrate, and the orthographic projections of the slit groups on the base substrate are located within the orthographic projections of the pixel openings 40 included in the corresponding sub-pixels on the base substrate, but the present invention is not limited thereto.

[0069] Exemplarily, the multiple slit groups are divided into multiple columns of slit groups, the multiple columns of slit groups are arranged along the second direction, and each column of slit groups includes multiple slit groups arranged along the first direction. The display substrate further includes multiple data lines DA, and the data lines DA are alternately arranged with the slit groups along the second direction.

[0070] In the display substrate provided in the above embodiment, by setting the extension direction of the slit 30 to be the same as the extension direction of at least part of the data line DA, the display substrate can be formed into a HADS display mode (i.e., an ultra-high-level hyper-dimensional field display mode), thereby reducing the proportion of dark fields formed by the display substrate, improving the overall lighting efficiency, effectively improving the display contrast of the display product, and ensuring the display quality of the display product.

[0071] As shown in Figures 6 and 7, in some embodiments, the bottom edge structure 201 includes a first bottom edge portion 201a and a second bottom edge portion 201b coupled to each other, the first bottom edge portion 201a extends along the second direction, the second bottom edge portion 201b extends along the first direction, and the second direction intersects with the first direction; the second bottom edge portion 201b is coupled to the transistor structure TFT.

[0072] Exemplarily, the first bottom edge portion 201a and the second bottom edge portion 201b form an integral structure, with the first bottom edge portion 201a located between the pixel opening area 40 in the sub-pixel to which it belongs and the second bottom edge portion 201b. For example, the orthographic projection of the first bottom edge portion 201a on the substrate is located between the orthographic projection of the slit group corresponding to the sub-pixel to which it belongs and the orthographic projection of the second bottom edge portion 201b on the substrate.

[0073] In the display substrate provided in the above embodiment, the orthographic projection of the first bottom edge portion 201a on the base substrate is located inside the orthographic projection of the common electrode layer 10 on the base substrate, and the orthographic projection of the second bottom edge portion 201b on the base substrate is located inside the orthographic projection of the common electrode layer 10 on the base substrate, so that the common electrode layer 10 can completely cover the bottom edge structure 201 of the pixel electrode 20, so that when the display substrate is applied to a display product, the degree of light leakage near the bottom edge structure 201 of the pixel electrode 20 of the display product in the dark state display can be effectively reduced, thereby improving the problem of high brightness of the display product in the dark state display, effectively improving the display contrast of the display product, and ensuring the display quality of the display product.

[0074] As shown in Figures 4, 5 and 11, in some embodiments, the data line DA includes a first data portion DA1 and a second data portion DA2 alternately arranged, the adjacent first data portion DA1 and the second data portion DA2 are coupled, the extension direction of the first data portion DA1 is the same as the extension direction of the slit 30, and the second data portion DA2 is coupled to the transistor structure TFT; the orthographic projection of the first data line DA portion on the base substrate at least partially overlaps with the orthographic projection of the common electrode layer 10 on the base substrate.

[0075] Exemplarily, the data line DA includes a plurality of first data portions DA1 and a plurality of second data portions DA2, the first data portions DA1 and the second data portions DA2 being alternately arranged along the first direction. Adjacent first data portions DA1 and second data portions DA2 form an integral structure. The second data portion DA2 and the first electrode 51 of the transistor structure TFT to which it is coupled form an integral structure.

[0076] Exemplarily, the first data portions DA1 extend in the same direction as the slits 30, and the first data portions DA1 and the slit groups are alternately arranged along the second direction. This arrangement enables the display substrate to be configured in a HADS display mode, thereby reducing the proportion of dark fields formed by the display substrate, improving overall lighting efficiency, effectively enhancing the display contrast of the display product, and ensuring the display quality of the display product.

[0077] Exemplarily, the orthographic projection of the first data portion on the base substrate is located inside the orthographic projection of the common electrode layer 10 on the base substrate.

[0078] In the display substrate provided by the above embodiment, by setting the orthographic projection of the first data line DA portion on the base substrate to at least partially overlap with the orthographic projection of the common electrode layer 10 on the base substrate, the common electrode layer 10 can cover at least a portion of the data line DA, so that when the display substrate is applied to a display product, the degree of light leakage near the data line DA in the dark state display of the display product can be effectively reduced, thereby improving the problem of high brightness of the display product in the dark state display, effectively improving the display contrast of the display product, and ensuring the display quality of the display product.

[0079] As shown in Figures 3 to 9, in some embodiments, the display substrate further includes a plurality of first common electrode lines 11 and a plurality of data lines DA, the extension direction of at least part of the first common electrode lines 11 is the same as the extension direction of the first data part DA1, the orthographic projection of the first common electrode line 11 on the base substrate at least partially overlaps with the orthographic projection of the corresponding first data part DA1 on the base substrate, and the plurality of first common electrode lines are respectively coupled to the common electrode layer 10.

[0080] Exemplarily, the plurality of first common electrode lines 11 are arranged along the second direction, and an extending direction of at least a portion of the first common electrode lines 11 is the same as an extending direction of the first data portion DA1 .

[0081] Exemplarily, the multiple first common electrode lines 11 correspond one-to-one to the multiple data lines DA, and the orthographic projections of the first common electrode lines 11 on the base substrate at least partially overlap with the orthographic projections of each first data part DA1 in the corresponding data line DA on the base substrate.

[0082] Exemplarily, the line width of the portion where the first common electrode line 11 overlaps the first data portion DA1 is equal to the line width of the first data portion DA1.

[0083] Exemplarily, the first common electrode line 11 may be arranged to completely overlap with the corresponding data line DA, but the present invention is not limited thereto.

[0084] Exemplarily, the first common electrode line 11 is made of metal material, such as molybdenum, but not limited thereto.

[0085] In the display substrate provided by the above embodiment, by providing the plurality of first common electrode lines respectively coupled to the common electrode layer 10 , the overall resistance of the common electrode layer 10 is reduced, thereby effectively reducing the loading of the common electrode layer 10 when transmitting signals.

[0086] As shown in FIG8 and FIG9, in some embodiments, the first common electrode line 11 includes a first common electrode portion 111 and a second common electrode portion 112 alternately arranged along a first direction, adjacent first common electrode portions 111 and second common electrode portions 112 are coupled, an extension direction of the first common electrode portion 111 is the same as an extension direction of the first data portion DA1, and an orthographic projection of the first common electrode portion 111 on the base substrate at least partially overlaps with an orthographic projection of the corresponding first data portion DA1 on the base substrate;

[0087] An orthographic projection of the second common electrode portion 112 on the base substrate and an orthographic projection of the active layer ACT of the transistor structure TFT on the base substrate are arranged along a second direction.

[0088] Exemplarily, the first common electrode line 11 includes a plurality of first common electrode portions 111 and a plurality of second common electrode portions 112, the first common electrode portions 111 and the second common electrode portions 112 are alternately arranged along the first direction, and adjacent first common electrode portions 111 and second common electrode portions 112 form an integrated structure.

[0089] Exemplarily, the orthographic projection of the first common electrode portion 111 on the base substrate coincides with the orthographic projection of the corresponding first data portion DA1 on the base substrate, but is not limited thereto.

[0090] Exemplarily, the first common electrode portion 111 and the second common electrode portion 112 have the same line width, and the line width of the first common electrode line 11 is uniform.

[0091] Exemplarily, an extending direction of the second common electrode portion 112 is the same as an extending direction of a boundary of the active layer ACT close to the second common electrode portion 112 .

[0092] In the display substrate provided in the above embodiment, the orthographic projection of the second common electrode portion 112 on the base substrate and the orthographic projection of the active layer ACT of the transistor structure TFT on the base substrate are arranged along the second direction, so that the first common electrode line 11 can avoid the active layer ACT, thereby avoiding the first common electrode line 11 from affecting the characteristics of the transistor structure TFT, thereby ensuring the stability of the characteristics of the transistor structure TFT.

[0093] As shown in Figure 13, in some embodiments, the distance d2 between the orthographic projection of the second common electrode portion 112 on the base substrate and the orthographic projection of the active layer ACT on the base substrate satisfies: d2≥(g^2+h^2+j^2+k^2)^0.5; g represents the line width fluctuation parameter of the first common electrode line 11, h represents the alignment fluctuation parameter of the first common electrode line 11, j represents the line width fluctuation parameter of the active layer ACT, and k represents the alignment fluctuation parameter of the active layer ACT.

[0094] Exemplarily, g and j are both in the range of -1 micron to +1 micron, inclusive. h and k are both in the range of -2 micron to +2 micron, inclusive. Distance d2 is less than 3.5 microns.

[0095] It should be noted that the line width fluctuation parameter of the first common electrode line 11 refers to the dimensional accuracy of the first common electrode line 11. The alignment fluctuation parameter of the first common electrode line 11 refers to the alignment accuracy of the first common electrode line 11 formed at a specified position. The line width fluctuation parameter of the active layer ACT refers to the dimensional accuracy of the active layer ACT. The alignment fluctuation parameter of the active layer ACT refers to the alignment accuracy of the active layer ACT formed at a specified position.

[0096] In the display substrate provided in the above embodiment, by setting the distance d2 to meet the above conditions, the first common electrode line 11 can better avoid the transistor structure TFT, thereby avoiding the first common electrode line 11 from affecting the characteristics of the transistor structure TFT, and ensuring the stability of the characteristics of the transistor structure TFT.

[0097] As shown in Figures 8 to 11, in some embodiments, the display substrate further includes a plurality of second common electrode lines 12 arranged along the first direction, the second common electrode lines 12 include at least a portion extending along a second direction, the second direction intersects with the first direction, and the plurality of second common electrode lines 12 are respectively coupled to the common electrode layer 10; the plurality of first common electrode lines 11 and the plurality of second common electrode lines 12 intersect to form a grid structure.

[0098] Exemplarily, the second common electrode line 12 and the first common electrode line 11 are provided in the same layer and made of the same material.

[0099] In the display substrate provided in the above embodiment, the multiple second common electrode lines 12 are respectively coupled to the common electrode layer 10, and the multiple first common electrode lines 11 and the multiple second common electrode lines 12 are crossed to form a grid structure, which further reduces the resistance of the common electrode layer 10, thereby effectively reducing the loading of the common electrode layer 10 when transmitting signals.

[0100] As shown in FIG1 to FIG4 , in some embodiments, the display substrate further includes a plurality of gate lines GA. The plurality of sub-pixels are divided into a plurality of sub-pixel rows. The gate lines GA are respectively coupled to the sub-pixels in a corresponding sub-pixel row. The sub-pixel rows and the gate lines GA are alternately arranged along a first direction. The gate lines GA include first gate portions GA1 and second gate portions GA2 alternately arranged along a second direction, where the second direction intersects the first direction. Adjacent first gate portions GA1 and second gate portions GA2 are coupled. The width of the first gate portion GA1 is greater than the width of the second gate portion GA2 along the first direction. The first gate portion GA1 is multiplexed as the gate 50 of the transistor structure TFT.

[0101] The transistor structure TFT includes a first electrode 51 and a second electrode 52. The first electrode 51 is coupled to the corresponding data line DA. The second electrode 52 includes a first portion 521, a second portion 522, and a third portion 523 coupled in sequence. The orthographic projection of the first portion 521 on the base substrate is located inside the orthographic projection of the gate 50 of the transistor structure TFT to which it belongs on the base substrate. The orthographic projection of the third portion 523 on the base substrate is located inside the orthographic projection of the gate 50 of the adjacent transistor structure TFT on the base substrate. The orthographic projection of the second portion 522 on the base substrate and the orthographic projection of the second gate portion GA2 on the base substrate are arranged along the first direction.

[0102] Exemplarily, the gate line GA includes a plurality of first gate portions GA1 and a plurality of second gate portions GA2 . The first gate portions GA1 and the second gate portions GA2 are alternately arranged along the second direction, and adjacent first gate portions GA1 and second gate portions GA2 form an integrated structure.

[0103] Exemplarily, the first portion 521, the second portion 522 and the third portion 523 are formed into an integral structure. The orthographic projection of the second portion 522 on the base substrate does not overlap with the orthographic projection of the first gate portion GA1 on the base substrate.

[0104] The above-mentioned second electrode 52 includes the third part 523, and the orthographic projection of the third part 523 on the substrate overlaps with the orthographic projection of the gate 50 of the adjacent transistor structure TFT on the substrate, so that the third part 523 forms a compensation capacitor to avoid the problem of inconsistent capacitance formed between the electrode and the gate 50 when the source and drain metal layers are offset.

[0105] As shown in Figures 1 to 4, in some embodiments, the second gate portion GA2 includes a first boundary 60 close to the second portion 522, the first boundary 60 includes a first corner portion 601; the second portion 522 includes a second corner portion 522a; the extension direction of the first corner portion 601 is the same as the extension direction of the second corner portion 522a.

[0106] Illustratively, the second gate portion GA2 forms a step at the first corner portion 601 , and the second portion 522 forms a step at the second corner portion 522 a .

[0107] By providing the second gate portion GA2 with a step at the first corner portion 601, the overall area of ​​the gate line GA is increased, thereby reducing the loading of the gate line GA. By setting the extension direction of the first corner portion 601 to be the same as the extension direction of the second corner portion 522a, the risk of short circuit between the second portion 522 and the second gate portion GA2 is greatly reduced.

[0108] It is worth noting that the specific shape of the step formed by the first corner portion 601 can be set to follow the shape of the step formed by the second portion 522 to achieve the effect of reducing the resistance of the gate line GA without increasing the parasitic capacitance of the gate line GA.

[0109] In the display substrate provided in the above embodiment, the manufacturing process is as follows: forming the plurality of gate lines GA on the base substrate using a gate metal material; forming a gate insulating layer; forming a semiconductor layer, the semiconductor layer including the active layer ACT of each of the transistor structures TFT; forming a source-drain metal layer, the source-drain metal layer including the plurality of data lines DA, the first electrode 51 and the second electrode 52 of the transistor structure TFT; forming an insulating layer, the insulating layer including a plurality of through holes Via1, the through holes Via1 being able to expose a portion of the second electrode 52, the insulating layer may include an organic insulating layer or an inorganic insulating layer, the insulating layer may be made of a resin material or inorganic insulating material, but not limited to this; forming a pixel electrode layer, the pixel electrode layer includes a plurality of pixel electrodes 20, and the pixel electrode layer can be made of indium tin oxide material; forming an insulating film layer, and forming a via pattern on the insulating film layer. Since the display area of ​​the display substrate does not need the via, there is no via pattern in the display area, and the via pattern can be formed in the packaging area of ​​the peripheral area of ​​the display substrate, but not limited to this; forming the first common electrode line 11 and the second common electrode line 12; forming a common electrode layer 10, the common electrode layer 10 can be made of indium tin oxide material, but not limited to this.

[0110] It should be noted that the active layer ACT and the source / drain metal layer can be formed by separate patterning processes, or can be formed simultaneously using a semi-transparent mask (HTM Mask).

[0111] The organic insulating layer is formed after the source / drain metal layer is formed, which can reduce the parasitic capacitance between the source / drain metal layer and the subsequently formed common electrode layer 10 , thereby further improving the charging rate of the display substrate.

[0112] An embodiment of the present disclosure also provides a display device, including the display substrate provided by the above embodiment, and the display device also includes a color filter substrate and a liquid crystal layer; the color filter substrate is arranged opposite to the display substrate, and the liquid crystal layer is located between the color filter substrate and the display substrate.

[0113] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0114] In the display substrate provided in the above embodiment, the bottom edge structure 201 of the pixel electrode 20 is connected to the transistor structure TFT. The orthographic projection of the bottom edge structure 201 on the base substrate is located within the orthographic projection of the common electrode layer 10 on the base substrate. This arrangement enables the common electrode layer 10 to completely cover the bottom edge structure 201 of the pixel electrode 20. When the display device provided in the embodiment of the present disclosure includes the above display substrate, it can effectively reduce the degree of light leakage near the bottom edge structure 201 of the pixel electrode 20 in the dark state of the display device, thereby improving the problem of high brightness of the display device in the dark state, effectively improving the display contrast of the display device, and ensuring the display quality of the display device.

[0115] In some embodiments, the color filter substrate includes a base, and a black matrix layer and a color filter layer both disposed on the base. The black matrix layer and the color filter layer are disposed on the same layer, and the thickness of the black matrix layer is greater than or equal to 1.3 microns.

[0116] The thickness of the black matrix layer is set to be greater than or equal to 1.3 micrometers, so that the black matrix layer has a thicker thickness, thereby being able to shield more chaotic lateral light.

[0117] In the display device provided by the above embodiment, the common electrode layer 10 in the display substrate can cover a larger area. Therefore, the line width of the black matrix layer can be narrowed in the non-pixel opening area covered by the common electrode layer 10, thereby further improving the transmittance of the display device.

[0118] In some embodiments, the color filter substrate further includes a planar layer, which is located on a side of the black matrix layer and the color filter layer facing away from the substrate, and has a thickness greater than or equal to 1.8 microns.

[0119] For example, when manufacturing the color filter substrate, a black matrix layer may be formed on the base first, and then a color filter layer is manufactured, and then the planar layer is formed.

[0120] The thickness of the flat layer is set to be greater than or equal to 1.8 microns, so that the flat layer has a thicker thickness, thereby making the side of the color filter substrate facing the liquid crystal layer as flat as possible, ensuring that the liquid crystal orientation is as consistent as possible, and effectively reducing dark-state light leakage of the display device.

[0121] In some embodiments, the display device abandons conventional Rubbing alignment and adopts light-controlled alignment, the purpose of which is to obtain better liquid crystal alignment uniformity and reduce dark-state light leakage.

[0122] In some embodiments, to ensure the response time of the liquid crystal, the viscosity coefficient γ1 of the liquid crystal material is no greater than 71 Pascals, and γ1 / K11 is no greater than 3.99. Furthermore, the scattering factor of the dark-state light-leaking liquid crystal is reduced to no greater than 0.0196. K11 represents the elastic constant of the liquid crystal material's extended area deformation under external force.

[0123] The display device provided by the above embodiment can achieve a contrast ratio of 2000.

[0124] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0125] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0126] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0127] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0128] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0129] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0130] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0131] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A substrate, a common electrode layer, and a plurality of sub-pixels, all of which are disposed on the substrate; The sub-pixel includes a transistor structure and a pixel electrode. The pixel electrode includes a bottom edge structure, and the bottom edge structure is connected to the transistor structure. A positive projection of the bottom edge structure on the substrate is located inside a positive projection of the common electrode layer on the substrate.

2. The display substrate according to claim 1, wherein, The common electrode layer includes a first opening, and a positive projection of the first opening on the substrate at least partially overlaps with a positive projection of the transistor structure on the substrate.

3. The display substrate according to claim 2, wherein The transistor structure includes an active layer, and a positive projection of a boundary of the first opening on the substrate surrounds a positive projection of the active layer on the substrate.

4. The display substrate according to claim 3, wherein, A distance d1 between a positive projection of the boundary of the first opening on the substrate and a positive projection of a channel portion included in the active layer on the substrate satisfies: d1≥(a^2 + b^2 + c^2 + e^2)^0.5; a represents a line width fluctuation parameter of the common electrode layer, b represents a registration fluctuation parameter of the common electrode layer, c represents a line width fluctuation parameter of a source-drain metal layer included in the display substrate, and e represents a registration fluctuation parameter of the source-drain metal layer.

5. The display substrate according to claim 3, wherein, A positive projection of the first opening on the substrate is located inside a positive projection of a gate of the transistor structure on the substrate.

6. The display substrate according to claim 1, wherein, The display substrate further includes a data line; the common electrode layer includes a plurality of slits distributed in an array, and an extending direction of the slits is the same as at least a part of an extending direction of the data line.

7. The display substrate according to claim 6, wherein, The bottom edge structure includes a first bottom edge part and a second bottom edge part that are coupled to each other. The first bottom edge part extends along a second direction, the second bottom edge part extends along a first direction, and the second direction intersects with the first direction; the second bottom edge part is coupled to the transistor structure.

8. The display substrate according to claim 6, wherein, The data line includes alternately arranged first data parts and second data parts, and adjacent first data parts and second data parts are coupled to each other. An extending direction of the first data part is the same as an extending direction of the slit, and the second data part is coupled to the transistor structure; a positive projection of the first data line part on the substrate at least partially overlaps with a positive projection of the common electrode layer on the substrate.

9. The display substrate according to claim 8, wherein, A positive projection of the first data line part on the substrate is located inside a positive projection of the common electrode layer on the substrate.

10. The display substrate according to claim 8, wherein, The display substrate further includes a plurality of first common electrode lines and a plurality of data lines. At least a part of an extending direction of the first common electrode line is the same as an extending direction of the first data part. A positive projection of the first common electrode line on the substrate at least partially overlaps with a positive projection of the corresponding first data part on the substrate, and the plurality of first common electrode lines are respectively coupled to the common electrode layer.

11. The display substrate according to claim 10, wherein, The first common electrode line comprises a first common electrode portion and a second common electrode portion alternately arranged along a first direction, the adjacent first common electrode portion and the second common electrode portion are coupled, the extension direction of the first common electrode portion is the same as the extension direction of the first data portion, and the orthographic projection of the first common electrode portion on the base substrate at least partially overlaps with the orthographic projection of the corresponding first data portion on the base substrate; An orthographic projection of the second common electrode portion on the base substrate and an orthographic projection of the active layer of the transistor structure on the base substrate are arranged along a second direction.

12. The display substrate according to claim 11, wherein, A distance d2 between the orthographic projection of the second common electrode part on the substrate and the orthographic projection of the active layer on the substrate satisfies: d2≥(g^2+h^2+j^2+k^2)^0.5; g represents a line width fluctuation parameter of the first common electrode line, h represents an alignment fluctuation parameter of the first common electrode line, j represents a line width fluctuation parameter of the active layer, and k represents an alignment fluctuation parameter of the active layer.

13. The display substrate according to claim 9, wherein, The display substrate also includes a plurality of second common electrode lines arranged along a first direction, the second common electrode lines include at least a portion extending along a second direction, the second direction intersects with the first direction, and the plurality of second common electrode lines are respectively coupled to the common electrode layer; the plurality of first common electrode lines and the plurality of second common electrode lines intersect to form a grid structure.

14. The display substrate according to any one of claims 1 to 13, wherein, The display substrate further comprises a plurality of gate lines, the plurality of sub-pixels are divided into a plurality of sub-pixel rows, the gate lines are respectively coupled to the sub-pixels in a corresponding row of sub-pixel rows, the sub-pixel rows and the gate lines are alternately arranged along a first direction, the gate lines comprise first gate portions and second gate portions alternately arranged along a second direction, the second direction intersecting the first direction; the adjacent first gate portions and second gate portions are coupled, the width of the first gate portion along the first direction is greater than the width of the second gate portion, and the first gate portion is reused as the gate of the transistor structure; The transistor structure includes a first electrode and a second electrode, the first electrode is coupled to a corresponding data line, the second electrode includes a first part, a second part and a third part coupled in sequence, the orthographic projection of the first part on the substrate is located inside the orthographic projection of the gate of the transistor structure to which it belongs on the substrate, the orthographic projection of the third part on the substrate is located inside the orthographic projection of the gate of an adjacent transistor structure on the substrate, and the orthographic projection of the second part on the substrate and the orthographic projection of the second gate part on the substrate are arranged along the first direction.

15. The display substrate according to claim 14, wherein, The second gate portion includes a first boundary close to the second portion, the first boundary includes a first corner portion; the second portion includes a second corner portion; and an extending direction of the first corner portion is the same as an extending direction of the second corner portion.

16. A display device includes a display substrate as described in any one of claims 1 to 15, and the display device further includes a color filter substrate and a liquid crystal layer; the color filter substrate is disposed opposite to the display substrate, and the liquid crystal layer is located between the color filter substrate and the display substrate.

17. The display device according to claim 16, wherein, The color filter substrate includes a substrate, and a black matrix layer and a color filter layer both disposed on the substrate. The black matrix layer and the color filter layer are disposed on the same layer, and the thickness of the black matrix layer is greater than or equal to 1.3 micrometers.

18. The display device according to claim 17, wherein, The color filter substrate further includes a planarization layer, the planarization layer is located on a side of the black matrix layer and the color filter layer facing away from the substrate, and the thickness of the planarization layer is greater than or equal to 1.8 micrometers.

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