Systems and methods for performing energy-efficient processing by reducing data movement

Abstract

A system for performing energy-efficient computations reduces the amount of data transferred between a processor and an external memory device. The processor and the external memory device are each equipped with a first and second near-data processing control unit (NCU) that coordinates offloading of preselected sub-processes from the processor to first processing circuitry disposed on or near the external memory device. The first NCU sends commands and memory addresses to the second NCU while the processor is executing one of the preselected processes. The processing circuitry on or near the memory device executes one or more sub-processes and the results are forwarded by the second NCU to the first NCU, which forwards the results to the processor to complete the process.

Description

[0001] Related technical descriptions

[0002] Computing devices may include multiple processor-based subsystems. Such computing devices may be, for example, portable computing devices (“PCDs”), such as laptops or handheld computers, cellular phones or smartphones, portable digital assistants, portable game consoles, etc. Other types of PCDs may be included in automotive and Internet of Things (“IoT”) applications.

[0003] Multiple subsystems may be included within the same integrated circuit chip or on different chips. A “system-on-a-chip” or “SoC” is an example of a chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a digital signal processor (“DSP”), and a neural processing unit (“NPU”). An SoC may include other subsystems, such as a transceiver or “modem” subsystem providing wireless connectivity, a memory subsystem, etc.

[0004] SoC processors (such as CPUs, GPUs, and DSPs) perform a large number of computations, which require the processor to write large amounts of data to and read large amounts of data from the SoC's main memory. These data transfers consume a significant amount of power within the SoC. For these large workloads, a way to reduce data movement is needed to better conserve energy in energy-constrained systems. Summary of the Invention

[0005] Systems, methods, and other examples for performing energy-efficient computing by reducing data movement between a processor and an external memory device are disclosed. The method may include using a processor to initiate a first process comprising at least a first subprocess. The method may also include using a first proximity data processing control unit (NCU) of the processor to output at least a first processing command associated with executing the first subprocess and a first address in the memory device for storing data associated with the first subprocess. The method may further include using a second NCU disposed on or near the memory device to receive the first processing command and the first address, and causing data stored at the first address to be read from the memory device and forwarded to processing circuitry disposed on or near the memory device. The method may further include executing at least the first subprocess in the processing circuitry by executing at least the first processing command on the data read from the first memory address to produce a first result.

[0006] The system may include a processor, which includes logic components configured to initiate at least a first process including at least a first subprocess. The system may also include a memory device, which includes a memory address configured to store data. The system may further include a first NCU embedded in or communicating with the processor, the first NCU including logic components configured to receive at least a first processing command and a first address from the processor. The first processing command may include one or more commands for executing the first subprocess. The first address is the address of the memory device storing data to be processed by the first subprocess. The system may also include a second NCU disposed on or near the memory device and communicating with the first NCU. The second NCU may include logic components configured to receive the first address and the first command from the first NCU. The system may also include processing circuitry disposed on or near the memory device, the processing circuitry including logic components configured to receive the first command and the first address from the second NCU, read data from the first address, and execute the first command on the data read from the first address to produce a first result.

[0007] The computer program disclosed herein includes computer instructions for performing energy-efficient computing by reducing data movement between a processor and an external memory device. These computer instructions are embodied in a non-transitory computer-readable medium and may include: a first set of computer instructions for execution by a processor to initiate a first process including at least a first sub-process; and a second set of computer instructions for execution by a first NCU of the processor to cause the first NCU to output at least a first processing command for executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device. The computer program may also include a third set of computer instructions for execution by a second NCU disposed on or near the memory device to cause the second NCU to receive the at least first processing command and the first address, and to cause data stored at the first address to be read from the memory device and forwarded to processing circuitry disposed on or near the memory device. The computer program may also include a fourth set of computer instructions for execution by processing circuitry to cause the processing circuitry to execute the at least first sub-process by executing the at least first processing command on the data read from the first address to produce a first result.

[0008] Another embodiment of a system for performing energy-efficient computing by reducing data movement between the processor and an external memory device may include a processor configured to initiate a first process comprising at least a first sub-process, the processor including logic unit configured to output at least a first processing command associated with the execution of the first sub-process and a first address in the memory device storing data associated with the first sub-process. The system may also include processing circuitry embedded in the memory device and configured to: receive the first processing command and the first address, and cause data stored at the first address to be read from the memory device and forwarded to the processing circuitry. The processing circuitry may include logic unit configured to execute at least the first sub-process by executing at least the first processing command on the data read from the first memory address to produce a first result.

[0009] These and other features and advantages will become apparent from the following description, drawings and claims. Attached Figure Description

[0010] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter characters, such as "101a" or "101b", the letter characters distinguish two similar parts or elements in the same figure. When the aim is to have the reference numerals cover all parts with the same reference numerals in all figures, the letter characters of the reference numerals may be omitted.

[0011] Figure 1 This is a block diagram of the tab switching process in an internet browser, illustrating the subprocesses that constitute the tab switching process executed in the CPU running the Google Chrome browser.

[0012] Figure 2 It is a graph showing the percentage of energy consumed by data movement between the CPU and memory compared to the energy consumed by calculating four different processes: (1) texture and color bit block transfer when scrolling in Google Chrome, (2) compression and decompression when switching tabs in Google Chrome, (3) packing, unpacking and quantization when using TensorFlow artificial intelligence (AI) machine learning software, and (4) subpixel interpolation and deblocking filtering when using the VP9 encoder / decoder.

[0013] Figure 3 yes Figure 1 The block diagram of the label switching process shown is modified to eliminate labels switched by... Figure 1 Boxes 102 and 104 represent the read and write processes, and will be... Figure 1Box 103 indicates that the compression subprocess is unloaded to processing circuitry located on or near the memory device.

[0014] Figure 4 It is a block diagram of a system for performing energy-efficient computing by reducing data movement between the processor and memory, based on a representative implementation.

[0015] Figure 5 This is a flowchart of a method for achieving energy-efficient computing by reducing the amount of data transferred between the processor and external memory devices, based on a representative implementation.

[0016] Figure 6 This is a flowchart of a method for achieving energy-efficient computing by reducing the amount of data transferred between the processor and external memory devices, based on a representative implementation.

[0017] Figure 7A This is a schematic diagram of a 3D stacked DRAM memory system, which has been modified to include a repository logic component within the logic die of the memory system. Figure 4 The second NCU and the first processing circuit are shown.

[0018] Figure 7B yes Figure 7A The block diagram shown depicts a repository logic component, which has embedded elements therein. Figure 4 The second NCU and the first processing circuit are shown.

[0019] Figure 8 This is a flowchart of the texture filling process currently being executed by the CPU.

[0020] Figure 9 It is based on the representative implementation scheme of this disclosure. Figure 8 The flowchart shown is for the texture filling process.

[0021] Figure 10 This is a flowchart of the TensorFlow packaging and quantization process currently being executed by the CPU.

[0022] Figure 11 It is a modification based on the representative implementation scheme of this disclosure. Figure 10 The flowchart shown is a TensorFlow process.

[0023] Figure 12 Examples of PCD are illustrated, including exemplary embodiments of systems, methods, computer-readable media, and other examples of providing energy-efficient processing with reduced data movement, which can be implemented according to the principles and concepts of the present invention. Detailed Implementation

[0024] The end of Dennard scaling left computing systems energy-constrained and widened the gap between computation speed and data transfer rate, a gap often referred to as the memory-wall. For data-intensive applications with finite-time locality, the primary energy bottleneck in processing throughput is data movement between the processor and main memory.

[0025] Figure 1 This is a block diagram of the tab switching process in an internet browser, illustrating the sub-processes that constitute the tab switching process executed in the CPU of the PCD. The first sub-process 101, executed by the CPU, retrieves N uncompressed pages 102 from main memory outside the CPU, where N is a positive integer corresponding to the number of pages to be swapped. The second sub-process 103, executed by the CPU, compresses the retrieved pages. The third sub-process 104, executed by the CPU, writes the compressed pages 105 to main memory.

[0026] A study of a very common internet browser workload running on the SoCs used in current PCDs reveals that a large percentage of energy consumption is due to data movement between the CPU and memory. Figure 2 It is a graph showing the percentage of energy consumed by data movement between the processor and memory compared to the energy consumed by calculating four different processes: (1) texture and color bit block transfer when scrolling in an internet browser, (2) compression and decompression when switching tabs in an internet browser, (3) packing, unpacking and quantization when using artificial intelligence (AI) machine learning software, and (4) subpixel interpolation and deblocking filtering when using a VP9 encoder / decoder.

[0027] Bars 201a and 201d represent the percentage of energy consumed due to data movement for the corresponding processes, and bars 202a and 202d represent the energy consumed due to computations performed by the corresponding processes. All these processes use relatively simple operations (such as shifting, addition, and multiplication) to perform their respective computations. As can be seen from the graphs, the percentage of energy consumed due to data movement is very high compared to the percentage consumed due to computation, and in some cases exceeds the percentage consumed due to computation. For data-intensive applications (such as deep neural networks and graphics processing applications) where there is little or no temporal locality in the data, the energy consumed due to data movement is a major bottleneck in achieving performance per milliwatt (mW).

[0028] This disclosure provides a solution for achieving energy-efficient computing by reducing the amount of data transferred between the processor and an external memory device. To achieve this, the processor is equipped with a first proximity data processing control unit (NCU). Processing circuitry and a second NCU are located on or near the external memory device. The first and second NCUs coordinate the offloading of pre-selected subprocesses from the processor to the processing circuitry located on or near the external memory device. When the processor is executing one of these pre-selected processes, which includes multiple subprocesses, the first NCU of the processor sends a command to the second NCU of the memory device, which instructs the processing circuitry in or near the memory device on how to execute the subprocess. The first NCU also transmits to the second NCU the memory address where data to be processed in the subprocess is stored in the memory device. The processing circuitry located on or near the memory device executes one or more subprocesses, and the second NCU then forwards the results of one or more subprocesses to the first NCU, which in turn forwards the results to the processor. The processor then uses the results to complete the process.

[0029] Therefore, the large amount of data movement between the processor and memory devices used to execute the process has been eliminated, while the processor is freed up to perform other tasks while the processing circuitry executes one or more sub-processes.

[0030] In the following detailed description, exemplary or representative embodiments with specific details disclosed are set forth for purposes of explanation and not limitation, in order to provide a thorough understanding of embodiments according to this teaching. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” The words “illustrative” or “representative” are used herein synonymously with “exemplary.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. However, it will be apparent to those skilled in the art, who benefit from this disclosure, that other embodiments according to this teaching that depart from the specific details disclosed herein remain within the scope of the appended claims. Furthermore, descriptions of well-known apparatuses and methods may be omitted so as not to obscure the description of exemplary embodiments. Such methods and apparatus are clearly within the scope of this teaching.

[0031] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting. The defined terms are supplementary to their technical and scientific meanings as generally understood and accepted in the technical field of this teaching content.

[0032] Unless the context clearly indicates otherwise, the terms “a,” “an,” and “the” as used in the specification and appended claims include both singular and plural references. Thus, for example, “an apparatus” includes one apparatus and multiple apparatuses.

[0033] Relative terms are used to describe the relationships between individual elements, as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, these relative terms are intended to cover different orientations of the equipment and / or elements.

[0034] It should be understood that when an element is described as being "connected to," "coupled to," or "electrically coupled to" another element, the element may be directly connected or coupled, or there may be intermediate elements present.

[0035] The term "external memory device" (as used herein) is intended to refer to a non-transitory computer-readable storage medium located outside the processor, rather than a memory device or structure embedded in the processor and capable of storing computer instructions or computer code for execution by one or more processors. References to "memory device" or "external memory device" herein should be interpreted to include memory controllers, memory banks, and associated elements positioned between the memory controller and the memory bank, such as associated physical layers, associated memory channels, and associated memory columns.

[0036] As used herein, the term "processor" encompasses any electronic component capable of executing computer programs or computer instructions. References to a computer including "processor" herein should be interpreted as one or more processors. A processor may be, for example, a multi-core processor comprising multiple processing cores, each of which may include multiple processing stages in a processing pipeline. A processor may also refer to a collection of processors within a single computer system or distributed across multiple computer systems.

[0037] Computing devices may include multiple subsystems, cores, or other components. Such computing devices may be, for example, PCDs, such as laptops or handheld computers, cellular phones or smartphones, portable digital assistants, portable game consoles, and automotive safety systems for autonomous vehicles.

[0038] In this document, the reference to "near" the external memory device means that the processing circuitry and the second NCU are physically located at a shorter distance from the memory device than they are from the processor (e.g., CPU, GPU, etc.), and that the processing circuitry and the second NCU are located somewhere between the interconnects that interconnect the processor with the system cache and the memory bank of the external memory device. For example, in the case where the processor is a CPU and the external memory device is a dynamic random access memory (DRAM) device, the processing circuitry and the second NCU may be located in the system cache controller, which is located between the aforementioned interconnects and the DRAM bank in the memory hierarchy.

[0039] CPU --> Interconnects --> System cache and cache controller (second NCU+ processing circuit) --> DRAM / HBM controller --> PHY --> DRAM channel --> DRAM column --> DRAM group.

[0040] In this document, the reference to "on" the second NCU and processing circuitry means that the processing circuitry and the second NCU are located in (1) the memory controller of the external memory device, (2) the memory bank of the external memory device, or (3) somewhere between the memory controller and the memory bank (e.g., in the associated physical layer, in the associated memory channel, in the associated memory column, or anywhere in between). For example, in the case where the processor is a CPU and the external memory device is a DRAM memory device, the processing circuitry and the second NCU may be located in the DRAM memory controller: CPU --> interconnect --> system cache and cache controller --> DRAM controller (second NCU + processing circuitry) --> PHY --> DRAM channel --> DRAM column --> DRAM bank.

[0041] Figure 3 yes Figure 1 The block diagram of the tag switching process shown is modified to eliminate the read process 101 and the write process 104 respectively, and offload the compression subprocess 103 to the processing circuitry 310 located on or near the memory device. Figure 1 The compression subprocess 103 executed by the CPU in Figure 3 The compression subprocess 303 executed by the processing circuit 310 has replaced the data movement between the processing circuit 310 and the memory, and the energy consumed by this data movement is negligible. Furthermore, it can be seen that the CPU processor is idle during the time it was previously occupied to execute the read subprocess 101, write subprocess 104, and compression subprocess 103 respectively, thereby freeing up the CPU to perform other tasks.

[0042] It should be noted that although the CPU is Figure 3 The CPU is shown as the processor from which the subprocesses unload, but the CPU can be any processor, including, for example, a GPU, DSP, NPU, or any other processor that can access external memory devices.

[0043] Figure 4This is a block diagram of a system 400 for performing energy-efficient computing by reducing data movement between processor 410 and external memory 430, according to an exemplary embodiment. System 400 can be used in, for example, a SoC package used in PCD, but the principles and concepts of the invention are not limited to the type of system employing them. For illustrative purposes, the systems and methods of this disclosure are described as being implemented in SoC package 401.

[0044] Processor 410 and external memory device 430 are respectively equipped with a first NCU 420 and a second NCU 440, which coordinate the offloading of preselection subprocesses from processor 410 to processing circuitry 450 disposed on or near external memory device 430. For illustrative purposes, the second NCU 440 and processing circuitry 450 are shown as embedded in memory device 430, but one or both of NCU 440 and processing circuitry 450 may alternatively be external to memory device 430 and very close to it and to each other. Processing circuitry 450 communicates with memory device 430 via a suitable interface for high-speed data transfer. Similarly, processing circuitry 450 communicates with second NCU 440 via a suitable interface.

[0045] While processor 410 is executing one of these pre-selected processes comprising multiple sub-processes, the first NCU 420 of processor 410 sends a command to the second NCU 440 of memory device 430, which processing circuit 450 uses to execute one or more sub-processes unloaded from processor 410 to processing circuit 450. The first NCU 420 also transmits to the second NCU 440 the memory address where data to be processed by the sub-processes is stored in memory device 430. Processing circuit 450 retrieves the data from the memory address and executes one or more sub-processes to produce a result. In some cases, this result may be stored by processing circuit 450 in memory device 430. For example, for Figure 3 In the process described, processing circuitry 310 writes compressed pages to memory. If further processing of the results by processor 410 is required, second NCU 440 forwards the results of one or more sub-processes to first NCU 420, which then forwards the results to processor 410. Processor 410 then uses the results to complete the entire process.

[0046] As indicated above, processor 410 can be any processor, such as CPU, GPU, DSP, NPU, etc. Memory device 430 can be any memory device, but is typically main memory and typically a DRAM device, although it can be any type of memory device.

[0047] Figure 5 This is a flowchart of a method for energy-efficient computing by reducing the amount of data transferred between a processor and an external memory device, according to an exemplary embodiment. According to this embodiment, the result generated by the processing circuitry is forwarded by a second NCU to a first NCU, which in turn forwards the result to the processor for further processing. A processor startup process is initiated, in which one or more pre-selected subprocesses are offloaded to processing circuitry located at or near the external memory device, as indicated in block 501. The first subprocess of this process may be a subprocess to be executed by the processor or a subprocess designated to be offloaded to processing circuitry located at or near the memory device. For ease of discussion, it will be assumed that the first subprocess will be offloaded and executed by processing circuitry located at or near the memory device.

[0048] The processor's first NCU transmits a sub-processing command and a first memory address containing data to be processed by the first sub-process to a second NCU located on or near an external memory device, as indicated in box 502. The second NCU reads the data stored at the first memory address on the memory device and forwards the read data and the command received from the first NCU to processing circuitry located on or near the memory device, as indicated in box 503. The processing circuitry executes one or more specified sub-processes on the read data to produce a result, as indicated in box 504. The second NCU transmits the result to the first NCU, as indicated in box 505, which forwards the result to the processor, as indicated in box 506. The processor processes the result, as indicated in box 507.

[0049] As indicated above, the processor may execute additional sub-processes or tasks utilizing the results produced by processing circuitry located on or near the memory device. The processor may execute one or more other related sub-processes to achieve other results. Results received from the second NCU in the first NCU may be used by the processor with the results of other related sub-processes executed by the processor, or may not be used by the processor with the results of other related sub-processes executed by the processor.

[0050] Figure 6 This is a flowchart of a method for energy-efficient computing by reducing the amount of data transferred between a processor and an external memory device, according to another exemplary embodiment. According to this embodiment, the result generated by the processing circuitry is not forwarded from the second NCU to the first NCU, but is instead stored in memory by the processing circuitry. According to this embodiment, no further processing of the result by the processor is required, and therefore the processing circuitry stores the result in memory.

[0051] The processor startup process, in which one or more pre-selected subprocesses are offloaded to processing circuitry located at or near an external memory device, as indicated in box 601. The first subprocess of this process may be a subprocess that the processor will execute or a subprocess designated to be offloaded to processing circuitry located at or near the memory device. For ease of discussion, it will be assumed that the first subprocess will be offloaded and executed by processing circuitry located at or near the memory device.

[0052] The processor's first NCU transmits a subprocessing command and a first memory address containing data to be processed by the first subprocess to a second NCU located on or near an external memory device, as indicated in box 602. The second NCU reads the data stored at the first memory address on the memory device and forwards the read data and the command received from the first NCU to processing circuitry located on or near the memory device, as indicated in box 603. The processing circuitry executes one or more specified subprocesses on the read data to produce a result, as indicated in box 604. The processing circuitry then stores the result in an external memory device, as indicated in box 605.

[0053] Refer again Figure 4 Each of NCU 420 and NCU 440 may be, for example, a hardware unit configured to execute Near Data Processing (NDP) Enable Instructions (NEIs). Each of NCU 420 and NCU 440 may include, for example, computational logic units and operand buffers. The operand buffer may be, for example, a small static random access memory (SRAM) buffer that stores the commands and addresses in memory where the data to be processed resides. The primary purpose of the operand buffer is to achieve instruction-level parallelism. For the use of the NCU in this solution, the ISA extension in the host processor 410 may be used to identify subprocesses designated for offloading to the first processing circuitry 450 located on or near memory 430.

[0054] It is important to note the differences between the systems and methods disclosed herein and known utilizations of computation caches. Computation caches are channels that utilize the temporal locality of data patterns. Before load / store operations are performed at the computation pipeline level, data needs to be brought back to the cache, which is an expensive off-chip data movement, especially when multiple cache lines need to be fetched or when data prefetching occurs speculatively. If workloads that do not have temporal locality exist, such as those utilizing, for example, matrix multiplication, using a computation cache to handle these workloads would require a large number of cache accesses, wasting energy in data movement: Total energy cost = Off-chip data movement energy cost + Computation energy cost.

[0055] The solution disclosed herein brings computation to memory or near memory, which is in contrast to the concept of computation cache and is well-suited for situations where the data to be processed has very little or no temporal locality.

[0056] The second NCU 440 and the first processing circuit 450 can be placed in the logic repository of, for example, a 3D stacked DRAM memory system, as will now be referred to. Figure 7A and Figure 7B As described. Figure 7A This is a schematic diagram of a 3D stacked DRAM memory device 700, which has... Figure 4 The second NCU 440 and processing circuit 450 shown are embedded in the repository logic component 720 of the logic die 710 of the DRAM memory device 700. Figure 7B It has embedded within it. Figure 4 The diagram shows a block diagram of the storage logic unit 720 for the second NCU 440 and processing circuitry 450. Since the storage logic unit 720 is close to the memory bank containing the DRAM die 711 in which data to be processed by the subprocess is stored, the data movement between the DRAM die 711 and the processing circuitry 450 located within the storage logic unit 720, as well as the energy costs associated with writing to and reading from memory, are negligible.

[0057] exist Figure 7A In the exemplary embodiment shown, a first interface device 730 mounted on a second interface device 740 of the SoC is used to interface the DRAM memory device 700 with the processor die 410 and to interface both components with other components of the SoC (not shown). However, the principles and concepts of the invention are not limited to this configuration. Figure 7A All components shown in the assembly may, for example, be integrated into the same SoC package and formed in layers of the SoC package, which are interconnected by vias, traces and other electrical wiring of the SoC.

[0058] It should be noted that the second NCU 440 and processing circuitry 450 can be located on or near an external memory device. Figure 7A and Figure 7BIn the 3D memory devices of the type shown, preferably, the second NCU 440 and processing circuitry 450 are disposed in the logic die of the external memory device, or at some other location along the route between the logic die and the memory bank. As indicated above, processing circuitry 450 can be implemented with relatively simple logic components (such as adders and multipliers), which will not consume a large amount of space and are therefore well-suited for implementation in the logic die of the memory device. For planar memory devices, processing circuitry 450 can be implemented in the processor-in-memory (PIM) computational logic unit of the external memory device and can be integrated per memory bank group to take advantage of memory bank-level parallelism.

[0059] Figure 8 This is a flowchart of the texture filling process currently performed by the CPU. The texture chunking process is the primary source of data movement between the CPU and main memory and utilizes large rasterized bitmaps (e.g., 4 megabytes (Mb)). Furthermore, the data processed during this process exhibits poor temporal locality, meaning that the process will not significantly benefit from using cache memory to reduce transfers between the CPU and main memory.

[0060] The process begins with a rasterization sub-process 801, which generates a linear bitmap and writes it to memory. The CPU then executes a sub-process 805, which reads the linear bitmap from memory 803, converts the linear bitmap into a texture tile 804, and writes the texture tile to memory 805.

[0061] Figure 9 This is a flowchart of a texture filling process according to a representative embodiment of the present disclosure, wherein the sub-processes of generating a linear bitmap 902 and converting the linear bitmap into a texture tile 903 are performed by a combination of actions of a second NCU 440 and processing circuitry 450 disposed on or near a memory. For ease of illustration, Figure 9 The second NCU 440 is not shown in the figure. Figure 4 The processor 410 shown is in Figure 9The process is represented by CPU 900. CPU 900 executes the rasterization subprocess 901 to generate a linear bitmap, and the second NCU 440 writes the linear bitmap to memory. The subprocesses of generating the linear bitmap 902 and converting the linear bitmap into texture tiles 903 are executed by processing circuitry 450. Because the second NCU 440 and processing circuitry 450 are located on or near the memory, data movement is negligible when writing the linear bitmap to and from memory, and when writing the texture file to and from memory. In addition, a large number of logic components are not required to implement the second NCU 440 and processing circuitry 450 because texture tile operations are relatively simple operations that require simple primitive processing, such as memory copying, bitwise operations, and simple arithmetic operations.

[0062] Figure 10 This is a flowchart of the packing / unpacking and quantization process currently executed by the CPU. This process is the primary source of data movement between the CPU and main memory and utilizes large amounts of data with poor temporal locality. The process executed by the CPU includes the following sub-processes: reading a 32-bit matrix from memory and finding the minimum and maximum values ​​of the matrix 1001; quantizing each matrix value using the minimum and maximum values ​​to produce an 8-bit matrix 1002; performing convolution on the 8-bit matrix to produce a 32-bit result matrix and writing the result matrix to memory 1003; subsequently requantizing the result matrix by reading the 32-bit result matrix from memory; finding the minimum and maximum matrix element values ​​1004; and using the minimum and maximum values ​​1005 to produce an 8-bit matrix.

[0063] Figure 11 yes Figure 9 The flowchart of the process shown is modified according to a representative embodiment of this disclosure to be executed by a combined operation of a second NCU 440 (not shown for illustration) disposed on or near the memory and a first processing circuit 450. Figure 10 The sub-processes of boxes 1001 and 1002 are respectively used as... Figure 11 Boxes 1101 and 1102 in the text. Similarly, Figure 10 The subprocesses of blocks 1004 and 1005 are executed by a combined action of a second NCU 440 and a processing circuit 450 located on or near the memory, respectively, as Figure 11 Boxes 1103 and 1104 in the diagram. To avoid having to use complex logic components in the processing circuit 450, the convolution subprocess 1103 can continue to be executed by the CPU 1100, since this convolution subprocess is a more processing-intensive subprocess than the others.

[0064] Therefore, by Figure 11The subprocesses represented by boxes 1101 to 1104 have all been offloaded from CPU 1100 to processing circuitry 450. This greatly reduces the amount of data movement between CPU 1100 and external memory, as well as the amount of energy consumed due to data movement, while also freeing up CPU 1100 to perform other tasks.

[0065] It should be noted that Figure 3 , Figure 9 and Figure 11 The subprocesses shown to be unloaded for execution on or near memory are merely examples of subprocesses applicable to unloading, due to the poor temporal locality of the data used in these processes, and also because the operations of these processes are relatively simple operations that can be performed in relatively simple logic components without consuming a large amount of die area.

[0066] Figure 12 Examples of the PCD 1200 are illustrated, such as mobile phones, smartphones, and portable game consoles (such as extended reality (XR) devices, virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices, etc.), in which systems, methods, exemplary embodiments of computer-readable media, and other examples of providing high-energy-efficiency processing with reduced data movement can be implemented according to the principles and concepts of the present invention. For clarity, Figure 12 Some interconnects, signals, etc. are not shown.

[0067] PCD 1200 may include SoC 1202. SoC 1202 may include CPU 1204, NPU 1205, GPU 1206, DSP 1207, analog signal processor 1208, modem / modem subsystem 1254, or other processors. CPU 1204 may include one or more CPU cores, such as a first CPU core 12041, a second CPU core 12042, and so on up to the Mth CPU core 1204. M .

[0068] Display controller 1209 and touchscreen controller 1212 may be coupled to CPU 1204. A touchscreen display 1214 external to SoC 1202 may be coupled to display controller 1210 and touchscreen controller 1212. PCD 1200 may also include a video decoder 1216 coupled to CPU 1204. Video amplifier 1218 may be coupled to video decoder 1216 and touchscreen display 1214. Video port 1220 may be coupled to video amplifier 1218. Universal Serial Bus (“USB”) controller 1222 may also be coupled to CPU 1204, and USB port 1224 may be coupled to USB controller 1222. Subscriber Identity Module (“SIM”) card 1226 may also be coupled to CPU 1204.

[0069] One or more memory units 1228 may be coupled to CPU 1204. The one or more memory units 1228 may include both volatile and non-volatile memory. Examples of volatile memory include static random access memory (“SRAM”) and dynamic random access memory (“DRAM”). Such memory may be external to or internal to SoC 1202. The one or more memory units 1228 may include local cache memory or system-level cache memory. A second NCU 440 and processing circuitry 450 may be disposed on or near the one or more memory units 1228.

[0070] A stereo audio CODEC 1234 can be coupled to an analog signal processor 1208. Additionally, an audio amplifier 1236 can be coupled to the stereo audio CODEC 1234. A first stereo speaker 1238 and a second stereo speaker 1240 can be coupled to the audio amplifier 1236, respectively. Furthermore, a microphone amplifier 1242 can be coupled to the stereo audio CODEC 1234, and a microphone 1244 can be coupled to the microphone amplifier 1242. An FM radio tuner 1246 can be coupled to the stereo audio CODEC 1234. An FM antenna 1248 can be coupled to the FM radio tuner 1246. Additionally, stereo headphones 1250 can be coupled to the stereo audio CODEC 1234. Other devices that can be coupled to the CPU 1204 include one or more digital (e.g., CCD or CMOS) cameras 1252.

[0071] A modem or RF transceiver 1254 may be coupled to an analog signal processor 1208 and a CPU 1204. An RF switch 1256 may be coupled to an RF transceiver 1254 and an RF antenna 1258. Additionally, a keypad 1260 and a mono headset 1262 with a microphone may be coupled to the analog signal processor 1208. The SoC 1202 may have one or more internal or on-chip thermal sensors 1270. A power supply 1274 and a PMIC 1276 may power the SoC 1202.

[0072] Firmware or software may be stored in any of the aforementioned memories, or in local memory directly accessible to the processor hardware on which the software or firmware is executed. Execution of such firmware or software can control aspects of any of the aforementioned methods or configure aspects of any of the aforementioned systems. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware is an example of a "computer-readable medium," as understood in the patent dictionary.

[0073] Specific implementation examples are described in the following numbered clauses:

[0074] 1. A method for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the method comprising:

[0075] Use the processor to initiate a first process that includes at least a first subprocess;

[0076] The processor's first near-data processing control unit (NCU) is used to output at least a first processing command associated with the execution of the first sub-process and a first address in the memory device for storing data associated with the first sub-process;

[0077] The first processing command and the first address are received using a second NCU located on or near the memory device, and the data stored at the first address is read from the memory device and forwarded to the processing circuitry located on or near the memory device; and

[0078] In the processing circuit, the at least first sub-process is executed by executing the at least first processing command on the data read from the first memory address to produce a first result.

[0079] 2. The method described in Clause 1 further includes:

[0080] The processing circuitry is used to store the first result in the memory device.

[0081] 3. The method described in Clause 1 further includes:

[0082] The second NCU is used to transmit the first result to the first NCU;

[0083] The first NCU is used to forward the first result to the processor; and the first result is processed in the processor.

[0084] 4. The method according to any one of clauses 1 to 3, wherein the first process includes a tag switching process, and the at least first sub-process includes a compression sub-process that compresses the data read from the first address to produce the first result.

[0085] 5. The method according to any one of Clauses 1 to 3, wherein the first process includes a texture tiling process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, the linear bitmap generation process processing the data read from the first address to generate a linear bitmap, and the conversion sub-process processing the linear bitmap to convert the linear bitmap into texture tiles.

[0086] 6. The method according to Clause 3, wherein the first process includes a quantization and packing process, and the at least first sub-process includes at least a first quantization sub-process, the at least first quantization process processing the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

[0087] 7. The method according to Clause 6, wherein the at least first quantization sub-process further includes a sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix, wherein the multi-bit matrix includes the first result forwarded by the second NCU to the host processor.

[0088] 8. The method described under Clause 7 further includes:

[0089] A sub-process is executed in the processor, the sub-process including performing a convolution on the multi-bit matrix to produce the first...

[0090] Two results;

[0091] The first NCU is used to forward the second result to the second NCU;

[0092] The second result is received in the second NCU and forwarded to the processing circuit.

[0093] as well as

[0094] A second quantization sub-process is executed in the processing circuit, which processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

[0095] 9. The method according to Clause 8, wherein the second quantization sub-process further comprises generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

[0096] 10. The method according to any one of clauses 1 to 9, wherein the host processor and the memory device are components of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device.

[0097] 11. A method for performing high energy efficiency by reducing data movement between the processor and a memory device external to the host processor.

[0098] The computing system includes:

[0099] A processor, the processor including logic configured to initiate at least a first process comprising at least a first subprocess.

[0100] Editing components;

[0101] A memory device, the memory device including a memory address configured to store data;

[0102] A first proximity data processing control unit (NCU), embedded in or communicating with the processor, includes logic components configured to receive at least a first processing command and a first address from the processor. The at least first processing command includes one or more commands for executing the first sub-process, and the first address is a storage address of the memory device to be processed by the first sub-process.

[0103] The address of the data processed in the process;

[0104] A second NCU, located on or near the memory device and communicating with the first NCU, is configured to receive the first address and the first command from the first NCU.

[0105] Logic components; and

[0106] A processing circuit disposed on or near the memory device, the processing circuit including a logic component configured to: receive the first command and the first address from the second NCU, read data from the first address, and execute the first command on the data read from the first address to produce a first result.

[0107] 12. The system according to Clause 11, wherein the processing circuitry is further configured to store the first result at an address of the memory device.

[0108] 13. The system according to Clause 11, wherein the second NCU is further configured to transmit the first result to the first NCU, and wherein the first NCU is further configured to forward the first result to the processor, the processor being further configured to process the first result.

[0109] 14. The system according to any one of clauses 11 to 13, wherein the first process includes a tag switching process, and the at least first sub-process includes a compression sub-process, the processing circuitry being further configured to execute the compression sub-process to compress the data read from the first address to produce the first result.

[0110] 15. The system according to any one of clauses 11 to 13, wherein the first process includes a texture chunking process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, the processing circuitry being further configured to execute the linear bitmap generation sub-process to process the data read from the first address to generate a linear bitmap, and to execute the conversion sub-process to process the linear bitmap to convert the linear bitmap into texture chunks.

[0111] 16. The system according to any one of clauses 11 to 13, wherein the first process includes a quantization and packaging process, and

[0112] The at least first sub-process includes at least a first quantization sub-process, and the processing circuit is configured to execute the at least first quantization process to process the data read from the first address, thereby determining a first minimum matrix element value and a first maximum matrix element value.

[0113] 17. The system method according to Clause 16, wherein the at least first quantization sub-process further includes a sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix, the processing circuitry being further configured to perform the sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix.

[0114] The subprocess, wherein the multi-bit matrix includes the first result forwarded by the second NCU to the processor.

[0115] 18. The system according to Clause 17, wherein the processor is further configured to execute a sub-process including performing a convolution on the multi-bit matrix to produce a second result, and wherein the first NCU is further configured to forward the second result to a second NCU, the second NCU being further configured to receive the second result and forward the second result to the processing circuitry, the processing circuitry being further configured to execute a second quantization sub-process that processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

[0116] 19. The system according to Clause 18, wherein the second quantization subprocess further includes a subprocess for generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, the processing circuitry being further configured to use the second minimum matrix element value and the second maximum matrix element value to generate the second multi-bit matrix subprocess.

[0117] 20. The system of claim 11, wherein the system is part of a system-on-chip (SoC) integrated circuit (IC) package of a portable computing device, and wherein the processing circuitry, the second NCU, and the memory device are part of a stacked dynamic random access (DRAM) memory system of the SoC IC package, the memory device comprising a plurality of stacked DRAM dies, the second NCU and the processing circuitry being embedded in a repository logic component of the logic dies of the stacked DRAM memory system.

[0118] 21. A computer program comprising computer instructions for performing energy-efficient computing by reducing data movement between a processor and a memory device external to the processor, the computer instructions being embodied in a non-transitory computer-readable medium.

[0119] The computer instructions include:

[0120] A first set of computer instructions, the first set of computer instructions being executed by a processor to initiate, including, to, […].

[0121] The first process with fewer first subprocesses;

[0122] A second set of computer instructions, which is executed by a first near data processing control unit (NCU) of the processor, to cause the first NCU to output at least a first processing command for executing the first sub-process and a first address for storing data associated with the first sub-process in the memory device;

[0123] A third set of computer instructions, executed by a second NCU located on or near the memory device, to cause the second NCU to receive the at least first processing command and the first address, and to cause the data stored at the first address to be read from the memory device and forwarded to the device.

[0124] Processing circuitry on or near the memory device; and

[0125] A fourth set of computer instructions, which is executed by the processing circuit to cause the processing circuit to execute the at least first sub-process by executing the at least first processing command on the data read from the first address to produce a first result.

[0126] 22. The computer program pursuant to Clause 21, further comprising:

[0127] A fifth set of computer instructions, which is executed by the processing circuit to cause the processing circuit to store the first result in the memory device.

[0128] 23. The computer program pursuant to Clause 21, further comprising:

[0129] A fifth set of computer instructions, which is executed by the second NCU to cause

[0130] The second NCU transmits the first result to the first NCU;

[0131] A sixth set of computer instructions, which is executed by the first NCU to cause

[0132] The first NCU forwards the first result to the processor; and

[0133] A seventh set of computer instructions, which is executed by the processor to cause the processor to process the first result.

[0134] 24. The computer program according to Clause 21, wherein the first process includes a tag switching process, and the at least first sub-process includes a compression sub-process, and the fourth set of computer instructions includes instructions for compressing the data read from the first address to produce the first result.

[0135] 25. The computer program according to Clause 21, wherein the first process includes a texture tiling process, and the at least first sub-process includes a linear bitmap generation sub-process and a conversion sub-process, and the fourth set of computer instructions includes computer instructions for processing the data read from the first address to generate a linear bitmap and computer instructions for processing the linear bitmap to convert the linear bitmap into texture tiles.

[0136] 26. The computer program according to Clause 23, wherein the first process includes a quantization and packaging process, and the at least first sub-process includes at least a first quantization sub-process, and the fourth set of computer instructions includes instructions for processing from the first...

[0137] A computer instruction that reads the data from an address to determine a first minimum matrix element value and a first maximum matrix element value.

[0138] 27. The computer program according to Clause 26, wherein the at least first quantization sub-process further includes a sub-process of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate a multi-bit matrix, and the fourth set of computer instructions further includes computer instructions of quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to generate the multi-bit matrix, wherein the multi-bit matrix includes the first result forwarded by the second NCU to the host processor.

[0139] 28. The computer program according to Clause 27, wherein the seventh set of computer instructions includes computer instructions for performing a convolution on the multi-bit matrix to produce a second result, and wherein the second set of computer instructions further includes computer instructions for causing the first NCU to forward the second result to the second NCU, and wherein the third set of computer instructions further includes computer instructions for causing the second NCU to receive the second result and forward the second result to the processing circuitry, and wherein the fourth set of computer instructions includes computer instructions for causing the processing circuitry to execute a second quantization sub-procedure, the second quantization sub-procedure processing the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

[0140] 29. The computer program according to Clause 27, wherein the second quantization subprocess further includes generating a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, and wherein the fourth set of computer instructions further includes computer instructions for generating the second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

[0141] 30. A method for performing high energy efficiency by reducing data movement between a processor and a memory device external to the processor.

[0142] The computing system includes:

[0143] A processor configured to initiate a first process including at least a first sub-process, the processor including a logic unit configured to output at least a first processing command associated with executing the first sub-process and a first address in the memory device storing data associated with the first sub-process; and

[0144] A processing circuit embedded in the memory device, the processing circuit including logic components configured to: receive a first processing command and a first address, and cause the data stored at the first address to be read from the memory device and forwarded to the processing circuit, the processing circuit including logic components configured to execute the at least first sub-process to produce a first result by executing the at least first processing command on the data read from the first memory address.

[0145] Alternative implementation schemes will become apparent to those skilled in the art. Therefore, although the aspects of the options have been illustrated and described in detail, it should be understood that various substitutions and changes can be made therein.

Claims

1. A method for performing high energy efficient computations by reducing data movement between a processor and a memory device external to the processor, the method comprising: initiating, with a processor, a first process comprising at least a first sub-process; outputting, with a first near data processing control unit (NCU) of the processor, at least a first processing command associated with executing the first sub-process and a first address of the memory device to store data associated with the first sub-process in the memory device; receiving, with a second NCU disposed on or near the memory device, the first processing command and the first address, and causing the data stored at the first address to be read from the memory device and forwarded to a processing circuit disposed on or near the memory device; and executing the at least first sub-process in the processing circuit by executing the at least first processing command on the data read from the first memory address to produce a first result; wherein the first process comprises a texture binning process, and the at least first sub-process comprises a linear bit map generation sub-process and a conversion sub-process, the linear bit map generation sub-process processes the data read from the first address to produce a linear bit map, and the conversion sub-process processes the linear bit map to convert the linear bit map into a texture tile.

2. The method of claim 1, further comprising: storing, with the processing circuit, the first result in the memory device.

3. The method of claim 1, further comprising: communicating, with the second NCU, the first result to a first NCU; forwarding, with the first NCU, the first result to the processor; and processing the first result in the processor.

4. The method of claim 1, wherein the first process comprises a label switching process, and the at least first sub-process comprises a compression sub-process that compresses the data read from the first address to produce the first result.

5. The method of claim 3, wherein the first process comprises a quantization and packing process, and the at least first sub-process comprises at least a first quantization sub-process that processes the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

6. The method of claim 5, wherein the at least first quantization sub-process further comprises a sub-process that quantizes the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, wherein the multi-bit matrix comprises the first result forwarded by the second NCU to a host processor.

7. The method of claim 6, further comprising: executing, in the processor, a sub-process comprising performing a convolution on the multi-bit matrix to produce a second result; forwarding, with the first NCU, the second result to the second NCU; receiving the second result in the second NCU and forwarding the second result to the processing circuitry; and performing a second quantization sub-process in the processing circuitry, the second quantization sub-process processing the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

8. The method of claim 7, wherein the second quantization sub-process further comprises using the second minimum matrix element value and the second maximum matrix element value to produce a second multi-bit matrix.

9. The method of claim 1, wherein the host processor and the memory device are components of a system on a chip (SoC) integrated circuit (IC) package of a portable computing device.

10. A system for performing energy efficient computing by reducing data movement between a processor and a memory device external to the host processor, the system comprising: a processor, the processor comprising logic configured to initiate at least a first process comprising at least a first sub-process; a memory device, the memory device comprising a memory address configured to store data; a first near data processing control unit (NCU) embedded in the processor or in communication with the processor, the first NCU comprising logic configured to receive at least a first processing command and a first address from the processor, the at least first processing command comprising one or more commands for performing the first sub-process, the first address being an address of the memory device at which data is to be stored to be processed by the first sub-process; a second NCU disposed on or near the memory device and in communication with the first NCU, the second NCU comprising logic configured to receive the first address and first command from the first NCU; and a processing circuitry disposed on or near the memory device, the processing circuitry comprising logic configured to receive the first command and the first address from the second NCU and read data from the first address and execute the first command on the data read from the first address to produce a first result; wherein the first process comprises a texture binning process and the at least first sub-process comprises a linear bit map generation sub-process and a conversion sub-process, the processing circuitry being further configured to perform the linear bit map generation sub-process to process the data read from the first address to produce a linear bit map and perform the conversion sub-process to process the linear bit map to convert the linear bit map into a texture tile.

11. The system of claim 10, wherein the processing circuitry is further configured to store the first result at an address of the memory device.

12. The system of claim 10, wherein the second NCU is further configured to communicate the first result to the first NCU, and wherein the first NCU is further configured to forward the first result to the processor, the processor being further configured to process the first result.

13. The system of claim 10, wherein the first process comprises a tag switch process, and the at least first sub-process comprises a compression sub-process, the processing circuitry being further configured to execute the compression sub-process to compress the data read from the first address to produce the first result.

14. The system of claim 12, wherein the first process comprises a quantization and packing process, and the at least first sub-process comprises at least a first quantization sub-process, the processing circuitry being configured to execute the at least first quantization sub-process to process the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

15. The system of claim 14, wherein the at least first quantization sub-process further comprises a sub-process to quantize the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, the processing circuitry being further configured to execute the sub-process to quantize the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, and wherein the multi-bit matrix comprises the first result forwarded by the second NCU to the processor.

16. The system of claim 15, wherein the processor is further configured to execute a sub-process comprising performing a convolution on the multi-bit matrix to produce a second result, and wherein the first NCU is further configured to forward the second result to the second NCU, the second NCU being further configured to receive the second result and forward the second result to the processing circuitry, the processing circuitry being further configured to execute a second quantization sub-process that processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

17. The system of claim 16, wherein the second quantization sub-process further comprises a sub-process to produce a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, the processing circuitry being further configured to execute the sub-process to produce a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

18. The system of claim 10, wherein the system is part of a system-on-a-chip (SoC) integrated circuit (IC) package of a portable computing device, and wherein the processing circuit, the second NCU, and the memory device are part of a stacked dynamic random access (DRAM) memory system of the SoC IC package, the memory device comprising a plurality of stacked DRAM dies, the second NCU and the processing circuit being embedded in a storage vault logic of a logic die of the stacked DRAM memory system.

19. A computer product comprising computer instructions for performing a high energy efficient computation by reducing data movement between a processor and a memory device external to the processor, the computer instructions being embodied in a non-transitory computer readable medium, the computer instructions comprising: a first set of computer instructions for execution by a processor to initiate a first process comprising at least a first sub-process; a second set of computer instructions for execution by a first near data processing control unit (NCU) of the processor to cause the first NCU to output at least a first processing command for executing the first sub-process and a first address in the memory device to store data associated with the first sub-process; a third set of computer instructions for execution by a second NCU disposed on or near the memory device to cause the second NCU to receive the at least first processing command and the first address, and cause the data stored at the first address to be read from the memory device and forwarded to a processing circuit disposed on or near the memory device; and a fourth set of computer instructions for execution by the processing circuit to cause the processing circuit to execute the at least first sub-process by executing the at least first processing command on the data read from the first address to produce a first result; wherein the first process comprises a texture binning process, and the at least first sub-process comprises a linear bit map generation sub-process and a conversion sub-process, the fourth set of computer instructions comprising computer instructions to process the data read from the first address to produce a linear bit map and computer instructions to process the linear bit map to convert the linear bit map to a texture tile.

20. The computer product of claim 19, further comprising: a fifth set of computer instructions for execution by the processing circuit to cause the processing circuit to store the first result in the memory device.

21. The computer product of claim 19, further comprising: a fifth set of computer instructions for execution by the second NCU to cause the second NCU to communicate the first result to the first NCU; a sixth set of computer instructions for execution by the first NCU to cause the first NCU to forward the first result to the processor; and ​ a seventh set of computer instructions for execution by the processor to cause the processor to process the first result.

22. The computer product of claim 19, wherein the first process comprises a tag switching process and the at least first sub-process comprises a compression sub-process, the fourth set of computer instructions comprising instructions for compressing the data read from the first address to produce the first result.

23. The computer product of claim 21, wherein the first process comprises a quantization and packing process and the at least first sub-process comprises at least a first quantization sub-process, the fourth set of computer instructions comprising computer instructions for processing the data read from the first address to determine a first minimum matrix element value and a first maximum matrix element value.

24. The computer product of claim 23, wherein the at least first quantization sub-process further comprises a sub-process for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce a multi-bit matrix, the fourth set of computer instructions further comprising computer instructions for quantizing the data read from the first address using the first minimum matrix element value and the first maximum matrix element value to produce the multi-bit matrix, wherein the multi-bit matrix comprises the first result forwarded by the second NCU to a host processor.

25. The computer product of claim 24, wherein the seventh set of computer instructions comprises computer instructions for performing a convolution on the multi-bit matrix to produce a second result, and wherein the second set of computer instructions further comprises computer instructions for causing the first NCU to forward the second result to the second NCU, and wherein the third set of computer instructions further comprises computer instructions for causing the second NCU to receive the second result and forward the second result to the processing circuitry, and wherein the fourth set of computer instructions comprises computer instructions for causing the processing circuitry to perform a second quantization sub-process that processes the second result to determine a second minimum matrix element value and a second maximum matrix element value of the second result.

26. The computer product of claim 25, wherein the second quantization sub-process further comprises producing a second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value, and wherein the fourth set of computer instructions further comprises computer instructions for producing the second multi-bit matrix using the second minimum matrix element value and the second maximum matrix element value.

27. A system for performing high energy efficient computations by reducing data movement between a processor and a memory device external to the processor, the system comprising: a processor configured to initiate a first process comprising at least a first sub-process, the processor comprising logic configured to output at least a first processing command associated with executing the first sub-process and a first address of the memory device to store data associated with the first sub-process in the memory device; and processing circuitry embedded in the memory device, the processing circuitry comprising logic configured to: receive the first processing command and the first address, and cause the data stored at the first address to be read from the memory device and forwarded to the processing circuitry, the processing circuitry comprising logic configured to execute the at least first sub-process by executing the at least first processing command on the data read from the first memory address to produce a first result; wherein the first process comprises a texture binning process, and the at least first sub-process comprises a linear bit map generation sub-process and a conversion sub-process, the processing circuitry comprising logic further configured to execute the linear bit map generation sub-process to process the data read from the first address to produce a linear bit map, and execute the conversion sub-process to process the linear bit map to convert the linear bit map into a texture tile.

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