Method and semiconductor device

Abstract

In at least one embodiment, a method for producing a semiconductor device (1), the method comprising: A) providing a semiconductor body (2) based on a Group IV semiconductor material, B) doping a first region (21) in the semiconductor body (2), the first region (21) being of a first conductivity type and starting from a surface (20) of the semiconductor body (2), and C) forming a semiconductor device (1) by selectively and wet-chemically etching the first region (21), a recess (3) is formed in the semiconductor body (2).

Description

Technical Field

[0001] A method for manufacturing a semiconductor device is provided. Also provided is a corresponding semiconductor device. Background Art

[0002] Document EP 1 011 130 A1 relates to a production method for a silicon-based acceleration sensor using electrochemical etching.

[0003] Document US 2022 / 0399442 A1 discloses a power semiconductor device having a recess in a semiconductor body.

[0004] The document “Analysis of Photoelectrochemical Processes in α-SiC substrates with Atomically Flat Surfaces” published by H. Mikami et al. in “Japanese Journal of Applied Physics”, Vol. 44, 8329 (2005), DOF 10.1143 / JJAP.44.8329, deals with etching SiC.

[0005] K. Kawahara et al., “Deep levels induced by reactiveion etching in n- and p-type 4H–SiC,” Journal of Applied Physics, Vol. 108, 023706 (2010), DOI: 10.1063 / 1.3460636, deals with energy levels in SiC.

[0006] T. Nakamura et al., “High-performance SiC trench devices with ultra-low on-resistance,” 2011 International Electron Devices Meeting, December 2011, DOI: 10.1109 / IEDM.2011.6131619, regarding SiC-based MOSFETs.

[0007] The paper “Optical properties of mesoporous 4H-SiC prepared by anodic electrochemical etching” by M. Rashid et al., published in “Journal of Applied Physics”, Vol. 120, 194303 (2016), DOI: 10.1063 / 1.4968172, and the paper “Systematic Characterization of Plasma-Etched Trenches on 4H-SiC Wafers” by M. D. Pirnacci et al., published in “ACS Omega”, Vol. 6, 20667 (2021), DOI: 10.1021 / acsomega.1c02905, both deal with SiC properties related to the processing of SiC.

[0008] The document “Vertical and bevel-structured SiC etching techniques incorporating different gas mixture plasmas for various microelectronic applications” by HK Sung et al., Scientific Reports, vol. 7, 3915 (2017), DOI: 10.1038 / s41598-017-04389-y, and the document “Surface polishing by electrochemical etching of p-type 4H SiC” by Y. Ke et al., Journal of Applied Physics, vol. 106, 064901 (2009), DOI: 10.1063 / 1.3212541, both relate to the roughness produced by etching of SiC. Summary of the Invention

[0009] An object to be achieved is to provide a method for efficiently producing semiconductor devices.

[0010] This object is achieved in particular by a method and a semiconductor device as defined in the independent patent claims. Exemplary further developments form the subject matter of the dependent claims.

[0011] For example, with this method, a trench is created in a SiC trench MOSFET by ion implantation and selective wet etching of the region subjected to the ion implantation.

[0012] In at least one embodiment, the method is for producing a semiconductor device and includes, for example, the following steps in the order recited:

[0013] A) providing a semiconductor body based on a Group IV semiconductor material,

[0014] B) doping one or more first regions in the semiconductor body, at least one first region being of a first conductivity type and starting, for example, from a surface of the semiconductor body, and

[0015] C) forming a recess in the semiconductor body by selectively and wet-chemically etching the at least one first region. Optionally, the finished semiconductor device is one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse-conducting insulated gate bipolar transistor (RC-IGBT). Further optionally, the method may further include:

[0016] D) doping a second region of the second conductivity type in the semiconductor body directly on the side of the first region away from the surface, the etching in step C) automatically stopping at the second region, so that after step C), the second region is directly located at the bottom surface of the surface (20) of the recess away from the semiconductor body, the root mean square RMS roughness of the bottom surface is at most 15nm, and the second region is configured as a shielding region in the finished semiconductor device.

[0017] Inductively coupled plasma reactive ion etching (ICP-RIE) is a selective dry etching process used to form trenches, mesas, and the like. This process relies on mask deposition, has good accuracy and reproducibility, and can be used for SiC device processing. Due to the chemical inertness of SiC, for example, different types of plasma can be used, typically chloride or fluoride, but also mixtures of oxygen and inert gases. The etching rate depends on the plasma and the power consumed, and can range from 500 nm / min to up to 800 nm / min. Among the side effects of using ICP-RIE, for example, the bottom surface of the SiC trench may become uneven due to reflection of plasma ions on the sidewalls. This unevenness can occur on the sidewalls themselves, creating micro-grooves. This adverse effect can be avoided through additional processing steps (such as a sidewall passivation layer) or by adding an oxide to the Cl-based plasma. Another adverse effect can be the formation of carbon vacancies in the etched epitaxial layer, i.e., in the epitaxially grown semiconductor layer. Furthermore, RIE may generate two electrically active energy levels labeled IN6 and EN at 1.0 eV and 1.6 eV below the conduction band edge, as described above by K. Kawahara et al.

[0018] Therefore, to improve semiconductor devices, in the method described herein, SiC trench devices can be produced without using RIE.

[0019] Instead of RIE, in the method described herein, ion implantation and electrochemical etching (ECE) are performed to form the trenches. ECE is a selective wet chemical etching method. ECE involves immersing the area to be etched in a solution, for example, based on HF. The SiC wafer can be used as an anode in the solution. The current density can be varied to control the etching rate. Etching occurs only in areas of the correct conductivity type (i.e., depending on the applied potential), which are conductive, for example, with a specific resistance of about 0.03Ωcm, while areas with a higher specific resistance remain intact. It is also possible to etch materials with the opposite conductivity type by reversing the polarity of the applied potential. The etching rate can be as high as 200μm / h.

[0020] Unlike using RIE, in the method described herein, no etch endpoint detection system is required because ECE stops when a region with different doping concentrations is reached. In addition, unlike RIE, ECE of the trench avoids point defects (such as carbon vacancies V C In addition, ECE can lead to a reduction in the roughness of the etched surface; for example, Cl-based RIE will produce a surface roughness of about 60nm to 70nm, while ECE can produce a surface roughness of about 2nm to 7nm (RMS).

[0021] By implantation, trenches of any depth and shape can be defined, and ECE forms these trenches much faster than RIE.

[0022] For example, plasma immersion ion implantation PIII after trench ECE can form an electric field limiting layer and remove possible V C .

[0023] Using the methods described herein, V-shaped trenches and the like can be fabricated by tilted ion implantation (eg, at an angle of 54.7° with respect to the 0-33-8 plane).

[0024] The final product can be reverse engineered using X-ray photoelectron spectroscopy (XPS). Compared to RIE-etched 4H-SiC, ECE-etched 4H-SiC exhibits unique features in the energy range of 280 eV to 290 eV, as shown in the references by M. Rashid et al. and MD Pirnac et al. mentioned above.

[0025] Deep Level Transient Spectroscopy (DLTS) can also be used to reverse engineer the final product. After implanting n-type SiC, the presence of ON1, ON2, and IN2 levels indicates the use of an ECE-based approach, as described in the reference by T. Nakamura et al. After implanting p-type SiC, the presence of HK0, IP5, IP7, and IP8 levels indicates the use of an ECE-based approach, as described in the reference by T. Nakamura et al.

[0026] According to at least one embodiment, the Group IV semiconductor material (also referred to as Group 14 semiconductor material) is C (such as diamond), Si, Ge, or any mixture thereof, such as SiC. In particular, the semiconductor material is SiC, such as stoichiometric SiC.

[0027] According to at least one embodiment, the first region is defined by doping. That is, all regions starting from the surface and doped in step B) can be referred to as first regions. In other words, the first region is defined by the doping in step B). However, multiple first regions can be defined by the doping in step B), but one or some of these first regions will not be etched; such first regions may be covered by another material before step C). Hereinafter, such regions covered by another material and not configured for etching are not referred to as first regions because such regions do not start from the surface as described in this context.

[0028] According to at least one embodiment, the recess in the semiconductor body is formed solely by wet-chemical etching of the first region. Consequently, all material removal to produce the recess results from the wet-chemical etching.

[0029] According to at least one embodiment, the wet chemical etching is selective etching. This means, for example, that the etching rate during the wet chemical etching of the first region is at least 10 times, or at least 100 times, or at least 10 times the etching rate of other regions of the semiconductor body exposed to the etching liquid used for the wet chemical etching. 3 times, or at least 10 4 times, or at least 10 5 Thus, “selectively” may mean that substantially only the at least one first region is etched, and no significant material removal occurs in other regions of the semiconductor body.

[0030] According to at least one embodiment, the at least one first region exposed to the etching liquid is completely etched away, so that the at least one first region does not remain in the finished semiconductor device.

[0031] According to at least one embodiment, the etching liquid is an acid or a solution containing at least one acid. For example, the etching liquid is an HF-based solution. For example, the HF-based solution is a 5% to 10% HF aqueous solution mixed with ethanol in a ratio of 1:1 or 2:1. Alternatively, for example, a ratio of HF (50%): acetic acid: HO of 4:6:2 or 1:1:5 can be used.

[0032] According to at least one embodiment, in ECE, the applied voltage is selected so that the current density is maintained at at least 10 mA / cm 2 and / or up to 80 mA / cm 2 .

[0033] According to at least one embodiment, method step B) comprises:

[0034] B1) applying an electrical potential to the semiconductor body such that at least a portion of the semiconductor body serves as an etching electrode, and

[0035] B2) Removal of the first region by means of electrochemical etching ECE (wet chemical etching).

[0036] Thus, ECE is used to selectively remove the at least one first region.

[0037] According to at least one embodiment, when the first conductivity type is p-type conductivity, the etching electrode is a cathode, or when the first conductivity type is n-type conductivity, the etching electrode is an anode. That is, if the first region is p-type conductivity, a negative voltage is applied to the semiconductor body, and correspondingly, if the first region is n-type conductivity, a positive voltage is applied to the semiconductor body.

[0038] According to at least one embodiment, the etching electrode is formed by at least a portion of a semiconductor substrate of a semiconductor body. For example, the portion is located on a side of the semiconductor body remote from a surface. For example, the surface is a top surface of the semiconductor body opposite the substrate. The top surface may be oriented perpendicular to a growth direction of an epitaxial layer of the semiconductor body.

[0039] According to at least one embodiment, the first region has a first doping concentration that is at least 10 times, or at least 10 times, higher than a second doping concentration of a material of the semiconductor body that is adjacent to the first region and is likewise of the first conductivity type. 2 times, or at least 100 times. Accordingly, the first region is also embedded in a semiconductor material of the first conductivity type, but with a lower doping concentration. Alternatively or additionally, the semiconductor body adjacent to the first region has a second conductivity type different from the first conductivity type. For example, in the latter case, the first region is n-doped and embedded in a p-doped region, or vice versa. The above two cases can be mixed.

[0040] According to at least one embodiment, the specific resistance of the first region is at most 10 Ωcm, or at most 1 Ωcm, or at most 0.1 Ωcm; the same may apply to the etching electrode. Accordingly, the first region can be considered conductive, as can the etching electrode. If the semiconductor material of the semiconductor body adjacent to the first region has the same first conductivity type, the specific resistance of the adjacent semiconductor material is, for example, greater than 10 Ωcm, or at least 0.1 kΩcm, or at least 1 kΩcm. The aforementioned values ​​may apply at room temperature, i.e., 293 K.

[0041] According to at least one embodiment, the etching electrode and the at least one first region are separated from each other. That is, the etching electrode and the at least one first region do not contact each other. For example, a non-conductive semiconductor material, i.e., a semiconductor material having a specific resistance greater than 10 Ωcm, or at least 0.1 kΩcm, or at least 1 kΩcm, may be present between the etching electrode and the at least one first region. The distance between the etching electrode and the at least one first region may be at least 1 μm, or at least 5 μm, or at least 40 μm.

[0042] According to at least one embodiment, the recess narrows monotonically or strictly monotonically in a direction away from the top side, as visible in a cross section perpendicular to the top side of the semiconductor body. "Monotonically" means that the thickness t at a position x is equal to or greater than the thickness t' at a position x+d further away from the top side: t(x)≥t'(x+d), where d is a distance greater than zero, d>0. Therefore, in the strictly monotonic case, t(x)>t'(x+d) applies. This applies to the actual sidewalls of the recess as well as to virtual sidewalls of the recess, visible in a cross section perpendicular to the top side of the recess and / or perpendicular to the main extension direction of the recess (the main extension direction is determined in a top view of the top side), the virtual sidewall being a best-fit straight line through the roughening of the actual sidewall.

[0043] According to at least one embodiment, the recess is formed without using reactive ion etching (RIE).

[0044] According to at least one embodiment, in step B), the first region is doped by means of ion implantation. Alternatively or additionally, in step B), the doping is performed by means of epitaxial growth.

[0045] According to at least one embodiment, the recess is a groove. For example, the aspect ratio of the maximum depth of the groove to the maximum width of the groove is at least 0.8, or at least 1, or at least 1.0, or at least 2. Alternatively or additionally, the aspect ratio is at most 20, or at most 10, or at most 5.

[0046] According to at least one embodiment, the method further comprises:

[0047] D) doping at least one second region of the second conductivity type in the semiconductor body, directly and exclusively, or at least on one side of the recess or on a side of the first region remote from the surface. The at least one second region can be remote from or directly located at the first region or the recess. Thus, the second region can be formed by doping before or after etching the recess.

[0048] According to at least one embodiment, the second region is configured as a shielding region. That is, the second region is highly doped and can be conductive. Regarding "conductive", see the definition provided above in the context of the first region.

[0049] According to at least one embodiment, the maximum depth of the recess is at least 1 μm, or at least 5 μm, or at least 15 μm. Alternatively or additionally, the maximum depth is at most 0.1 mm, or at most 50 μm, or at most 30 μm.

[0050] According to at least one embodiment, the maximum doping concentration of the first region is at least 10 18 cm -3 , or at least 5x10 18 cm-3 , or at least 1x 10 19 cm -3 Alternatively or additionally, the doping concentration is at most 10 21 cm -3 , or up to 5x 10 20 cm -3 .

[0051] According to at least one embodiment, the recess is formed in the epitaxially grown layers of the semiconductor body. When growing, all of the layers may be of the first conductivity type. For example, the doping concentration of the layers when growing is at most 10 16 cm -3 , or up to 5x 10 15 cm -3 Alternatively or additionally, the doping concentration is at least 5x10 14 cm -3 , or at least 1x 10 15 cm -3 .

[0052] According to at least one embodiment, after the recess is formed, the method further comprises:

[0053] E1) applying an electrically insulating film to the walls of the recess, and

[0054] E2) Providing a gate electrode in the recess.

[0055] Thus, the finished semiconductor device may include a gate electrode housed in the trench (ie, housed in the recess).

[0056] A semiconductor device is also provided. By means of the method, a semiconductor device can be produced as indicated in conjunction with at least one of the above embodiments. Therefore, for the method, the features of the semiconductor device are also disclosed, and vice versa.

[0057] In at least one embodiment, a semiconductor device includes a semiconductor body based on a Group IV semiconductor material (e.g., Si or SiC), and the semiconductor device is one of a metal-insulator-semiconductor field-effect transistor (MISFET), a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse-conducting insulated gate bipolar transistor (RC-IGBT). At least one recess is formed in the semiconductor body, and a root mean square (RMS) roughness of a bottom surface of the recess is at most 15 nm, or at most 10 nm, or at most 7 nm, and / or at least 1 nm, or at least 2 nm. A gate electrode is located in the at least one recess.

[0058] According to at least one embodiment, the semiconductor device is one of a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse conducting insulated gate bipolar transistor (RC-IGBT). BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The methods and semiconductor devices described herein are explained in more detail below by way of exemplary embodiments with reference to the accompanying drawings. Identical elements in the various figures are indicated by the same reference numerals. However, the relationships between the elements are not shown to scale, and individual elements may be shown exaggerated to aid understanding.

[0060] In the attached figure:

[0061] Figure 1 is a schematic block diagram of an exemplary embodiment of a method for producing a semiconductor device described herein,

[0062] Figures 2 to 6 is a schematic cross-sectional view of method steps of an exemplary embodiment of a method for producing a semiconductor device described herein,

[0063] Figure 7 is a schematic cross-sectional view of a bottom surface of a trench of an exemplary embodiment of a semiconductor device described herein,

[0064] Figures 8 to 12 is a schematic cross-sectional view of method steps of an exemplary embodiment of another method for producing a semiconductor device described herein,

[0065] Figure 13 and Figure 14 is a schematic cross-sectional view of method steps of an exemplary embodiment of another method for producing a semiconductor device described herein,

[0066] Figures 15 to 20 is a schematic cross-sectional view of method steps of an exemplary embodiment of another method for producing a semiconductor device described herein,

[0067] Figure 21 is a schematic cross-sectional view of an exemplary embodiment of a semiconductor device described herein,

[0068] Figure 22 is a schematic top view of various recesses for exemplary embodiments of semiconductor devices described herein, and

[0069] Figure 23 are schematic cross-sectional views of various recesses for exemplary embodiments of semiconductor devices described herein. DETAILED DESCRIPTION

[0070] exist Figure 1 In FIG. 1 , a block diagram of a method for producing a semiconductor device 1 is shown. In a first method step S1, a semiconductor body 2 is provided, see also below Figure 2 The semiconductor body 2 is based on a group IV semiconductor material, such as SiC or also Si.

[0071] In a subsequent method step S2, a first region 21 is defined by doping a portion of the semiconductor body 2, see also below. Figure 3 The first region 21 is of the first conductivity type and starts from the surface 20 of the semiconductor body 2 .

[0072] Then, in method step S3, the recess 3 is formed in the semiconductor body 2 by selective and wet-chemical etching of the first region 21, see also below. Figure 4 As an option, method step S3 may comprise or consist of two steps S31 and S32. In step S31, a potential is applied to the semiconductor body 2 so that the semiconductor body 2 or a part of the semiconductor body 2 serves as an etching electrode 41, as described below. Figure 4 In step S32, the first region 21 is removed by means of electrochemical etching ECE. Steps S31 and S32 can be performed simultaneously. ECE can be continuous etching or pulse etching.

[0073] As a further option, there is a subsequent method step S5 in which the gate electrode 44 is produced, in contrast to the following Figure 11 Step S5 may include step S51 and step S52. In step S51, an electrical insulating film 5 is applied to the wall and bottom surface of the recess 3. Thereafter, in step S52, a gate electrode material (such as polysilicon) is applied in the recess 3 to form a gate electrode.

[0074] As a further option, in step S4, a second region 22 of the second conductivity type is formed in the semiconductor body 2 by means of doping, for example directly on one side of the recess 3 or on the side of the first region 21 facing away from the surface 20, for example in contrast to the following Figure 6 and Figure 9 Step S4 may be performed, for example, between step S2 and step S3, or may be performed after step S3, such as between step S3 and step S5.

[0075] exist Figures 2 to 6 An example of this approach is described in more detail in . Figure 2In the embodiment, a semiconductor body 2 is provided. For example, the semiconductor body 2 comprises a semiconductor substrate 23, for example made of highly n-doped SiC. On the semiconductor substrate 23, a layer 29 is epitaxially grown. For example, the layer 29 is made of moderately n-doped SiC. The main side of the layer 29 facing away from the substrate 23 is the top side 20 and corresponds to the following example: Figure 1 Surface 20 mentioned.

[0076] Then, in Figure 3 In a step of forming the epitaxially grown layer 29, the first region 21 is applied. In cross section, the first region 21 may have a rectangular shape. Figure 3 The first region 21 may extend in a straight line relative to the drawing plane in FIG. 1 . The first region 21 terminates to be spaced apart from the substrate 23 .

[0077] For example, first region 21 is formed with a box-shaped profile using ion implantation. The term "box-shaped profile" may also be referred to as a multi-energy implantation profile. Thus, the doping concentration in first region 21 can be approximately constant, for example, between 0.5 and 2 times the average doping concentration, or between 0.75 and 1.3 times. Thus, first region 21 is conductive, but the remaining portion of epitaxial layer 29, which has the same conductivity type as first region 21 and has an exposed surface, is only semi-conductive. This allows only conductive material of the correct conductivity type to be etched with high selectivity through ECE.

[0078] exist Figure 4 , selective etching is performed. Thus, the first region 21 is placed in an etching liquid 62 in an etching tube 61 and exposed to the etching liquid. An external electrode 63 for etching is applied to the substrate 23, which serves as an etching electrode 41 of the semiconductor body 2, and a voltage is applied between the etching liquid 62 and the etching electrode 41. In the case of an n-type conductive first region, the etching electrode 41 is an anode, as shown in FIG. Figure 4 Schematically illustrated in FIG.

[0079] exist Figure 4 In FIG. 1 , the first region 21 is shown as being only partially removed because etching is still in progress, but after etching is complete, see FIG. Figure 5 , the first region 21 is completely removed. Therefore, the shape of the resulting recess 3 is determined by Figure 3 The shape of the doped region is defined in the step.

[0080] according to Figure 6 After forming the recess 3, a second region 22 of the second conductivity type may optionally be created. This is done, for example, by ion implantation through the recess 3. The recess 3 may be referred to as a trench, which is perpendicular to the Figure 6 The drawing plane is extended in .

[0081] Thus, for example, from a thickness of 10 μm to 100 μm and a doping concentration of 1 x 10 15 cm -3 to 1x 10 16 cm -3 The n-type 4H-SiC epitaxial layer 29 is implanted with N, P, B and / or Al to obtain an implantation doping concentration of about 1×10 18 cm -3 Up to 1x10 20 cm -3 The one or more implantation energies for producing the first region 21 are selected between 100 keV and 100 MeV to form a trench with a depth of, for example, 0.2 μm to 90 μm. For example, after the implantation, activation may be performed at about 1600° C. or about 1700° C. for 30 minutes. + or p + After the first region 21 , ECE is performed, and the trench 3 is formed by ECE.

[0082] The electric field limiting layer, ie the second region 22, can then be formed, for example, by ion beam technology: thus, starting from the n-type epitaxial layer 29, the p + or n + implanted and activated to produce the first region 21. Figures 2 to 6 For example, n + Implantation is performed in the first region 21. If the first region 21 is n + Type, you can inject p + After the dopant activation, the electric field limiting layer 22 is formed by ECE etching. + The first region 21, which will form the trench 3 and the exposed p at the bottom 71 + Region 22. Accordingly, the second region 22 can be formed after ECE (e.g. Figure 6 As shown), or it can also be formed before ECE.

[0083] Optionally, after trench ECE is performed in the n-type epitaxial layer 29, an energy of 5 keV to 10 keV and 10 15 cm -2 with 10 16 cm -2 Plasma immersion ion implantation of C is performed at room temperature with a dose between 100 and 100 Å. This will implant carbon atoms into the epitaxial layer 29 to remove carbon vacancies throughout the layer 29.

[0084] exist Figures 2 to 6In the figure, for simplicity, only one trench 3 is shown. On the contrary, there can of course be multiple trenches 3, and multiple semiconductor devices 1 can be produced simultaneously. Trenches 3 of different shapes (for example, different depths) can be produced simultaneously because etching automatically stops at the corresponding trench 3 when the designated first region 21 is completely removed. The same applies to all other examples.

[0085] In addition, with Figure 1 The same situation can also apply to Figures 2 to 6 ,vice versa.

[0086] It should be noted that Cl-based RIE for SiC etching results in surface roughness in the range of 60 nm to 70 nm, whereas ECE can achieve surface roughness of only 2 nm to 7 nm, see for example the references by HK Sung et al. and Y. Ke et al. mentioned above. Thus, ECE provides much better surface roughness and thus improved electrical performance. This is Figure 7 , in which the RMS value of the roughened portion 7 at the bottom surface 71 of the recess 3 is less than 10 nm.

[0087] In addition, with Figures 1 to 6 The same situation can also apply to Figure 7 ,vice versa.

[0088] exist Figures 8 to 12 Another example of this method is described in . Figure 8 In, similar to Figure 2 , providing a semiconductor body 2. Then, a first region 21 and a second region 22 are formed by ion implantation, wherein the first region 21 is n + type, and the second region 22 is p + Type, see Figure 9 .

[0089] according to Figure 10 , n + The first region 21 of the type is completely removed. The ECE is formed at p due to the applied voltage. + Type 2 automatically stops at 22, and n - The epitaxial layer 29 is not etched due to its insufficient conductivity.

[0090] Then, see Figure 11 An electrically insulating film 5 is applied to the walls of the trench 3 and also to the bottom 71 . Subsequently, a gate electrode 44 is applied in the remaining part of the trench 3 .

[0091] Finally, see Figure 12 , for example, by means of ion implantation to produce a p-type well region 25, p + Type plug area 27 and n +The type source region 26 is formed, thereby completing the semiconductor body 2.

[0092] Not shown in the figures, further electrodes, passivation and protection layers as well as bonding pads etc. can subsequently be produced.

[0093] Therefore, the above method can be used to manufacture SiC trench MOSFET. For example, first, provide + A SiC epitaxial layer 29 is grown on a substrate 29. For example, high-dose P and Al implants are performed in any order at 200°C to 600°C, followed by activation at a temperature above 1600°C to form the first region 21 and the second region 22. + Type 1 region 21 and p + After the second zone 22 is formed, ECE is performed, using only n + The polarity of the p-type injection region. + The type region will serve as the field limiting layer 22. Alternatively, it can be + Type 1 zone 21 ECE followed by p + In either case, the formation of p + After the second region is formed, C plasma ion implantation can be performed, for example, PIII, at 5keV to 30keV, with a dose of 10 12 cm -2 to 10 16 cm -2 In this way, the previously formed carbon vacancies can be removed. Thereafter, the trench is filled with SiO2 and then the gate electrode 44 is filled with polysilicon. Finally, regions 25, 26, 27 are formed.

[0094] In addition, with Figures 1 to 7 The same situation can also apply to Figures 8 to 12 ,vice versa.

[0095] By using the method described in this article using ECE followed by implantation, V-shaped trench MOSFETs can also be fabricated. Figure 13 and Figure 14 Starting from the 4H-SiC epitaxial layer 29, p + Type plug area 27, p + The p-type second region 22, the p-type well region 25 and the n-type + Type first zone 21. n + The first region 21 is formed by, for example, implanting N or P at an angle of 54.7° along the 0-33-8 plane of SiC. Figure 13 .

[0096] Afterwards, the n + Type first zone 21 (such as Figure 14Finally, n is formed by implantation and activation. + Type source region 26. Similar to Figure 11 , the trench 3 can then also be coated with SiO 2 and the gate electrode can be applied.

[0097] In addition, with Figures 1 to 12 The same situation can also apply to Figure 13 and Figure 14 ,vice versa.

[0098] Figures 15 to 20 Another example of this method is shown in FIG. Therefore, another possibility is to use Al or BPIII to form the channel without using ion implantation. + Type and p + Type injection, see Figure 15 The area 21a close to the top side 20 is p + type, while the deeper lower region 21b is n + type.

[0099] The ECE then proceeds to remove the p near the top side 20. + Type area 21a, see Figure 16 . After completion, for example, with 5keV to 30keV and 10 12 cm -2 to 10 14 cm -2 Perform Al PIII at a dose of Figure 17 As shown, see the arrow pointing to the wall of the trench 3. Afterwards, ECE is completed to remove the n + Type area 21b, see Figure 18 .

[0100] Then, a field limiting second region 22 is formed at the bottom surface 71 of the trench 3, see Figure 19 The trench 3 is also filled with oxide and polysilicon for the electrically insulating film 5 and the gate electrode 44, respectively.

[0101] Finally, p + type plug region 27, p-type well region 25 and n + Type source region 26, such as Figure 20 shown.

[0102] In addition, with Figures 1 to 14 The same situation can also apply to Figures 15 to 20 ,vice versa.

[0103] exist Figure 21, a finished semiconductor device 1 is schematically shown, wherein only one trench 3 is illustrated. As is possible in all other examples, regions 25, 26, 27, 28 may be arranged on both sides of the trench 3.

[0104] according to Figure 20 The semiconductor device 1 is an insulated gate bipolar transistor IGBT, or a metal-insulator-semiconductor field effect transistor MISFET or a metal-oxide-semiconductor field effect transistor MOSFET. In the case of an IGBT, the region 25 is a well region. In the well region 25, there is a p + Plug area 27, the p + The plug region is located at the first electrode 42, which is an emitter electrode. Further, in the well region 25, there is an n-type electrode configured as an emitter region. + Zone 26. Therefore, zone 24 is n - The doping concentration of the drift layer 24 is, for example, about 2×10 14 cm -3 .

[0105] As an option, there is a further layer 284 of the semiconductor body 2 below the drift region 24, which further layer can be a buffer region. For example, the buffer region 284 is n-doped with a maximum doping concentration of approximately 1 x 10 18 cm -3 For example, the thickness of the buffer region 284 may be between 2 μm and 10 μm (inclusive).

[0106] Another region 28 of the semiconductor body 2 is located on the side of the drift region 24 away from the top side 20 or on the side of the buffer region 284 away from the top side 20. The other region 28 is a collector region having the same conductivity type as the plug region 27. The doping concentration of the collector region 28 is, for example, approximately 1×10 19 cm -3 The second electrode 43 at the collector region 28 is a collector electrode.

[0107] Similarly, the semiconductor device 1 may be a MISFET or a MOSFET. In this case, the region 284 may be omitted, and the region 28 is an n-type doped drain region with a maximum doping concentration of, for example, at least 1 x 10 18 cm -3 , or at least 5x 10 18 cm -3 , or at least 1x 10 19 cm -3 , and / or up to 5x 10 20 cm -3 , or up to 2x 10 20 cm -3 , or up to 1x 1020 cm -3 In this case, the region 26 is a source region, and the first electrode 42 and the second electrode 43 are the source and the drain, respectively.

[0108] In addition, with Figures 1 to 20 The same situation can also apply to Figure 21 ,vice versa.

[0109] exist Figure 22 In FIG, it is shown that various geometric shapes of the recess 3 can be achieved by means of doping the first region 21, as can be seen in a top view. For example, as can be seen in a top view, the recess 3 has a square, rectangular, triangular, trapezoidal, pentagonal, hexagonal, octagonal or polygonal shape, or can even be shaped as a cross. Although in FIG. Figure 22 Regular triangles, pentagons, hexagons, octagons, and polygons are shown in FIG, but irregular shapes with different angles at the corners can also be used. For example, Figure 22 Any combination of the shapes shown in .

[0110] Accordingly, the control Figure 23 By means of doping the first region 21 and subsequent ECE, the resulting recess can have different cross-sectional shapes. Figure 22 , in the same semiconductor device 1, any combination of shapes is possible.

[0111] For example, the recess can have a symmetrical or asymmetrical trapezoidal shape that widens or narrows toward the top side 20, a triangular shape, a square shape, a rectangular shape, or a pentagonal shape with the tip pointing away from the top side, as seen in cross section. Furthermore, sharp and rounded corners are also possible. Furthermore, a U-shaped groove 3 with a curved bottom surface 71 is also possible.

[0112] In addition, with Figures 1 to 21 The same situation can also apply to Figure 22 and Figure 23 ,vice versa.

[0113] Unless otherwise indicated, components shown in the figures are illustratively positioned directly above one another in a particular order. Components that are not in contact in the figures are illustratively spaced apart from one another. If lines are drawn parallel to one another, the corresponding surfaces may be oriented parallel to one another. Similarly, unless otherwise indicated, the positions of the components drawn relative to one another are accurately reproduced in the figures.

[0114] The invention described herein is not restricted to the description based on the exemplary embodiments. On the contrary, the invention covers any novel feature and any combination of features, in particular including any combination of features in the patent claims, even if this feature or this combination itself is not explicitly specified in the patent claims or the exemplary embodiments.

[0115] European Patent Application 23164334.7 from which this patent application claims priority, the disclosure content of which is incorporated herein by reference.

[0116] List of Reference Numerals

[0117] 1. Semiconductor devices

[0118] 2 Semiconductor body

[0119] 20 Surface (top side)

[0120] 21. First area (etching limit area)

[0121] 22. Second Zone (Shielded Zone)

[0122] 23 Semiconductor substrate

[0123] 24 Drift Zone

[0124] 25-well region

[0125] 26 Source region / Emitter region

[0126] 27 Plug Area

[0127] 28 Drain region / Collector region

[0128] 284 Buffer

[0129] 29 Epitaxial growth layer

[0130] 3 recess (groove)

[0131] 41 Etched Electrode

[0132] 42 first electrode (source electrode, emitter electrode)

[0133] 43 Second electrode (drain electrode, collector electrode)

[0134] 44 gate electrode

[0135] 5 Electrical insulating film

[0136] 61 Etched Tube

[0137] 62 Etching Liquid

[0138] 62 External electrodes for etching

[0139] 7 Roughened area

[0140] 71 Bottom of recess

[0141] S.. Method Steps

Claims

1. A method for producing a semiconductor device (1), wherein the semiconductor device is one of a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse conducting insulated gate bipolar transistor (RC-IGBT), the method comprising: A) providing a semiconductor body (2) based on a Group IV semiconductor material, B) doping a first region (21) in the semiconductor body (2), the first region (21) being of a first conductivity type and starting from a surface (20) of the semiconductor body (2), and C) forming a recess (3) in the semiconductor body (2) by selectively and wet-chemically etching the first region (21).

2. The method according to the preceding claim, in, The method further comprises: D) doping a second region (22) of a second conductivity type in the semiconductor body (2) directly on a side of the first region (21) remote from the surface (20), wherein the etching in step C) automatically stops at the second region (22), so that after step C), the second region (22) is directly located at a bottom surface (71) of the recess (3) remote from the surface (20) of the semiconductor body (2), the root mean square (RMS) roughness of the bottom surface (31) being at most 15 nm, and The second region (22) is configured as a shielding region in the finished semiconductor device (1).

3. A method according to any one of the preceding claims, wherein Step B) comprises: B1) applying an electrical potential to the semiconductor body (2) so that the semiconductor body (2) serves as an etching electrode (41), and B2) removing the first region (21) by means of electrochemical etching ECE, Wherein, when the first conductive type is p-type conductive, the etching electrode (41) is a cathode, or when the first conductive type is n-type conductive, the etching electrode (41) is an anode, and Wherein, the Group IV semiconductor material is SiC.

4. The method according to the preceding claim, in, The etching electrode (41) is formed by a portion of the semiconductor substrate (23) of the semiconductor body (2), the portion being located on a side of the semiconductor body (2) remote from the surface (20).

5. A method according to any one of the preceding claims, wherein One or both of the following apply: The first region (21) has a first doping concentration which is at least 10 times greater than a second doping concentration of the semiconductor body (2) which is adjacent to the first region (21) and is also of the first conductivity type. 2 times, or The semiconductor body (2) adjacent to the first region (21) has a second conductivity type different from the first conductivity type.

6. The method according to any one of the preceding claims, in, In a section perpendicular to the top side (20) of the semiconductor body (2), it can be seen that the recess (3) narrows monotonically or strictly monotonically in a direction away from the top side (20).

7. The method according to any one of the preceding claims, in, The recess (3) is formed without using reactive ion etching (RIE).

8. The method according to any one of the preceding claims, in, In step B), the first region (21) is doped by means of at least one of ion implantation or epitaxial growth.

9. The method according to any one of the preceding claims, in, The recess (3) is a groove, The aspect ratio of the maximum depth of the groove to the maximum width of the groove is at least 1 and at most 10.

10. The method according to any one of the preceding claims, in, - the maximum depth of the recess (3) is at least 5 μm and at most 50 μm, - the maximum doping concentration of the first region (21) is at least 10 18 cm -3 and at most 10 21 cm -3 .

11. The method according to any one of the preceding claims, in, The recess (3) is formed in an epitaxial growth layer (29) of the semiconductor body (2), the epitaxial growth layer being of the first conductivity type and having a doping concentration of at most 10 16 cm -3 .

12. The method according to any one of the preceding claims, in, After forming the recess (3), the method further comprises: E1) applying an electrically insulating film (5) to the walls of the recess (3), and E2) Providing a gate electrode (44) in the recess (3).

13. A semiconductor device (1), comprising a semiconductor body (2) based on a Group IV semiconductor material, wherein the semiconductor device is one of a metal-insulator-semiconductor field effect transistor (MISFET), a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a reverse conducting insulated gate bipolar transistor (RC-IGBT), in, A recess (3) is formed in the semiconductor body (2), and a bottom surface (71) of the recess (3) has a root mean square (RMS) roughness of at most 15 nm, and The gate electrode (44) is located in the recess (3).

14. Semiconductor device (1) according to the preceding claim, The semiconductor device is produced by the method according to any one of claims 1 to 12, and in, The Group IV semiconductor material is SiC.

15. Semiconductor device (1) according to any of the two preceding claims, in, In the semiconductor body (2), directly on the side of the recess (3) facing away from the surface (20) of the semiconductor body (2), there is a second region (22) of a second conductivity type, which is different from the first conductivity type, and the second region (22) is configured as a shielding region.

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