Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer; a connecting member embedded in the insulating layer; and an electrode portion embedded in the insulating layer and overlapping the connecting member in a vertical direction, in which the connecting member includes an electrode pattern disposed on the connecting member, and the electrode pattern is electrically floating with respect to the electrode portion.

Description

Technical Field

[0001] Embodiments relate to a semiconductor package, and more particularly, to a semiconductor package having improved bonding strength between an insulating substrate and a connection member. Background Art

[0002] As the performance of electrical and electronic products improves, technologies for arranging more semiconductor devices on a semiconductor package substrate of limited size are being proposed and studied. However, since general semiconductor packages are based on mounting a single semiconductor device, there are limitations in achieving the desired performance.

[0003] Therefore, a semiconductor package has recently been provided that uses multiple circuit boards to mount multiple semiconductor devices. This semiconductor package has a structure in which multiple semiconductor devices are connected to each other horizontally and / or vertically on the circuit board. Consequently, the semiconductor package has the advantages of efficiently utilizing the mounting area of ​​the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Due to these advantages, the semiconductor package as described above is widely used in mobile devices and the like.

[0005] In addition, as the number of semiconductor devices and / or the size of each semiconductor device increases according to the trend of high integration, or as the functional parts of semiconductor devices are divided, semiconductor packaging used in products that provide the Internet of Things (IoT), autonomous vehicles, and high-performance servers will expand the concept to semiconductor small chips (chiplets).

[0006] Therefore, mutual communication between semiconductor devices and / or semiconductor chiplets has become important, and thus, there is a trend to provide an interposer between a circuit board of a semiconductor package and the semiconductor device.

[0007] The interposer may be used as a redistribution layer that gradually increases the width or depth of a circuit pattern from a semiconductor device to a semiconductor package to facilitate mutual communication between semiconductor devices and / or semiconductor chiplets, or interconnect a semiconductor device and a semiconductor package circuit board, thereby smoothly transmitting electrical signals between the semiconductor device and the semiconductor package circuit board, which has a relatively large circuit pattern compared to the circuit pattern of the semiconductor device.

[0008] The packaging circuit board and / or interposer used in semiconductor packaging is also provided with a connecting member connected to the semiconductor device and / or semiconductor chiplet. The connecting member is used to horizontally connect multiple semiconductor devices and / or semiconductor chiplets. Therefore, the connecting member can be embedded in the packaging circuit board and / or interposer.

[0009] At this time, the connecting member can be an inorganic bridge or an organic bridge. In addition, the electrodes provided in the connecting member can have a smaller width and / or spacing than the electrodes provided in the packaging substrate and / or the interposer. For example, the connecting member includes a high-density electrode. Therefore, the surface roughness of the electrode provided in the connecting member can have a relatively small value. That is, as the surface roughness of the electrode increases, it may be difficult to refine the line width or spacing of the electrode. Therefore, if the connecting member is embedded in the packaging substrate and / or the interposer, the adhesion between the connecting member and the packaging substrate and / or the interposer may be reduced. Therefore, the problem of the connecting member peeling off from the packaging substrate and / or the interposer may occur. Summary of the Invention

[0010]

Technical Issues

[0011] Embodiments provide a semiconductor package having a novel structure.

[0012] In addition, embodiments provide a semiconductor package including a substrate and a connection member embedded in the substrate.

[0013] In addition, embodiments provide a semiconductor package having improved mechanical and electrical reliability.

[0014] In addition, the embodiment provides a semiconductor package capable of improving adhesion between a substrate and a connection member.

[0015] In addition, embodiments provide a semiconductor package capable of preventing a substrate and / or a connection member from being greatly bent in a specific direction.

[0016] The technical problems to be solved by the proposed implementations are not limited to the above-mentioned technical problems, and those skilled in the art to which the implementations proposed in the following description belong can clearly understand other technical problems not mentioned.

[0017]

Technical solution

[0018] According to an embodiment, a circuit board includes an insulating layer; a connecting member embedded in the insulating layer; and an electrode portion, which is embedded in the insulating layer and overlaps with the connecting member in a vertical direction, wherein the connecting member includes an electrode pattern provided on the connecting member, and wherein the electrode pattern is electrically floating relative to the electrode portion.

[0019] In addition, the connecting member includes a first connecting electrode and a second connecting electrode spaced apart from the electrode pattern in a horizontal direction, the electrode portion includes a first electrode portion and a second electrode portion, the first electrode portion overlaps with the first connecting electrode in a vertical direction, the second electrode portion overlaps with the second connecting electrode in a vertical direction, and the electrode pattern is electrically floating relative to the first electrode portion, the second electrode portion, the first connecting electrode, and the second connecting electrode.

[0020] In addition, the insulating layer includes a first insulating layer having a cavity; and a second insulating layer arranged on the first insulating layer and filling at least a portion of the cavity, and the connecting member is arranged in the cavity, the first electrode portion includes a first through electrode and a second through electrode, the first through electrode penetrates at least a portion of the second insulating layer and overlaps with the first connecting electrode in the vertical direction, the second through electrode penetrates at least a portion of the second insulating layer and overlaps with the first connecting electrode in the vertical direction, and the electrode pattern does not overlap with the first through electrode and the second through electrode in the vertical direction.

[0021] In addition, the first electrode portion includes a first wiring electrode provided on the first through-electrode and a second wiring electrode provided on the second through-electrode, and the electrode pattern does not overlap with the first wiring electrode and the second wiring electrode in a vertical direction.

[0022] In addition, the electrode pattern is provided on the upper surface of the connection member in the same plane as the first connection electrode and the second connection electrode.

[0023] In addition, the surface roughness value of the electrode pattern is greater than the surface roughness value of at least one of the first connection electrode and the second connection electrode.

[0024] In addition, each of the first connection electrode and the second connection electrode is provided in plural, and a plane area of ​​a single electrode pattern is larger than a plane area of ​​a single electrode of each of the plurality of first connection electrodes and the second connection electrodes.

[0025] In addition, an edge shape of an upper surface of each of the first and second connection electrodes is identical to each other, and an edge shape of an upper surface of the electrode pattern is different from an edge shape of the first and second connection electrodes.

[0026] In addition, the circuit board also includes a dummy through-electrode and a dummy wiring electrode. The dummy through-electrode is arranged on the electrode pattern and overlaps with at least a portion of the first through-electrode and the second through-electrode in the horizontal direction. The dummy wiring electrode is arranged on the dummy through-electrode and overlaps with the first wiring electrode and the second wiring electrode in the horizontal direction.

[0027] In addition, the circuit board also includes a protective layer arranged on the insulating layer; and a first protruding electrode, which penetrates at least a portion of the protective layer and overlaps with the first wiring electrode in the vertical direction; a second protruding electrode, which penetrates at least a portion of the protective layer and overlaps with the second wiring electrode in the vertical direction; and a dummy protruding electrode, which penetrates at least a portion of the protective layer and overlaps with the dummy wiring electrode in the vertical direction.

[0028] Meanwhile, a semiconductor package according to an embodiment includes a circuit board and a semiconductor device arranged on the circuit board, the semiconductor device including a first semiconductor device and a second semiconductor device spaced apart in a horizontal direction on the circuit board, and an electrode pattern overlaps with a separation area between the first semiconductor device and the second semiconductor device in a vertical direction.

[0029] In addition, the first semiconductor device includes a first terminal overlapping with the first connection electrode in the vertical direction, and the second semiconductor device includes a second terminal overlapping with the second connection electrode in the vertical direction.

[0030] In addition, at least a portion of the electrode pattern does not vertically overlap the first semiconductor device and the second semiconductor device.

[0031] In addition, the electrode pattern is electrically floated with respect to the first and second terminals of the first and second semiconductor devices.

[0032] In addition, a lower surface of each of the first and second through electrodes is positioned lower than an upper surface of the connection member, and the electrode pattern is provided on the upper surface of the connection member to overlap with the first and second through electrodes in a horizontal direction.

[0033] In addition, each of the first and second connection electrodes is provided in plurality, and each of the plurality of first and second connection electrodes is spaced apart from each other on the connection member with a dummy region interposed therebetween, and the electrode pattern is provided in the dummy region of the connection member.

[0034] In addition, the width of the dummy region in the horizontal direction satisfies the range of 160 μm to 310 μm.

[0035] In addition, a first terminal among the multiple first terminals that is located closest to an edge of a surface of the first semiconductor device is spaced apart from the edge of the surface of the first semiconductor device in a range of 40 μm to 80 μm, and a second terminal among the multiple second terminals that is located closest to an edge of a surface of the second semiconductor device is spaced apart from the edge of the surface of the second semiconductor device in a range of 40 μm to 80 μm.

[0036] In addition, the first semiconductor device and the second semiconductor device include side portions horizontally facing each other, and a horizontal distance between the side portions satisfies a range of 80 μm to 150 μm.

[0037] In addition, a horizontal distance between a first terminal and a second terminal that are disposed closest to each other among the plurality of first terminals and the plurality of second terminals satisfies a range of 160 μm to 310 μm.

[0038] In addition, the semiconductor package also includes a third semiconductor device, which is arranged on the circuit board and vertically overlaps with at least a portion of the connecting member, and the electrode pattern includes a first dummy electrode pattern and a second dummy electrode pattern, the first dummy electrode pattern vertically overlaps with the separation area between the first semiconductor device and the second semiconductor device, and the second dummy electrode pattern is arranged in an area vertically overlapping with the separation area between the first semiconductor device or the second semiconductor device and the third semiconductor device.

[0039] Beneficial effects

[0040] A semiconductor package of an embodiment may include an insulating layer and a connecting member embedded in the insulating layer. The connecting member may include a first connecting electrode and a second connecting electrode. In addition, the semiconductor package may include a first electrode portion and a second electrode portion disposed in the insulating layer. The first electrode portion may vertically overlap with the first connecting electrode of the connecting member. In addition, the second electrode portion may vertically overlap with the second connecting electrode of the connecting member. In addition, the electrode portion may further include a third electrode portion disposed between the first electrode portion and the second electrode portion or between the first connecting electrode and the second connecting electrode. The third electrode portion may be electrically floating relative to the connecting member and may physically contact the connecting member. The third electrode portion may be disposed in an area of ​​the upper surface of the connecting member where no connecting electrode is disposed. The third electrode portion may improve adhesion between the insulating layer and the connecting member.

[0041] Thus, the embodiment can increase the adhesion between the insulating layer and the connection member, thereby solving the problem of the connection member being peeled off from the insulating layer.

[0042] Furthermore, embodiments can improve the mechanical reliability of the semiconductor package by increasing the rigidity of the connecting member and / or the rigidity of the semiconductor package using the third electrode portion. Thus, embodiments can address the problem of significant bending of the connecting member and / or the semiconductor package in a particular direction. Thus, embodiments can enable the semiconductor package to operate stably. Furthermore, embodiments can enable smooth operation of electronic products and / or servers employing the semiconductor package.

[0043] Additionally, the surface roughness of the third electrode portion can be greater than the surface roughness of the connection electrode disposed in the connection member. Thus, by ensuring that the surface roughness of the connection electrode is less than that of the third electrode portion, embodiments minimize signal transmission loss, which increases proportionally with increasing surface roughness, thereby improving the signal transmission characteristics of the semiconductor package. Furthermore, embodiments can further improve the adhesion between the insulating layer and the connection member without compromising signal transmission characteristics by increasing the surface roughness of the dummy electrode.

[0044] Meanwhile, the dummy electrode in one embodiment may comprise only a dummy electrode pattern provided on the connecting member. In another embodiment, the dummy electrode may comprise a dummy through-electrode extending from the upper surface of the first insulating layer to a portion of the first insulating layer, and a dummy electrode pattern. In another embodiment, the third electrode portion may comprise a dummy through-electrode and a dummy protruding electrode, as well as a dummy electrode pattern. Furthermore, when the third electrode portion comprises a dummy through-electrode and a dummy protruding electrode, the adhesion between the connecting member and the insulating layer can be further improved, while further enhancing the rigidity of the semiconductor package. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0046] Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0047] Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0048] Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0049] Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0050] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0051] Figure 3 It is viewed from above Figure 2 A plan view of the circuit board.

[0052] Figure 4 is included Figure 2 A cross-sectional view of a semiconductor package on a circuit board.

[0053] Figure 5 yes Figure 4 A magnified view of a local area.

[0054] Figure 6 is embedded in the Figure 2 A plan view of a connecting member in a circuit board.

[0055] Figure 7 is a plan view of a connection member including a dummy electrode provided on the connection member according to the first embodiment.

[0056] Figure 8 It shows Figure 7 Cross-sectional view of the surface roughness of the connecting electrode and the dummy electrode.

[0057] Figure 9 is a plan view of a connection member including a dummy electrode provided in the connection member according to the second embodiment.

[0058] Figure 10 is a plan view of a connection member including a dummy electrode provided in the connection member according to a third embodiment.

[0059] Figure 11 is a plan view of a connection member including a dummy electrode provided therein according to a fourth embodiment.

[0060] Figure 12 is a diagram illustrating a detailed layer structure of a connection member according to one embodiment.

[0061] Figure 13 It is shown that the Figure 2 Cross-sectional view of the detailed layer structure of the protruding electrodes in the circuit board.

[0062] Figure 14 is a cross-sectional view showing a circuit board according to a second embodiment.

[0063] Figure 15 is a cross-sectional view showing a circuit board according to a third embodiment.

[0064] Figure 16 is a cross-sectional view showing a circuit board according to a fourth embodiment. DETAILED DESCRIPTION

[0065] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, wherein the same figure numerals are used to represent the same or similar elements, and their redundant descriptions will be omitted. The suffixes "module" and "part" of the components used in the following description are given or mixed only in consideration of the ease of preparing the specification, and there is no meaning or function that distinguishes one from another. In addition, in the following description of the embodiments of the present invention, when it is determined that the relevant technology may make the subject of the embodiments disclosed herein difficult to understand, its detailed description will be omitted. In addition, the drawings are included to provide a further understanding of the present invention, and the drawings are incorporated into and constitute a part of this specification, and it should be understood that the present invention is intended to cover all modifications, equivalents or alternatives that fall within the spirit and scope of the present invention.

[0066] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the elements are not limited by these terms. These terms are only used to distinguish one component from another.

[0067] When a component is referred to as being “connected” or “in contact with” another component, it may be directly connected or joined to the other component, but it should be understood that other components may exist between them. When a component is referred to as being “directly connected” or “directly in contact with” another component, it should be understood that other components may not exist between them.

[0068] A singular expression includes a plural expression unless the context clearly implies otherwise.

[0069] In this application, terms such as "include" or "have" are used to specify the presence of features, numbers, steps, operations, components, parts or their combinations described in the specification; however, it should be understood that these terms do not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts or their combinations.

[0070] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0071] -Electronic devices-

[0072] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments is applied will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiments. Various semiconductor devices can be mounted on the semiconductor package.

[0073] Semiconductor devices may include active devices and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs) in which hundreds to millions of devices are integrated into a single semiconductor device. Semiconductor devices may include logic chips, memory chips, and the like. Logic chips may include central processing units (CPUs), graphics processing units (GPUs), and the like. For example, a logic chip may include an application processor (AP) chip that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, an analog-to-digital converter, an application-specific integrated circuit (ASIC), and the like, or a chipset that includes a specific combination of those listed thus far.

[0074] The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), or a flash memory.

[0075] On the other hand, the product group of the semiconductor package to which the embodiment is applied may be any one of CSP (chip scale package), FC-CSP (flip chip - chip scale package), FC-BGA (flip chip ball grid array), POP (stacked package) and SIP (system in package), but is not limited thereto.

[0076] In addition, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and any other electronic device that processes data may be used in addition to these.

[0077] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package of the embodiment may have various package structures including a circuit board to be described later.

[0078] In addition, the circuit board in one embodiment may be the first circuit board described below.

[0079] Alternatively, the circuit board in another embodiment may be the second circuit board described below.

[0080] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1eis a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0081] refer to Figure 1a , the semiconductor package according to the first embodiment may include a first circuit board 1100 , a second circuit board 1200 and a semiconductor device 1300 .

[0082] The first circuit board 1100 may represent a package circuit board.

[0083] For example, the first circuit board 1100 may provide a space for coupling at least one external circuit board. The external circuit board may refer to the second circuit board 1200 coupled to the first circuit board 1100. In addition, the external circuit board may refer to a main board included in the electronic device coupled to the lower portion of the first circuit board 1100.

[0084] In addition, although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

[0085] The first circuit board 1100 may include at least one insulating layer, and an electrode portion disposed on the at least one insulating layer.

[0086] The second circuit board 1200 may be disposed on the first circuit board 1100 .

[0087] The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space for mounting at least one semiconductor device. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space for mounting a first semiconductor device 1310 and a second semiconductor device 1320. The second circuit board 1200 may electrically connect the first and second semiconductor devices 1310 and 1320 to the first circuit board 1100 while also electrically connecting the first and second semiconductor devices 1310 and 1320. In other words, the second circuit board 1200 may perform both a horizontal connection function between multiple semiconductor devices and a vertical connection function between the semiconductor devices and the package circuit board.

[0088] Figure 1a The first semiconductor device 1310 and the second semiconductor device 1320 are shown to be disposed on the second circuit board 1200, but are not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor devices may be disposed.

[0089] The second circuit board 1200 may be disposed between the at least one semiconductor device 1300 and the first circuit board 1100 .

[0090] In one embodiment, the second circuit board 1200 may be an active interposer used as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the semiconductor package of the embodiment may have a structure vertically stacked on the first circuit board 1100, and may have the functions of multiple logic chips. Having the function of a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may have the function of an active device. In addition, the active interposer may perform the functions of the corresponding logic chip while performing the signal transmission function between the second logic chip provided thereon and the first circuit board 1100.

[0091] According to another embodiment, the second circuit board 1200 may be a passive interposer. For example, the second circuit board 1200 may serve as a signal relay between the semiconductor device 1300 and the first circuit board 1100 and may also function as a passive component such as a resistor, capacitor, or inductor. For example, due to 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals in the semiconductor device 1300 is gradually increasing. Specifically, the number of terminals provided in the semiconductor device 1300 is increasing, thereby reducing the width of the terminals or the spacing between the multiple terminals. In this case, the first circuit board 1100 may be connected to the main board of the electronic device. However, in order to ensure that the electrodes provided on the first circuit board 1100 have a width and spacing sufficient to connect to the semiconductor device 1300 and the main board, respectively, the thickness of the first circuit board 1100 increases or the layer structure of the first circuit board 1100 becomes complex. Therefore, in the first embodiment, the second circuit board 1200 may be provided on the first circuit board 1100 and the semiconductor device 1300. In addition, the second circuit board 1200 may include electrodes having fine widths and intervals corresponding to the terminals of the semiconductor device 1300 .

[0092] The semiconductor device 1300 may be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, or an analog-to-digital converter, an application-specific integrated circuit (ASIC), or the like, or a chipset including a specific combination of those listed so far. The memory chip may be a stacked memory such as HBM. The memory chip may also include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, or the like.

[0093] Meanwhile, the semiconductor package of the first embodiment may include a connection portion.

[0094] For example, the semiconductor package may include a first connection portion 1410 disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 may couple the second circuit board 1200 while electrically connecting them to the first circuit board 1100.

[0095] For example, the semiconductor package may include a second connection portion 1420 disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 may couple the semiconductor device 1300 while electrically connecting them to the second circuit board 1200.

[0096] The semiconductor package may include a third connection portion 1430 provided on a lower surface of the first circuit board 1100. The third connection portion 1430 may couple the first circuit board 1100 while electrically connecting them to the main board.

[0097] At this time, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 can electrically connect multiple components using at least one bonding method selected from wire bonding, solder bonding, and direct metal bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 have the function of electrically connecting multiple components, when direct metal bonding is used, the connection portion of the semiconductor package can be understood as an electrical connection portion, rather than solder or wire.

[0098] Wire bonding methods may refer to electrically connecting multiple components using wires such as gold (Au). Furthermore, solder bonding methods may use a material containing at least one of Sn, Ag, and Cu to electrically connect multiple components. Furthermore, direct metal bonding methods may refer to recrystallization by applying heat and pressure between multiple components in the absence of solder, wires, conductive adhesives, etc. Furthermore, it may refer to direct bonding between multiple components. Furthermore, direct metal bonding methods may refer to bonding methods achieved through second connection portion 1420. In this case, second connection portion 1420 may represent a metal layer formed by recrystallization between multiple components.

[0099] Specifically, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 may couple the plurality of components to each other through a thermal compression (TC) bonding method. Thermocompression bonding may refer to a method of directly coupling the plurality of components by applying heat and pressure to the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430.

[0100] At this time, in at least one of the first circuit board 1100 and the second circuit board 1200, the electrodes on which the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are provided may be provided with protrusions protruding outward from the insulating layer of the corresponding circuit board. The protrusions may protrude outward from the first circuit board 1100 or the second circuit board 1200.

[0101] The protrusion may be a bump. The protrusion may be a pillar. The protrusion may be referred to as a pillar. Preferably, the protrusion may refer to an electrode on the second circuit board 1200 on which the second connection portion 1420 for coupling with the semiconductor device 1300 is provided. That is, as the pitch of the terminals of the semiconductor device 1300 becomes finer, a short circuit may occur between the multiple second connection portions 1420 respectively connected to the multiple terminals of the semiconductor device 1300 via a conductive adhesive such as solder. Therefore, in an embodiment, thermocompression bonding may be performed to reduce the volume of the second connection portion 1420. In addition, in order to ensure diffusion prevention and alignment to prevent the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the interposer and / or the circuit board, the protrusion may be included in the electrode on the second circuit board 1200 on which the second connection portion 1420 is provided.

[0102] In addition, the semiconductor package may include a connection member 1210 .

[0103] The connecting member may be referred to as a bridge circuit board. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may function to electrically connect multiple semiconductor devices horizontally to one another. For example, because the area required by semiconductor devices is generally too large, the connecting member 1210 may include a redistribution layer. Because semiconductor packages and semiconductor devices differ significantly in terms of circuit pattern width or spacing, a buffering effect of the circuit pattern is required for electrical connection. The buffering effect may refer to having a dimension between the width or spacing of the circuit pattern of the semiconductor package and the width or spacing of the circuit pattern of the semiconductor device, and the redistribution layer may include a function of performing the buffering effect.

[0104] In one embodiment, the connection member 1210 may be an inorganic bridge. As an example, the inorganic bridge may include a silicon bridge. That is, the connection member 1210 may include a silicon circuit board and a redistribution layer disposed on the silicon circuit board.

[0105] In another embodiment, the connecting member 1210 may be an organic material bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic circuit board containing an organic material, rather than a silicon circuit board. The connecting member 1210 may be embedded in the second circuit board 1200.

[0106] To this end, the second circuit board 1200 may include a cavity, and the connection member 1210 may be disposed in the cavity of the second circuit board 1200. The connection member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200.

[0107] refer to Figure 1b , the semiconductor package according to the second embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the second embodiment may have a structure in which the first circuit board 1100 is removed, compared with the semiconductor package of the first embodiment.

[0108] That is, the second circuit board 1200 of the second embodiment may be used as a package circuit board while performing the interposer function.

[0109] The first connection portion 1410 provided on the lower surface of the second circuit board 1200 may couple the second circuit board 1200 to a main board of the electronic device.

[0110] refer to Figure 1c , the semiconductor package according to the third embodiment may include a first circuit board 1100 and a semiconductor device 1300 .

[0111] In this case, the semiconductor package of the third embodiment may have a structure in which the second circuit board 1200 is omitted, compared with the semiconductor package of the first embodiment.

[0112] That is, the first circuit board 1100 of the third embodiment can function as a packaging circuit board while also performing the function of connecting the semiconductor device 1300 and the main board. To this end, the first circuit board 1100 can include a connecting member 1110 for connecting multiple semiconductor devices. The connecting member 1110 can be an inorganic bridge or an organic material bridge that connects the multiple semiconductor devices.

[0113] refer to Figure 1d Compared with the semiconductor package of the third embodiment, the semiconductor package of the fourth embodiment may further include a third semiconductor device 1330 .

[0114] To this end, the fourth connection portion 1440 may be provided on the lower surface of the first circuit board 1100 .

[0115] The third semiconductor device 1330 may be disposed on the fourth connection portion 1400. That is, the semiconductor package of the fourth embodiment may have a structure in which semiconductor devices are mounted on upper and lower sides, respectively.

[0116] In this case, the third semiconductor device 1330 may have a Figure 1bThe structure on the lower surface of the second circuit board 1200 in the semiconductor package.

[0117] refer to Figure 1e The semiconductor package according to the fifth embodiment may include a first circuit board 1100. A first semiconductor device 1310 and a second semiconductor device 1320 may be provided on the first circuit board 1100. To this end, a first connection portion 1410 may be provided between the first circuit board 1100 and the first and second semiconductor devices 1310 and 1320.

[0118] The connection member 1110 may be embedded in the first circuit board 1110. The connection member 1110 may horizontally connect the first semiconductor device 1310 and the second semiconductor device 1320.

[0119] In addition, the first circuit board 1100 may include a conductive coupling portion 1450. The conductive coupling portion 1450 may also protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive coupling portion 1450 may be referred to as a bump, or alternatively, a pillar. The conductive coupling portion 1450 may be provided as a protruding structure on the electrode provided on the uppermost side of the first circuit board 1100.

[0120] The third semiconductor device 1330 may be provided on the conductive coupling portion 1450. In this case, the third semiconductor device 1330 may be connected to the first circuit board 1100 through the conductive coupling portion 1450. In addition, the second connection portion 1420 may be provided between the first and second semiconductor devices 1310 and 1320 and the third semiconductor device 1330.

[0121] Thus, the third semiconductor device 1330 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420 .

[0122] That is, the third semiconductor device 1330 may be connected to the first circuit board 1100 through the conductive coupling portion 1450 , and may also be connected to the first and second semiconductor devices 1310 and 1320 through the second connection portion 1420 .

[0123] In this case, the third semiconductor device 1330 may receive a power signal and / or electric power through the conductive coupling portion 1450 . In addition, the third semiconductor device 1330 may exchange communication signals with the first and second semiconductor devices 1310 and 1320 through the second connection portion 1420 .

[0124] The semiconductor package according to the fifth embodiment may provide a power signal and / or electric power to the third semiconductor device 1330 through the conductive coupling portion 1450 , thereby providing sufficient power to drive the third semiconductor device 1330 or enabling smooth control of power operation.

[0125] Therefore, embodiments can improve the driving characteristics of the third semiconductor device 1330. That is, embodiments can solve the problem of insufficient power provided to the third semiconductor device 1330. In addition, in embodiments, at least one of the power signal, electrical power, and communication signal of the third semiconductor device 1330 can be provided via different paths through the conductive coupling portion 1450 and the second connection portion 1420. Thus, embodiments can solve the problem of communication signal loss due to power signal loss. For example, embodiments can minimize mutual interference between communication signals and power signals.

[0126] Meanwhile, the second semiconductor device 1320 in the fifth embodiment may have a package-on-package (POP) structure in which a plurality of package circuit boards are stacked, and may be provided on the first circuit board 1100. For example, the third semiconductor device 1330 may be a memory package including a memory chip. Alternatively, the memory package may be coupled to the conductive coupling portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310 and the second semiconductor device 1320.

[0127] Hereinafter, a circuit board of an embodiment will be described. The circuit board described below may be a first circuit board 1100 or a second circuit board 1200 of a semiconductor package.

[0128] Figure 2 is a sectional view showing a circuit board according to a first embodiment, Figure 3 It is observed from above Figure 2 The plan view of the circuit board, Figure 4 is included Figure 2 A cross-sectional view of a circuit board with a semiconductor package, Figure 5 yes Figure 4 A magnified view of a local area, Figure 6 is embedded in the Figure 2 A plan view of a connecting member in a circuit board, Figure 7 is a plan view of a connection member including a dummy electrode provided on the connection member according to the first embodiment, Figure 8 It shows Figure 7 Cross-sectional view of the surface roughness of the connecting electrode and the dummy electrode, Figure 9 is a plan view of a connection member including a dummy electrode provided in the connection member according to a second embodiment, Figure 10is a plan view of a connection member including a dummy electrode provided in the connection member according to a third embodiment, Figure 11 is a plan view of a connection member including a dummy electrode provided in the connection member according to a fourth embodiment, Figure 12 is a diagram showing a detailed layer structure of a connection member according to one embodiment, Figure 13 It is shown that the Figure 2 A cross-sectional view of the detailed layer structure of the protruding electrodes in the circuit board, Figure 14 is a sectional view showing a circuit board according to a second embodiment, Figure 15 is a sectional view showing a circuit board according to a third embodiment, Figure 16 is a cross-sectional view showing a circuit board according to a fourth embodiment.

[0129] In the following, reference will be made to Figures 2 to 16 A semiconductor package according to an embodiment is described in detail.

[0130] refer to Figure 2 The circuit board according to the first embodiment may include an insulating portion 110 , an electrode portion, and a connection member 200 . The insulating portion 110 may include an insulating layer 111 , a first protective layer 112 , and a second protective layer 113 .

[0131] The insulating layer 111 may have a layer structure of at least one layer. Preferably, the insulating layer 111 may have a stacked structure in which multiple layers are stacked in a vertical direction. It may have multiple stacked structures. The stacked structure may be distinguished by the electrode portion. For example, the electrode portion may include a wiring electrode EP1 and a through electrode EP2. The wiring electrode EP1 and the through electrode EP2 may have different widths. In addition, the stacked structure may be distinguished by the width difference between the wiring electrode EP1 and the through electrode EP2. The wiring electrode EP1 may have a wider width than the through electrode EP2. Thus, the wiring electrode EP1 and the through electrode EP2 may be distinguished in the electrode portion. The wiring electrode EP1 may represent a pad and / or trace of the electrode portion. The through electrode EP2 may represent a via electrode connected to the wiring electrode. The through electrode EP2 may be arranged between multiple wiring electrodes EP1 arranged in different layers. Through the above-mentioned stacked structure, the circuit board of the embodiment can effectively electrically connect at least one semiconductor device and / or the second circuit board to the mainboard.

[0132] In addition, when the multiple layers of the insulating layer 111 include the same insulating material, the interfaces between the multiple layers may not be distinguished. In this case, the stacked structure can be distinguished by the wiring electrode EP1 and the through electrode EP2 of the electrode portion.

[0133] The insulating layer 111 can be rigid or flexible. For example, the insulating layer 111 can be made of glass or plastic. For example, the insulating layer 111 can be made of chemically strengthened or semi-strengthened glass, such as soda lime glass or aluminosilicate glass. For example, the insulating layer 111 can be made of reinforced or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 111 can be made of sapphire. For example, the insulating layer 111 can be made of an optically isotropic film. For example, the insulating layer 111 can be made of cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 111 can be formed of a material including an inorganic filler and an insulating resin. For example, the insulating layer 111 may have a structure in which an inorganic filler of silica or alumina is provided in a thermosetting resin or a thermoplastic resin.

[0134] The insulating layer 111 may have a structure in which a plurality of different insulating materials are stacked, and an exemplary arrangement structure will be described in more detail below.

[0135] In one embodiment, the insulating layer 111 may include a first insulating layer corresponding to a core layer including a reinforcing member. Here, the core layer may refer to an insulating layer including a reinforcing member and having a thickness of more than 30 μm in the vertical direction. In addition, the insulating layer may include an upper buildup insulating layer provided at the upper portion of the core layer and a lower buildup insulating layer provided at the lower portion of the core layer. In one embodiment, the upper buildup insulating layer and / or the lower buildup insulating layer may not have a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0136] The term "reinforcement member" can refer to the glass fiber material extending horizontally along the insulation layer and can have a different meaning from the inorganic filler spaced apart from each other. That is, the core layer's reinforcement member can have a different horizontal length or width than the filler in the upper and / or lower stacked insulation layers. Furthermore, the core layer's reinforcement member can have a structure extending in one direction, but because the filler in the upper and / or lower stacked insulation layers can have arbitrary dimensions and be arranged dispersed throughout the upper and / or lower stacked insulation layers, the core layer's reinforcement member and the filler in the upper and / or lower stacked insulation layers can be distinguished from each other. For example, the glass fiber can extend to have a surface length greater than the width of the core layer. Here, "having a surface length greater than the width of the core layer" can mean that the glass fiber can be arranged in a curved shape in the horizontal direction. Furthermore, since even if the upper and / or lower stacked insulation layers contain filler, it is not more effective than the glass fiber in the core layer in preventing problems such as warping, the reinforcement member is described separately from the filler in the upper and / or lower stacked insulation layers.

[0137] In another embodiment, insulating layer 111 may be a coreless circuit board that does not include a core layer. For example, insulating layer 111 may be composed of an organic material without reinforcing members, resulting in excellent workability, enabling a thinner circuit board, and miniaturizing the electrode portion of the circuit board. For example, insulating layer 111 may use ABF (Ajinomoto built-up film), a product released by Ajinomoto Co., Ltd., and may use materials such as FR-4, bismaleimide triazine (BT), photoimageable dielectric resin (PID), and BT. For example, insulating layer 111 may have a structure in which multiple built-up insulating layers composed of ABF are stacked vertically. If insulating layer 111 is composed solely of ABF without reinforcing members, the rigidity of the circuit board may be reduced. Therefore, insulating layer 111 may be composed of ABF (Ajinomoto built-up film), and at least one of the multiple built-up insulating layers that constitute insulating layer 111 of the circuit board may include a reinforcing member. For example, insulating layer 111 may also include a first insulating layer composed of a first ABF containing a resin and a filler. In addition, the insulating layer 111 may include a second insulating layer composed of a second ABF including a resin, a filler, and a reinforcing member. At this time, the reinforcing member included in the second ABF may include a glass core primer (GCP) material, but is not limited thereto.

[0138] The layer of insulating layer 111 excluding reinforcement members can have a thickness in the range of 10 μm to 40 μm. Preferably, the layer of insulating layer 111 excluding reinforcement members can have a thickness in the range of 15 μm to 35 μm. More preferably, the layer of insulating layer 111 excluding reinforcement members can have a thickness in the range of 18 μm to 32 μm. If the thickness of the layer of insulating layer 111 excluding reinforcement members is less than 10 μm, the rigidity of the circuit board may be reduced. Furthermore, if the thickness of the layer of insulating layer 111 excluding reinforcement members is less than 10 μm, the electrode portion of the circuit board may not be stably protected, resulting in reduced electrical reliability. Furthermore, if the thickness of the layer of insulating layer 111 excluding reinforcement members exceeds 40 μm, the total thickness of the circuit board may increase, and thus the thickness of the semiconductor package. Furthermore, if the thickness of the layer of insulating layer 111 excluding reinforcement members exceeds 40 μm, miniaturization of the electrode portion of the circuit board may be difficult.

[0139] The thickness may correspond to the distance between wiring electrodes EP1 arranged in different layers in the vertical direction of the circuit board. That is, the thickness may represent the length from the upper surface to the lower surface of the circuit board or from the lower surface to the upper surface, and may represent the length in the vertical direction of the circuit board. Here, the upper surface may represent the highest position in the vertical direction of each component, and the lower surface may represent the lowest position in the vertical direction of each component. Furthermore, the positions may be referred to interchangeably.

[0140] The insulating portion 110 may include a first protective layer 112 and a second protective layer 113. The first protective layer 112 and the second protective layer 113 of the circuit board may be resist layers. For example, the first protective layer 112 of the circuit board may be a first resist layer disposed on the uppermost side of the circuit board. Alternatively, the second protective layer 113 of the circuit board may be a second resist layer disposed on the lowermost side of the circuit board.

[0141] In one embodiment, the first protective layer 112 and the second protective layer 113 of the circuit board may include the same insulating material as the insulating layer 111. In this case, it may be difficult to distinguish the interface between the insulating layer 111 and the first protective layer 112 and the second protective layer 113. In this case, the wiring electrode EP1 and the through electrode EP2 of the electrode portion provided in the insulating layer 111, the first protective layer 112, and the second protective layer 113 can be used to distinguish the interface between the insulating layer 111, the first protective layer 112, and the second protective layer 113.

[0142] The circuit board may include an electrode portion, which may include a first electrode portion 130 , a second electrode portion 135 , a third electrode portion 140 , and a fourth electrode portion 150 provided in the insulating layer 100 .

[0143] The first electrode portion 130 , the second electrode portion 135 , and the third electrode portion 140 may refer to electrodes vertically overlapping the connection member 200 within the insulating layer 100 .

[0144] The fourth electrode portion 150 may refer to an electrode that does not vertically overlap the connection member 200 within the insulating layer 100 .

[0145] The first electrode portion 130 and the second electrode portion 135 may mean electrodes electrically connected to the connection member 200 .

[0146] For example, the connection member 200 may have a connection electrode 210. The connection electrode 210 may include a first connection electrode 210A and a second connection electrode 210B spaced apart from the first connection electrode 210A.

[0147] The first electrode portion 130 may be an electrode vertically overlapped with the first connection electrode 210A of the connection member 200. For example, the first electrode portion 130 may be an electrode electrically connected to the first connection electrode 210A of the connection member 200.

[0148] The second electrode portion 135 may be an electrode vertically overlapped with the second connection electrode 210B of the connection member 200. For example, the second electrode portion 135 may be an electrode electrically connected to the second connection electrode 210B of the connection member 200.

[0149] In one embodiment, the third electrode portion 140 may be disposed between the first electrode portion 130 and the second electrode portion 135. In another embodiment, the third electrode portion 140 may be disposed between the first connection electrode 210A and the second connection electrode 210B of the connection member 200.

[0150] The third electrode portion 140 can be electrically floating relative to the connection member 200. For example, the third electrode portion 140 can be a dummy electrode. For example, the third electrode portion 140 can be a dummy electrode that electrically floats relative to the connection member 200 and the semiconductor device while being located between the connection member 200 and the semiconductor device. The third electrode portion 140 can be located between the first electrode portion 130 and the second electrode portion 135 or between the first connection electrode 210A and the second connection electrode 210B of the connection member 200, and can function to improve the adhesion between the insulating layer 100 and the connection member 200. Here, in one embodiment, the third electrode portion 140 can be a component of the electrode portion of the circuit board that is different from the connection electrode of the connection member 200. In this case, after performing a process of embedding the connection member 200 in the insulating layer 111 during the manufacturing process of the circuit board, embodiments may perform a process of forming the third electrode portion 140 so that it horizontally overlaps with the first connection electrode 210A and the second connection electrode 210B of the connection member 200 and electrically floats relative to the first connection electrode 210A and the second connection electrode 210B. In another embodiment, the third electrode portion 140 may be a component of the connection member 200. In this case, the connection member 200 may be provided with the third electrode portion 140 disposed between the first connection electrode 210A and the second connection electrode 210B.

[0151] The connecting member 200 can horizontally connect the terminals of multiple semiconductor devices. Specifically, multiple semiconductor devices can be arranged on a circuit board and spaced apart horizontally. The multiple semiconductor devices can exchange signals with each other. Therefore, the terminals provided in each of the multiple semiconductor devices include terminals that are connected to each other. As the functions provided by the multiple semiconductor devices increase, the number of terminals provided in the multiple semiconductor devices also increases. Consequently, the number of terminals in the multiple semiconductor devices that need to be connected to each other also increases. Furthermore, due to the miniaturization of semiconductor packages and / or multiple semiconductor devices, the size of the terminals provided in the multiple semiconductor devices has become smaller. Therefore, it can be difficult to connect the terminals of the multiple semiconductor devices solely to the electrodes provided on the circuit board within a limited space. Furthermore, the size of the electrodes provided on the circuit board differs significantly from the size of the terminals provided in the semiconductor devices. Therefore, if the terminals in the semiconductor devices are connected solely to the electrodes provided on the circuit board, signal transmission loss may increase and signal transmission characteristics may deteriorate. The connecting member 200 can be embedded in the circuit board and electrically connect the terminals of the multiple semiconductor devices that should be connected to each other.

[0152] The connection member 200 may include a connection electrode 210, and the connection electrode 210 may include a first connection electrode 210A and a second connection electrode 210B. Taking into account the positions of the terminals of the first and second semiconductor devices disposed on the circuit board and the horizontal separation distance between the first and second semiconductor devices, the first and second connection electrodes 210A and 210B may be disposed on the connection member 200 at a predetermined distance in the horizontal direction. The upper surface of the connection member 200 may include a first region disposed with the first connection electrode 210A, a second region disposed with the second connection electrode 210B, and a third region between the first and second regions where no connection electrodes are disposed.

[0153] To this end, the connection electrodes 210 provided in the connection member 200 can have a high density and a relatively low surface roughness. Therefore, since the connection electrodes 210 of the connection member 200 have a relatively low surface roughness and are not provided in a specific area of ​​the upper surface of the connection member 200, the adhesion between the insulating layer 100 and the connection member 200 may be reduced. As a result, the connection member 200 may peel off from the insulating layer 100. In addition, various thermal stresses may occur during the manufacturing process and / or in the use environment of the semiconductor package, and these thermal stresses may cause cracks to form in the connection member 200, the connection member 200 to peel off, or the connection member 200 to bend significantly in a specific direction.

[0154] Therefore, embodiments may include a third electrode portion 140 disposed on the connection member 200. The third electrode portion 140 may be an electrode formed through a different process from the connection electrode 210 of the connection member 200. However, without limitation thereto, the third electrode portion 140 may be formed together with the connection electrode 210 in the process of manufacturing the connection member 200. In this case, when the third electrode portion 140 is disposed on the connection member 200 together with the connection electrode 210, a process of embedding the connection member 200 in the insulating layer 100 may be performed.

[0155] The third electrode portion 140 may be physically combined with the connection member 200 while being electrically floated with respect to the connection member 200 .

[0156] Thus, the third electrode portion 140 can have a function of improving the adhesion between the connecting member 200 and the insulating layer 100. Thus, the embodiment can solve the mechanical reliability problem of the connecting member 200 being peeled off from the insulating layer 100 by using the third electrode portion 140. In addition, the third electrode portion 140 can have a function of increasing the rigidity of the connecting member 200 and / or the circuit board. For example, the third electrode portion 140 can be coupled to the connecting member 200 to prevent the connecting member 200 and / or the circuit board from being significantly bent in a specific direction. Thus, the embodiment can enable a plurality of semiconductor devices arranged on the circuit board to operate stably. In addition, the embodiment can enable electronic products and / or servers to which the semiconductor package is applied to operate smoothly.

[0157] Meanwhile, the fourth electrode portion 150 may horizontally overlap the first and second electrode portions 130 and 135 , but may not vertically overlap the connection member 200 .

[0158] The fourth electrode portion 150 may be an electrode connected to a semiconductor device. For example, the fourth electrode portion 150 may be connected to a semiconductor device connected to each of the first electrode portion 130 and the second electrode portion 135 .

[0159] The electrode portion of the embodiment may include a protruding electrode. For example, the electrode portion may include a first protruding electrode 160A disposed on the first electrode portion 130. In addition, the electrode portion may include a second protruding electrode 160B disposed on the second electrode portion 135. In addition, the electrode portion may include a third protruding electrode 180 disposed on the fourth electrode portion 150.

[0160] The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may penetrate from the upper surface of the insulating layer 100 to a portion of the insulating layer 100 .

[0161] In addition, the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may protrude above the upper surface of the insulating layer 100 .

[0162] The first protruding electrodes 160A, the second protruding electrodes 160B, and the third protruding electrodes 180 may improve bonding between a plurality of semiconductor devices and a circuit board.

[0163] The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 can be referred to as bumps. They can also be referred to as pillars. The first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 can also be referred to as pillars. Preferably, the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may refer to electrodes on which conductive bonding members for bonding with semiconductor devices are disposed. Specifically, as the pitch of semiconductor device terminals becomes finer, short circuits may occur between multiple conductive bonding members connected to the multiple terminals of the semiconductor device via a conductive adhesive such as solder. Therefore, embodiments may perform thermocompression bonding to reduce the volume of the conductive bonding members. Therefore, embodiments may provide the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 with guaranteed alignment, diffusion, and anti-diffusion capabilities to prevent intermetallic compounds (IMCs) formed between the conductive adhesive such as solder and the protruding portions from diffusing into the circuit board.

[0164] according to Figure 3 and Figure 4 In an embodiment, the first semiconductor device 310 and the second semiconductor device 320 may be mounted on a circuit board. The first semiconductor device 310 may include a plurality of first terminals 315 . In addition, the second semiconductor device 320 may include a plurality of second terminals 325 .

[0165] The first and second semiconductor devices 310 and 320 may be electrically coupled to the first, second, and third protruding electrodes 160A, 160B, and 180 provided on the circuit board. To this end, the conductive adhesive member 300 may be provided between the first and second terminals 315 and 325 of the first and second semiconductor devices 310 and 320 and the first, second, and third protruding electrodes 160A, 160B, and 180.

[0166] In addition, the molding member 330 may be provided on the circuit board. The molding member 330 may be provided on the circuit board, and the first semiconductor device 310 and the second semiconductor device 320 may be molded by the molding member.

[0167] The first protruding electrode 160A may represent a bonding electrode electrically connected to the first terminal 315 of the first semiconductor device 310 . The second protruding electrode 160B may represent a bonding electrode electrically connected to the second terminal 325 of the second semiconductor device 320 .

[0168] The first protruding electrode 160A and the second protruding electrode 160B may be spaced apart from each other in the horizontal direction. For example, based on the positions of the first terminal 315 provided in the first semiconductor device 310 and the second terminal 325 provided in the second semiconductor device 320 and the separation distance between the first semiconductor device 310 and the second semiconductor device 320, the first protruding electrode 160A and the second protruding electrode 160B may be spaced apart from each other by a predetermined horizontal distance.

[0169] Meanwhile, the third protruding electrodes 180 may include a first group of third protruding electrodes 180A and a second group of third protruding electrodes 180B. The first group of third protruding electrodes 180A may be disposed adjacent to the first protruding electrode 160A. For example, the first group of third protruding electrodes 180A may be disposed on one side of the first protruding electrode 160A. The first group of third protruding electrodes 180A may vertically overlap with the first semiconductor device 310. The first group of third protruding electrodes 180A may be connected to the first terminal 315 of the first semiconductor device 310. The second group of third protruding electrodes 180B may be disposed adjacent to the second protruding electrode 160B. For example, the second group of third protruding electrodes 180B may be disposed on the other side of the second protruding electrode 160B. The second group of third protruding electrodes 180B may vertically overlap with the second semiconductor device 320. The second group of third protruding electrodes 180B may be connected to the second terminal 325 of the second semiconductor device 320.

[0170] Each of the first and second protruding electrodes 160A and 160B may be provided in the form of a plurality of units spaced apart from each other in a horizontal direction, and the third protruding electrode 180 may also be provided in the form of a plurality of units spaced apart from each other in the horizontal direction.

[0171] according to Figure 5 In an embodiment, a plurality of first terminals 315 may be provided on one surface of the first semiconductor device 310. The first terminals 315 may be spaced apart from an edge of the one surface of the first semiconductor device 310 by a first distance W1. For example, among the plurality of first terminals provided on the first semiconductor device 310, a first terminal disposed closest to an edge of the one surface of the first semiconductor device 310 may be spaced apart from the edge by the first distance W1.

[0172] In addition, a plurality of second terminals 325 may be provided on one surface of the second semiconductor device 320. The second terminals 325 may be spaced apart by a second interval W2 from an edge of the one surface of the second semiconductor device 320. For example, among the plurality of second terminals provided in the second semiconductor device 320, a second terminal that is most adjacent to an edge of the one surface of the second semiconductor device 320 may be spaced apart from the edge by a second interval W2.

[0173] At this time, each of the first interval W1 and the second interval W2 may satisfy the range of 40 μm to 80 μm. Preferably, each of the first interval W1 and the second interval W2 may satisfy the range of 45 μm to 75 μm. More preferably, each of the first interval W1 and the second interval W2 may satisfy the range of 50 μm to 70 μm.

[0174] If each of the first and second intervals W1, W2 is less than 40 μm, the mechanical reliability and / or electrical reliability of the first terminal 315 and / or the second terminal 325 may deteriorate. For example, if each of the first and second intervals W1, W2 is less than 40 μm, during the cutting process in the process of manufacturing the first semiconductor device 310 and / or the second semiconductor device 320, an impact may be applied to the electrode located closest to the edge, and cracks or electrode peeling may occur in the electrode due to the impact. In addition, if each of the first and second intervals W1, W2 exceeds 80 μm, the dummy area in which the first and / or second terminals are not located will increase the area corresponding thereto. In addition, when the dummy area increases, the size of the first semiconductor device 310 and / or the second semiconductor device 320 may increase, which may increase the size of the semiconductor package, and further, it may be difficult to miniaturize the size of the electronic product or server.

[0175] The first semiconductor device 310 and the second semiconductor device 320 may be arranged on the circuit board with a third distance W3 therebetween. The third distance W3 may be in a range of 80 μm to 150 μm. Preferably, the third distance W3 may be in a range of 85 μm to 140 μm. More preferably, the third distance W3 may be in a range of 90 μm to 120 μm.

[0176] If the third spacing W3 is less than 80 μm, the separation distance between the first semiconductor device 310 and the second semiconductor device 320 becomes narrower, and thus, workability in the process of mounting the first semiconductor device 310 and the second semiconductor device 320 on the circuit board may be deteriorated. For example, if the third spacing W3 is less than 80 μm, during the process of mounting the second semiconductor device 320 after mounting the first semiconductor device 310, the two semiconductor devices may come into contact with each other, or space for the mounting process of the second semiconductor device 320 may not be secured, and thus, a problem may arise in which the first semiconductor device 310 and / or the second semiconductor device 320 cannot be stably mounted. In addition, if the third spacing W3 is less than 80 μm, as the distance between them becomes narrower, a circuit short circuit problem may occur in which electrodes that should not be connected to each other are connected to each other in the first terminal 315 of the first semiconductor device 310 and the second terminal 325 of the second semiconductor device 320.

[0177] In addition, if the third interval W3 exceeds 150 μm, the separation distance between the first semiconductor device 310 and the second semiconductor device 320 may become too large, and thus the signal transmission distance between them may increase. Signal transmission loss may also increase in proportion to the increase in signal transmission distance. As a result, communication characteristics may deteriorate. In addition, if the third interval W3 exceeds 150 μm, the size of the semiconductor package may increase.

[0178] Therefore, the first terminal 315 and the second terminal 325 disposed closest to each other in the first and second semiconductor devices 310 and 320 may be spaced apart by a fourth interval W4. The fourth interval W4 may be determined by the sum of the first interval W1, the second interval W2, and the third interval W3.

[0179] For example, the fourth interval W4 may satisfy the range of 160 μm to 310 μm. In addition, if the fourth interval W4 is less than 160 μm or exceeds 310 μm, one of the first interval W1, the second interval W2, and the third interval W3 may not satisfy the above range, and thus the above problem may occur.

[0180] refer to Figure 6 , the connection member 200 may include a first connection electrode 210A connected to the first terminal 315 of the first semiconductor device 310 and a second connection electrode 210B connected to the second terminal 325 of the second semiconductor device 320 .

[0181] The first connection electrode 210A of the connection member 200 may vertically overlap the first terminal 315 of the first semiconductor device 310 . In addition, the second connection electrode 210B of the connection member 200 may vertically overlap the second terminal 325 of the second semiconductor device 320 .

[0182] At this time, electrodes of the first terminal 315 and the second terminal 325 that are most adjacent to each other may be spaced apart by a fourth interval W4.

[0183] Therefore, the first connection electrode 210A and the second connection electrode 210B provided in the connection member 200 may also be spaced apart by a fourth interval W4. For example, the upper surface of the connection member 200 may be provided with an area where the connection electrode 210 is not provided corresponding to the fourth interval W4.

[0184] refer to Figure 7, embodiments may perform a process of forming the third electrode portion 140 on the connection member 200 in a state where the connection member 200 is disposed on the insulating layer 111. The third electrode portion 140 may be disposed in a region between the first connection electrode 210A and the second connection electrode 210B disposed in the connection member 200. The third electrode portion 140 may physically contact the connection member 200 and may be electrically floating.

[0185] Meanwhile, the first connection electrode 210A of the connection member 200 may include a plurality of connection electrodes. In addition, the second connection electrode 210B of the connection member 200 may include a plurality of connection electrodes.

[0186] In this case, the planar area of ​​the third electrode portion 140 may be larger than the planar area of ​​a single electrode of the first connection electrode 210A and the planar area of ​​a single electrode of the second connection electrode 210B. Preferably, the third electrode portion 140 may be provided as a single unit, and the planar area of ​​the third electrode portion 140 may be larger than each of the planar area of ​​a single electrode of the first connection electrode 210A and the planar area of ​​a single electrode of the second connection electrode 210B. For example, the third electrode portion 140 may be provided as a plurality of units, in which case the planar area of ​​a single electrode of the third electrode portion 140 may be larger than each of the planar area of ​​a single electrode of the first connection electrode 210A and the planar area of ​​a single electrode of the second connection electrode 210B.

[0187] Thus, the planar area of ​​a single electrode of the third electrode portion 140 is greater than the planar area of ​​a single electrode of the first connection electrode 210A and the planar area of ​​a single electrode of the second connection electrode 210B. Therefore, embodiments can further improve the adhesion between the connection member 200 and the insulating layer 111 through the third electrode portion 140, thereby resolving the problem of the connection member 200 being peeled off from the insulating layer 100. Furthermore, embodiments can maximize the effect of improving the rigidity of the connection member 200 and / or the effect of improving the rigidity of the circuit board through the third electrode portion 140, thereby resolving the problem of the connection member 200, the circuit board, and / or the semiconductor package being significantly bent in a specific direction.

[0188] refer to Figure 8 , the connection electrode 210 of the connection member 200 and the third electrode portion 140 may have different surface roughnesses. The connection electrode 210 of the connection member 200 may have a relatively small surface roughness value to minimize signal transmission loss due to the skin effect. In contrast, the third electrode portion 140 is a dummy electrode rather than an electrode through which signals are transmitted, and therefore, the surface roughness value of the third electrode portion 140 may be greater than the surface roughness value of the connection electrode 210 of the connection member 200.

[0189] Thus, embodiments can further enhance adhesion between the insulating layer 100 and the third electrode portion 140 by making the surface roughness value of the third electrode portion 140 relatively large, and further enhance adhesion between the connection member 200 physically coupled to the third electrode portion 140 and the insulating layer 100 .

[0190] refer to Figure 9 The planar shape of the third electrode portion 140 may have various shapes. For example, the planar shape of the third electrode portion 140 in the previous embodiment is shown as having a square shape, but is not limited thereto. For example, the planar shape of the third electrode portion 140 may have a circular shape or an elliptical shape. In addition, the planar shape of the third electrode portion 140 may be modified to a triangular shape, a polygonal shape, or the like.

[0191] refer to Figure 10 , the third electrode portion 140 may include multiple dummy electrode patterns. For example, the third electrode portion 140 in the previous embodiment is provided as a single electrode between the first connection electrode 210A and the second connection electrode 210B of the connection member 200, but is not limited thereto. For example, the third electrode portion 140 may include multiple dummy electrode patterns spaced apart from each other in the region between the first connection electrode 210A and the second connection electrode 210B of the connection member 200. In this case, when the third electrode portion 140 includes multiple dummy electrode patterns, the contact area between the insulating layer 100 and the third electrode portion 140 can be further increased, thereby further improving the adhesion between the insulating portion 110 and the connection member 200.

[0192] Meanwhile, although the first semiconductor device 310 and the second semiconductor device 320 are illustrated as being disposed on a circuit board in the previous embodiment, the embodiment is not limited thereto.

[0193] For example, the semiconductor package may include first and second semiconductor devices 310 and 320 spaced apart in a first horizontal direction, and may include a third semiconductor device spaced apart from the first and second semiconductor devices 310 and 320 in a second horizontal direction different from the first horizontal direction.

[0194] like Figure 11 As shown, the connection electrodes 210 of the connection member 200 may include a first connection electrode 210A vertically overlapping a terminal of the first semiconductor device 310 , a second connection electrode 210B vertically overlapping a second semiconductor device 320 , and a third connection electrode 210C vertically overlapping a third semiconductor device.

[0195] In addition, the third electrode part 140 may include a first dummy electrode 140A disposed between the first connection electrode 210A and the second connection electrode 210B on the connection member 200 , and a second dummy electrode 140B disposed between the first connection electrode 210A, the second connection electrode 210B, and the third connection electrode 210C.

[0196] The detailed layer structure of the connecting member 200 is described below. The connecting member 200 may be an inorganic bridge. For example, the inorganic bridge may be a silicon bridge. Thus, the connecting member 200 may include an insulating member containing a silicon material and a connecting electrode disposed on the insulating member. In another embodiment, the connecting member 200 may be an organic bridge. For example, the organic bridge may include an organic insulating layer. For example, the connecting member 200 may include multiple organic insulating layers.

[0197] Specifically, according to Figure 12 In an embodiment, the connection member 200 may include a first insulating layer 201 , a second insulating layer 202 , and a third insulating layer 203 .

[0198] In addition, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 may include different insulating materials. However, the embodiment is not limited thereto. For example, the first insulating layer 201 may include an organic material. The first insulating layer 201 may include a material different from that of the second insulating layer 202, but is not limited thereto.

[0199] The first insulating layer 201 can have properties that enable the formation of the electrode layer 206 of the connecting member 200, which includes a microelectrode pattern. For example, the first insulating layer 201 can be made of an insulating material with excellent workability and elasticity. For example, the first insulating layer 201 of the connecting member 200 can be made of polyimide (PI). In this case, the connecting member in the prior art is an inorganic bridge, such as a silicon bridge. Silicon has a different thermal expansion coefficient than that of the insulating layer 111, and therefore can easily crack due to thermal stress. In another embodiment, the first insulating layer 201 of the connecting member 200 can be made of an organic material with a thermal expansion coefficient similar to that of the insulating layer 111. This embodiment can minimize the stress applied to the connecting member 200. Furthermore, this embodiment can solve the problem of cracks in the connecting member 200 or the connecting member 200 peeling off the circuit board. As a result, the embodiment can improve the mechanical and electrical reliability of the semiconductor package.

[0200] In addition, when the first insulating layer 201 of the connection member 200 includes polyimide, the cost of the connection member 200 may be reduced compared to a silicon bridge.

[0201] In addition, the connection member 200 can be provided with a via electrode having a small width. In addition, the alignment between the multiple via electrodes arranged in different layers can have a significant impact on the operating characteristics of the connection member 200, the operating characteristics of the semiconductor package, and the operating characteristics of the electronic product or server using the semiconductor package. In this case, the polyimide can have transparent properties. Therefore, the embodiment can improve the alignment of the multiple via electrodes arranged in different layers. As a result, the operating characteristics of the connection member 200, the operating characteristics of the semiconductor package, and the operating characteristics of the electronic product or server using the semiconductor package can be further improved.

[0202] Alternatively, first insulating layer 201 may represent an insulating layer disposed within the inner layer of connecting member 200. Furthermore, the overall properties of connecting member 200 may be determined by the properties of first insulating layer 201. In this case, first insulating layer 201 may be elastic and have a thermal expansion coefficient similar to that of the insulating layer of the circuit board. Thus, when the circuit board deforms due to heat, first insulating layer 201 of connecting member 200 may move along with the circuit board. Thus, embodiments can address the potential for cracks in connecting member 200 due to thermal deformation of the circuit board.

[0203] Furthermore, by including polyimide (PI) in the first insulating layer 201 of the connecting member 200, embodiments can easily control the thickness of the connecting member 200. Consequently, embodiments can minimize the difference between the depth of the cavity C, which serves as a receiving space for the connecting member 200 formed in the circuit board, and the thickness of the connecting member 200. Consequently, embodiments can minimize the height difference between the first electrode portion 130 and the fourth electrode portion 150 and / or the height difference between the first protruding electrode 160, the second protruding electrode 160B, and the third protruding electrode 180. Consequently, embodiments can stably couple a semiconductor device to the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180.

[0204] The connection member 200 may include a second insulating layer 202 disposed on the first insulating layer 201. The second insulating layer 202 may include an insulating material different from the insulating material of the first insulating layer 201, but is not limited thereto. For example, the second insulating layer 202 may include polyimide, which is the same insulating material as the first insulating layer 201. For example, the first insulating layer 201 may include the same insulating material as the insulating material of the second insulating layer 202 described below, instead of polyimide.

[0205] The second insulating layer 202 may include a photosensitive material. For example, the second insulating layer 202 may include a PID. For example, the second insulating layer 202 may be a PID in which the photosensitive material is a resin layer and a filler is dispersed in the resin layer.

[0206] In another embodiment, the second insulating layer 202 may include the same insulating material as the insulating layer 111. For example, the second insulating layer 202 may include ABF, which is the same insulating material as the insulating layer 111. Meanwhile, the second insulating layer 202 may be provided on each of both surfaces of the first insulating layer 201.

[0207] In addition, the connection member 200 may include a third insulating layer 203 disposed on the second insulating layer 202. The third insulating layer 203 may be a protective layer. For example, the third insulating layer 203 may be a solder resist layer.

[0208] At this time, the side surface of the connection member 200 may have a step. For example, the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 of the connection member 200 may have a step.

[0209] For example, the horizontal width of the first insulating layer 201 of the connection member 200 may be different from the horizontal width of the second insulating layer 202 and the horizontal width of the third insulating layer 203. Preferably, the horizontal width of the first insulating layer 201 of the connection member 200 may be greater than the horizontal width of the second insulating layer 202 and the horizontal width of the third insulating layer 203.

[0210] That is, among the insulating layers of the connection member 200, the elasticity and / or rigidity of the first insulating layer 201 may be the highest compared to the second insulating layer 202 and the third insulating layer 203. Therefore, embodiments allow the first insulating layer 201 of the connection member 200 to have the largest width. Therefore, embodiments allow an impact applied to the connection member 200 to be absorbed by the first insulating layer 201, thereby preventing the impact from being transmitted to the second insulating layer 202 and / or the third insulating layer 203.

[0211] In addition, the width of the second insulating layer 202 of the connecting member 200 in the horizontal direction may be different from the width of the third insulating layer 203 in the horizontal direction. The width of the second insulating layer 202 in the horizontal direction may be greater than the width of the third insulating layer 203 in the horizontal direction. At this time, the third insulating layer 203 may be a solder resist, and therefore, cracks are easily generated due to external impact. In addition, the manufacturing process of the connecting member 200 may include a sawing process. The above-mentioned sawing process may be a process for individually separating a plurality of connecting members. At this time, if an impact is applied to the third insulating layer 203 in the above-mentioned sawing process, there is a problem of cracks occurring in the third insulating layer 203. Therefore, by making the width of the third insulating layer 203 smaller than the widths of the first insulating layer 201 and the second insulating layer 202, the embodiment makes it possible to protect the third insulating layer 203 from the influence of impact.

[0212] Specifically, the horizontal distance from the side end of the first insulating layer 201 of the connecting member 200 to the side end of the third insulating layer 203 can meet the range of 50μm to 70μm. If the horizontal distance from the side end of the first insulating layer 201 of the connecting member 200 to the side end of the third insulating layer 203 is less than 50μm, an impact may be applied to the third insulating layer 203 during the sawing process, and thus cracks may occur in the third insulating layer 203. In addition, if the horizontal distance from the side end of the first insulating layer 201 of the connecting member 200 to the side end of the third insulating layer 203 exceeds 70μm, the circuit layer included in the connecting member 200 may not be stably protected, or the area of ​​the connecting member 200 where the circuit layer is not provided may increase, thereby possibly reducing circuit integration.

[0213] Therefore, the side surfaces of the first, second, and third insulating layers 201, 202, and 203 of the connection member 200 may have steps relative to each other.

[0214] Meanwhile, the connection member 200 may be provided with a circuit pattern 204. The circuit pattern 204 may include a connection electrode 210 provided at the uppermost side of the connection member 200.

[0215] In this case, the upper surface of the connecting electrode 210 of the connecting member 200 may be positioned lower than the upper surface of the third insulating layer 203 of the connecting member 200. For example, the connecting electrode 210 of the connecting member 200 may include only a pad portion. Furthermore, when the connecting electrode 210 of the connecting member 200 includes only a pad portion, the third electrode portion 140 may not horizontally overlap with the connecting electrode 210. In another embodiment, the connecting electrode 210 of the connecting member 200 may further include a bump portion disposed on the pad portion. Thus, the connecting electrode 210 of the connecting member 200 protrudes from the upper surface of the connecting member 200. In this case, the third electrode portion 140 may be disposed on the connecting member 200. For example, the third electrode portion 140 may be disposed on the upper surface of the third insulating layer 203 of the connecting member 200 in an area that does not vertically overlap with the connecting electrode 210. Furthermore, when the connecting electrode 210 of the connecting member 200 includes a bump portion, the third electrode portion 140 may horizontally overlap with the connecting electrode 210 of the connecting member 200.

[0216] refer to Figure 13 , each of the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180 may include a plurality of metal layers.

[0217] For example, each of the first protruding electrode 160A and the second protruding electrode 160B may include a first metal layer 160-1 disposed on the first electrode portion 130 and the second electrode portion 135, respectively. In addition, each of the first protruding electrode 160A and the second protruding electrode 160B may include a second metal layer 160-2 disposed on the first metal layer 160-1. In this case, the first metal layer 160-1 and the second metal layer 160-2 may include different metal materials.

[0218] Preferably, the first metal layer 160-1 may include nickel. Alternatively, the second metal layer 160-2 may include copper. The first metal layer 160-1 may improve the bonding strength between the second metal layer 160-2 and the first electrode portion 130 or the second electrode portion 135. For example, when the second metal layer 160-2 is directly disposed on the first electrode portion 130 or the second electrode portion 135, oxidation of the first electrode portion 130 or the second electrode portion 135 may occur, which may reduce the bonding strength therebetween. Therefore, the first metal layer 160-1 may be used to prevent oxidation of the first electrode portion 130 or the second electrode portion 135 while improving the bonding strength therebetween. In addition, the first metal layer 160-1 may address the issue of the first protruding electrode 160A and the second protruding electrode 160B peeling off from the first electrode portion 130 or the second electrode portion 135 due to the contraction and expansion of the first protective layer 112 caused by thermal stress.

[0219] Specifically, when first metal layer 160-1 includes nickel, adhesion between first electrode portion 130 or second electrode portion 135 and second metal layer 160-2 can be improved. Furthermore, when electrical connection is later made to first electrode portion 130 or second electrode portion 135 using a material such as solder, the solder may diffuse into first electrode portion 130 or second electrode portion 135 to form an intermetallic compound, which can degrade mechanical and electrical reliability. In particular, when second metal layer 160-2 is made of copper, the problem of intermetallic compound formation may be further exacerbated. However, when nickel is included, diffusion of solder can be prevented, thereby preventing the formation of intermetallic compounds and improving the electrical and mechanical reliability of the semiconductor package.

[0220] In this case, the first electrode portion 130 and the second electrode portion 135 may include a gap 130C. For example, the upper surfaces of the first electrode portion 130 and the second electrode portion 135 may include a gap 130C that is recessed toward the lower surface of the first electrode portion 130 or the second electrode portion 135 and vertically overlaps the first protruding electrode 160A and the second protruding electrode 160B. The gap 130C may be filled with the first metal layer 160-1. This increases the contact area between the first electrode portion 130 or the second electrode portion 135 and the first protruding electrode 160A and the second protruding electrode 160B, thereby further improving the bonding strength.

[0221] Additionally, the third protruding electrode 180 may also include a first metal layer 180-1 and a second metal layer 180-2. The first metal layer 180-1 of the third protruding electrode 180 may be disposed on the fourth electrode portion 150. Furthermore, the second metal layer 180-2 of the third protruding electrode 180 may be disposed on the first metal layer 180-1. A slit 150C may be provided on the upper surface of the fourth electrode portion 150, and the first metal layer 180-1 of the third protruding electrode 180 may be disposed so as to fill the slit 150C of the fourth electrode portion 150.

[0222] refer to Figure 14 The third electrode portion 140 may include a dummy through electrode 145 horizontally overlapping the first electrode portion 130 and the second electrode portion 135. The dummy through electrode 145 may improve the rigidity of the circuit board while preventing the circuit board from being greatly bent in a specific direction.

[0223] refer to Figure 15 , the circuit board may further include a dummy protruding electrode 170 disposed on the dummy through-electrode 145. The dummy protruding electrode 170 may be disposed between the first protruding electrode 160A and the second protruding electrode 160B. In addition, the dummy protruding electrode 170 may improve the rigidity of the circuit board and transfer the heat generated from the connecting member 200 to the end of the circuit board. In addition, the dummy protruding electrode 170 may also serve as an identification unit that can identify the coupling positions of multiple semiconductor devices on the circuit board. For example, an embodiment may easily identify the coupling positions of the first semiconductor device and the second semiconductor device based on the dummy protruding electrode 170 having a relatively large size, thereby allowing the first semiconductor device and the second semiconductor device to be stably coupled on the circuit board at a precise position.

[0224] In addition, a dummy protruding electrode 170 may be provided between the first protruding electrode 160A and the second protruding electrode 160B. For example, the dummy protruding electrode 170 may be provided in a region corresponding to the separation distance between the first semiconductor device 310 and the second semiconductor device 320. Therefore, at least a portion of the dummy protruding electrode 170 may not vertically overlap with the first semiconductor device 310 and the second semiconductor device 320.

[0225] In addition, the dummy protruding electrode 170 may be provided as a single unit, or alternatively, may be provided as a plurality of units.

[0226] However, the planar area of ​​a single electrode of the dummy protruding electrode 170 can be greater than the planar area of ​​a single electrode of each of the first protruding electrode 160A, the second protruding electrode 160B, and the third protruding electrode 180. Thus, the embodiment can maximize the planar area of ​​the dummy protruding electrode 170, thereby improving the rigidity of the semiconductor package. In addition, the dummy protruding electrode 170 can contact the molding member 330. The adhesion of the molding member 330 to the metal material can be stronger than the adhesion to the insulating material. Therefore, the embodiment can maximize the planar area of ​​the dummy protruding electrode 170, thereby increasing the contact area with the molding member 330 and further improving the adhesion therebetween. In addition, the embodiment can further improve the heat dissipation characteristics of the heat generated in the first semiconductor device 310, the second semiconductor device 320, and the connecting element 200 by maximizing the planar area of ​​the dummy protruding electrode 170.

[0227] refer to Figure 16 , the connection member 200 may be provided in a cavity provided in the first insulating part 110. At this time, the cavity may be provided in at least a portion of a layer of the first insulating portion 110.

[0228] The circuit board 100 may further include an adhesive member 190 disposed on the bottom surface of the cavity. The adhesive member 190 may enable the connection member 200 to be securely fixed to the cavity. The adhesive member 190 may have a different width than the connection member 200. In addition, the adhesive member 190 may have a different width than the width of the cavity.

[0229] For example, the width of the adhesive member 190 may be greater than the width of the connecting member 200. This prevents the connecting member 200 from being peeled off due to various impacts applied in the operating environment of the semiconductor package. For example, the adhesive member 190 may have a width greater than the connecting member 200 in order to improve the bonding strength with the connecting member 200.

[0230] Additionally, the width of adhesive member 190 can be smaller than the width of the cavity. For example, adhesive member 190 may not contact the sidewalls of the cavity. Thus, embodiments can prevent adhesive member 190 from contacting the inner wall of the cavity when adhesive member 190 expands due to damage. Thus, embodiments can minimize the stress applied by the expansion of adhesive member 190.

[0231] A semiconductor package of an embodiment may include an insulating layer and a connecting member embedded in the insulating layer. The connecting member may include a first connecting electrode and a second connecting electrode. In addition, the semiconductor package may include a first electrode portion and a second electrode portion disposed in the insulating layer. The first electrode portion may vertically overlap with the first connecting electrode of the connecting member. In addition, the second electrode portion may vertically overlap with the second connecting electrode of the connecting member. In addition, the electrode portion may further include a third electrode portion disposed between the first electrode portion and the second electrode portion or between the first connecting electrode and the second connecting electrode. The third electrode portion may be electrically floating relative to the connecting member and may physically contact the connecting member. The third electrode portion may be disposed in an area of ​​the upper surface of the connecting member where no connecting electrode is disposed. The third electrode portion may improve adhesion between the insulating layer and the connecting member.

[0232] Thus, the embodiment can increase the adhesion between the insulating layer and the connection member, thereby solving the problem of the connection member being peeled off from the insulating layer.

[0233] Furthermore, embodiments can improve the mechanical reliability of the semiconductor package by increasing the rigidity of the connecting member and / or the rigidity of the semiconductor package using the third electrode portion. Thus, embodiments can address the problem of significant bending of the connecting member and / or the semiconductor package in a particular direction. Thus, embodiments can enable the semiconductor package to operate stably. Furthermore, embodiments can enable smooth operation of electronic products and / or servers employing the semiconductor package.

[0234] Additionally, the surface roughness of the third electrode portion can be greater than that of the connection electrode disposed in the connection member. Thus, by making the surface roughness of the connection electrode smaller than that of the third electrode portion, embodiments can minimize signal transmission loss, which increases proportionally with the surface roughness, thereby improving the signal transmission characteristics of the semiconductor package. Furthermore, by increasing the surface roughness of the dummy electrode, embodiments can further improve the adhesion between the insulating layer and the connection member without affecting signal transmission characteristics.

[0235] Meanwhile, the dummy electrode in one embodiment may comprise only a dummy electrode pattern provided on the connecting member. In another embodiment, the dummy electrode may comprise a dummy through-electrode extending from the upper surface of the first insulating layer to a portion of the first insulating layer, and a dummy electrode pattern. In another embodiment, the third electrode portion may comprise a dummy through-electrode and a dummy protruding electrode, as well as a dummy electrode pattern. Furthermore, when the third electrode portion comprises a dummy through-electrode and a dummy protruding electrode, the adhesion between the connecting member and the insulating layer can be further improved, while further enhancing the rigidity of the semiconductor package.

[0236] On the other hand, when a circuit board having the above-mentioned features of the present invention is used in IT equipment or household appliances (such as smartphones, server computers, TVs, etc.), it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs a semiconductor packaging function, the circuit board can be used to safely protect the semiconductor chip from external moisture or contaminants. Alternatively, it can address issues such as leakage current, electrical shorts, and electrical opens between terminals provided to the semiconductor chip. Furthermore, when the signal transmission function is primary, noise issues can be addressed. Thus, a circuit board having the above-mentioned features of the present invention can maintain the stable functionality of IT equipment or household appliances, allowing the entire product to which the present invention is applied and the circuit board to achieve functional unification or technical interlocking with each other.

[0237] When a circuit board having the features of the present invention is used in a transport device such as a vehicle, it can resolve issues with signal distortion transmitted to the transport device. Alternatively, it can further enhance the safety of the transport device by externally and securely protecting the semiconductor chip controlling the transport device and resolving issues such as leakage current, electrical shorts, or electrical opens between the terminals connected to the semiconductor chip. Thus, the transport device and the circuit board employing the present invention can achieve functional integrity or technical interlocking with each other.

[0238] The characteristics, structures, and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, those skilled in the art can even combine or modify the characteristics, structures, and effects shown in each embodiment with respect to other embodiments. Therefore, it should be understood that the contents related to such combinations and such modifications are included in the scope of the embodiments.

[0239] The description focuses on the embodiments, but it is merely illustrative and does not limit the embodiments. Those skilled in the art will appreciate that various modifications and applications not shown above are possible without departing from the essential features of the embodiments. For example, each component specifically shown in the embodiments can be modified and implemented. In addition, it should be understood that differences related to such changes and applications are included within the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; a connecting member embedded in the insulating layer; as well as an electrode portion embedded in the insulating layer and overlapping the connecting member in a vertical direction, wherein the connecting member includes an electrode pattern provided on the connecting member, and wherein the electrode pattern is electrically floating relative to the electrode portion.

2. The circuit board according to claim 1 , wherein the connecting member comprises a first connecting electrode and a second connecting electrode spaced apart from the electrode pattern in a horizontal direction, wherein the electrode portion includes a first electrode portion and a second electrode portion, the first electrode portion overlaps with the first connection electrode in the vertical direction, the second electrode portion overlaps with the second connection electrode in the vertical direction, and wherein the electrode pattern electrically floats relative to the first electrode portion, the second electrode portion, the first connection electrode, and the second connection electrode.

3. The circuit board according to claim 2 , wherein the insulating layer comprises a first insulating layer having a cavity; and a second insulating layer provided on the first insulating layer and filling at least a portion of the cavity, and wherein the connecting member is arranged in the cavity, wherein the first electrode portion includes a first through electrode and a second through electrode, the first through electrode penetrates at least a portion of the second insulating layer and overlaps with the first connecting electrode in the vertical direction, the second through electrode penetrates at least a portion of the second insulating layer and overlaps with the first connecting electrode in the vertical direction, and The electrode pattern does not overlap with the first through-electrode and the second through-electrode in the vertical direction.

4. The circuit board according to claim 3 , wherein the first electrode portion includes a first wiring electrode provided on the first through-electrode, and a second wiring electrode provided on the second through-electrode, and The electrode pattern does not overlap with the first wiring electrode and the second wiring electrode in the vertical direction. 5 . The circuit board according to claim 2 , wherein the electrode pattern is provided on an upper surface of the connection member in the same plane as the first connection electrode and the second connection electrode. 6 . The circuit board according to claim 2 , wherein a surface roughness value of the electrode pattern is greater than a surface roughness value of at least one of the first connection electrode and the second connection electrode.

7. The circuit board according to claim 7, wherein each of the first connection electrode and the second connection electrode is provided in plural, and The planar area of ​​a single electrode pattern is larger than the planar area of ​​a single electrode of each of the plurality of first connecting electrodes and the second connecting electrodes.

8. The circuit board according to claim 2, wherein an edge shape of an upper surface of each of the first connection electrode and the second connection electrode is identical to each other, and The edge shape of the upper surface of the electrode pattern is different from the edge shapes of the first connecting electrode and the second connecting electrode.

9. The circuit board according to claim 4, further comprising: a dummy through-electrode provided on the electrode pattern and overlapping at least a portion of the first through-electrode and the second through-electrode in a horizontal direction, and a dummy wiring electrode provided on the dummy through-electrode and overlapping the first wiring electrode and the second wiring electrode in the horizontal direction.

10. The circuit board according to claim 9, further comprising: a protective layer, the protective layer being disposed on the insulating layer; as well as a first protruding electrode, the first protruding electrode penetrating at least a portion of the protective layer and overlapping the first wiring electrode in the vertical direction; a second protruding electrode, the second protruding electrode penetrating at least a portion of the protective layer and overlapping the second wiring electrode in the vertical direction; as well as A dummy protruding electrode is provided, the dummy protruding electrode penetrating at least a portion of the protection layer and overlapping the dummy wiring electrode in the vertical direction.

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