Semiconductor integrated circuit device

Abstract

In a semiconductor integrated circuit device, a standard cell (C1) includes an active region (2P) constituting a channel, a source, and a drain of a transistor, and a power supply wiring (11) extending in an X direction. The power supply wiring (11) is formed on the rear surface side of the transistor, and has an overlapping portion with the active region (2P) in plan view. Power supply wiring (71) extending in the Y direction is formed in a wiring layer lower than the power supply wiring (11). The power supply wiring (71) is connected to the power supply wiring (11) via the through hole (81), and has an overlapping portion with the active region (2P) in plan view.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor integrated circuit device. Background Art

[0002] The standard cell method is a well-known method for forming semiconductor integrated circuits on semiconductor substrates. This method involves pre-preparing basic units with specific logical functions (such as inverters, latches, flip-flops, and full adders) as standard cells, arranging multiple standard cells on the semiconductor substrate, and then connecting these standard cells with wiring to create an LSI (Large Scale Integration) chip.

[0003] Furthermore, by reducing the gate length (scaling) of transistors, a fundamental component of LSIs, semiconductor integrated circuits have achieved increased integration density, lower operating voltages, and higher operating speeds. However, in recent years, excessive scaling has led to significant increases in off-state current and power consumption. To address this, research has been actively underway on three-dimensional transistors, which transform the conventional planar transistor structure into a three-dimensional one. One example of a three-dimensional transistor is the nanosheet FET (Field Effect Transistor).

[0004] Patent Document 1 discloses a technology in which, in order to achieve further high integration, multilayer wiring is provided on the back surface of a substrate directly below a transistor, and power supply wiring and signal wiring are laid on the back surface of the substrate.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0037252 Summary of the Invention

[0008] -Technical problem to be solved by the invention-

[0009] However, in the technology disclosed in Patent Document 1, since the area for laying signal wiring is set on the back side of the substrate, there is insufficient area for laying power wiring. This leads to a reduction in power supply capacity, resulting in power supply voltage drop (IR-drop) and the accompanying circuit malfunction.

[0010] Furthermore, in the technology disclosed in Patent Document 1, since signal wiring is provided on both sides of the substrate front surface side and the substrate back surface side above the transistor, there is a problem that the design becomes complicated and difficult.

[0011] The present disclosure provides a layout structure capable of sufficiently ensuring power supply capability for a semiconductor integrated circuit device having a structure in which multilayer wiring is provided on the back side of a transistor.

[0012] -Technical solutions to solve technical problems-

[0013] A semiconductor integrated circuit device according to a first aspect of the present disclosure includes a plurality of cell rows, each of the cell rows including a plurality of standard cells arranged along a first direction. A first cell row, one of the plurality of cell rows, includes a first standard cell. The first standard cell includes a first active region and a first power supply wiring. The first active region constitutes a channel, a source, and a drain of a first transistor of a first conductivity type. The first active region includes a first nanosheet extending along the first direction as the channel. The first power supply wiring is formed on the back side of the first transistor, extends along the first direction, overlaps with the first active region in a plan view, and supplies a first power supply voltage. The semiconductor integrated circuit device also includes a second power supply wiring. The second power supply wiring is formed in a wiring layer below the first power supply wiring, extends in a second direction perpendicular to the first direction, and supplies the first power supply voltage. The second power supply wiring overlaps with the first active region in a plan view and is connected to the first power supply wiring via a via.

[0014] According to this aspect, in a semiconductor integrated circuit device, a first standard cell includes a first active area and a first power supply wiring, wherein the first active area constitutes a channel, a source, and a drain of a first transistor, and the first power supply wiring extends along the first direction. The first power supply wiring is formed on the back side of the first transistor and has an overlapping portion with the first active area when viewed from above. In addition, a second power supply wiring extending along the second direction is formed in a wiring layer lower than the first power supply wiring. The second power supply wiring is connected to the first power supply wiring via a through-hole and has an overlapping portion with the first active area when viewed from above. As described above, since the power supply wiring can be arranged at a high density on the back side of the transistor, it is possible to fully ensure power supply capacity.

[0015] -Effects of the Invention-

[0016] According to the present disclosure, it is possible to ensure sufficient power supply capability for a semiconductor integrated circuit device having a structure in which multilayer wiring is provided on the back side of a transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a plan view showing a layout example of circuit blocks included in the semiconductor integrated circuit device according to this embodiment;

[0018] Figure 2is a plan view showing an example of a layout structure of an inverter cell included in a semiconductor integrated circuit device according to an embodiment;

[0019] Figure 3 (a) and (b) are Figure 2 A cross-sectional view of an inverter unit in FIG.

[0020] Figure 4 yes Figures 2 and 3 The circuit diagram of the inverter unit shown in ;

[0021] Figure 5 (a) and (b) are other structural examples of the semiconductor integrated circuit device according to the embodiment;

[0022] Figure 6 1 is a plan view showing an example of a layout structure included in a semiconductor integrated circuit device according to an embodiment, wherein (a) is a two-input NAND gate cell, and (b) is a two-input NOR gate cell;

[0023] Figure 7 (a) is the circuit diagram of a two-input NAND gate unit, and (b) is the circuit diagram of a two-input NOR gate unit;

[0024] Figure 8 yes Figure 1 A partial enlarged view of the layout example shown;

[0025] Figure 9 (a) and (b) are plan views showing examples of block-level layouts according to variations of the embodiment;

[0026] Figure 10 It shows the composition Figure 9 Layout structure of the unit in the block-level layout, (a) shows the inverter unit, (b) shows the two-input NAND gate unit, and (c) shows the two-input NOR gate unit. DETAILED DESCRIPTION

[0027] The following embodiments are described with reference to the accompanying drawings. In the following embodiments, a semiconductor integrated circuit device includes multiple standard cells (sometimes referred to simply as cells in this specification), at least some of which include nanosheet FETs (Field Effect Transistors). Nanosheet FETs are FETs formed using a thin sheet (nanosheet) through which current flows. The nanosheet is formed, for example, of silicon. It should be noted that in this disclosure, the transistors included in the standard cells are not limited to nanosheet FETs.

[0028] In this specification, "VDD" and "VSS" refer to power supply voltages or power supplies themselves. In addition, in this specification, expressions such as "same wiring width" and the like, which mean that the widths are equal, include a range of variations due to manufacturing.

[0029] (Structure of circuit block)

[0030] Figure 1 It is a plan view showing an example of the layout of circuit blocks included in the semiconductor integrated circuit device according to the embodiment. Figure 1 The block-level layout in is constructed by arranging standard cells. Figure 1 The figure shows only the cell frame and power supply wiring of the standard cell; the internal structure of the standard cell and inter-cell wiring are omitted. In this embodiment, the power supply wiring is formed in the BM0 (Backside Metal 0) and BM1 (Backside Metal 1) layers, which are wiring layers provided on the back side of the semiconductor chip where the transistors are formed. The BM1 layer is located below the BM0 layer, that is, it is located farther away from the transistors.

[0031] It should be noted that in the following description, Figure 1 In the top view, the horizontal direction of the drawing is the X direction (equivalent to the first direction), the vertical direction of the drawing is the Y direction (equivalent to the second direction), and the direction perpendicular to the substrate surface is the Z direction (equivalent to the depth direction). In the following description, components denoted by the same reference numerals refer to the same components, and their description may be omitted.

[0032] exist Figure 1 In the layout shown, a cell row CR is composed of a plurality of cells arranged along the X direction. Figure 1 The cells are arranged in the Y direction (six rows in the figure). The cells include inverters, NAND gates, NOR gates, and other logic-function cells.

[0033] Each cell has power supply wiring formed at both ends of the BM0 layer in the Y direction. Each cell receives external power supply voltages VDD and VSS via these wiring. The cell rows CR are arranged in the Y direction, alternating with each other. At the junction of adjacent cell rows CR, the VDD supply wiring connects in the Y direction, and the VSS supply wiring connects in the Y direction. In other words, the BM0 layer has power supply wiring extending in the X direction, with the VDD supply wiring and the VSS supply wiring alternating in the Y direction.

[0034] The BM1 layer has power supply wiring extending in the Y direction, with power supply wiring for VDD and power supply wiring for VSS arranged alternately in the X direction. The VDD power supply wiring formed on the BM0 and BM1 layers is connected via vias formed in overlapping areas when viewed from above. The VSS power supply wiring formed on the BM0 and BM1 layers is connected via vias formed in overlapping areas when viewed from above. In other words, a mesh-like power supply wiring network is formed on the BM0 and BM1 layers for each of the power supply voltages, VDD and VSS. This enhances power supply capability.

[0035] The power wiring in the BM1 layer is laid out during block-level layout design after standard cells are laid out. In this embodiment, the power wiring supplying VDD and VSS is laid out alternately in the BM1 layer, with the spacing between them being the minimum allowed by the manufacturing process. This maximizes the power wiring layout in the BM1 layer, effectively minimizing power supply voltage drops and preventing problems such as circuit malfunction.

[0036] The power wiring of the BM1 layer overlaps with the power wiring of each cell when viewed from above. As described later, the active region of each cell overlaps with the power wiring of the BM1 layer. The active region is the region that constitutes the channel, source, and drain of the transistor. The active region of a nanosheet FET has a nanosheet serving as the channel. The portions of the active region that become the source and drain located on either side of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0037] On the other hand, Figure 1 In the circuit block shown, signal wiring for connecting cells is not arranged in the BM0 and BM1 layers, but is laid out only in the wiring layer on the substrate surface side above the transistors. This simplifies the design of signal wiring.

[0038] It should be noted that one or more wiring layers can be provided below the BM1 layer, and the power wiring can be laid in this wiring layer. This can further strengthen the power wiring. In this case, it is preferred that the direction of the power wiring alternates according to the wiring layer, for example, the direction of the power wiring in the BM2 layer is in the X direction, and the direction of the power wiring in the BM3 layer is in the Y direction.

[0039] <Inverter unit>

[0040] Figures 2 and 3 A diagram showing an example of a layout structure of inverter cells included in a semiconductor integrated circuit device according to an embodiment. Figure 2 It is a top view. Figure 3 (a) and (b) are cross-sectional views. Figure 3 (a) is along Figure 2A cross-sectional view taken along the transverse line X1-X1' in the top view, Figure 3 (b) is along Figure 2 A sectional view taken along the longitudinal line Y1-Y1' in the top view.

[0041] Figure 4 yes Figures 2 and 3 The circuit diagram of the inverter unit is shown in FIG. Figure 4 As shown, Figures 2 and 3 The inverter cell shown has a P-type transistor P1 and an N-type transistor N1.

[0042] Power supply lines 11 and 12 extending in the X direction are each formed in the BMO wiring layer on the back side of the semiconductor chip where the transistors are formed. Power supply line 11 supplies the power supply voltage VDD, and power supply line 12 supplies the power supply voltage VSS. The spacing between power supply lines 11 and 12 in the Y direction is the minimum spacing constrained by the manufacturing process. Power supply lines 11 and 12 are shared with other cells in a cell row containing an inverter cell, forming power supply lines extending in the X direction. Furthermore, power supply lines 11 and 12 are shared between adjacent cell rows in the Y direction.

[0043] An active region 2P constituting a channel, source, and drain of the P-type transistor is formed in the P-type transistor region on the N-type well (NWell). The active region 2P overlaps with the power supply line 11 in a plan view.

[0044] A P-type transistor P1 is formed in the P-type transistor region. Transistor P1 has a nanosheet 21a as its channel. This nanosheet 21a is composed of three overlapping sheets when viewed from above, extending in the X direction. In other words, transistor P1 is a nanosheet FET. In the active region 2P, the source of transistor P1 is connected to the power supply line 11 via a via 61.

[0045] An active region 2N, which forms the channel, source, and drain of the N-type transistor, is formed in the N-type transistor region on the P-type substrate (PSub). The active region 2N overlaps with the power supply line 12 in a plan view. It should be noted that the N-type transistor region can also be formed on a P-type well.

[0046] An N-type transistor N1 is formed in the N-type transistor region. Transistor N1 has a nanosheet 26a as its channel. This nanosheet 26a is composed of three overlapping sheets when viewed from above and extends in the X direction. In other words, transistor N1 is a nanosheet FET. In the active region 2N, the portion serving as the source of transistor N1 is connected to the power supply line 12 via a via 62.

[0047] A gate wiring 31 extending in the Y direction extends from the P-type transistor region to the N-type transistor region. Gate wiring 31 surrounds the outer periphery of nanosheet 21a of transistor P1 in the Y and Z directions, and the outer periphery of nanosheet 26a of transistor N1 in the Y and Z directions, via a gate insulating film (not shown). Gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0048] Dummy gate wirings 32a and 32b are formed on the cell frames at both ends in the X direction in the P-type transistor region. Dummy gate wirings 33a and 33b are formed on the cell frames at both ends in the X direction in the N-type transistor region. Dummy gate wirings 32a and 33a are shared with other cells on the left side of the drawing. Dummy gate wirings 32b and 33b are shared with other cells on the right side of the drawing.

[0049] The local wiring layer includes local wirings 41a, 41b, and 41c extending in the Y direction. Local wiring 41a is connected to the portion of the active region 2P that serves as the source of transistor P1. Local wiring 41b is connected to the portion of the active region 2N that serves as the source of transistor N1. Local wiring 41c extends from the P-type transistor region to the N-type transistor region and is connected to both the portion of the active region 2P that serves as the drain of transistor P1 and the portion of the active region 2N that serves as the drain of transistor N1.

[0050] Metal wiring 51 and 52 extending along the X direction are formed in the M0 wiring layer, a metal wiring layer located above the local wiring layer. Metal wiring 51 is connected to gate wiring 31 via a via. Metal wiring 52 is connected to local wiring 41c via a via. Metal wiring 51 corresponds to node A, and metal wiring 52 corresponds to node Y.

[0051] exist Figures 2 and 3 In the inverter cell shown, power supply wiring 11 supplying VDD and power supply wiring 12 supplying VSS are arranged in the Y direction with minimal spacing on the BM0 layer. When viewed from above, power supply wiring 11 overlaps with the active region 2P of the P-type transistor; power supply wiring 12 overlaps with the active region 2N of the N-type transistor. No wiring can be routed between power supply wiring 11 and power supply wiring 12 on the BM0 layer. This maximizes the width of the power supply wiring within the cell, effectively suppressing power supply voltage drops and preventing problems such as circuit malfunction.

[0052] Furthermore, in the block-level layout design, as described above, power supply wiring extending in the Y direction is placed in the BM1 layer, the layer below the BM0 layer. Power supply wiring 11 is connected to the VDD power supply wiring of the BM1 layer via a via, and power supply wiring 12 is connected to the VSS power supply wiring of the BM1 layer via a via.

[0053] It should be noted that while the power supply wiring 11 and 12 are formed in a wiring layer located on the back side of the semiconductor chip, this is not limiting. In this disclosure, the power supply wiring can be formed on the back side of the transistor. The back side of a transistor refers to the side of the transistor opposite to the side where the local wiring, metal wiring, and other layers connected to the transistor are stacked.

[0054] The power supply wirings 11 , 12 may be formed in a plurality of wiring layers.

[0055] (Other structural examples)

[0056] The power supply wiring formed on the back surface side of the transistor may be formed using a semiconductor chip different from the semiconductor chip forming the transistor.

[0057] Figure 5 (a) is another configuration example of the semiconductor integrated circuit device according to the embodiment. Figure 5 The semiconductor integrated circuit device 100 shown in (a) is constructed by stacking a first semiconductor chip 101 (chip A) and a second semiconductor chip 102 (chip B). Chip A is equipped with standard cells, including the inverter cell described above. Chip B has power supply wiring formed in a wiring layer provided on the surface. Chip B is bonded to the back side of chip A using bumps or the like.

[0058] Figure 5 (b) shows the structure of this example, along Figure 2 The cross section of the inverter unit is taken along the line Y1-Y1'. Figure 5 As shown in (b), power supply wiring 11 for supplying VDD and power supply wiring 12 for supplying VSS are formed in the wiring layer provided on the surface of chip B. Power supply wiring 11 is connected to active area 2P of chip A via via 61. Power supply wiring 12 is connected to active area 2N of chip A via via 62.

[0059] This structural example also achieves the same functions and effects as the inverter unit described above. It should be noted that, in this structural example, power supply wiring 11 and 12 can also be formed in multiple wiring layers. Furthermore, in this structural example, the power supply wiring of the BM1 layer and the layers below it are also formed in chip B.

[0060] <Two-input NAND gate unit and two-input NOR gate unit>

[0061] Figure 6 is a plan view showing an example of a layout structure of cells included in a semiconductor integrated circuit device according to an embodiment. Figure 6 (a) is a two-input NAND gate unit, Figure 6 (b) is a two-input NOR gate unit. Figure 7 (a) is the circuit diagram of a two-input NAND gate unit. Figure 7 (b) is the circuit diagram of a two-input NOR gate unit.

[0062] against Figure 6 The layout structure of the inverter unit can be easily understood from Figure 7 The circuit diagram class is introduced, so the detailed description is omitted here.

[0063] exist Figure 6 In the two-input NAND gate cell shown in (a), power supply wiring 11 supplying VDD and power supply wiring 12 supplying VSS are arranged in the Y direction with minimal spacing in the BM0 layer. Power supply wiring 11 overlaps with the active region 2P1 of the P-type transistor when viewed from above, while power supply wiring 12 overlaps with the active region 2N1 of the N-type transistor when viewed from above.

[0064] exist Figure 6 In the two-input NOR gate cell shown in (b), also on the BM0 layer, power supply wiring 11 supplying VDD and power supply wiring 12 supplying VSS are arranged in the Y direction with minimal spacing. When viewed from above, power supply wiring 11 overlaps with active region 2P2 of the P-type transistor, while power supply wiring 12 overlaps with active region 2N2 of the N-type transistor.

[0065] exist Figure 6 The two-input NAND gate unit shown in (a) and Figure 6 In the two-input NOR gate cell shown in (b), the power supply wiring width in the cell can also be maximized, so that the power supply voltage drop can be suppressed, thereby avoiding problems such as malfunction of the circuit.

[0066] Figure 8 yes Figure 1 An enlarged view of section A1 in the block-level layout is shown. Figure 8 In the structure shown, the inverter unit C1, the two-input NAND gate unit C2, and the two-input NOR gate unit C3 are arranged in order from the left side of the figure. The layout structure of each unit C1, C2, and C3 is as described above.

[0067] The BM1 layer has power supply lines 71, 72, and 73 extending in the Y direction. Power supply lines 71 and 73 supply power supply voltage VDD, while power supply line 72 supplies power supply voltage VSS. Power supply lines 71 and 73 are connected to power supply line 11 via vias 81. Power supply line 72 is connected to power supply line 12 via vias 81.

[0068] In inverter cell C1, active regions 2P and 2N overlap with power supply wiring 71 in plan view. In two-input NAND gate cell C2, active regions 2P1 and 2N1 overlap with power supply wiring 71 and power supply wiring 72 in plan view. In two-input NOR gate cell C3, active regions 2P2 and 2N2 overlap with power supply wiring 72 and power supply wiring 73 in plan view.

[0069] like Figure 8 As shown, inverter cell C1 includes an active area 2P and a power supply line 11 extending in the X direction. Power supply line 11 is formed on the back side of the transistor and overlaps with active area 2P when viewed from above. Furthermore, power supply line 71 extending in the Y direction is formed in a wiring layer below power supply line 11. Power supply line 71 is connected to power supply line 11 via a via 81 and overlaps with active area 2P when viewed from above.

[0070] The two-input NAND gate cell C2 includes an active area 2N1 and a power supply wiring 12 extending in the X direction. Power supply wiring 12 is formed on the back side of the transistor and overlaps with the active area 2N1 when viewed from above. Furthermore, a power supply wiring 72 extending in the Y direction is formed in a wiring layer below power supply wiring 12. Power supply wiring 72 is connected to power supply wiring 12 via a via 81 and overlaps with the active area 2N1 when viewed from above.

[0071] The two-input NOR gate cell C3 includes an active area 2P2 and a power supply wiring 11 extending in the X direction. Power supply wiring 11 is formed on the back side of the transistor and overlaps with the active area 2P2 when viewed from above. Furthermore, a power supply wiring 73 extending in the Y direction is formed in a wiring layer below power supply wiring 11. Power supply wiring 73 is connected to power supply wiring 11 via a via 81 and overlaps with the active area 2P2 when viewed from above.

[0072] As described above, according to this embodiment, power supply wiring can be arranged at a high density on the back surface side of the transistor, and thus sufficient power supply capability can be ensured.

[0073] (Variation)

[0074] Figure 9 : is a top view showing an example of a block level layout according to a modification of the embodiment. Figure 9 The through holes are omitted in the figure. Figure 1 The power supply wiring for supplying VDD formed in the BM0 layer and the BM1 layer is connected by a through-hole formed in an overlapping portion when viewed from above, and the power supply wiring for supplying VSS formed in the BM0 layer and the BM1 layer is connected by a through-hole formed in an overlapping portion when viewed from above.

[0075] exist Figure 9In the block-level layout shown in (a), the power supply wiring in the BM0 layer is not shared between adjacent cell rows along the Y direction. Furthermore, in the BM0 layer, the spacing between the power supply wiring for VDD and the power supply wiring for VSS is the minimum spacing constrained by the manufacturing process.

[0076] exist Figure 9 In (b), each cell row is not flipped in the Y direction, and each cell is arranged in the same direction. Figure 9 As in (a), the power supply wiring in the BM0 layer is not shared between adjacent cell rows along the Y direction. Moreover, in the BM0 layer, the spacing between the power supply wiring for VDD and the power supply wiring for VSS is the minimum spacing restricted by the manufacturing process.

[0077] Figure 10 It shows the composition Figure 9 A diagram of the layout structure of a block-level layout unit. Figure 10 (a) shows the inverter unit, Figure 10 (b) shows a two-input NAND gate unit, Figure 10 (c) shows a two-input NOR gate unit.

[0078] Figure 10 The structure of the inverter unit in (a) is basically the same as Figure 2 The inverter cells in FIG. 1 are the same. However, the width of the power supply wirings 11A and 12A in the Y direction is smaller than the width of the power supply wirings 11 and 12 in the Y direction. In addition, there is a gap between the cell frame on the upper side of the drawing and the power supply wiring 11A, and there is a gap between the cell frame on the lower side of the drawing and the power supply wiring 12A. This gap is, for example, equivalent to 1 / 2 of the minimum gap restricted by the manufacturing process. In addition, Figure 10 In the structure of (a), the width of Nwell and Psub in the Y direction is less than Figure 2 The width of Nwell and Psub in the Y direction of the structure.

[0079] Figure 10 The two-input NAND gate unit in (b) and Figure 10 The structures of the two-input NOR gate units in (c) are respectively Figure 6 The two-input NAND gate unit in (a) and Figure 6 The two-input NOR gate cell in (b) is basically the same. However, like the inverter cell, the width of the power supply wiring 11A and 12A in the Y direction is smaller than the width of the power supply wiring 11 and 12 in the Y direction. In addition, there is a gap between the cell frame on the upper side of the figure and the power supply wiring 11A, and there is a gap between the cell frame on the lower side of the figure and the power supply wiring 12A. This gap is equivalent to, for example, 1 / 2 of the minimum gap restricted by the manufacturing process. In addition, Figure 10In the structures shown in (b) and (c), the width of Nwell and Psub in the Y direction is smaller than Figure 6 The widths of Nwell and Psub in the Y direction in the structures shown in (a) and (b).

[0080] It should be noted that in the above embodiments, the nanosheet is formed by overlapping three sheet structures in a plan view, and the cross-sectional shape of the sheet structure is shown as a rectangle. However, the number of sheet structures and the cross-sectional shape of the nanosheet are not limited to this.

[0081] In addition, in the above embodiments, the transistor is a nanosheet FET, but the present invention is not limited thereto and may be, for example, a fin FET or other types of transistors.

[0082] Industrial Applicability

[0083] The present disclosure provides a layout structure capable of sufficiently ensuring power supply capability for a semiconductor integrated circuit device having a structure in which multilayer wiring is provided on the back side of a transistor. Therefore, the present disclosure is useful, for example, for reducing the cost and improving the performance of the semiconductor integrated circuit device.

[0084] - Explanation of symbols -

[0085] 11.12 Power supply wiring

[0086] 21a, 26a nanosheets

[0087] 71, 72, 73 Power supply wiring

[0088] 100 Semiconductor integrated circuit devices

[0089] 101 First Semiconductor Chip

[0090] 102 second semiconductor chip

[0091] 2P, 2P1, 2P2 active area

[0092] 2N, 2N1, 2N2 active areas

[0093] C1, C2, C3 standard cells

[0094] CR unit row.

Claims

1. A semiconductor integrated circuit device, characterized in that: The semiconductor integrated circuit device includes a plurality of cell rows, each of the cell rows including a plurality of standard cells arranged along a first direction. One of the plurality of cell rows, namely a first cell row, includes a first standard cell, The first standard cell includes a first active area and a first power wiring, The first active region constitutes a channel, a source, and a drain of a first transistor of a first conductivity type, and the first active region includes a first nanosheet extending along the first direction as the channel. The first power supply wiring is formed on the back side of the first transistor, extends along the first direction, overlaps with the first active region in a plan view, and supplies a first power supply voltage. The semiconductor integrated circuit device includes a second power supply wiring, The second power supply wiring is formed in a wiring layer lower than the first power supply wiring, extends in a second direction perpendicular to the first direction, and supplies the first power supply voltage. The second power supply wiring has an overlapping portion with the first active region in a plan view, and is connected to the first power supply wiring via a through-hole.

2. The semiconductor integrated circuit device according to claim 1, wherein: The first standard cell includes a second active area, The second active region constitutes a channel, a source, and a drain of a second transistor of a second conductivity type, and the second active region includes a second nanosheet extending along the first direction and serving as the channel. The second power supply wiring has an overlapping portion with the second active region in a plan view.

3. The semiconductor integrated circuit device according to claim 1, wherein: The semiconductor integrated circuit device includes a third power supply wiring formed in the same wiring layer as the second power supply wiring, extending along the second direction, and supplying a second power supply voltage. The third power supply wiring has an overlapping portion with the first active region in a plan view.

4. The semiconductor integrated circuit device according to claim 1, wherein: The first power supply wiring and the second power supply wiring are formed in a wiring layer provided in a first semiconductor chip in which the first active region is formed.

5. The semiconductor integrated circuit device according to claim 1, wherein: The first power supply wiring and the second power supply wiring are formed in a wiring layer provided in a second semiconductor chip, and the second semiconductor chip is bonded to the back surface side of the first semiconductor chip in which the first active region is formed.

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