A high-temperature-resistant piezoresistive pressure sensor chip and a processing method thereof

Abstract

The application relates to the technical field of pressure sensors, in particular to a high-temperature-resistant piezoresistive pressure sensor chip and a processing method. The high-temperature-resistant piezoresistive pressure sensor chip comprises a device layer, a buried oxygen layer, a support layer and a sealing base layer, and the buried oxygen layer and the device layer are sequentially arranged on the support layer; wherein the device layer comprises a piezoresistor and a wire, the piezoresistor and the wire are arranged on the buried oxygen layer, and a metal pad is arranged on the wire; the piezoresistor and the wire are made of P-type silicon material or N-type silicon material with a doping concentration greater than 10 14 cm ‑3 ; the sealing base layer is connected with the device layer, and a reference pressure cavity is formed between the sealing base layer and the device layer; or the sealing base layer is connected with the side, away from the device layer, of the support layer, and a reference pressure cavity is formed between the sealing base layer and the support layer. The application improves the processing efficiency of the high-temperature-resistant piezoresistive pressure sensor chip and improves the electrical stability of the chip in a high-temperature environment.

Description

Technical Field

[0001] This invention relates to the field of pressure sensor technology, specifically to a high-temperature resistant piezoresistive pressure sensor chip and its fabrication method. Background Technology

[0002] A high-temperature pressure sensor is a device capable of accurately measuring pressure parameters in environments exceeding 200°C. As industrial technology advances towards high-temperature, high-precision pressure measurement, the importance of these sensors in fields such as aerospace, energy, chemical engineering, and nuclear energy is increasingly prominent. High-temperature pressure sensors act as the "nerve endings" connecting high-temperature environments to digital control systems, and their technological advancements directly determine the reliability, energy efficiency, and safety of industrial equipment.

[0003] Early pressure sensors were primarily based on the silicon-based piezoresistive effect. However, silicon has a narrow bandgap, and when the temperature exceeds 150°C, silicon-based sensors suffer from signal distortion or even failure due to intrinsic carrier excitation. To overcome this limitation, wide-bandgap semiconductor materials such as silicon carbide, sapphire, and aluminum nitride have been used to manufacture high-temperature pressure sensors. However, due to limitations in processing technology and cost, mass production of high-temperature pressure sensor chips has not yet been achieved. The maturity of silicon-on-insulator (SiI) technology has further propelled the development of high-temperature pressure sensors.

[0004] However, in the existing methods for fabricating high-temperature pressure sensors based on ion implantation and thermal diffusion, the core fabrication process, ion implantation, includes multiple auxiliary micromachining processes such as photolithography, overlay shielding layer etching, etching, and annealing. Because of these additional processing steps, the superposition of multiple micromachining steps, such as multiple photolithography, etching, ion implantation, and annealing steps, each step can introduce certain process errors. The more process steps there are, the lower the overall yield of the device, leading to low production efficiency and increased costs. Simultaneously, the complex process requires stricter environmental control (such as cleanliness, temperature, and humidity), further increasing production costs and reducing the efficiency of high-temperature pressure sensor fabrication. Furthermore, high-temperature pressure sensor chips fabricated using traditional ion implantation methods suffer from poor ion distribution uniformity and low activation rates of doped elements, resulting in poor consistency in piezoresistive molding. Moreover, because traditional methods use a step-by-step ion doping approach, such as phosphorus first and then boron in P-type piezoresistors, mutual compensation occurs between donor and acceptor impurities, leading to unstable carrier concentrations. Especially at high temperatures, the different ionization degrees between the two impurities and their carried carriers result in significant resistivity variations. Therefore, the high-temperature pressure chips prepared by existing methods have poor electrical stability in high-temperature environments.

[0005] Therefore, there is a need to provide a high-temperature resistant piezoresistive pressure sensor chip and its fabrication method to solve the above problems. Summary of the Invention

[0006] This invention provides a high-temperature resistant piezoresistive pressure sensor chip and its processing method to solve existing problems.

[0007] The first aspect of this invention provides a high-temperature resistant piezoresistive pressure sensor chip employing the following technical solution:

[0008] A support layer, on which a buried oxide layer and a device layer are sequentially disposed;

[0009] The device layer includes a piezoresistor and conductive lines, with metal pads on the conductive lines; the piezoresistor and conductive lines are doped with a doping concentration greater than 10%. 14 cm -3 P-type silicon materials or N-type silicon materials;

[0010] And a sealing substrate layer, wherein the sealing substrate layer and the device layer are connected and a reference pressure cavity is formed between them, or the sealing substrate layer and the support layer are connected on the side away from the device layer and a reference pressure cavity is formed between them.

[0011] In a further technical solution of the present invention, the support layer includes: a silicon substrate, an annular cavity is provided on the side of the silicon substrate away from the buried oxide layer, a boss is formed inside the annular cavity, and a silicon thin film is formed between the inner bottom surface of the annular cavity and the surface of the buried oxide layer connecting the support layer.

[0012] In a further technical solution of the present invention, the thickness of the silicon thin film is greater than twice the thickness of the buried oxide layer.

[0013] In a further technical solution of the present invention, the center line of the piezoresistor in the device layer and the cavity wall of the annular cavity on the support layer are collinear.

[0014] In a further technical solution of the present invention, the thickness of the device layer is 0.2μm~10μm, the thickness of the buried oxide layer is 0.2~5μm, and the thickness of the support layer is 200μm~1000μm.

[0015] A further technical solution of the present invention includes a sealing substrate comprising a glass substrate, wherein a cavity is formed on the glass substrate, and the cavity side of the glass substrate is connected to the device layer to form a reference pressure cavity, or the cavity side of the glass substrate is connected to the side of the support layer away from the device layer to form a reference pressure cavity, wherein the cavity depth on the sealing substrate is greater than 50 μm.

[0016] A second aspect of the present invention provides a method for fabricating a high-temperature resistant piezoresistive pressure sensor chip, comprising:

[0017] P-type or N-type silicon wafers with a set doping concentration are formed using in-situ doping; the set doping concentration is greater than 10. 14 cm -3The N-type silicon wafer or P-type silicon wafer is used as the wafer corresponding to the device layer; silicon and silicon oxide are used to make the wafer corresponding to the support layer; the wafer corresponding to the support layer is dry oxidized to form the wafer corresponding to the buried oxide layer; the side of the wafer corresponding to the buried oxide layer away from the support layer is bonded to the wafer corresponding to the device layer to obtain the SOI wafer.

[0018] Piezoresistors and wires are fabricated on the surface of the wafer corresponding to the device layer in the SOI wafer;

[0019] In an SOI wafer, a ring-shaped cavity is machined on the wafer surface opposite to the conductor to form a boss;

[0020] Metal pads are formed by sputtering metal onto the conductors of the device layer.

[0021] A cavity is fabricated on a glass substrate with a sealing substrate layer, and the cavity surface of the glass substrate and the annular cavity surface of the SOI wafer are bonded together to form a pressure sensor chip.

[0022] A further technical solution of the present invention includes the step of sputtering metal onto a conductor to form a metal pad:

[0023] Cr, Pt and Au materials are sputtered sequentially onto the conductor to form metal pads;

[0024] Alternatively, Cr, TiN, and Au materials can be sputtered sequentially onto the conductor to form a metal pad.

[0025] A further technical solution of the present invention is characterized in that a piezoresistor and a wire are processed on the upper surface of the SOI wafer by dry etching or wet etching, wherein the thickness of the piezoresistor and the wire is the wafer thickness corresponding to the device layer.

[0026] A third aspect of the present invention provides another method for fabricating a high-temperature resistant piezoresistive pressure sensor chip, comprising:

[0027] P-type or N-type silicon wafers with a set doping concentration are formed using in-situ doping; the set doping concentration is greater than 10. 14 cm -3 The N-type silicon wafer or P-type silicon wafer is used as the wafer corresponding to the device layer; silicon and silicon oxide are used to make the wafer corresponding to the support layer; the wafer corresponding to the support layer is dry oxidized to form the wafer corresponding to the buried oxide layer; the side of the wafer corresponding to the buried oxide layer away from the support layer is bonded to the wafer corresponding to the device layer to obtain the SOI wafer.

[0028] Piezoresistors and wires are fabricated on the surface of the wafer corresponding to the device layer in the SOI wafer;

[0029] In an SOI wafer, a ring-shaped cavity is machined on the wafer surface opposite to the conductor to form a boss;

[0030] A cavity is fabricated on the glass substrate of the sealing substrate layer, the cavity surface of the glass substrate is bonded to the piezoresistive surface of the SOI wafer, and a through hole for connecting wires is set in the glass substrate.

[0031] Metal bonding pads are formed by sputtering metal onto the inner wall of the through hole and the wires to obtain the pressure sensor chip.

[0032] The beneficial effects of this invention are:

[0033] By designing the device layer and using P-type or N-type silicon material with a set doping concentration, the lattice integrity, uniformity of doping distribution, and low defect state density are improved by using in-situ doping technology during silicon growth. The carrier concentration in the piezoresistor is relatively stable at high temperatures, thus significantly improving the electrical stability of the piezoresistor at high temperatures.

[0034] Secondly, in the fabrication method of the high-temperature piezoresistive pressure sensor chip, an in-situ doping method is used to form a P-type silicon wafer or an N-type silicon wafer with a set doping concentration. This P-type or N-type silicon wafer is then used as the device layer wafer, on which the piezoresistor and wires are fabricated. This invention's fabrication method only requires two steps: in-situ doping to prepare the device layer wafer and etching the piezoresistor and wires onto it. Traditional ion implantation and thermal diffusion processes typically produce wires and piezors by first phosphorus and then boron. This leads to mutual compensation between donor and acceptor impurities within the piezoresistor, resulting in unstable carrier concentrations. Especially at high temperatures, the different ionization levels of the two impurities and their carried carriers cause significant resistivity variations. However, the in-situ doping method proposed in this invention uses only phosphorus or boron. With single-element doping, there is no such compensation effect; the carrier concentration is primarily determined by the concentration of the single impurity. This improves lattice integrity, the uniformity of doping distribution, and reduces the low defect state density of the crystal, significantly enhancing the electrical stability of the piezoresistor at high temperatures. In addition, this invention patent uses in-situ doping and etching technologies to replace ion implantation and thermal diffusion technologies, avoiding the associated multiple photolithography, etching, ion implantation, and annealing processes, reducing cumulative process errors, thereby improving the processing efficiency of high-temperature piezoresistive pressure sensor chips, and improving the electrical stability of the chips in high-temperature environments. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the SOI wafer structure of a high-temperature piezoresistive pressure sensor chip according to an embodiment of the present invention;

[0037] Figure 2 In order to be in Figure 1 A schematic diagram of a piezoresistor and wires fabricated on an SOI wafer;

[0038] Figure 3 This is a schematic diagram of the overall structure of a high-temperature piezoresistive pressure sensor chip according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic flowchart of Embodiment 1 of the processing method of a high-temperature piezoresistive pressure sensor chip according to the present invention;

[0040] Figure 5 This is a schematic flowchart of Embodiment 2 of the processing method of a high-temperature piezoresistive pressure sensor chip according to the present invention;

[0041] Figure 6 The bottom noise result of the high-temperature piezoresistive pressure sensor chip prepared according to an embodiment of the present invention at a high temperature of 200°C is shown in the figure.

[0042] Figure 7 The bottom noise result of the high-temperature piezoresistive pressure sensor chip fabricated by the existing ion implantation process at a high temperature of 200℃ is shown in the figure.

[0043] In the diagram: 1. Device layer; 2. Buried oxide layer; 3. Support layer; 4. Conductor; 5. Piezoresistor; 6. Silicon substrate; 7. Boss; 8. Metal pad; 9. Cavity; 10. Sealing substrate layer; 11. Through-hole. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] An embodiment of a high-temperature resistant piezoresistive pressure sensor chip of the present invention, such as... Figure 1 , Figure 2 and Figure 3 As shown, the sensor chip includes: a device layer 1, a buried oxide layer 2, a support layer 3, and a sealing substrate layer 10. The buried oxide layer 2 and the device layer 1 are sequentially disposed on the support layer 3 to form a structure as shown. Figure 1 The SOI wafer shown; wherein, a buried oxide layer 2 is disposed on the support layer 3 to form a sensitive thin film layer, such as Figure 2 As shown, in this embodiment, device layer 1 includes a piezoresistor 5 and a conductive line 4, which are disposed on the buried oxide layer 2. Metal pads 8 are disposed on the conductive line 4. The piezoresistor 5 and the conductive line 4 are doped with a doping concentration greater than or equal to 10. 14 cm -3 The silicon material is either P-type or N-type; wherein the sealing substrate layer 10 and the support layer are connected on the side opposite to the device layer 1, and a reference pressure cavity is formed between them, or the sealing substrate layer 10 and the device layer 1 are connected, and a reference pressure cavity is formed between them, such as... Figure 3 As shown, in this embodiment, the sealing base layer 10 and the support layer are connected on the side away from the device layer 1, and a reference pressure cavity is formed between the two.

[0046] For example, such as Figure 2 As shown, in one specific embodiment, the support layer 3 includes: a silicon substrate 6, an annular cavity formed on the side of the silicon substrate 6 opposite to the buried oxide layer 2, a boss 7 formed inside the annular cavity, and a silicon thin film formed between the inner bottom surface of the annular cavity and the surface of the buried oxide layer 2 connecting the support layer 3, the thickness of the silicon thin film being 1μm~100μm; the center line of the piezoresistor 5 of the device layer 1 and the cavity wall of the cavity 9 on the support layer 3 are collinear; the thickness of the silicon thin film is greater than twice the thickness of the buried oxide layer 2. Specifically, in this embodiment, the thickness of the silicon thin film is three times the thickness of the buried oxide layer 2.

[0047] For example, in one specific embodiment, the thickness of device layer 1 is 0.2μm~10μm, the thickness of buried oxide layer 2 is 0.2μm~5μm, and the thickness of support layer 3 is 200μm~1000μm; the resistivity of device layer 1 is less than or equal to 100Ω·cm, and the resistivity of support layer 3 is less than or equal to 100Ω·cm.

[0048] For example, in one specific embodiment, the sealing substrate 10 includes a glass substrate, on which a cavity 9 is formed. The cavity side of the glass substrate is connected to the device layer 1 to form a reference pressure cavity, or the cavity side of the glass substrate is connected to the side of the support layer away from the device layer 1 to form a reference pressure cavity. The depth of the cavity 9 on the sealing substrate 10 is 1μm to 100μm.

[0049] This invention provides an embodiment 1 of a method for fabricating a high-temperature resistant piezoresistive pressure sensor chip, as shown below. Figure 4As shown, the processing method of Example 1 includes:

[0050] S1. Fabrication of SOI wafers;

[0051] Specifically, in-situ doping is used to form P-type or N-type silicon wafers with a set doping concentration; the set doping concentration is greater than 10. 14 cm -3 The N-type or P-type silicon wafer is used as the wafer corresponding to device layer 1; a wafer corresponding to support layer 3 is fabricated using silicon and silicon oxide; the wafer corresponding to support layer 3 is dry-oxidized to form the wafer corresponding to buried oxide layer 2 on the wafer of support layer 3; the side of the wafer corresponding to buried oxide layer 2 facing away from support layer 3 is bonded to the wafer corresponding to device layer 1 to obtain the wafer as shown in the figure. Figure 1 The SOI wafer shown.

[0052] For example, in one specific embodiment, a P-type silicon wafer with a set doping concentration is formed by in-situ doping; that is, boron is used as a dopant to form a P-type silicon wafer in this embodiment.

[0053] For example, in a specific embodiment, the wafer corresponding to the support layer 3 is subjected to dry oxidation to form silicon oxide covering the wafer corresponding to the support layer 3, and the silicon oxide on the wafer corresponding to the support layer 3 is removed by wet etching process, leaving only the silicon oxide on one surface as the wafer corresponding to the buried oxide layer 2.

[0054] For example, in one specific embodiment, the wafer thickness corresponding to device layer 1 is less than the total wafer thickness of support layer 3 and buried oxide layer 2.

[0055] S2, Device layer etching;

[0056] Specifically, piezoresistors and wires are fabricated on the surface of the wafer corresponding to the device layer.

[0057] For example, in one specific embodiment, a piezoresistor 5 and a wire 4 are processed on the upper surface of the SOI wafer by dry etching or wet etching. The thickness of the piezoresistor 5 and the wire 4 is the wafer thickness corresponding to the device layer 1. Specifically, in this embodiment, the piezoresistor 5 and the wire 4 are processed on the upper surface of the SOI wafer by dry etching.

[0058] S3, Etching of the support layer;

[0059] Specifically, an annular cavity is machined on the wafer surface opposite to the conductor 4 corresponding to the support layer 3 to form a boss.

[0060] For example, in one specific embodiment, an annular cavity is processed on the lower surface of the SOI wafer by dry etching or wet etching, a boss 7 is formed inside the annular cavity, and a silicon thin film is formed between the inner bottom surface of the annular cavity and the connection surface between the buried oxide layer 2 and the support layer 3.

[0061] S4. Metal sputtering onto the conductor;

[0062] Specifically, metal is sputtered onto the conductor 4 of the device layer to form a metal pad 8.

[0063] For example, in one specific embodiment, the step of sputtering bonding metal to form metal pads 8 on the conductor 4 is as follows: Cr, Pt, and Au materials are sputtered sequentially on the conductor 4 to form metal pads 8; or Cr, TiN, and Au materials are sputtered sequentially on the conductor 4 to form metal pads 8. In this embodiment, Cr, Pt, and Au materials are sputtered sequentially on the conductor 4 to form metal pads 8.

[0064] S5, bonding support layer and sealing substrate layer;

[0065] Specifically, a cavity 9 is fabricated on the glass substrate of the sealing substrate layer 10, and the surface of the cavity 9 on the glass substrate and the surface of the annular cavity on the SOI wafer are anodicly bonded, that is, the cavity 9 on the glass substrate is sealed to realize the preparation of the reference pressure chamber and form a pressure sensor chip.

[0066] This invention provides a second embodiment of a method for fabricating a high-temperature resistant piezoresistive pressure sensor chip, as shown below. Figure 5 As shown, the processing method of Example 1 includes:

[0067] S1. Fabrication of SOI wafers;

[0068] Specifically, in-situ doping is used to form P-type or N-type silicon wafers with a set doping concentration; the set doping concentration is greater than 10. 14 cm -3 The process involves using an N-type silicon wafer or a P-type silicon wafer as the wafer corresponding to device layer 1; fabricating the wafer corresponding to support layer 3 using silicon and silicon oxide; performing dry oxidation on the wafer corresponding to support layer 3 to form the wafer corresponding to buried oxide layer 2; and bonding the side of the wafer corresponding to buried oxide layer 2 away from support layer 3 to the wafer corresponding to device layer 1 to obtain an SOI wafer.

[0069] For example, in one specific embodiment, a P-type silicon wafer with a set doping concentration is formed by in-situ doping; that is, boron is used as a dopant to form a P-type silicon wafer in this embodiment.

[0070] For example, in a specific embodiment, the wafer corresponding to the support layer 3 is subjected to dry oxidation to form silicon oxide covering the wafer corresponding to the support layer 3, and the silicon oxide on the wafer corresponding to the support layer 3 is removed by wet etching process, leaving only the silicon oxide on one surface as the wafer corresponding to the buried oxide layer.

[0071] S2, Device layer etching;

[0072] Specifically, piezoresistors and wires are fabricated on the surface of the wafer corresponding to the device layer.

[0073] For example, in one specific embodiment, a piezoresistor 5 and a wire 4 are processed on the upper surface of the SOI wafer by dry etching or wet etching. The thickness of the piezoresistor 5 and the wire 4 is the wafer thickness corresponding to the device layer 1. Specifically, in this embodiment, the piezoresistor 5 and the wire 4 are processed on the upper surface of the SOI wafer by dry etching.

[0074] S3, Etching of the support layer;

[0075] Specifically, an annular cavity is machined on the wafer surface opposite to the conductor 4 corresponding to the support layer 3 to form a boss.

[0076] For example, in one specific embodiment, an annular cavity is processed on the lower surface of the SOI wafer by dry etching or wet etching, a boss 7 is formed inside the annular cavity, and a silicon thin film is formed between the inner bottom surface of the annular cavity and the connection surface between the buried oxide layer 2 and the support layer 3.

[0077] S4, bonding support layer and sealing substrate layer;

[0078] Specifically, a cavity 9 is fabricated on the glass substrate of the sealing substrate layer 10, and the surface of the cavity on the glass substrate and the surface of the piezoresistor 5 on the SOI wafer are anoly bonded, that is, the cavity 9 of the glass substrate is sealed to realize the preparation of the reference pressure cavity, and a through hole 11 for connecting wires is set on the glass substrate.

[0079] S5, Metal sputtering onto the conductor;

[0080] Specifically, metal is sputtered onto the inner wall of the through hole 11 and the wire 4 to form a metal pad 8, thus obtaining the pressure sensor chip.

[0081] For example, in one specific embodiment, the step of sputtering the bonding metal on the conductor 4 to form a metal pad is as follows: Cr, Pt, and Au materials are sputtered sequentially on the conductor 4 to form a metal pad 8; or Cr, TiN, and Au materials are sputtered sequentially on the conductor 4 to form a metal pad 8. In this embodiment, Cr, TiN, and Au materials are sputtered sequentially on the conductor 4 to form the metal pad 8. Specifically, in this embodiment, photoresist protection is first applied to the etched device layer 1 to reveal the location of the conductor 4 where the bonding metal needs to be sputtered. Cr, TiN, and Au materials are then sputtered sequentially in the exposed area using sputtering or vapor deposition to form the metal pad 8. Finally, ohmic contact between the metal pad 8 and the conductor 4 of the semiconductor silicon is achieved through rapid annealing or conventional annealing processes.

[0082] It should be noted that during the process of processing the cavity 9 on the glass substrate of the sealing base layer 10 in step S5 of Example 1 and step S4 of Example 2, the cavity 9 with a depth of 1~100μm is formed by laser etching, spray etching or wet etching on the glass substrate. In the bonding process of step S5 of Example 1 or step S4 of Example 2, this cavity 9 corresponds to the annular cavity of the support layer 3. After standard RCA cleaning is performed on the etched glass substrate, oxygen cleaning is performed. After aligning the cavity 9 with the annular cavity of the support layer 3, anodic bonding is performed.

[0083] Secondly, in step S2 of Examples 1 and 2, the excess silicon wafer from the wafer of device layer 1 to the surface of buried oxide layer 2 is etched away by top-layer etching until the remaining silicon wafer is etched into a resistor with a set resistance value and a wire 4 connecting the resistor. The resistor is directly used as the piezoresistor 5 of the pressure sensor chip for pressure measurement. There is no need to perform ion implantation or ion diffusion process again. At the same time, it avoids the multi-step auxiliary process of processing, etching and annealing of the shielding layer twice in the prior art.

[0084] According to the carrier migration theory of solid-state semiconductors, the phonon vibrations of piezoresistor 5 intensify at high temperatures, increasing the scattering probability and leading to a decrease in carrier mobility within piezoresistor 5. Therefore, the resistance of piezoresistor 5 gradually increases with increasing temperature. Existing ion implantation techniques introduce lattice defects due to high-energy ion bombardment, increasing the number of scattering centers. Mutual compensation occurs between donor and acceptor impurities, resulting in unstable carrier concentration. Especially at high temperatures, the different degrees of ionization between the two impurities and their carried carriers lead to significant resistivity variations. In contrast, in-situ doping sources are uniformly integrated into the lattice during material growth, resulting in fewer defects, weaker lattice scattering, and slower mobility decay at high temperatures. There is no mutual compensation between donor and acceptor impurities, leading to more stable carrier concentration and therefore smaller resistance variations. Therefore, piezoresistors prepared by in-situ doping and dry etching methods exhibit better electrical stability at high temperatures.

[0085] The invention will be further explained below with reference to specific simulation data:

[0086] First, a high-temperature resistant pressure sensor chip was designed. To fabricate the high-temperature resistant pressure sensor chip, the silicon-on-insulator (SiInsulator) device layer 1 was designed with a thickness of 2 μm, a resistivity of 0.05 Ω·cm, and an in-situ boron doping concentration of 2 × 10⁻⁶. 19 cm -3 The thickness of the intermediate buried oxygen layer 2 is 2μm, the thickness of the support layer 3 is 400μm, and the resistivity is 10Ω·cm.

[0087] Dry etching is used to etch a 2μm depth into the buried oxide layer 2 of device layer 1, removing excess material and leaving only the piezoresistor 5 and the conductive line 4. Dry etching is then used to etch away the 380μm thick material of the support layer 3, forming an annular cavity. The thickness of the silicon film between the inner bottom surface of the annular cavity and the contact surface between the buried oxide layer 2 and the support layer 3 is 20μm. This 20μm silicon film and the 2μm buried oxide layer 2 form a multilayer composite high-temperature pressure-sensitive film with a thickness of 22μm. Then, Cr, Pt, and Aμ multilayer metal sputtering is sequentially performed on the conductive line 4, with sputtering thicknesses of 20nm, 100nm, and 200nm, respectively. After annealing at 400℃, metal pads 8 are formed, achieving ohmic contact between the semiconductor conductive line 4 and the metal pads 8. A 100 μm deep cavity 9 was etched into a glass substrate using laser etching technology. After standard RCA cleaning and oxygen cleaning, the edge of the cavity 9 was aligned with the edge of the high-temperature pressure-sensitive film. The support layer 3 and the sealing substrate layer 10 were then vacuum anoly bonded to achieve the fabrication of a 0 kPa reference pressure chamber. The bottom noise result of the high-temperature pressure sensor chip fabricated in this embodiment at 200°C is shown in Figure 6; the bottom noise result of the high-temperature pressure sensor chip fabricated by ion implantation based on existing technology at 200°C is shown in Figure 6. Figure 7 As shown, comparison Figure 6 and Figure 7 The bottom noise of the ion implantation sensor chip based on the existing technology is 27μV at a high temperature of 200℃, while the bottom noise of the sensor chip based on in-situ doping is 12μV at a high temperature of 200℃. That is, the bottom noise of the present invention is significantly lower than that of the high temperature pressure sensor chip prepared by the traditional ion implantation technology.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a high-temperature resistant piezoresistive pressure sensor chip, characterized in that, include: P-type or N-type silicon wafers with a predetermined doping concentration are formed using in-situ doping with a single element; the predetermined doping concentration is greater than 10. 14 cm -3 The process involves: using an N-type or P-type silicon wafer as the wafer corresponding to the device layer; fabricating a wafer corresponding to the support layer using silicon and silicon oxide; dry oxidizing the wafer corresponding to the support layer to form a wafer corresponding to the buried oxide layer; bonding the side of the wafer corresponding to the buried oxide layer away from the support layer to the wafer corresponding to the device layer to obtain an SOI wafer; fabricating a piezoresistor and conductive lines on the surface of the wafer corresponding to the device layer in the SOI wafer; fabricating an annular cavity on the surface of the wafer corresponding to the support layer in the SOI wafer away from the conductive lines to form a boss; sputtering bonding metal onto the conductive lines of the device layer to form metal pads; fabricating a cavity on the glass substrate of the sealing substrate, and bonding the cavity surface of the glass substrate to the annular cavity surface of the SOI wafer to form a pressure sensor chip; and so on. Alternatively, after forming a boss by machining an annular cavity on the wafer surface opposite to the conductor in the support layer of the SOI wafer, a cavity is machined on the glass substrate of the sealing substrate layer. The cavity surface of the glass substrate is bonded to the piezoresistive surface of the SOI wafer, and a through hole is set in the glass substrate to connect the conductor. Metal bonding is sputtered on the inner wall of the through hole and on the conductor to form a metal pad, thus obtaining the pressure sensor chip. The pressure sensor chip includes a support layer, on which a buried oxide layer, a device layer, and a sealing substrate layer are sequentially disposed. The device layer includes a piezoresistor and conductive wires, with metal pads on the conductive wires. The piezoresistor and conductive wires are doped with a single element with a doping concentration greater than 10%. 14 cm -3 The silicon material is either P-type or N-type; the sealing substrate layer and the device layer are connected and form a reference pressure cavity between them, or the sealing substrate layer and the support layer are connected on the side away from the device layer and form a reference pressure cavity between them.

2. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 1, characterized in that, The support layer includes: A silicon substrate has an annular cavity on the side of the silicon substrate away from the buried oxide layer. A boss is formed inside the annular cavity, and a silicon thin film is formed between the inner bottom surface of the annular cavity and the surface of the buried oxide layer connecting the support layer.

3. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 2, characterized in that, The thickness of the silicon thin film is more than twice the thickness of the buried oxide layer.

4. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 2, characterized in that, The centerline of the piezoresistor in the device layer is collinear with the cavity wall of the annular cavity on the support layer.

5. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 2, characterized in that, The device layer thickness is 0.2μm~10μm, the buried oxide layer thickness is 0.2~5μm, and the support layer thickness is 200μm~1000μm.

6. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 1, characterized in that, The sealing substrate includes a glass substrate with a cavity formed thereon. The cavity side of the glass substrate is connected to the device layer to form a reference pressure cavity, or the cavity side of the glass substrate is connected to the side of the support layer away from the device layer to form a reference pressure cavity. The cavity depth on the sealing substrate is 1~100μm.

7. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 1, characterized in that, The steps for sputtering metal onto a conductor to form a metal pad are as follows: Cr, Pt and Au materials are sputtered sequentially onto the conductor to form metal pads; Alternatively, Cr, TiN, and Au materials can be sputtered sequentially onto the conductor to form a metal pad.

8. The method for fabricating a high-temperature resistant piezoresistive pressure sensor chip according to claim 1, characterized in that, Piezoresistors and wires are fabricated on the upper surface of SOI wafers using dry etching or wet etching methods, wherein the thickness of the piezoresistors and wires is the wafer thickness corresponding to the device layer.

Images