Testing device and testing method for chip dynamic failure analysis
By introducing a liquid cooling cover and optical observation equipment into the chip dynamic failure analysis test device, the contradiction between observation and heat dissipation caused by hardware modification was resolved, and low-cost chip dynamic failure analysis was achieved.
Patent Information
- Application Number
- CN202510704603.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-19
AI Technical Summary
Existing chip dynamic failure analysis test equipment requires overall hardware modification on the wafer test machine, and the hole design of the heat sink cannot take into account both observation and heat dissipation effects, resulting in high hardware costs and difficult observation.
A test device is designed, which includes a rack, a test mainboard, a substrate, a liquid cooling cover and an optical observation device. An observation window is opened on the top of the liquid cooling cover. By combining liquid cooling and optical observation, the heat dissipation and observation of the chip can be achieved, thereby reducing hardware costs.
It realizes simple chip dynamic failure analysis test, reduces hardware cost, and solves the problem of radiator blocking observation through the combination of liquid cooling and optical observation, thereby improving observation efficiency.
Smart Images
Figure CN120669091A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the technical field of chip failure analysis, and in particular to a test device and a test method for dynamic chip failure analysis. Background Art
[0002] The solution to chip failure is based on the combination of failure analysis strategies and hardware tools. In current chip failure analysis testing, the dynamic FA (Failure Analysis) solution is a common analysis strategy used by mainstream companies. Traditional chips generate a lot of heat when powered on or when a program is running. Therefore, a heat sink is often installed on the top of the chip. However, this heat sink will cause the chip to be obscured, making it impossible to observe.
[0003] Some test devices supporting dynamic FA failure analysis strategies are modified from wafer testers and equipped with the hardware failure analysis tool EMMI (Emission Microscope). This approach uses the machine's constant temperature plate to control temperature, while stimulating the chip with test signals. However, this comprehensive hardware modification solution based on the wafer tester is not only cumbersome but also requires holes in the heat dissipation cavity of the constant temperature plate for observation. If the holes are too small, observation is difficult, while if they are too large, they cannot achieve effective heat dissipation. Summary of the Invention
[0004] In view of this, the embodiments of the present application provide a test device and a test method for chip dynamic failure analysis, which implement a simple chip dynamic failure analysis test and reduce the hardware cost of chip dynamic failure analysis.
[0005] In a first aspect, an embodiment of the present application provides a test device for dynamic failure analysis of a chip, comprising: a rack, on which a test mainboard interface is configured; a test mainboard, which is arranged on the rack and electrically connected to the test mainboard interface on the rack; a substrate, which is arranged on the test mainboard and electrically connected to the test mainboard, and is provided with a test interface for connecting to a chip to be tested; a liquid cooling hood, which is arranged on the substrate, and a liquid cooling chamber capable of accommodating cooling liquid is formed between the liquid cooling hood and the substrate, and an observation window is provided on the top of the liquid cooling hood.
[0006] Optionally, the chip to be tested is a chip to be tested from which part of its packaging structure is removed and an internal structure layer to be observed of the chip to be tested is exposed.
[0007] Optionally, when a chip to be tested is connected to the test interface, the observation window corresponds to an internal structure layer to be observed of the chip to be tested.
[0008] Optionally, a transparent barrier is provided at the observation window.
[0009] Optionally, when a chip to be tested is connected to the test interface on the substrate, there is a gap between the transparent blocking member and the upper surface of the chip to be tested.
[0010] Optionally, the internal height of the liquid cooling chamber is higher than the thickness of the chip to be tested, so that when the cooling liquid is injected into the liquid cooling chamber, the cooling liquid can immerse the chip to be tested.
[0011] Optionally, a liquid inlet pipe is provided on the first side of the liquid cooling cover, and a liquid outlet pipe is provided on the second side, and the liquid inlet pipe and the liquid outlet pipe are respectively connected to the liquid cooling cavity; a heat dissipation module is connected between the liquid inlet pipe and the liquid outlet pipe to dissipate heat from the coolant circulating between the liquid inlet pipe and the liquid outlet pipe.
[0012] Optionally, the heat dissipation module includes a heat sink, which is provided with a flow channel; the inlet end of the flow channel is connected to the liquid outlet pipe, and the outlet end of the flow channel is connected to the liquid inlet pipe; a centrifugal pump is provided between the inlet end of the flow channel and the liquid outlet pipe, or between the outlet end of the flow channel and the liquid inlet pipe.
[0013] Optionally, it further includes: an air pressure pump, which is connected to the liquid cooling chamber to apply and maintain a preset air pressure in the liquid cooling chamber after a preset volume of coolant is injected into the liquid cooling chamber.
[0014] Optionally, it further includes: an optical observation device, wherein a lens of the optical observation device is arranged above the liquid cooling cover and corresponds to the observation window, so as to observe the chip to be tested through the observation window.
[0015] In a second aspect, an embodiment of the present application provides a chip dynamic failure analysis test method, comprising: removing part of the packaging structure of the chip to be tested and exposing the internal structure layer to be observed of the chip to be tested; placing the chip to be tested with part of the packaging structure removed in a liquid cooling cover, and making the internal structure layer to be observed of the chip to be tested face the observation window opened at the top of the liquid cooling cover; injecting coolant into the liquid cooling cover; inputting a test signal excitation to the chip to be tested, and using optical observation equipment to observe the internal structure layer to be observed of the chip to be tested through the observation window.
[0016] Optionally, the chip to be tested is arranged on a substrate, the liquid cooling cover is arranged on the substrate, a transparent baffle is provided at the observation window, and a closed liquid cooling chamber is formed between the liquid cooling cover, the substrate and the transparent baffle; wherein, after the coolant is injected into the liquid cooling cover and before the test signal is input to stimulate the chip to be tested, the method further includes: applying a preset air pressure in the space between the upper surface of the coolant and the inner top of the liquid cooling cover.
[0017] Optionally, after injecting coolant into the liquid cooling cover, during the process of observing the internal structure layer of the chip to be tested through the observation window using optical observation equipment, the method further comprises: circulating cooling the coolant in the liquid cooling cover.
[0018] The embodiment of the present application provides a test device and test method for chip dynamic failure analysis, which comprises a test mainboard interface configured on a rack, a test mainboard arranged on the rack and electrically connected to the test mainboard interface on the rack, a substrate arranged on the test mainboard and electrically connected to the test mainboard, and a test interface for electrically connecting to a chip to be tested configured on the substrate, so as to input a test signal stimulus into the chip to be tested through the test mainboard interface on the rack, the test mainboard, the substrate and the test interface on the substrate, and perform an stimulus test on the chip to be tested; a liquid cooling cover is arranged on the substrate, so that the coolant in the liquid cooling chamber of the liquid cooling cover can perform liquid cooling and heat dissipation on the chip to be tested, thereby improving the heat dissipation efficiency; and an observation window is opened on the top of the liquid cooling cover, so as to observe the chip to be tested through the observation window, thereby realizing a simple chip dynamic failure analysis test and reducing the hardware cost of the chip dynamic failure analysis. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0020] Figure 1 A cross-sectional schematic diagram of a test device for chip dynamic failure analysis according to an embodiment of the present application; Figure 2 A cross-sectional schematic diagram of a test device with a transparent baffle for dynamic failure analysis of a chip according to an embodiment of the present application; Figure 3 This is a schematic diagram of the coolant circulation of a test device for dynamic failure analysis of a chip according to an embodiment of the present application; Figure 4 This is a schematic flow chart of a chip dynamic failure analysis test method according to an embodiment of the present invention; In the figure: 1. Test device; 2. Rack; 3. Test motherboard; 4. Baseboard; 5. Liquid cooling cover; 51. Observation window; 52. Transparent baffle; 53. Liquid inlet pipe; 54. Liquid outlet pipe; 6. Chip to be tested; 7. Optical observation equipment; 8. Heat dissipation module; 9. Centrifugal pump; 10. Coolant tank. DETAILED DESCRIPTION
[0021] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0022] It should be clear that the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of this application.
[0023] Example 1: Figure 1 This is a cross-sectional schematic diagram of a test device for chip dynamic failure analysis according to an embodiment of the present application; Figure 1 , an embodiment of the present application provides a test device 1 for dynamic failure analysis of a chip, comprising: a rack 2, a test mainboard 3, a substrate 4 and a liquid cooling cover 5; the rack 2 is provided with a test mainboard interface; the test mainboard 3 is arranged on the rack 2 and is electrically connected to the test mainboard interface on the rack 2; the substrate 4 is arranged on the test mainboard 3 and is electrically connected to the test mainboard 3, and the substrate 4 is provided with a test interface for connecting to a chip to be tested 6; the liquid cooling cover 5 is provided on the substrate 4, and a liquid cooling chamber capable of accommodating cooling liquid is formed between the liquid cooling cover 5 and the substrate 4, and an observation window 51 is provided on the top of the liquid cooling cover 5.
[0024] In this embodiment, the rack 2 is used to support the test mainboard 3 and its substrate 4, liquid cooling cover 5, and chip to be tested 6 and other structures; the test mainboard 3 is electrically connected to the test mainboard interface on the rack 2 to receive test signal excitation, and the test signal excitation is input to the chip to be tested 6 through the test mainboard 3 to realize failure analysis of the chip to be tested 6.
[0025] The substrate 4 is fixedly and electrically connected to the test motherboard 3 via welding or a socket. The chip under test 6 is also electrically connected to the substrate 4 via welding or a socket. The test motherboard 3 electrically connects to the chip under test 6 via a test interface on the substrate 4, which is used to connect to the chip under test 6, and inputs test signal excitation to the chip under test 6.
[0026] The liquid cooling cover 5 is placed over the substrate 4 and is sealed to the substrate 4. In some embodiments, a sealing material such as resin can be used to seal the connection between the liquid cooling cover 5 and the substrate 4 to prevent leakage of the coolant in the liquid cooling cover 5. An observation window 51 is provided on the top of the liquid cooling cover 5 to enable an external optical observation device 7 to observe the chip under test 6 through the observation window 51.
[0027] In some embodiments, the chip to be tested 6 is a chip to be tested in which part of the packaging structure is removed and the internal structure layer to be observed of the chip to be tested 6 is exposed, so as to facilitate observation of the structure layer inside the chip to be tested 6 when a test signal is input to stimulate the chip to be tested 6, and to facilitate discovery of abnormal bright spots in the internal structure layer of the chip to be tested 6.
[0028] In some embodiments, when a chip under test 6 is connected to the test interface, the observation window 51 corresponds to the internal structure layer to be observed of the chip under test 6, so that the optical observation device 7 outside the observation window 51 can observe observable information of the internal structure layer to be observed of the chip under test 6. It is understandable that the chip under test 6 does not have to be placed directly below the observation window 51. As long as it is within the movable range of the lens of the optical observation device 7, an optical path can be formed between the lens of the optical observation device 7 and the internal structure layer to be observed of the chip under test 6 through the observation window 51, so that the optical observation device 7 can observe the internal structure layer to be observed of the chip under test 6 without being obstructed. At the same time, it is also necessary to avoid the situation where there is a reflective structure at the observation window 51, in which case the optical observation device 7 cannot observe the internal structure layer to be observed of the chip under test 6 due to the irremovable reflective effect. Therefore, after avoiding factors such as obstruction and reflection, the chip under test 6 should be placed in a position corresponding to the observation window 51 and enabling the optical observation device 7 to observe the internal structure layer to be observed of the chip under test 6.
[0029] In some embodiments, the rack 2 is also configured with a power supply interface and other auxiliary excitation interfaces for supplying power to the test mainboard 3. During the process of inputting test signal excitation to the chip to be tested 6, a control excitation signal can be input to the chip to be tested 6 through the test mainboard interface or other auxiliary excitation interfaces to improve the accuracy of the test of the chip to be tested 6.
[0030] In some embodiments, the substrate 4 cooperates with the liquid cooling cover 5 to form a liquid cooling chamber, that is, the substrate 4 can be in contact with the coolant in the liquid cooling chamber, so that the coolant in the liquid cooling cover 5 can dissipate heat to the chip to be tested 6 and the substrate 4 at the same time, avoiding inaccurate test results due to high temperature of the substrate 4 or the chip to be tested 6.
[0031] In the embodiment of the present application, a test mainboard interface is configured on the rack 2, and the test mainboard 3 is arranged on the rack 2 and electrically connected to the test mainboard interface on the rack 2; the substrate 4 is arranged on the test mainboard 3 and electrically connected to the test mainboard 3, and at the same time, a test interface for electrically connecting to the chip to be tested 6 is configured on the substrate 4, and the chip to be tested 6 is electrically connected to the test interface, so as to facilitate the input of the test signal excitation into the chip to be tested 6 through the test mainboard interface on the rack 2, the test mainboard 3, the substrate 4 and the test interface on the substrate 4, so as to perform an excitation test on the chip to be tested 6; the test signal excitation comes from the test device, and the test device can be arranged on the rack 2 or outside the rack 2 and electrically connected to the rack 2; during the test signal excitation process on the chip to be tested 6, the chip to be tested 6 will generate a lot of heat. The chip to be tested 6 is placed in a liquid cooling cavity formed by the liquid cooling cover 5 and the substrate 4. The liquid cooling cavity can be filled with coolant to achieve liquid cooling and heat dissipation of the chip to be tested 6; an observation window 51 is opened on the top of the liquid cooling cover 5 and the observation window 51 is made to correspond to the internal structure layer to be observed of the chip to be tested 6, so that the internal structure layer to be observed of the chip to be tested 6 can be observed through the observation window 51. While solving the problem of using liquid cooling for the chip to be tested 6, it meets the chip failure analysis observation needs and solves the contradiction that a radiator needs to be installed above the chip to be tested 6 in traditional observation, but the radiator will block the chip to be tested 6, resulting in an inability to observe, thereby realizing a simple chip dynamic failure analysis test and reducing the hardware cost of chip dynamic failure analysis.
[0032] Figure 2 This is a schematic diagram of a test device with a transparent baffle for dynamic failure analysis of a chip according to an embodiment of the present application. Figure 2 In some embodiments, a transparent blocking member 52 is provided at the observation window 51 .
[0033] In this embodiment, the transparent baffle 52 is provided to prevent the coolant from causing harm to the observer and polluting the observation environment when observing the chip to be tested 6, and to prevent external impurities from entering the liquid cooling cover 5 and polluting the coolant, thereby affecting the observation results of the chip to be tested 6.
[0034] In some embodiments, the thickness M of the transparent barrier 52 satisfies the following relationship: 0 < M ≤ 1 mm, ensuring that the internal structure of the chip under test 6 within the liquid cooling cover 5 can be effectively observed through the transparent barrier 52 while ensuring the strength of the transparent barrier 52. In some examples, M can be 0.2 mm, 0.3 mm, 0.5 mm, 0.8 mm, or 1 mm.
[0035] In some embodiments, the transparent blocking member 52 may be made of quartz glass or resin, or other materials with high transparency.
[0036] In some embodiments, the transparent baffle 52 is made of a material that is transparent and allows visual observation of the chip to be tested 6 in the liquid cooling cover 5, ensuring that the transmittance of the transparent baffle 52 is greater than 90%. When liquid cooling is used to dissipate heat from the chip to be tested 6, the chip to be tested 6 can be observed through the transparent material of the transparent baffle 52.
[0037] In some embodiments, when a chip under test 6 is connected to the test interface on the substrate 4 , a gap exists between the transparent blocking member 52 and the upper surface of the chip under test 6 , thereby preventing the transparent blocking member 52 from damaging the chip under test 6 .
[0038] In some embodiments, the gap size D satisfies the following: 0 < D ≤ 1 cm. This gap size, when combined with the distance between the lens of the optical observation device 7 and the upper surface of the chip under test 6 being less than 2 cm, enables the external optical observation device 7 to accurately observe the chip under test 6. In some examples, D can be 0.1 cm, 0.2 cm, 0.3 cm, 0.5 cm, 0.8 cm, or 1 cm.
[0039] In some embodiments, the internal height of the liquid cooling chamber is higher than the thickness of the chip under test 6 , so that when the cooling liquid is injected into the liquid cooling chamber, the cooling liquid can immerse the chip under test 6 .
[0040] In this embodiment, when the chip to be tested 6 is connected to the test interface of the substrate 4, the internal height of the liquid cooling chamber is ensured to be higher than the thickness of the chip to be tested 6, so that a certain gap is left between the inner surface of the top of the liquid cooling cover 5 and the upper surface of the chip to be tested 6, so as to avoid damage to the chip to be tested 6 when the liquid cooling cover 5 is placed on the substrate 4; at the same time, when the coolant is injected into the liquid cooling chamber, the coolant is able to immerse and surround the chip to be tested 6, and the chip to be tested 6 is dissipated by liquid cooling to avoid the local temperature being too high when the chip to be tested 6 is not completely immersed in the coolant, resulting in the inability to accurately obtain the test results; it can be understood that the coolant is a transparent material, and the chip to be tested 6 is immersed in the coolant to achieve all-round liquid cooling and heat dissipation at the chip level while solving the problem of traditional radiators blocking chip observation.
[0041] In some embodiments, the coolant is a single-phase coolant with a boiling point of ≥150° C. and an electrical conductivity of ≤1 μS / cm.
[0042] In this embodiment, the high heat capacity and good thermal conductivity of the single-phase coolant are used to ensure that the chip under test 6 maintains a stable temperature environment during the test process, avoid the uneven phase change problem that may occur in the multi-phase coolant, and avoid the bubbles in the coolant from affecting the observation effect, thereby ensuring the stability and reliability of the heat dissipation effect and the observation effect.
[0043] Single-phase coolant requires a boiling point of ≥150°C to avoid evaporation, boiling, or bubble formation at high temperatures, a conductivity of ≤1μS / cm to reduce signal interference, short circuits, and other circuit problems, as well as non-corrosiveness and low bubble content.
[0044] A single-phase coolant is used in combination with immersion liquid cooling to solve the heat dissipation problem caused by the heat generated when observing the chip. In order to avoid the bubbles in the coolant affecting the observation effect, a single-phase coolant for chip observation can be configured to achieve an overall good observation environment; the single-phase coolant is not limited to the electronic fluoride liquid widely used in the industry. Other materials that meet the above requirements and can achieve good heat dissipation, observation, and safety effects can be used as the coolant in this embodiment.
[0045] In some embodiments, in order to reduce the generation of bubbles when the coolant flows in the liquid cooling cover 5 and thus affect observation, a foam suppressant may be added to the coolant to suppress the generation of bubbles in the coolant in the liquid cooling cover 5 .
[0046] In some embodiments, the testing device 1 may further include an air pressure pump (not shown in the figure), which is connected to the liquid cooling chamber to apply and maintain a preset air pressure in the liquid cooling chamber after a preset volume of coolant is injected into the liquid cooling chamber, such as applying and maintaining a preset pressure of 0.13~0.15Mpa. This can increase the solubility of the gas in the coolant and reduce the precipitation of gas from the coolant, thereby avoiding the generation of bubbles in the coolant and affecting the observation.
[0047] In some embodiments, a liquid inlet pipe 53 is provided on the first side of the liquid cooling cover 5, and a liquid outlet pipe 54 is provided on the second side. The liquid inlet pipe 53 and the liquid outlet pipe 54 are respectively connected to the liquid cooling cavity; a heat dissipation module 8 is connected between the liquid inlet pipe 53 and the liquid outlet pipe 54 to dissipate heat from the coolant circulating between the liquid inlet pipe 53 and the liquid outlet pipe 54.
[0048] In this embodiment, the liquid cooling cover 5 is provided with a liquid inlet pipe 53 and a liquid outlet pipe 54 connected to the liquid cooling chamber so that the coolant circulates in the liquid cooling cover 5 and the heat dissipation module 8 outside the liquid cooling cover 5, so that the heat dissipation module 8 can discharge the coolant heated by the chip under test 6 in the liquid cooling cover 5 to the heat dissipation module 8 for heat dissipation, thereby avoiding the temperature of the chip under test 6 in the liquid cooling cover 5 being too high when the chip under test 6 is tested.
[0049] In some embodiments, the heat dissipation module 8 includes a heat sink, and a flow channel is provided on the heat sink; the inlet end of the flow channel is connected to the liquid outlet pipe 54, and the outlet end of the flow channel is connected to the liquid inlet pipe 53; a centrifugal pump 9 is provided between the inlet end of the flow channel and the liquid outlet pipe 54, or between the outlet end of the flow channel and the liquid inlet pipe 53.
[0050] In this embodiment, the heat dissipation module 8 includes a heat sink, which is used to increase the heat dissipation area and accelerate the heat dissipation of the heat sink through air convection; a flow channel is provided on the heat sink, and the coolant flows in the flow channel to transfer the heat of the chip to be tested 6 in the liquid cooling cover 5 to the heat sink, thereby achieving heat dissipation of the chip to be tested 6; a centrifugal pump 9 is provided between the inlet end of the flow channel and the liquid outlet pipe 54 or between the outlet end of the flow channel and the liquid inlet pipe 53, so that the centrifugal pump 9 pumps or outputs the coolant into the liquid cooling cover 5, thereby promoting the flow of the coolant in the flow channel and the liquid cooling cover 5, accelerating the transfer of the heat of the chip to be tested 6 in the liquid cooling cover 5 to the heat sink, and dissipating it into the air, thereby avoiding the large amount of heat generated by the chip to be tested 6 during observation from accumulating in the liquid cooling cover 5, causing damage to the chip to be tested 6 and other structures in the liquid cooling cover 5, and affecting the observation process; an air-cooled heat dissipation structure can also be installed on the heat sink to improve the heat dissipation efficiency of the coolant in the flow channel of the heat sink, thereby improving the heat dissipation effect of the chip to be tested 6.
[0051] Figure 3 This is a schematic diagram of the cooling liquid circulation of a test device for chip dynamic failure analysis according to an embodiment of the present application. Figure 3 In some embodiments, a coolant tank 10 is further connected between the liquid inlet pipe 53 and the liquid outlet pipe 54. The coolant tank 10 is used to store coolant and adjust the pressure, so that the coolant flowing out of the liquid outlet pipe 54 dissipates heat in the heat sink and then enters the coolant tank 10 and stands still for a period of time before being recirculated from the liquid inlet pipe 53 into the liquid cooling cover 5, thereby preventing the coolant that may not have completely dissipated heat from the heat sink from directly entering the liquid cooling cover 5 again from the liquid inlet pipe 53 and being heated by the chip under test 6, thereby achieving a better heat dissipation effect; at the same time, the coolant enters the coolant tank 10 and stands still, which can avoid the coolant flowing rapidly in the flow channels of the liquid inlet, liquid cooling cover 5, liquid outlet and heat sink from generating a large number of bubbles, thereby preventing the formation of bubbles in the coolant from affecting observation.
[0052] In some embodiments, the heat dissipation module 8, the centrifugal pump 9 and the coolant tank 10 adopt a split structure and can be arranged independently. Then, pipe sealing connections are used between the heat dissipation module 8, the centrifugal pump 9 and the coolant tank 10, as well as the liquid outlet pipe 54 and the liquid inlet pipe 53. This can adapt to different space sizes and hardware layouts. When a component in the heat dissipation module 8, the centrifugal pump 9 and the coolant tank 10 is damaged, only the corresponding component needs to be replaced without the need for overall disassembly, thereby reducing maintenance costs.
[0053] In some embodiments, the testing apparatus 1 further includes an optical observation device 7, wherein a lens of the optical observation device 7 is disposed above the liquid cooling cover 5 and corresponds to the observation window 51, so as to observe the chip under test 6 through the observation window 51. The optical observation device 7 may be an EMMI micro-light microscope.
[0054] In this embodiment, an optical path is formed between the chip to be tested 6, the observation window 51 and the lens of the optical observation device 7. When an abnormal bright spot occurs on the chip to be tested 6, the bright light can be transmitted along the above-mentioned optical path to the optical observation device 7, so that the optical observation device 7 can observe the chip to be tested 6 through the observation window 51; when the chip to be tested 6 is a chip to be tested with part of the packaging structure removed and its internal structure layer to be observed exposed, the internal structure layer to be observed of the chip to be tested 6 can also be observed. When an abnormal bright spot appears in the internal structure layer to be observed of the chip to be tested 6, it can be recorded and analyzed, thereby realizing failure analysis of the chip to be tested 6.
[0055] Example 2: See Figure 4 The present invention provides a chip dynamic failure analysis test method, including the following steps: S10, removing part of the packaging structure of the chip to be tested and exposing the internal structure layer to be observed of the chip to be tested; S11, placing the chip under test with part of the packaging structure removed in a liquid cooling cover, with the internal structure layer of the chip under test to be observed facing the observation window opened on the top of the liquid cooling cover; S12, injecting coolant into the liquid cooling cover; S13 , inputting a test signal stimulus to the chip under test, and using an optical observation device to observe the internal structure layer to be observed of the chip under test through the observation window.
[0056] In this embodiment, the chip to be tested with part of the packaging structure removed is placed in a liquid cooling cover, and coolant is injected into the liquid cooling cover. Then, a test signal is input to the chip to be tested to stimulate the internal structure layer to be observed of the chip to be tested through the observation window using optical observation equipment. In this way, the chip failure analysis observation requirements are met while solving the problem of using liquid cooling for heat dissipation of the chip to be tested. This solves the contradiction that in traditional observation, a radiator needs to be installed above the chip to be tested, but the radiator will block the chip to be tested, resulting in an inability to observe. This thereby realizes a simple chip dynamic failure analysis test and reduces the hardware cost of chip dynamic failure analysis.
[0057] In some embodiments, the chip to be tested is arranged on a substrate, the liquid cooling cover is arranged on the substrate, a transparent baffle is provided at the observation window, and a closed liquid cooling cavity is formed between the liquid cooling cover, the substrate and the transparent baffle; wherein, after the coolant is injected into the liquid cooling cover and before the test signal is input to stimulate the chip to be tested, the method further includes: applying a preset air pressure in the space between the upper surface of the coolant and the inner top of the liquid cooling cover to increase the solubility of the gas in the coolant and reduce the precipitation of gas from the coolant, thereby avoiding the generation of bubbles in the coolant and avoiding affecting the observation.
[0058] In some embodiments, after injecting cooling liquid into the liquid cooling cover, during the process of observing the internal structure layer of the chip to be tested through the observation window using optical observation equipment, the method further includes: circulating cooling the cooling liquid in the liquid cooling cover.
[0059] In this embodiment, after the coolant is injected into the liquid cooling cover and the test excitation signal is input to the chip to be tested, the chip to be tested will generate a large amount of heat. During the process of observing the internal structure layer to be observed of the chip to be tested through the observation window, the coolant in the liquid cooling cover also needs to be circulated and cooled so that the coolant around the chip to be tested is within a normal temperature range to avoid damage to the chip to be tested due to high temperature and the inability to complete the observation.
[0060] In some embodiments, the distance between the lens of the optical observation device and the upper surface of the chip to be tested is ensured to be ≤2 cm, ensuring that the optical observation device can track in real time the deformation, crack expansion, abnormal bright spots and other phenomena on the surface of the internal structure layer to be observed of the chip to be tested due to stress. This close-range setting allows for the capture of rapidly changing processes, ensuring the timeliness and accuracy of the data.
[0061] During the test process, especially when the coolant circulates to dissipate heat, temperature fluctuations may cause the mirror surface to fog up. This phenomenon will hinder imaging quality and affect data collection. If the condensation is severe, it will not only cause blurred images but may also damage optical components. The optical observation equipment lens is equipped with a high-temperature-resistant, chemically stable anti-liquid cooling mist coating, which can effectively inhibit the occurrence of condensation and keep the mirror surface clear. The coating has extremely high light transmittance to ensure that imaging quality is not affected. At the same time, the coating does not change the focal length or aperture parameters of the lens, ensuring the consistency of equipment performance.
[0062] The chip dynamic failure analysis test method provided in the embodiment of the present application can be applied to the aforementioned chip dynamic failure analysis test device. Its implementation process and technical effects are basically the same and will not be described in detail.
[0063] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A test device for dynamic failure analysis of a chip, characterized in that: include: A rack, wherein the rack is provided with a test mainboard interface; A test mainboard, the test mainboard being arranged on the rack and electrically connected to the test mainboard interface on the rack; a substrate, the substrate being disposed on the test mainboard and electrically connected to the test mainboard, the substrate being provided with a test interface for connecting to a chip to be tested; A liquid cooling cover is provided on the substrate, a liquid cooling cavity capable of accommodating cooling liquid is formed between the liquid cooling cover and the substrate, and an observation window is provided on the top of the liquid cooling cover.
2. The testing device according to claim 1, wherein: The chip to be tested is a chip to be tested with a portion of its packaging structure removed so that an internal structure layer to be observed of the chip to be tested is exposed.
3. The testing device according to claim 2, characterized in that When a chip to be tested is connected to the test interface, the observation window corresponds to an internal structure layer to be observed of the chip to be tested.
4. The testing device according to claim 1, wherein: A transparent blocking piece is provided at the observation window.
5. The testing device according to claim 4, characterized in that: When a chip to be tested is connected to the test interface on the substrate, a gap exists between the transparent blocking member and the upper surface of the chip to be tested.
6. The testing device according to claim 1, characterized in that The internal height of the liquid cooling chamber is higher than the thickness of the chip to be tested, so that when the cooling liquid is injected into the liquid cooling chamber, the cooling liquid can immerse the chip to be tested.
7. The testing device according to claim 1, characterized in that A liquid inlet pipe is provided on the first side of the liquid cooling cover, and a liquid outlet pipe is provided on the second side. The liquid inlet pipe and the liquid outlet pipe are respectively connected to the liquid cooling cavity; a heat dissipation module is connected between the liquid inlet pipe and the liquid outlet pipe to dissipate heat from the coolant circulating between the liquid inlet pipe and the liquid outlet pipe.
8. The testing device according to claim 7, characterized in that: The heat dissipation module includes a heat sink, and a flow channel is provided on the heat sink; the inlet end of the flow channel is connected to the liquid outlet pipe, and the outlet end of the flow channel is connected to the liquid inlet pipe; A centrifugal pump is provided between the inlet end of the flow channel and the liquid outlet pipe, or between the outlet end of the flow channel and the liquid inlet pipe.
9. The testing device according to claim 1, wherein: Also includes: An air pressure pump is connected to the liquid cooling chamber to apply and maintain a preset air pressure in the liquid cooling chamber after a preset volume of coolant is injected into the liquid cooling chamber.
10. The testing device according to claim 1, wherein: Also includes: An optical observation device, wherein a lens of the optical observation device is arranged above the liquid cooling cover and corresponds to the observation window, so as to observe the chip to be tested through the observation window.
11. A chip dynamic failure analysis test method, characterized in that: include: Removing part of the packaging structure of the chip to be tested and exposing the internal structure layer to be observed of the chip to be tested; Placing the chip to be tested with part of the packaging structure removed in a liquid cooling cover, with the internal structure layer to be observed of the chip to be tested facing the observation window opened on the top of the liquid cooling cover; injecting coolant into the liquid cooling cover; A test signal is inputted to the chip under test to stimulate the chip under test, and an optical observation device is used to observe the internal structure layer to be observed of the chip under test through the observation window.
12. The testing method according to claim 11, characterized in that: The chip to be tested is arranged on a substrate, the liquid cooling cover is arranged on the substrate, a transparent baffle is provided at the observation window, and a closed liquid cooling cavity is formed between the liquid cooling cover, the substrate and the transparent baffle; Wherein, after injecting the coolant into the liquid cooling cover and before inputting the test signal stimulus to the chip under test, the method further includes: A preset air pressure is applied in the space between the upper surface of the coolant and the inner top of the liquid cooling cover.
13. The testing method according to claim 11, characterized in that: After injecting cooling liquid into the liquid cooling cover, in the process of observing the internal structure layer to be observed of the chip to be tested through the observation window using optical observation equipment, the method further includes: The coolant in the liquid cooling cover is circulated and cooled.