Circuit, chip and device for positive and negative insertion automatic identification and small voltage loss of single bus protocol

Abstract

The invention provides a circuit, a chip and a device for positive and negative insertion automatic identification and small voltage loss of a single bus protocol. The circuit comprises a power supply selection circuit and a power supply locking control circuit, the power supply selection circuit comprises an identification selection unit and a connection terminal group, the connection terminal group comprises a first terminal, a second terminal, a third terminal and a fourth terminal, and the first terminal and the second terminal are used for being positively inserted or reversely inserted between an external data line and a ground wire; the identification selection unit connects the data line with the third terminal and connects the ground line with the fourth terminal, and the power supply locking control circuit is used for outputting a first control signal and a second control signal to lock the connection of the ground line and the fourth terminal. The circuit can be normally used during forward insertion or reverse insertion, the voltage obtained from the data line can be increased, the voltage loss is reduced, good support is provided for a single bus to work in a lower voltage environment, meanwhile, complex peripheral circuits are not needed for selection, and the implementation mode is simple.

Description

Technical Field

[0001] The present invention relates to the technical field of single bus communication, and in particular to a circuit, a chip and a device for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss. Background Art

[0002] The core design concept of the single-bus (1-wire) protocol is to achieve data transmission and power supply with only one data line and ground line. Compared with other protocols such as I2C and SPI that require multiple signal lines, the single-bus protocol greatly simplifies hardware connections and is suitable for low-cost, low-power embedded systems and sensor networks. Therefore, it is widely used in application scenarios such as smart homes and the Internet of Things.

[0003] Single-bus devices support two power supply methods. One is external power: the device has its own independent power supply, and the data line is used only for communication. The other is parasitic power: the data line is used not only for communication but also for device power. Compared to parasitic power, external power requires an additional power pin on the device, which increases costs and is unacceptable in some applications (such as e-cigarettes). Using two pins, i.e., powering via the data line, is more widely used and convenient.

[0004] See also Figure 1 , Figure 1 This is a common circuit for preventing reverse power connection. It uses four diodes to form a rectifier bridge. Regardless of which pad the power enters from, it can flow to VC1. Because the diodes' unidirectional conductivity causes the power supply pad to flow to VC1, and VS1 to flow to the grounded pad. This circuit, which uses a rectifier bridge, does work with both forward and reverse power connections. However, there's a diode voltage drop between VC1 and the data line, and another between VS1 and ground, resulting in two diode voltage drops. This makes it unsuitable for low-voltage devices.

[0005] See also Figure 2 , Figure 2This is another common circuit that uses MCU control to identify data lines and ground lines. When chip 100 is connected to the circuit, IO1 and IO2 alternately open M1 and M4 or M2 and M3, and IO0 detects changes in the load to determine whether the chip is reversely connected. After the judgment is completed, IO1 and IO2 select the PAD connected to the power line and connect it to VC2. In this way, the chip can be adjusted to a positive connection regardless of whether it is forward or reverse connected. However, this solution requires adding a large number of switches and wiring on the PCB board, which makes it difficult to connect multiple chips to the bus at the same time. That is, if multiple single-bus chips are connected to PAD3 and PAD4, even if the forward and reverse connection problem of the first chip is solved by adding an MCU and a switch, the forward and reverse connection problem of the shared bus of the second or subsequent chips cannot be solved, which greatly limits the forward and reverse connection scenario of multiple chips sharing the same bus. Summary of the Invention

[0006] The first object of the present invention is to provide a circuit for automatically identifying forward and reverse plugging in a single bus protocol and having low voltage loss, which can reduce voltage loss while achieving automatic forward and reverse plugging identification and is suitable for forward and reverse plugging scenarios where multiple chips share a bus.

[0007] A second object of the present invention is to provide a chip comprising the above-mentioned circuit for automatic identification of forward and reverse insertion of a single bus protocol and having low voltage loss.

[0008] A third object of the present invention is to provide a device comprising the above chip.

[0009] In order to achieve the above-mentioned first purpose, the present invention provides a circuit for automatic identification of forward and reverse insertion of a single bus protocol with low voltage loss, which includes: a power selection circuit and a power lock control circuit; the power selection circuit includes an identification selection unit and a connection terminal group, the connection terminal group includes a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal and the second terminal are used for forward insertion or reverse insertion between an external data line and a ground line; the identification selection unit includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a first diode, a second diode and an energy storage capacitor; the first terminal is respectively connected to the drain of the first NMOS tube, the gate of the second NMOS tube, the drain of the third NMOS tube, the first electrode of the fifth NMOS tube, and the anode of the first diode; the second terminal is respectively connected to the gate of the first NMOS tube, the drain of the second NMOS tube, the fourth NMOS tube, and the fifth NMOS tube. The drain of the OS transistor, the second electrode of the fifth NMOS transistor, and the anode of the second diode; the third terminal is connected to the cathode of the first diode and the cathode of the second diode respectively; the fourth terminal is connected to the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor, and the source of the fourth NMOS transistor respectively; the third terminal and the fourth terminal are connected via an energy storage capacitor; the first NMOS transistor, the second NMOS transistor, the first diode, and the second diode cooperate to connect the data line to the third terminal and the ground line to the fourth terminal; the power lock control circuit is used to output a first control signal to the gate of the third NMOS transistor that is opposite to the level state when the first terminal is initially connected, and output a second control signal to the gate of the fourth NMOS transistor that is opposite to the level state when the second terminal is initially connected; the gate of the fifth NMOS transistor is used to obtain a response signal, and the fifth NMOS transistor is turned on when the response signal is obtained.

[0010] As can be seen from the above scheme, the power selection circuit of the present invention realizes the identification of the data line and the ground line, so that no matter whether the first terminal and the second terminal are inserted in the forward or reverse direction between the data line and the ground line, the data line can be connected to the third terminal and the ground line can be connected to the fourth terminal, so that the third terminal can be used as a power supply terminal and the fourth terminal can be provided to the outside as a ground terminal. By setting a power lock control circuit, the connection between the fourth terminal and the ground line can be locked regardless of the forward or reverse insertion situation, preventing the fourth terminal from being left floating. While ensuring the automatic identification function of forward and reverse insertion, the present invention can increase the voltage obtained from the data line, reduce voltage loss, and provide good support for the single bus to operate in a lower voltage environment. At the same time, there is no need for complex peripheral circuits for selection, and the implementation method is simple.

[0011] A further solution is that the power lock control circuit includes a first D flip-flop and a second D flip-flop, the first D flip-flop is used to store a first control signal that is opposite to the level state when the output is initially connected to the first terminal, and the second D flip-flop is used to store a second control signal that is opposite to the level state when the output is initially connected to the second terminal.

[0012] It can be seen that the power lock control circuit latches the control signal through the D flip-flop, ensuring that the ground line can be reliably locked with the fourth terminal to prevent the fourth terminal from being suspended.

[0013] A further solution is that the power lock control circuit also includes a power-on reset unit, a delay unit, a first inverter, and a second inverter; the output end of the power-on reset unit is respectively connected to the input end of the delay unit, the reset end of the first D flip-flop, and the reset end of the second D flip-flop; the output end of the delay unit is respectively connected to the clock end of the first D flip-flop and the clock end of the second D flip-flop; the input end of the first inverter is connected to the first terminal, and the output end of the first inverter is connected to the D end of the first D flip-flop; the input end of the second inverter is connected to the second terminal, and the output end of the second inverter is connected to the D end of the second D flip-flop.

[0014] It can be seen that the power-on reset unit, the delay unit, the first inverter, and the second inverter cooperate to achieve stable output of the first control signal and the second control signal. Among them, the setting of the original unit is that after the reset of the power-on reset unit is released, the D flip-flop provides a sampling clock for state latching only after the signals of the data line and the ground line are stable, so as to avoid latching abnormal signals of the data line (for example, the voltage of the data line has not yet completely stabilized or there are fluctuations, because in the initial power-on stage, the external module or external chip to which the data line needs to be connected is powered on, and the waveform will not be as steep as a square wave). The delay time of the delay unit can be determined according to the specific power-on situation.

[0015] A further solution is that the first inverter and the second inverter are both Schmitt inverters.

[0016] It can be seen that the use of Schmitt inverter can play the role of shaping filter. When the D flip-flop DFF is sampling, the burrs on the data line and the ground line may cause the latching of the wrong signal.

[0017] A further solution is that the first diode is a sixth NMOS transistor used as a diode connection, and the second diode is a seventh NMOS transistor used as a diode connection.

[0018] A further solution is that the gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the first terminal, and the source of the sixth NMOS transistor is connected to the third terminal;

[0019] The gate of the seventh NMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the seventh NMOS transistor is connected to the second terminal, and the source of the seventh NMOS transistor is connected to the third terminal.

[0020] A further solution is that the identification and selection unit also includes a first NAND gate, a second NAND gate, a first PMOS tube, and a second PMOS tube; the input end of the first NAND gate is connected to the first terminal and obtains a second control signal whose level state is opposite to that when the second terminal is initially connected, the output end of the first NAND gate is connected to the gate of the first PMOS tube, the source of the first PMOS tube is connected to the first terminal, and the drain of the first PMOS tube is connected to the third terminal; the input end of the second NAND gate is connected to the second terminal and obtains the first control signal whose level state is opposite to that when the first terminal is initially connected, the output end of the second NAND gate is connected to the gate of the second PMOS tube, the source of the second PMOS tube is connected to the second terminal, and the drain of the second PMOS tube is connected to the third terminal.

[0021] Thus, by providing a PMOS transistor to control the connection between the data line and the third terminal, the diode voltage drop between the data line and the ground line can be eliminated. Furthermore, since the control signal remains unchanged until the next power failure after the data line is automatically identified, the addition of a NAND gate can promptly shut down the PMOS transistor connecting the data line and the third terminal when the data line loses power. This prevents the potential of the third terminal from changing along with the data line due to the first control signal being directly connected to the first PMOS transistor and the second control signal being directly connected to the second PMOS transistor.

[0022] A further solution is that the identification and selection unit also includes a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube and a sixth PMOS tube; the drain of the third PMOS tube is connected to the first terminal, the gate of the third PMOS tube is connected to the third terminal, the gate of the fourth PMOS tube is connected to the first terminal, and the drain of the fourth PMOS tube is connected to the third terminal; the substrate of the third PMOS tube, the source of the third PMOS tube, the substrate of the fourth PMOS tube, the source of the fourth PMOS tube, and the substrate of the first PMOS tube are connected to each other; the drain of the fifth PMOS tube is connected to the second terminal, the gate of the fifth PMOS tube is connected to the third terminal, the gate of the sixth PMOS tube is connected to the second terminal, and the drain of the sixth PMOS tube is connected to the third terminal; the substrate of the fifth PMOS tube, the source of the fifth PMOS tube, the substrate of the sixth PMOS tube, the source of the sixth PMOS tube, and the substrate of the second PMOS tube are connected to each other.

[0023] It can be seen from this that the substrate of the PMOS tube can always be connected to the high voltage side, preventing the substrate bias effect of the PMOS tube from causing leakage when the PMOS tube is turned on.

[0024] In order to achieve the above-mentioned second purpose, the present invention provides a chip, including a shell, wherein: the shell includes an automatic forward and reverse plug-in identification module and a functional module, the automatic forward and reverse plug-in identification module includes the above-mentioned circuit for automatic forward and reverse plug-in identification with low voltage loss for the single bus protocol; the functional module includes a power supply terminal and a ground terminal, the power supply terminal is connected to the third terminal, and the ground terminal is connected to the fourth terminal. The functional chip is also used to provide a response signal to the gate of the fifth NMOS tube.

[0025] As can be seen from the above scheme, the chip of the present invention can automatically identify and match the corresponding data line and ground line regardless of whether it is inserted forward or reverse, and can supply power to the chip normally, and enable the chip to receive and send data from the data line, greatly improving the user experience. Since it can be inserted forward or reverse at will, it provides convenience for subsequent chip installation, and can prevent the chip from burning out, thereby enhancing the safety of the chip. In addition, the present invention does not require the setting of peripheral circuits for selection. After the chip is installed, it automatically identifies the corresponding data line and ground line when it is powered on, and the scheme supports the forward and reverse insertion of multiple chips on the bus at the same time instead of only supporting one chip. At the same time, due to the use of an optimized design, the scheme can maximize the power supply voltage obtained from the data line, thereby providing good support for single-bus chips to operate in a lower voltage environment.

[0026] In order to achieve the third objective mentioned above, the present invention provides a device including a housing, wherein the housing includes the above-mentioned chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The invention discloses a circuit principle diagram of a circuit for automatically identifying whether a power supply is plugged in forward or reversely in the prior art.

[0028] Figure 2 The invention is a circuit principle diagram of another circuit for automatically identifying the forward and reverse insertion of a power supply in the prior art.

[0029] Figure 3 This is a circuit schematic diagram of a power selection circuit in a first embodiment of a circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss according to the present invention.

[0030] Figure 4 This is a timing diagram of each terminal in the power selection circuit under the forward insertion condition in the first embodiment of the circuit for automatic recognition of forward and reverse insertion of the single bus protocol with low voltage loss in the present invention.

[0031] Figure 5 This is a circuit schematic diagram of a power lock control circuit in a first embodiment of a circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss according to the present invention.

[0032] Figure 6This is a timing diagram of various signals during the process of locking the ground wire of the power lock control circuit after power-on in the first embodiment of the circuit for automatic identification of forward and reverse insertion of the single bus protocol with low voltage loss of the present invention.

[0033] Figure 7 The present invention is a timing diagram of various signals in the process of receiving data from the data line and returning data to the data line in the first embodiment of the circuit for automatic recognition of forward and reverse insertion of the single bus protocol with low voltage loss under the condition of forward insertion.

[0034] Figure 8 This is a schematic diagram illustrating the effect of reducing voltage loss in the first embodiment of the circuit for automatic identification of forward and reverse insertion of a single bus protocol and low voltage loss according to the present invention.

[0035] Figure 9 This is a circuit schematic diagram of a power selection circuit in a second embodiment of a circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss according to the present invention.

[0036] Figure 10 This is a timing diagram of various signals in the second embodiment of the circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss in the forward insertion situation.

[0037] Figure 11 This is a schematic diagram illustrating the effect of reducing voltage loss in the second embodiment of the circuit for automatic identification of forward and reverse insertion of a single bus protocol and low voltage loss according to the present invention.

[0038] Figure 12 It is a schematic structural diagram of a chip embodiment of the present invention.

[0039] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0040] The present invention provides a circuit for automatically identifying forward and reverse plugging with minimal voltage loss for a single-bus protocol. The circuit automatically identifies and matches corresponding data lines and ground lines, provides power and ground terminals via pre-set terminals, and thereby receives and transmits data from and to the data lines based on the power terminals, maximizing the power voltage obtained from the data lines. The present invention also provides a chip and device including the circuit for automatically identifying forward and reverse plugging with minimal voltage loss for a single-bus protocol.

[0041] First embodiment of a circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss:

[0042] In a single-bus protocol, data transmission and power supply can be achieved through a single data line and ground line. This embodiment is applied to the single-bus protocol and specifically includes a power selection circuit and a power lock control circuit. The power selection circuit is connected to the power lock circuit. The power selection circuit is used to identify and match the data line and ground line after connection. The power lock control circuit is used to identify and lock the ground line after the power selection circuit completes the identification and matching of the data line and ground line.

[0043] See also Figure 3 The power selection circuit includes a connection terminal group and an identification and selection unit. The connection terminal group includes a first terminal J1, a second terminal J2, a third terminal J3, and a fourth terminal J4. The identification and selection unit includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a first diode, a second diode, and an energy storage capacitor CAP1.

[0044] The gate of the first NMOS transistor N1 is connected to the second terminal J2, the drain of the first NMOS transistor N1 is connected to the first terminal J1, and the source of the first NMOS transistor N1 is connected to the fourth terminal J4. The gate of the second NMOS transistor N2 is connected to the first terminal J1, the drain of the second NMOS transistor N2 is connected to the second terminal J2, and the source of the second NMOS transistor N2 is connected to the fourth terminal J4.

[0045] The gate of the third NMOS transistor N3 is connected to the power lock control circuit and receives the first control signal CRTL1 from the power lock control circuit. The drain of the third NMOS transistor N3 is connected to the first terminal J1, and the source of the third NMOS transistor N3 is connected to the fourth terminal J4. The gate of the fourth NMOS transistor N4 is connected to the power lock control circuit and receives the second control signal CRTL2 from the power lock control circuit. The drain of the fourth NMOS transistor N4 is connected to the second terminal J2, and the source of the fourth NMOS transistor N4 is connected to the fourth terminal J4.

[0046] The first terminal J1 is also connected to the first electrode of the fifth NMOS transistor N5 and the anode of the first diode, respectively. The second terminal J2 is also connected to the second electrode of the fifth NMOS transistor N5 and the anode of the second diode, respectively. The third terminal J3 is also connected to the cathode of the first diode and the cathode of the second diode, respectively. The third terminal J3 is connected to the fourth terminal J4 via the energy storage capacitor CAP1, that is, the two ends of the energy storage capacitor CAP1 are connected to the third and fourth terminals J4, respectively.

[0047] In this embodiment, the first electrode of the fifth NMOS transistor N5 serves as the drain of the fifth NMOS transistor N5, and the second electrode of the fifth NMOS transistor N5 serves as the source of the fifth NMOS transistor N5. In other embodiments, the first electrode of the fifth NMOS transistor N5 serves as the source of the fifth NMOS transistor N5, and the second electrode of the fifth NMOS transistor N5 serves as the drain of the fifth NMOS transistor N5.

[0048] In this embodiment, the first diode is the sixth NMOS transistor N6 used as a diode connection, and the second diode is the seventh NMOS transistor N7 used as a diode connection. The gate of the sixth NMOS transistor N6 is connected to the drain of the sixth NMOS transistor N6, the drain of the sixth NMOS transistor N6 is connected to the first terminal J1, and the source of the sixth NMOS transistor N6 is connected to the third terminal J3. The gate of the seventh NMOS transistor N7 is connected to the drain of the seventh NMOS transistor N7, the drain of the seventh NMOS transistor N7 is connected to the second terminal J2, and the source of the seventh NMOS transistor N7 is connected to the third terminal J3. The sixth NMOS transistor N6 used as a diode connection and the seventh NMOS transistor N7 used as a diode connection both use low-threshold NMOS transistors to reduce the voltage drop consumed.

[0049] The first terminal J1 and the second terminal J2 are used for forward or reverse insertion between an external data line and a ground line. Regardless of whether the device is forward or reversed, the identification and selection unit controls the data line and the ground line, and then establishes a connection between the data line and the third terminal J3, and between the ground line and the fourth terminal J4. The power lock control circuit then locks the connection between the ground line and the fourth terminal J4.

[0050] Specifically, the first NMOS transistor N1, the second NMOS transistor N2, the first diode, and the second diode cooperate to connect the data line to the third terminal J3 and the ground line to the fourth terminal J4. The first diode and the second diode can identify the data line and connect it to the third terminal J3, while the first NMOS transistor N1 and the second NMOS transistor N2 can identify the ground line and connect it to the fourth terminal J4. The third terminal J3 serves as a power source, and the fourth terminal J4 serves as a ground source to supply power to the external device. Data is received from and sent to the data line based on the single bus protocol.

[0051] For example, the first terminal J1 is connected to the data line, and the second terminal J2 is connected to the ground line, i.e., in a forward connection state. Before data is received from the data line, the voltage level on the data line is always high, and the voltage level on the ground line is always low. Therefore, when the first terminal J1 is just connected to the data line and the second terminal J2 is just connected to the ground line, and no data has yet been received from the data line, the voltage level on the first terminal J1 is high. This high voltage level turns on the second NMOS transistor N2, connecting the fourth terminal J4 to the second terminal J2 through the second NMOS transistor N2 and thus to the ground line. The first terminal J1 is connected to the third terminal J3 via the sixth NMOS transistor N6 connected as a diode, and the third terminal J3 is connected to the data line via the sixth NMOS transistor N6 connected as a diode. The specific potential of the third terminal J3 is the potential of the first terminal J1 minus the voltage drop across the sixth NMOS transistor N6 connected as a diode. At the same time, the first NMOS transistor N1 is in the off state. Due to the unidirectional conductivity of the seventh NMOS transistor N7 used as a diode, the potential of the second terminal J2 does not affect the potential of the third terminal J3. See also Figure 4 , Figure 4 The timing diagram at this time is shown.

[0052] For illustration, let's take the case where the first terminal J1 is connected to the ground line and the second terminal J2 is connected to the data line, i.e., reverse insertion. Before data is received from the data line, the voltage level on the data line is always high, and the voltage level on the ground line is always low. Therefore, when the first terminal J1 is just connected to the ground line and the second terminal J2 is just connected to the data line, and no data has yet been received from the data line, the voltage level on the second terminal J2 is high. This high voltage level turns on the first NMOS transistor N1, connecting the fourth terminal J4 to the first terminal J1 through the first NMOS transistor N1 and thus to the ground line. The second terminal J2 is connected to the third terminal J3 through the seventh NMOS transistor N7 connected as a diode, and the third terminal J3 is connected to the data line through the seventh NMOS transistor N7 connected as a diode. The specific potential of the third terminal J3 is the potential of the second terminal J2 minus the voltage drop across the seventh NMOS transistor N7 connected as a diode. Simultaneously, the second NMOS transistor N2 is in the off state. Due to the unidirectional conductivity of the sixth NMOS transistor N6, which functions as a diode, the potential of the first terminal J1 does not affect the potential of the third terminal J3.

[0053] During the process of receiving data from the data line, the data line may be pulled low, that is, the voltage levels of the first terminal J1 and the second terminal J2 are both low, and the first NMOS transistor N1, the second NMOS transistor N2, the sixth NMOS transistor N6, and the seventh NMOS transistor N7 are all in the off state. In this case, the energy storage capacitor CAP1 is used to maintain the voltage level of the third terminal J3. To prevent the fourth terminal J4 from floating, the power lock control circuit controls the first terminal J1 and the second terminal J2 so that the ground line and the fourth terminal J4 are locked when the first terminal J1 and the second terminal J2 are inserted between the data line and the ground line, regardless of whether they are inserted in the forward or reverse direction. The power lock control circuit is used to output a first control signal CRTL1 to the gate of the third NMOS transistor N3 and a second control signal CRTL2 to the gate of the fourth NMOS transistor N4. When the circuit of this embodiment is initially powered on, the first control signal CRTL1 and the second control signal CRTL2 are both 0. Whether the device is plugged in the forward or reverse direction, the connection between the terminal (which may be the first terminal J1 or the second terminal J2) connected to the ground line selected by the power selection circuit and the fourth terminal J4 is not affected. After the power lock circuit is powered on, before it starts to receive data from the data line, the level state of the first control signal CRTL1 changes to the opposite level state when the first terminal J1 is initially connected, and the level state of the second control signal CRTL2 changes to the opposite level state when the second terminal J2 is initially connected. Thereafter, before power is turned off, the level states of the first lock control signal CRTL1 and the second control signal CRTL2 remain unchanged.

[0054] Taking the forward insertion as an example, when the first terminal J1 is initially connected, the voltage level is high, while when the second terminal J2 is initially connected, the voltage level is low. During initial power-up, both the first control signal CRTL1 and the second control signal CRTL2 are 0. After power-up, before receiving data from the data line, the voltage level of the first control signal CRTL1 changes to the opposite of the voltage level when the first terminal J1 was initially connected, that is, the first control signal CRTL1 is low, which turns off the third NMOS transistor N3. The voltage level of the second control signal CRTL2 changes to the opposite of the voltage level when the second terminal J2 was initially connected, that is, the second control signal CRTL2 is high, which turns on the fourth NMOS transistor N4, thereby connecting the fourth terminal J4 to ground and preventing it from floating. Thereafter, the voltage levels of the first control signal CRTL1 and the second control signal CRTL2 remain unchanged until power is removed.

[0055] Taking reverse insertion as an example, the voltage level of the first terminal J1 is low when it is initially connected, and the voltage level of the second terminal J2 is high when it is initially connected. During initial power-up, before receiving data from the data line, the voltage level of the first control signal CRTL1 changes to the opposite of the voltage level when the first terminal J1 is initially connected. That is, the first control signal CRTL1 is high. This first control signal CRTL1 turns on the third NMOS transistor N3, thereby connecting the fourth terminal J4 to the ground line and preventing the fourth terminal J4 from floating. The voltage level of the second control signal CRTL2 changes to the opposite of the voltage level when the second terminal J2 is initially connected. That is, the second control signal CRTL2 is low. This second control signal CRTL2 turns off the fourth NMOS transistor N4. Thereafter, the voltage levels of the first control signal CRTL1 and the second control signal CRTL2 remain unchanged until power is removed.

[0056] Two D flip-flops are provided in the power lock control circuit, one of which is used to store a signal opposite to the level state when the first terminal J1 is initially connected and output a first control signal CRTL1; the other D flip-flop is used to store a signal opposite to the level state when the second terminal J2 is initially connected and output a second control signal CRTL2.

[0057] See also Figure 5 The power lock control circuit of this embodiment includes a power-on reset unit 11, a delay unit 21, a first D flip-flop 31, a second D flip-flop 41, a first inverter 51, and a second inverter 61. The first inverter 51 and the second inverter 61 are both Schmitt inverters.

[0058] The output of the power-on reset unit 11 is connected to the input of the delay unit 21, the reset terminal RN1 of the first D flip-flop, and the reset terminal RN2 of the second D flip-flop. The output of the delay unit 21 is connected to the clock terminal CK1 of the first D flip-flop and the clock terminal CK2 of the second D flip-flop. The input of the first inverter 51 is connected to the first terminal J1, and the output of the first inverter 51 is connected to the D terminal D1 of the first D flip-flop. The input of the second inverter 61 is connected to the second terminal J2, and the output of the second inverter 61 is connected to the D terminal D2 of the second D flip-flop.

[0059] The power selection circuit identifies the data line and ground line, connects the data line to the third terminal J3, and the ground line to the fourth terminal J4. The power-on reset unit 11 (POR) begins operation. When the potential of the third terminal J3 rises to the POR reset release voltage, it resets the first D flip-flop 31 and the second D flip-flop 41. After reaching the POR reset release voltage, it outputs a high-level RSTN signal to release the first and second D flip-flops. The RSTN signal passes through the delay unit 21 to generate the RSTN_DLY signal. Before the RSTN_DLY signal is obtained, the first control signal CRTL1 and the second control signal CRTL2 are both 0, and the connection between the ground line and the fourth terminal J4 is not locked. After obtaining the RSTN_DLY signal, the RSTN_DLY signal serves as the sampling clock of the first D flip-flop 31 and the second D flip-flop 41, and latches the signal after the levels on the data line and the ground line are inverted, that is, the level state of the first control signal CRTL1 is changed to the opposite level state when the first terminal J1 is initially connected, and the level state of the second control signal CRTL2 is changed to the opposite level state when the second terminal J2 is initially connected. The first control signal CRTL1 and the second control signal CRTL2 cause the power selection circuit to turn on the third NMOS tube N3 or the fourth NMOS tube N4, and lock the connection state between the ground line and the fourth terminal J4.

[0060] See also Figure 6 Taking the forward insertion as an example, point A indicates that the potential of the third terminal J3 reaches the POR reset release voltage, the RSTN signal goes high, and the first and second D flip-flops are reset and released. Point B indicates that after a time delay of t, the RSTN_DLY signal goes high. The first D flip-flop 31 and the second D flip-flop 41 latch the signals at this time. The first control signal CRTL1 output by the first D flip-flop is low, and the second control signal CRTL2 output by the second D flip-flop is high. As a result, the third NMOS transistor N3 is turned off and the fourth NMOS transistor N4 is turned on. Since the data line and the ground line do not exchange after connection, the first control signal CRTL1 and the second control signal CRTL2 do not change before power is removed, thus locking the ground line and the fourth terminal J4, preventing the fourth terminal J4 from floating.

[0061] During single-bus communication, after receiving data from the data line, response data must also be sent to the data line. Therefore, a response signal is obtained through the gate of the fifth NMOS transistor N5. When the response signal is obtained, the fifth NMOS transistor N5 is turned on, short-circuiting the first terminal J1 and the second terminal J2. As a result, regardless of whether the first terminal J1 or the second terminal J2 is connected to the data line, the ground line pulls it down due to the conduction of the fifth NMOS transistor N5. In addition, the potential of the third terminal J3 slowly decreases when receiving low-level data from the data line or sending data to the data line. This is because when receiving low-level data from the data line or sending data to the data line, the data line level state changes to a low level state, the sixth NMOS transistor N6 and the seventh NMOS transistor N7 are both turned off, and the potential of the third terminal J3 is provided by the energy storage capacitor CAP1.

[0062] See also Figure 7 , taking the positive insertion as an example, Figure 7 The figure shows a timing diagram for a positive insertion. Segment C represents the stage where the external host sends a code to the data line, that is, receives data from the data line. It can be seen that due to the presence of energy storage capacitor CAP1, the third terminal J3 does not lose power. Segment D represents the stage where the response data is sent to the external data line, that is, the stage where data is sent to the data line. During this stage, the fifth NMOS transistor receives a response signal, which is the DATA_OUT signal in a high-level state. At this time, the fifth NMOS transistor N5 is in the on state, the first terminal J1 and the second terminal J2 are short-circuited, and the data line is pulled low. The external host then determines that a response signal is present based on the low state of the data line.

[0063] Therefore, regardless of whether the device is plugged in forward or reverse, this embodiment can identify the data line and the ground line through the power selection circuit, and lock the connection of the ground line through the power locking circuit to prevent the fourth terminal J4 from being left floating, and can receive data from the data line and send corresponding response data to the data line.

[0064] Since the conduction conditions of the sixth NMOS transistor N6 and the seventh NMOS transistor N7 used as diode connections are both Vgs>Vth, the voltage provided by the data line to the third terminal needs to be subtracted by a voltage of Vth, that is, there will be a diode voltage drop. Figure 8 Compared with the diode full-wave rectification scheme, this embodiment has only one diode voltage drop between the data line and the ground line. Compared with the method of using MCU control, the design of this article improves the integration and reduces the production cost.

[0065] Second embodiment of a circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss:

[0066] The difference between this embodiment and the first embodiment of the circuit for automatically identifying forward and reverse plugging with low voltage loss for a single bus protocol lies in the specific structure of the identification and selection unit.

[0067] See also Figure 9 On the basis of the first embodiment, the identification and selection unit of this embodiment further includes a first NAND gate 101, a second NAND gate 102, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5 and a sixth PMOS transistor P6.

[0068] An input end of the first NAND gate 101 is connected to the first terminal J1 and obtains the second control signal CRTL2. An output end of the first NAND gate 101 is connected to the gate of the first PMOS transistor P1. The source of the first PMOS transistor P1 is connected to the first terminal J1. The drain of the first PMOS transistor P1 is connected to the third terminal J3.

[0069] An input end of the second NAND gate 102 is connected to the second terminal J2 and obtains the first control signal CRTL1. An output end of the second NAND gate 102 is connected to the gate of the second PMOS transistor P2. A source of the second PMOS transistor P2 is connected to the second terminal J2. A drain of the second PMOS transistor P2 is connected to the third terminal J3.

[0070] The drain of the third PMOS transistor P3 is connected to the first terminal J1, the gate of the third PMOS transistor P3 is connected to the third terminal J3, the gate of the fourth PMOS transistor P4 is connected to the first terminal J1, and the drain of the fourth PMOS transistor P4 is connected to the third terminal J3; the substrate of the third PMOS transistor P3, the source of the third PMOS transistor P3, the substrate of the fourth PMOS transistor P4, the source of the fourth PMOS transistor P4, and the substrate of the first PMOS transistor P1 are connected to each other.

[0071] The drain of the fifth PMOS transistor P5 is connected to the second terminal J2, the gate of the fifth PMOS transistor P5 is connected to the third terminal J3, the gate of the sixth PMOS transistor P6 is connected to the second terminal J2, and the drain of the sixth PMOS transistor P6 is connected to the third terminal J3; the substrate of the fifth PMOS transistor P5, the source of the fifth PMOS transistor P5, the substrate of the sixth PMOS transistor P6, the source of the sixth PMOS transistor P6, and the substrate of the second PMOS transistor P2 are connected to each other.

[0072] In this embodiment, after the data line and the ground line are identified, the signal at the first terminal J1 and the second control signal CRTL2 control the first PMOS transistor P1 after passing through the first NAND gate 101, and the second terminal J2 and the first control signal CRTL1 control the second PMOS transistor P2 after passing through the second NAND gate 102. As a result, the data line is connected to the third terminal J3 through the first PMOS transistor P1 or the second PMOS transistor P2. When transmitting a high level, there is no threshold loss in the first PMOS transistor P1 and the second PMOS transistor P2, thereby achieving the purpose of further eliminating the diode voltage drop.

[0073] The third PMOS transistor P3 and the fourth PMOS transistor P4 function to select a substrate for the first PMOS transistor P1 , and the fifth PMOS transistor P5 and the sixth PMOS transistor P6 function to select a substrate for the second PMOS transistor P2 .

[0074] See also Figure 10 Taking the third PMOS transistor P3 and the fourth PMOS transistor P4 as an example of selecting a substrate for the first PMOS transistor P1, when the potential of the third terminal J3 is higher than the potential of the first terminal J1, the fourth PMOS transistor P4 is turned on and the third PMOS transistor P3 is turned off, so that the substrate of the first PMOS transistor P1 is connected to the third terminal J3; when the potential of the third terminal J3 is lower than the potential of the first terminal J1, the third PMOS transistor P3 is turned on and the fourth PMOS transistor P4 is turned off, so that the substrate of the first PMOS transistor P1 is connected to the first terminal J1.

[0075] See also Figure 10 , Figure 10 The figure shows a timing diagram for positive insertion. Under the influence of the RSTN_DLY signal, the level of the first control signal CRTL1 is locked to the opposite level of the level when the first terminal J1 is initially connected, that is, the low level state. The level of the second control signal CRTL2 is locked to the opposite level of the level when the second terminal J2 is initially connected, that is, the high level state. When the external host sends a code to the data line, that is, when receiving data from the data line, the first terminal J1 drops to a low level, shutting off the first PMOS transistor P1. At this time, the potential at the third terminal J3 is maintained by CAP1, and the substrate of the first PMOS transistor P1 is connected to the third terminal J3.

[0076] Since the conduction conditions of the first PMOS transistor P1 and the second PMOS transistor P2 are both |Vgs|>|Vth| and |Vds|<|Vgs|-|Vth|, Vds can be equal to 0, that is, the diode voltage drop is eliminated. Figure 11 Since there is no threshold loss in the first PMOS transistor P1 and the second PMOS transistor P2 when transmitting a high level, the purpose of eliminating the diode voltage drop can be achieved.

[0077] Chip Example:

[0078] See also Figure 12 The chip 1 of this embodiment includes a shell, which includes an automatic forward and reverse plug-in identification module 10 and a functional module 20. The automatic forward and reverse plug-in identification module includes the circuit of the first embodiment or the second embodiment for automatic forward and reverse plug-in identification of the single bus protocol with low voltage loss.

[0079] The functional module 20 includes a power terminal VC3 and a ground terminal VS3 . The power terminal VC3 is connected to the third terminal J3 , and the ground terminal VS3 is connected to the fourth terminal J4 .

[0080] The chip of this embodiment can be used in any scenario using a single bus communication protocol. When chip 1 communicates with an external device via a single bus protocol 1, it is connected to two pads of the external device, namely PAD30 and PAD40. In one case, PAD30 corresponds to the data line and PAD40 corresponds to the ground line. In another case, PAD30 corresponds to the ground line and PAD40 corresponds to the data line. However, no matter which case, the forward and reverse automatic identification module 10 can identify the pads corresponding to the data line and the ground line, and connect the pad corresponding to the data line to the third terminal J3, and connect the pad corresponding to the ground line to the fourth terminal J4, thereby using the third terminal J3 as the power supply terminal of the functional module 20 and the fourth terminal J4 as the ground terminal of the functional module 20.

[0081] Thus, the functional module 20 realizes single bus communication with the external device. When the functional module 20 sends a response signal to the data line, the response signal is sent by providing the response signal to the gate of the fifth NMOS transistor.

[0082] Optionally, according to actual needs, there may be multiple functional modules 20, and the power terminals of the functional modules 20 are all connected to the third terminal J3, and the ground terminals of the functional modules 20 are all connected to the fourth terminal J4.

[0083] Device Example:

[0084] This embodiment includes a housing, wherein the housing includes the aforementioned chip.

[0085] In summary, the power selection circuit of the present invention realizes the identification of the data line and the ground line, so that no matter whether the first terminal and the second terminal are inserted forward or reversely between the data line and the ground line, the data line can be connected to the third terminal and the ground line can be connected to the fourth terminal. While ensuring the automatic identification function of forward and reverse insertion, the voltage obtained from the data line can be increased, the voltage loss can be reduced, and good support can be provided for the single bus to operate in a lower voltage environment. At the same time, no complex peripheral circuit is required for selection, and the implementation method is simple. The chip implemented by the present invention based on the above circuit can automatically identify and match the corresponding data line and ground line regardless of whether it is inserted forward or reverse, and can normally power the chip, so that the chip can receive data from the data line and send data to the data line, greatly improving the user experience. In addition, it supports the forward and reverse insertion of multiple chips on the bus at the same time instead of only supporting one chip.

[0086] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit for automatic identification of forward and reverse insertion of a single bus protocol with low voltage loss, characterized in that: include: Power selection circuit and power lock control circuit; The power selection circuit includes an identification and selection unit and a connection terminal group, the connection terminal group includes a first terminal, a second terminal, a third terminal and a fourth terminal, the first terminal and the second terminal are used for forward insertion or reverse insertion between an external data line and a ground line; The identification and selection unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first diode, a second diode and an energy storage capacitor; The first terminal is respectively connected to the drain of the first NMOS transistor, the gate of the second NMOS transistor, the drain of the third NMOS transistor, the first electrode of the fifth NMOS transistor, and the anode of the first diode; The second terminal is respectively connected to the gate of the first NMOS transistor, the drain of the second NMOS transistor, the drain of the fourth NMOS transistor, the second electrode of the fifth NMOS transistor, and the anode of the second diode; The third terminal is connected to the cathode of the first diode and the cathode of the second diode respectively; The fourth terminal is connected to the source of the first NMOS transistor, the source of the second NMOS transistor, the source of the third NMOS transistor, and the source of the fourth NMOS transistor respectively; The third terminal and the fourth terminal are connected via the energy storage capacitor; The first NMOS transistor, the second NMOS transistor, the first diode, and the second diode cooperate to connect the data line to the third terminal and the ground line to the fourth terminal, and the power lock control circuit is used to output a first control signal to the gate of the third NMOS transistor that is opposite to the level state when the first terminal is initially connected, and output a second control signal to the gate of the fourth NMOS transistor that is opposite to the level state when the second terminal is initially connected; The gate of the fifth NMOS transistor is used to obtain a response signal, and the fifth NMOS transistor is turned on when the response signal is obtained.

2. The circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss as claimed in claim 1, characterized in that: The power lock control circuit includes a first D flip-flop and a second D flip-flop, the first D flip-flop is used to store a first control signal that is opposite to the level state when the output is initially connected to the first terminal, and the second D flip-flop is used to store a second control signal that is opposite to the level state when the output is initially connected to the second terminal.

3. The circuit for automatically identifying forward and reverse insertion of a single bus protocol and having low voltage loss as claimed in claim 2, characterized in that: The power lock control circuit further includes a power-on reset unit, a delay unit, a first inverter, and a second inverter; The output end of the power-on reset unit is respectively connected to the input end of the delay unit, the reset end of the first D flip-flop, and the reset end of the second D flip-flop; The output end of the delay unit is respectively connected to the clock end of the first D flip-flop and the clock end of the second D flip-flop; the input end of the first inverter is connected to the first terminal, and the output end of the first inverter is connected to the D end of the first D flip-flop; the input end of the second inverter is connected to the second terminal, and the output end of the second inverter is connected to the D end of the second D flip-flop.

4. The circuit for automatically identifying forward and reverse insertion of a single bus protocol and having low voltage loss as claimed in claim 3, characterized in that: The first inverter and the second inverter are both Schmitt inverters.

5. The circuit for automatically identifying forward and reverse insertion of a single bus protocol and having low voltage loss as claimed in claim 1, characterized in that: The first diode is a sixth NMOS transistor used for diode connection, and the second diode is a seventh NMOS transistor used for diode connection.

6. The circuit for automatically identifying forward and reverse insertion of a single bus protocol and having low voltage loss as claimed in claim 5, characterized in that: The gate of the sixth NMOS transistor is connected to the drain of the sixth NMOS transistor, the drain of the sixth NMOS transistor is connected to the first terminal, and the source of the sixth NMOS transistor is connected to the third terminal; The gate of the seventh NMOS transistor is connected to the drain of the seventh NMOS transistor, the drain of the seventh NMOS transistor is connected to the second terminal, and the source of the seventh NMOS transistor is connected to the third terminal.

7. The circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss as claimed in claim 1, characterized in that: The identification and selection unit further includes a first NAND gate, a second NAND gate, a first PMOS transistor, and a second PMOS transistor; An input end of the first NAND gate is connected to the first terminal and obtains a second control signal having a level state opposite to that when the second terminal is initially connected, an output end of the first NAND gate is connected to the gate of the first PMOS transistor, a source of the first PMOS transistor is connected to the first terminal, and a drain of the first PMOS transistor is connected to the third terminal; The input end of the second NAND gate is connected to the second terminal and obtains the first control signal whose level state is opposite to that when the first terminal is initially connected. The output end of the second NAND gate is connected to the gate of the second PMOS transistor, the source of the second PMOS transistor is connected to the second terminal, and the drain of the second PMOS transistor is connected to the third terminal.

8. The circuit for automatically identifying forward and reverse insertion of a single bus protocol with low voltage loss as claimed in claim 7, characterized in that: The identification and selection unit further includes a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor; The drain of the third PMOS transistor is connected to the first terminal, the gate of the third PMOS transistor is connected to the third terminal, the gate of the fourth PMOS transistor is connected to the first terminal, and the drain of the fourth PMOS transistor is connected to the third terminal; the substrate of the third PMOS transistor, the source of the third PMOS transistor, the substrate of the fourth PMOS transistor, the source of the fourth PMOS transistor, and the substrate of the first PMOS transistor are connected to each other; The drain of the fifth PMOS transistor is connected to the second terminal, the gate of the fifth PMOS transistor is connected to the third terminal, the gate of the sixth PMOS transistor is connected to the second terminal, and the drain of the sixth PMOS transistor is connected to the third terminal; the substrate of the fifth PMOS transistor, the source of the fifth PMOS transistor, the substrate of the sixth PMOS transistor, the source of the sixth PMOS transistor, and the substrate of the second PMOS transistor are connected to each other.

9. A chip, comprising a housing, characterized in that: The housing includes a forward and reverse plug-in automatic identification module and a functional module, wherein the forward and reverse plug-in automatic identification module includes a circuit for automatic forward and reverse plug-in identification of a single bus protocol with low voltage loss according to any one of claims 1 to 8; The functional module includes a power supply terminal and a ground terminal, the power supply terminal is connected to the third terminal, and the ground terminal is connected to the fourth terminal. The functional chip is further used to provide a response signal to the gate of the fifth NMOS tube.

10. A device comprising a housing, characterized in that: The housing includes the chip as claimed in claim 9.

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