Superposition protection state machine coordination method, state machine coordinator and system

Abstract

The invention discloses a state machine coordination method, state machine coordinator and system for superposition protection, and relates to the field of SDH. The method comprises the following steps: setting a first register, and storing main and standby SDH port alarms of an MSP protection group and all VC4 time slot alarms under SDH ports; setting a second sum register, and storing all VC4 time slot alarms under main and standby SDH ports of the SNCP protection group; an MSP state machine of the MSP protection group performs operation according to alarm of the main and standby SDH ports in the first register, and sends a switching result to the second register after the operation is finished; and if protection switching occurs and when the MSP and the SNCP are subjected to superposition protection, the second register obtains a VC4 time slot alarm under the corresponding SDH port from the first register and outputs the VC4 time slot alarm to an SNCP state machine of the SNCP protection group. According to the invention, it is ensured that MSP protection is executed first and SNCP protection is executed later, so that the SNCP protection is prevented from being mistakenly switched for many times.

Description

Technical Field

[0001] The present application relates to the field of SDH, and in particular to a state machine coordination method, a state machine coordinator and a system for superimposed protection. Background Art

[0002] In the SDH (Synchronous Digital Hierarchy) field, dual-fiber Multiplex Section 1+1 Protection (MSP1+1) overlaid with Subnetwork Connection Protection (SNCP1+1) works as follows: MSP1+1 controls the switching of all 64 VC4 timeslots on an SDH port, while SNCP1+1 controls the switching of only a single VC4 timeslot on an SDH port. Typically, MSP (Multiplex Section Protection) is implemented as an outer layer, while SNCP (Subnetwork Connection Protection) is implemented as an inner layer. Switching in the outer layer must occur before switching in the inner layer. This requires coordination between the MSP and up to 64 SNCPs, making it extremely difficult. Consequently, the inner SNCP protection often suffers from multiple erroneous switching.

[0003] When MSP1+1 is superimposed on SNCP1+1 (multiple groups are possible), the SNCP1+1 protection group must obtain the alarm source of its input based on the MSP1+1 switching result. The SNCP active channel is divided into active 1 and active 2 (the active and standby channels of MSP1), and the SNCP standby channel is divided into standby 1 and standby 2 (the active and standby channels of MSP2). Once an alarm changes, the SNCP protection must wait for the MSP protection to switch first before reading the correct VC4 timeslot alarm and performing protection state machine calculations. Figure 1 As shown in the figure, SNCP_1 to SNCP_64 represent SNCP protection groups 1 to 64, respectively; MSP1+1_1 represents the first MSP1+1 protection group. If MSP1+1_1 is in active mode, the active alarm for SNCP_1 reads SDH.VC4 = 1.1; if MSP1+1_1 is in standby mode, the active alarm for SNCP_1 reads SDH.VC4 = 2.1; if MSP1+1_2 is in active mode, the standby alarm for SNCP_1 reads SDH.VC4 = 3.1; if MSP1+1_2 is in standby mode, the standby alarm for SNCP_1 reads SDH.VC4 = 4.1.

[0004] The SNCP1+1 protection state machine and the MSP1+1 protection state machine are executed by the CPU in software and can be placed in one thread or multiple threads. For a single thread, the MSP protection and SNCP protection state machines are executed sequentially in a large loop, and their sequence cannot be 100% guaranteed. Figure 2As shown in the figure, if an alarm occurs on the primary MSP line and the software reaches T1, the execution order is MSP1, MSP2, and SNCP, ensuring that MSP protection executes before SNCP protection. If the software reaches T2 or T3 at this time, missing a round of MSP state machine processing, SNCP protection will switch first in this round, and MSP protection will switch first in the second round. After the MSP protection switches, the primary SNCP protection alarm disappears. After waiting for recovery, SNCP protection will switch back to its primary position. This phenomenon appears to be multiple switching.

[0005] like Figure 3 As shown, a state machine using two threads executes MSP protection and SNCP protection, respectively. Without thread mutual exclusion, the execution order of MSP and SNCP protection is highly random. Even with thread mutual exclusion, only one of thread 1 and thread 2 is guaranteed to execute before the other. However, the order of execution of threads 1 and 2 is also random, and their order cannot be 100% guaranteed. This means that when the alarm occurs at time T1, there is a 50% probability that either thread will execute first. If SNCP protection executes first, the same problem as in the single-thread mode exists, with multiple SNCP protection switching issues, and the probability of failure is even greater than in the single-thread mode.

[0006] It can be seen from this that, regardless of single-thread or multi-thread, when an alarm changes, it cannot be guaranteed that MSP protection will be executed first and SNCP protection will be executed later, and there is a problem of multiple erroneous switching of SNCP protection. Summary of the Invention

[0007] The present application provides a state machine coordination method, a state machine coordinator, and a system for superimposed protection, which can solve the technical problem of multiple erroneous switching of SNCP protection in the prior art.

[0008] In a first aspect, an embodiment of the present application provides a state machine coordination method for overlay protection, the method comprising: Set the first register to store the alarms of the primary and backup SDH ports of the MSP protection group and all VC4 timeslot alarms under the SDH port; set the second register to store all VC4 timeslot alarms under the primary and backup SDH ports of the SNCP protection group; The MSP state machine of the MSP protection group performs calculations based on the primary and backup SDH port alarms in the first register, and sends the switching results to the second register after the calculations are completed; If protection switching occurs and MSP and SNCP superimpose protection, the second register obtains the VC4 time slot alarm under the corresponding SDH port from the first register and outputs it to the SNCP state machine of the SNCP protection group; otherwise, it obtains the corresponding VC4 time slot alarm under the primary and backup SDH ports of the SNCP protection group from the alarm bus and outputs it to the SNCP state machine of the SNCP protection group.

[0009] In conjunction with the first aspect, in one embodiment, the method further includes: VC service alarms from the alarm bus are stored in real time and stored according to the index of port value+SDH port alarm+64 VC4 time slot alarms; the first register and the second register obtain corresponding alarms from the storage.

[0010] In conjunction with the first aspect, in one embodiment, the method further includes: The primary and backup SDH port values ​​of the MSP protection group and the VC4 timeslot of the SNCP protection group are obtained, and based on this, it is determined that when MSP and SNCP superimposed protection is used, after the SNCP state machine operation is completed, the switching results of the MSP state machine and the SNCP state machine are integrated and a switching instruction is issued.

[0011] In combination with the first aspect, in one embodiment, the switching result is sent via a pulse signal, and the two MSP state machines respectively send the MSP switching result superimposed on the primary SNCP and the MSP switching result superimposed on the backup SNCP.

[0012] In a second aspect, an embodiment of the present application provides a state machine coordinator for overlay protection, including: The first register is used to store the primary and backup SDH port alarms of the MSP protection group and all VC4 timeslot alarms under the SDH port; The second register is used to store the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group; it is also used to receive the switching result of the MSP state machine after the primary and backup SDH port alarm calculation in the first register is completed; the second register is also used to obtain the VC4 time slot alarms under the corresponding SDH port from the first register when protection switching occurs and MSP protection and SNCP protection are superimposed, and output it to the SNCP state machine; otherwise, it obtains the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group from the alarm bus and outputs it to the SNCP state machine.

[0013] In conjunction with the second aspect, in one embodiment, the method further includes: The alarm register is used to store VC service alarms from the alarm bus in real time and store them according to the index of port value + SDH port alarm + 64 VC4 time slot alarms; it is also used to send the primary and backup SDH port alarms of the MSP protection group and all VC4 time slot alarms under the SDH port to the first register; and send the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group to the second register.

[0014] In conjunction with the second aspect, in one embodiment, the method further includes: An MSP protection group module is used to receive and output the primary and backup SDH port values ​​of the MSP protection group; An SNCP protection group module is configured to receive and output the primary and backup SDH port values ​​and corresponding VC4 timeslots of the SNCP protection group; A comparator is used to determine whether it is superposition protection according to the outputs of the MSP protection group module and the SNCP protection group module, and the comparator outputs a superposition enable signal to the second register.

[0015] In combination with the second aspect, in one embodiment, the MSP protection group module and the SNCP protection group module are also used to send alarm query signals to the alarm register after receiving the reception feedback signal of the comparator, notifying the alarm register to send corresponding alarms to the first register and the second register.

[0016] In conjunction with the second aspect, in one embodiment, the method further includes: A switching instruction issuer, which is used to obtain the primary and backup SDH port values ​​of the MSP protection group from the MSP protection group module, obtain the VC4 timeslot of the SNCP protection group from the SNCP protection group module, and determine whether MSP and SNCP superposition protection exists based on the obtained values; The switching instruction issuer is also used to receive the switching results of the MSP protection group state machine and the SNCP protection group state machine. When superimposed switching is performed, after the SNCP state machine operation is completed, the switching results of the MSP state machine and the SNCP state machine are integrated and a switching instruction is issued.

[0017] In a third aspect, an embodiment of the present application provides a protection system based on a state machine coordinator of any of the superimposed protections, including an MSP state machine of two MSP protection groups, an SNCP state machine of 64 SNCP protection groups, and a state machine coordinator; The state machine coordinator stores the SDH port alarms and the corresponding 64 VC4 time slot alarms from the alarm bus in real time, and provides corresponding alarms for the two MSP state machines and 64 SNCP state machines; The MSP state machine inputs the SDH port value and the switching result to the state machine coordinator, and the SNCP state machine inputs the SDH port value, the corresponding VC4 time slot, and the switching result to the state machine coordinator; When MSP and SNCP superimpose protection and protection switching occurs, the state machine coordinator obtains the VC4 time slot alarms under the SDH ports of the two MSP state machines and outputs them to the SNCP state machine of the SNCP protection group; otherwise, it outputs 64 VC4 time slot alarms from the alarm bus to the SNCP state machine of the SNCP protection group.

[0018] The beneficial effects of the technical solutions provided in the embodiments of the present application include: By configuring a first register and a second register, the first register provides SDH port alarms for the MSP protection group. The MSP state machine performs calculations and sends the switching results to the second register. If a protection switch occurs and MSP and SNCP protection overlap, the second register retrieves the VC4 timeslot alarm for the corresponding SDH port from the first register and outputs it to the SNCP state machine of the SNCP protection group. This ensures that when an alarm changes, MSP protection is executed first, followed by SNCP protection (this can be for multiple groups), resolving the problem of multiple SNCP protection switching errors that occurs in existing technologies.

[0019] Currently, adding a delay to SNCP protection—that is, waiting for a period of time, ranging from 50ms to over, when an alarm occurs—can only reduce the probability of false switching. However, if the delay is insufficient, due to factors such as CPU task jamming and blocking, exceeding the delay time, SNCP protection can still result in multiple false switchings. Furthermore, when only a VC4 timeslot alarm is present, SNCP protection will inevitably time out when switching is required. In contrast, the present application can 100% guarantee the execution order of MSP protection followed by SNCP protection, without affecting SNCP protection's independent handling of VC4 timeslot alarms. This eliminates the need for delays and prevents switching timeouts.

[0020] In addition, the present application can use a state machine coordinator to intervene in MSP protection and SNCP protection in a modular manner, maintaining the standardization of the MSP state machine and the SNCP state machine, without the need for strong coupling to modify the state machine, thereby maintaining communication with old equipment and protection of other manufacturers without being affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the protection relationship of MSP1+1 superimposed on N groups of SNCP1+1 in the background technology; Figure 2 A schematic diagram of a single-threaded mode in the background technology; Figure 3 A schematic diagram of a multi-threaded mode in the background technology; Figure 4 This is a flow chart of the state machine coordination method for superimposed protection according to an embodiment of the present application; Figure 5 This is a structural diagram of the state machine coordinator for superimposed protection according to an embodiment of the present application; Figure 6 This is a schematic diagram of a state machine coordination system for superimposed protection according to an embodiment of the present application; Figure 7 This is a schematic diagram of the alarm register according to an embodiment of the present application; Figure 8 This is a schematic diagram of the MSP protection group module in an embodiment of the present application; Figure 9This is a schematic diagram of the SNCP protection group module according to an embodiment of the present application; Figure 10 This is a schematic diagram of a comparator according to an embodiment of the present application; Figure 11 This is a schematic diagram of the first register in an embodiment of the present application; Figure 12 This is a schematic diagram of the second register in an embodiment of the present application; Figure 13 This is a schematic diagram of a switching instruction issuer according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0023] To make the objectives, technical solutions, and advantages of this application more clear, the following detailed description of the embodiments of this application is provided in conjunction with the accompanying drawings. For ease of explanation, in this application, unless otherwise specified, MSP represents MSP1+1, SNCP represents SNCP1+1, MSPN represents the Nth group of MSPs, and SNCPN represents the Nth group of SNCPs.

[0024] In a first aspect, an embodiment of the present application provides a state machine coordination method for superposition protection.

[0025] In one embodiment, referring to Figure 4 , is a flow chart of an embodiment of the state machine coordination method for superimposed protection of this application. Figure 4 As shown, the method includes: S1: Set the first register to store the alarms of the primary and backup SDH ports of the MSP protection group and all VC4 timeslot alarms under the SDH port. Set the second register to store all VC4 timeslot alarms under the primary and backup SDH ports of the SNCP protection group.

[0026] S2: The MSP state machine of the MSP protection group performs calculations based on the primary and backup SDH port alarms in the first register, and sends the switching results to the second register after the calculations are completed.

[0027] S3: If protection switching occurs and MSP and SNCP superimpose protection, the second register obtains the VC4 timeslot alarm under the corresponding SDH port from the first register and outputs it to the SNCP state machine of the SNCP protection group; otherwise, it obtains the corresponding VC4 timeslot alarm under the primary and backup SDH ports of the SNCP protection group from the alarm bus and outputs it to the SNCP state machine of the SNCP protection group.

[0028] In this embodiment, by setting the first register and the second register, the second register is under the superimposed protection of MSP and SNCP, and when protection switching occurs, the VC4 timeslot alarm under the corresponding SDH port is obtained from the first register and output to the SNCP state machine of the SNCP protection group. This can strictly ensure that when the alarm changes, the MSP protection is executed first and the SNCP protection is executed later, thereby solving the problem of multiple erroneous switching of SNCP protection in the prior art.

[0029] Furthermore, the above method also includes: S4: Obtain the primary and backup SDH port values ​​of the MSP protection group and the VC4 timeslot of the SNCP protection group, and use this to determine whether MSP and SNCP superimposed protection is used. When MSP and SNCP superimposed protection are used, after the SNCP state machine operation is completed, the switching results of the MSP state machine and the SNCP state machine are integrated, and finally a switching instruction is issued.

[0030] Furthermore, in step S2, the switching result is sent via a pulse signal, and the two MSP state machines respectively send the MSP switching result superimposed on the primary SNCP and the MSP switching result superimposed on the backup SNCP.

[0031] Furthermore, in one embodiment, the method further comprises: storing VC service alarms from the alarm bus in real time, and storing them according to the index of port value+SDH port alarm+64 VC4 time slot alarms. The first register and the second register obtain corresponding alarms from the storage.

[0032] Second, as Figure 5 As shown, an embodiment of a state machine coordinator for superimposed protection is provided, which can implement the state machine coordination method for superimposed protection. The state machine coordinator is a state machine coordinator for MSP1+1 protection superimposed on N groups of SNCP1+1 protection, which can be implemented in hardware on an FPGA or in software on a CPU. Figure 6 Figure 2 shows a schematic diagram of the state machine coordination system for superimposed protection. The state machine coordinator sits between the alarm source, the MSP state machine, and the SNCP state machine, coordinating their execution order. The system includes two MSP state machines for MSP protection groups and 64 SNCP state machines for 64 protection groups.

[0033] like Figure 5 As shown, the state machine coordinator of the superposition protection includes a first register and a second register. The first register is used to store the primary and backup SDH port alarms of the MSP protection group and all VC4 timeslot alarms under the SDH port. The first register is also used to output the primary and backup SDH port alarms to the MSP state machine.

[0034] The second register is used to store the corresponding VC4 timeslot alarms under the primary and backup SDH ports of the SNCP protection group; it is also used to receive the switching result of the MSP state machine after the primary and backup SDH port alarm calculations in the first register are completed. The second register is also used to obtain the corresponding VC4 timeslot alarms under the SDH port from the first register and output it to the SNCP state machine when protection switching occurs and MSP protection and SNCP protection overlap; otherwise, it obtains the corresponding VC4 timeslot alarms under the primary and backup SDH ports of the SNCP protection group from the alarm bus and outputs it to the SNCP state machine. In this application, the MSP protection group includes the MSP1 protection group and the MSP2 protection group, and the SNCP protection group includes SNCP1 to 64.

[0035] Furthermore, in one embodiment, the state machine coordinator also includes an alarm register for storing VC service alarms from the alarm bus in real time, and storing them according to the index of SDH port alarm + 64 VC4 time slot alarms; it is also used to send the primary and backup SDH port alarms of the MSP protection group and all VC4 time slot alarms under the SDH port to the first register; and send the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group to the second register.

[0036] Furthermore, in one embodiment, the state machine coordinator also includes an MSP protection group module, an SNCP protection group module and a comparator. The MSP protection group module is used to receive and output the primary and backup SDH port values ​​of the MSP protection group. The SNCP protection group module is used to receive and output the primary and backup SDH port values ​​and corresponding VC4 time slots of the SNCP protection group. The comparator is used to determine whether it is superposition protection based on the outputs of the MSP protection group module and the SNCP protection group module, and the comparator outputs a superposition enable signal to the second register. The MSP protection group module and the SNCP protection group module are also used to send an alarm query signal to the alarm register respectively after receiving the reception feedback signal of the comparator, and notify the alarm register to send the corresponding alarm to the first register and the second register.

[0037] Furthermore, in one embodiment, the state machine coordinator further includes a switching instruction issuer configured to obtain the primary and backup SDH port values ​​of the MSP protection group from the MSP protection group module and the VC4 timeslot values ​​of the SNCP protection group from the SNCP protection group module, and to determine whether MSP and SNCP overlapping protection is implemented based on these values. The switching instruction issuer is further configured to receive the switching results of the MSP protection group state machine and the SNCP protection group state machine. When overlapping switching is required, after the SNCP state machine completes its calculations, the switching results of the MSP and SNCP state machines are integrated and a switching instruction is issued.

[0038] Thirdly, as Figure 6 As shown, an embodiment of a protection system based on the state machine coordinator of the superimposed protection is provided. The system includes MSP state machines of two MSP protection groups, SNCP state machines of 64 SNCP protection groups, and a state machine coordinator.

[0039] The state machine coordinator stores SDH port alarms and the corresponding 64 VC4 timeslot alarms from the alarm bus in real time, and provides processed alarms to two MSP state machines (MSP1 state machine and MSP2 state machine) and 64 SNCP state machines (SNCP1 state machine, SNCP2 state machine...SNCP64 state machine).

[0040] The MSP state machine inputs the SDH port value and switching result to the state machine coordinator, and the SNCP state machine inputs the SDH port value, the corresponding VC4 time slot, and switching result to the state machine coordinator.

[0041] When MSP and SNCP superimpose protection and protection switching occurs, the state machine coordinator obtains the VC4 timeslot alarms under the SDH ports of the two MSP state machines and outputs them to the SNCP state machine of the SNCP protection group; otherwise, it outputs the 64 VC4 timeslot alarms from the alarm bus to the SNCP state machine of the SNCP protection group.

[0042] Specifically, A1 and B1 represent the coordinator's output signals to the MSP1 state machine, used to output the primary and backup SDH port alarms of the MSP1 protection group. A2 and B2 represent the coordinator's output signals to the MSP2 state machine, used to output the primary and backup SDH port alarms of the MSP2 protection group.

[0043] C1 and C2 are the input signals of MSP1 state machine and MSP2 state machine to the state machine coordinator respectively, and input the SDH port values ​​of the two MSP protection groups.

[0044] E1 and E2 are the input signals of MSP1 state machine and MSP2 state machine to the state machine coordinator respectively, and are the switching results of the input MSP protection group. In this application, the switching result also carries an operation end signal.

[0045] X1 and Y1 represent the coordinator's output signals to the SNCP1 state machine, outputting a VC4 timeslot alarm to the SNCP1 state machine. Similarly, X64 and Y64 represent the coordinator's output signals to the SNCP64 state machine, outputting a VC4 timeslot alarm to the SNCP64 state machine.

[0046] W1~W64 are the input signals of SNCP1~SNCP64 state machines to the state machine coordinator, inputting the SDH port value + VC4 time slot of each SNCP protection group.

[0047] Z1~Z64 are the input signals of SNCP1 state machine~SNCP64 state machine to the state machine coordinator, which input the switching results of each SNCP protection group. In this application, the switching result also carries a calculation end signal.

[0048] The internal modules of the state machine coordinator for overlay protection are described in detail below.

[0049] like Figure 7 As shown, the alarm memory has 3 input signals: IN1 is the VC service alarm input from the alarm bus, which is stored in the form of port value + corresponding SDH port alarm + index of 64 VC4 timeslot alarms.

[0050] IN2 comes from the MSP protection group module OUT2 and is the alarm query signal of the MSP protection group's active and standby SDH modules.

[0051] IN3 comes from OUT2 of the SNCP protection group module and is the alarm query signal of the active and standby SDH and VC4 timeslot modules of each SNCP protection group.

[0052] The alarm memory has two output signals: OUT1 outputs the alarms of the primary and backup SDH ports of the MSP protection group and all VC4 timeslot alarms under the SDH port to IN1 of the first register.

[0053] OUT2 outputs the corresponding VC4 timeslot alarms of the SNCP1~64 active / standby ports to IN1 of the second register.

[0054] The alarm memory receives and stores alarms via IN1. It receives alarm query signals from the MSP protection group's primary and backup SDH modules via IN2 and outputs the corresponding MSP protection group's primary and backup SDH port alarms (i.e., primary and backup channel SDH port alarms) and all VC4 timeslot alarms associated with those ports to the first register. The alarm memory receives alarm query signals from the SNCP protection group's primary and backup SDH and VC4 timeslot modules via IN3 and outputs the corresponding VC4 timeslot alarms associated with the SNCP protection group's primary and backup SDH ports to the second register.

[0055] like Figure 8 As shown, the MSP protection group module has one input signal IN1, which is the SDH port value from the MSP state machine, namely, C1 and C2 signals.

[0056] The MSP protection group module has three output signals: OUT1 outputs the SDH port value to the switching instruction issuer IN1.

[0057] OUT2 outputs the alarm query signal of the MSP protection group to the alarm memory IN2.

[0058] OUT3 outputs the primary and backup SDH port values ​​of the MSP protection group to the comparator IN1.

[0059] The MSP protection group informs the MSP protection group module of its primary and backup SDH port values. After receiving the initialization write from the peripheral MSP protection group, the MSP protection group module outputs the SDH port value to the comparator. After the comparator receives the data sent by the MSP protection group module (from high impedance to valid value), it replies with a feedback signal to notify the MSP protection group module that the data has been received. In this embodiment, the feedback signal is a low-high-low pulse signal. After receiving the feedback signal, the MSP protection group module sends an alarm query signal to the alarm memory. After receiving the alarm query signal, the alarm memory outputs the corresponding MSP protection group primary and backup SDH port alarms (i.e., primary and backup channel SDH port alarms) and all VC4 time slot alarms under the port to the first register. The process of the module will be triggered only when the IN1 signal of the MSP protection group module changes. If there is no change, the MSP protection group module maintains the last output signal.

[0060] like Figure 9 As shown, the SNCP protection group module is similar to the MSP protection group module and has one input signal IN1. IN1 is the primary and backup SDH port values ​​+ VC4 timeslot values ​​from 1 to 64 SNCP protection groups, namely W1 to W64.

[0061] The SNCP protection group module has three output signals: OUT1 outputs the SDH port value + the corresponding single time slot to the switching instruction issuer IN2.

[0062] OUT2 outputs the alarm query signal of the primary and backup SDH port values ​​+ VC4 timeslot value of the SNCP protection group to the alarm memory IN3.

[0063] OUT3 outputs the primary and backup SDH port values ​​of the SNCP protection group to the comparator IN2.

[0064] The process of this module will be triggered only when the IN1 signal of the SNCP protection group module changes. If there is no change, the SNCP protection group module maintains the last output signal.

[0065] The SNCP protection group informs the SNCP protection group module of its primary and backup SDH port values ​​+ VC4 time slot values. After receiving the initialization write from 1 to 64 external SNCP protection groups, the SNCP protection group module outputs the primary and backup SDH port values ​​of the SNCP protection group to the comparator via OUT3. After receiving the data (from high impedance to valid value), the comparator responds with a feedback signal to notify the SNCP protection group module that the data has been received. In this embodiment, the feedback signal is a low-high-low pulse signal. After receiving the feedback signal, the SNCP protection group module sends an alarm query signal to the alarm memory. After receiving the alarm query signal, the alarm memory outputs the VC4 time slot alarm under the primary and backup SDH ports of the SNCP protection group to the second register. The process of the SNCP protection group module is triggered only when the IN1 signal of the SNCP protection group module changes. If there is no change, the SNCP protection group module maintains the last output signal.

[0066] like Figure 10 As shown, the comparator has two input signals: IN1 is the MSP protection group primary and backup SDH port values ​​from the MSP protection group module OUT3.

[0067] IN2 is the primary and backup SDH port values ​​of SNCP1 to 64 from SNCP protection group module OUT3.

[0068] The comparator has an output signal OUT1, and OUT1 outputs a superposition enable signal to IN2 of the second register.

[0069] The comparator compares the SDH port values ​​based on the two input signals to see if they are consistent. If they are consistent, it means that there is a superposition relationship between MSP protection and SNCP protection, and a superposition enable signal is sent to the second register; if they are inconsistent, it means that there is no superposition relationship between MSP protection and SNCP protection, and the second register is notified through a superposition enable signal.

[0070] like Figure 11 As shown, the first register has one input signal IN1, and IN1 inputs the MSP protection group active and standby SDH port alarms and all VC4 time slot alarms under the SDH port from the alarm memory OUT1.

[0071] The first register has 5 output signals: OUT1 outputs the MSP1 active SDH port alarm (i.e., A1) to the MSP1 state machine.

[0072] OUT2 outputs the MSP1 standby SDH port alarm (i.e., B1) to the MSP1 state machine.

[0073] OUT3 outputs the MSP2 active SDH port alarm (i.e., A2) to the MSP2 state machine.

[0074] OUT4 outputs the MSP2 standby SDH port alarm (i.e., B2) to the MSP2 state machine.

[0075] OUT5 outputs the VC4 timeslot alarms of the standby SDH ports of the MSP1 state machine and the MSP2 state machine to the second register IN3.

[0076] The first register retrieves alarms from the MSP protection group's primary and backup SDH ports from the alarm memory. Any changes are immediately output to the corresponding MSP state machine via OUT1-4, which initiates operations based on the alarm changes. The first register extracts the VC4 timeslot alarms from the MSP protection group's backup SDH port and outputs them to the second register via OUT5 for use by SNCP1-64 protection. If the first register's IN1 signal remains unchanged, OUT1-5 signals remain latched.

[0077] like Figure 12 As shown, the second register has 5 input signals: IN1 inputs the VC4 timeslot alarms of the primary and backup SDH ports of the SNCP protection group (SNCP1 to 64) from the alarm register OU1.

[0078] IN2 inputs the superposition enable signal from the comparator OUT1.

[0079] IN3 inputs the VC4 timeslot alarm of the standby SDH port of each of the MSP1 state machine and the MSP2 state machine from the first register OUT5.

[0080] IN4 inputs the switching result (i.e., E1) from the MSP1 protection group. The switching results are divided into non-switching and switching. Both can be represented by pulse signals. Non-switching is represented by: high resistance → low-high-low → high resistance, and switching is represented by: high resistance → high-low-high → high resistance.

[0081] IN5 inputs the switching result (i.e., E2) from the MSP2 protection group. The switching results are divided into non-switching and switching. Both can be represented by pulse signals. Non-switching is represented by: high resistance → low-high-low → high resistance, and switching is represented by: high resistance → high-low-high → high resistance.

[0082] The second register has 2 output signals: OUT1 outputs the active VC4 timeslot alarm (i.e., X1 to X64) to the peripheral SNCP1 to 64 state machines.

[0083] OUT2 outputs the spare VC4 timeslot alarm (i.e., X1 to X64) to the peripheral SNCP1 to 64 state machines.

[0084] The second register is the processing module for the primary and backup VC4 timeslot alarms of the SNCP1-64 protection groups. If the superposition enable signal from the comparator module is invalid, the VC4 alarms from IN1 are directly output to OUT1 and OUT2. If the superposition enable signal from the comparator module is valid (i.e., superposition protection is in effect), the alarms are output according to the superposition principle. For the primary channels of SNCP1-64, there can be two alarm sources: the first is a VC4 timeslot alarm on the primary SDH port of the SNCP protection group itself, and the second is a VC4 timeslot alarm on the backup SDH port of the superimposed MSP1. The alarm output from OUT1 of the second register to the primary SNCP1-64 depends on the E1 signal input to IN4. Similarly, the output of OUT2 depends on the E2 signal input to IN5. E1 corresponds to MSP1 superimposed on the SNCP master, and E2 corresponds to MSP2 superimposed on the SNCP backup. The second register may receive only E1 or only E2 signals each time, or both E1 and E2 may coexist. When both E1 and E2 coexist, only one of them may change while the other remains unchanged.

[0085] like Figure 13 As shown, the switching instruction issuer includes 5 input signals: IN1 inputs the MSP1 protection group primary and backup SDH port values ​​output by the MSP protection group module OUT1.

[0086] IN2 inputs the SDH port value + the corresponding single time slot output from the SNCP protection group module OUT1.

[0087] IN3 inputs the switching result (ie, E1) from the peripheral MSP1 state machine. In this application, the switching result also carries an operation completion signal.

[0088] IN4 inputs the switching result (ie, E2) from the peripheral MSP2 state machine. In this application, the switching result also carries an operation end signal.

[0089] IN5 inputs the switching result (ie, Z1 to Z64) from the peripheral SNCP1 to SNCP64 state machines. In this application, the switching result also carries an operation completion signal.

[0090] The switching instruction issuer includes an output signal OUT1, which outputs the switching results of the SDH port + all VC4 time slots through a group of control buses.

[0091] The switching command issuer obtains the two SDH port values ​​of the MSP1 state machine, the two SDH port values ​​of the MSP2 state machine, and the SNCP-protected VC4 timeslots from the MSP protection group module and the SNCP protection group module, respectively. Because MSP protection controls the switching of all VC4s under its SDH port, the switching command issuer must overwrite the corresponding switching result of the MSP protection group state machine with the switching result of a specific VC4 timeslot, thereby integrating the switching results of the MSP and SNCP state machines. For example, if MSP1 protection switches with the primary SDH=1, all 64 VC4s under SDH=1 will be switched. However, the result of the superimposed SNCP state machine calculation is no switching. Since SNCP1's primary SDH.VC4=1.5 is used, the fifth VC4 under SDH=1 will not be switched. The switching instruction issuer is updated upon receiving the completion trigger of the MSP operation, that is, after the MSP operation is completed, it waits for the SNCP protection operation to be completed, and after integrating the above switching results, it issues the switching instruction.

[0092] In this embodiment, the second register ensures that the source of the SNCP protection group's alarm remains unchanged while the MSP protection group's switching status remains unchanged. Once the MSP protection group's switching status changes, the switching command issuer transmits a new alarm to the SNCP protection group based on the situation, ensuring a strict switching order of MSP protection first and SNCP protection second.

[0093] The following provides a detailed embodiment to illustrate the state machine coordination method of the superposition protection of the present application, which includes the following steps: a1: The MSP protection group module receives the configuration data of the MSP protection group state machine, namely, the C1 and C2 signals.

[0094] a2: The MSP protection group module outputs the MSP protection group primary and backup SDH port values ​​to the comparator for superposition enable judgment.

[0095] a3: The comparator receives the data sent by the MSP protection group module (from high impedance to effective value) and replies a feedback signal to the MSP protection group module. In this embodiment, the feedback signal is a low-high-low pulse signal.

[0096] a4: The MSP protection group module receives the pulse signal from the comparator, believes that the data has been received by the comparator, and starts sending an alarm query signal to the alarm register.

[0097] a5: After receiving the alarm query signal from the MSP protection group module, the alarm register outputs the alarm of the primary and backup SDH ports of the corresponding MSP protection group and all VC4 timeslot alarms under the port to the first register.

[0098] a6: The first register output provides the MSP protection group master and backup SDH port alarms to the peripheral MSP1 state machine and MSP2 state machine for calculation.

[0099] a7: The MSP1 state machine and the MSP2 state machine output the switching result carrying the operation completion signal to the second register and the switching instruction issuer respectively. The switching instruction issuer determines whether there is superposition protection.

[0100] a8: The SNCP protection group module receives the configuration data of the state machines of the SNCP protection groups 1 to 64, namely W1 to W64.

[0101] a9: The SNCP protection group module outputs the primary and backup SDH port values ​​of the SNCP protection group to the comparator.

[0102] a10: The comparator receives the data sent by the SNCP protection group module (from high impedance to effective value), combines it with the data received from the MSP protection group module in step a3, makes a superposition enable judgment, and outputs a superposition enable signal to the second register. After a delay of 10ms, it then sends a feedback signal to the SNCP protection group module. In this embodiment, the feedback signal is a low-high-low pulse signal.

[0103] a11: The SNCP protection group module receives the pulse signal from the comparator, believes that the data has been received by the comparator, and starts sending an alarm query signal to the alarm register.

[0104] a12: After the alarm register receives the alarm query signal from the SNCP protection group module, the corresponding VC4 timeslot alarms under the SNCP1~64 active and standby ports are sent to the second register.

[0105] a13: The second register determines the superposition protection based on the superposition enable signal sent by the comparator. It waits for the switching results E1 and E2 from MSP1 and MSP2 (if MSP is configured before SNCP, E1 and E2 have already been received, and the second register will store the previous switching results of E1 and E2). Based on the E1 and E2 results, the first register or the alarm register is selected as the VC4 alarm source.

[0106] a14: The peripheral MSP1 state machine and MSP2 state machine run in real time. Each time they run, if the switching result changes, they output a pulse signal to E1 and E2.

[0107] a15: After receiving pulse signals from E1 and E2, the second register detects a change in the MSP protection. Based on the E1 and E2 switching results, it selects the corresponding alarm from the alarm memory or the first register and sends it to the SNCP1-64 protection group. While E1 and E2 are high-impedance, the second register maintains the output of the last selected source to the SNCP1-64 protection group.

[0108] a16: The peripheral SNCP1~64 state machines run in real time. Each time they run, once the switching result changes, the switching result is output to the switching instruction issuer through the Z1~Z64 signals.

[0109] a17: The switching command issuer receives the pulse signals of E1 and E2, as well as the pulse signals of SNCP1 to 64, obtains the final switching results of the current MSP1, MSP2 and SNCP1 to 64, integrates them and issues a switching command.

[0110] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0111] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit the "first", "second" and "third" to different types.

[0112] In the description of the embodiments of this application, the words "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of this application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0113] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0114] In some processes described in the embodiments of the present application, multiple operations or steps are included that appear in a specific order. However, it should be understood that these operations or steps may not be performed in the order in which they appear in the embodiments of the present application or may be performed in parallel. The sequence numbers of the operations are only used to distinguish between different operations, and the sequence numbers themselves do not represent any order of execution. In addition, these processes may include more or fewer operations, and these operations or steps may be performed in sequence or in parallel, and these operations or steps may be combined.

[0115] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above and includes a number of instructions for enabling a terminal device to execute the methods described in each embodiment of this application.

[0116] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A state machine coordination method for superposition protection, characterized in that: The method comprises: Set the first register to store the alarms of the primary and backup SDH ports of the MSP protection group and all VC4 timeslot alarms under the SDH port; set the second register to store all VC4 timeslot alarms under the primary and backup SDH ports of the SNCP protection group; The MSP state machine of the MSP protection group performs calculations based on the primary and backup SDH port alarms in the first register, and sends the switching results to the second register after the calculations are completed; If protection switching occurs and MSP and SNCP superimpose protection, the second register obtains the VC4 time slot alarm under the corresponding SDH port from the first register and outputs it to the SNCP state machine of the SNCP protection group; otherwise, it obtains the corresponding VC4 time slot alarm under the primary and backup SDH ports of the SNCP protection group from the alarm bus and outputs it to the SNCP state machine of the SNCP protection group.

2. The state machine coordination method for superposition protection according to claim 1, characterized in that: Also includes: Stores VC service alarms from the alarm bus in real time and stores them according to the index of port value + SDH port alarm + 64 VC4 timeslot alarms; The first register and the second register obtain corresponding alarms from the storage.

3. The state machine coordination method for superposition protection according to claim 1, characterized in that: Also includes: The primary and backup SDH port values ​​of the MSP protection group and the VC4 timeslot of the SNCP protection group are obtained, and based on this, it is determined that when MSP and SNCP superimposed protection is used, after the SNCP state machine operation is completed, the switching results of the MSP state machine and the SNCP state machine are integrated and a switching instruction is issued.

4. The state machine coordination method for overlay protection according to claim 1, wherein: The switching result is sent via a pulse signal, and the two MSP state machines respectively send the MSP switching result superimposed on the primary SNCP and the MSP switching result superimposed on the backup SNCP.

5. A state machine coordinator for superposition protection, characterized in that: include: The first register is used to store the primary and backup SDH port alarms of the MSP protection group and all VC4 timeslot alarms under the SDH port; The second register is used to store the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group; it is also used to receive the switching result of the MSP state machine after the primary and backup SDH port alarm calculation in the first register is completed; the second register is also used to obtain the VC4 time slot alarms under the corresponding SDH port from the first register when protection switching occurs and MSP protection and SNCP protection are superimposed, and output it to the SNCP state machine; otherwise, it obtains the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group from the alarm bus and outputs it to the SNCP state machine.

6. The state machine coordinator for overlay protection according to claim 5, characterized in that: Also includes: The alarm register is used to store VC service alarms from the alarm bus in real time and store them according to the index of port value + SDH port alarm + 64 VC4 time slot alarms; it is also used to send the primary and backup SDH port alarms of the MSP protection group and all VC4 time slot alarms under the SDH port to the first register; and send the corresponding VC4 time slot alarms under the primary and backup SDH ports of the SNCP protection group to the second register.

7. The state machine coordinator for overlay protection according to claim 6, wherein: Also includes: An MSP protection group module is used to receive and output the primary and backup SDH port values ​​of the MSP protection group; An SNCP protection group module is configured to receive and output the primary and backup SDH port values ​​and corresponding VC4 timeslots of the SNCP protection group; A comparator is used to determine whether it is superposition protection according to the outputs of the MSP protection group module and the SNCP protection group module, and the comparator outputs a superposition enable signal to the second register.

8. The state machine coordinator for overlay protection according to claim 7, wherein: The MSP protection group module and the SNCP protection group module are further configured to send an alarm query signal to the alarm register respectively after receiving a reception feedback signal from the comparator, and notify the alarm register to send a corresponding alarm to the first register and the second register.

9. The state machine coordinator for overlay protection according to claim 7, wherein: Also includes: A switching instruction issuer, which is used to obtain the primary and backup SDH port values ​​of the MSP protection group from the MSP protection group module, obtain the VC4 timeslot of the SNCP protection group from the SNCP protection group module, and determine whether MSP and SNCP superposition protection exists based on the obtained values; The switching instruction issuer is also used to receive the switching results of the MSP protection group state machine and the SNCP protection group state machine. When superimposed switching is performed, after the SNCP state machine operation is completed, the switching results of the MSP state machine and the SNCP state machine are integrated and a switching instruction is issued.

10. A protection system based on the state machine coordinator of the superimposed protection according to any one of claims 5 to 9, characterized in that: Includes MSP state machines for two MSP protection groups, SNCP state machines for 64 SNCP protection groups, and a state machine coordinator; The state machine coordinator stores the SDH port alarms and the corresponding 64 VC4 time slot alarms from the alarm bus in real time, and provides corresponding alarms for the two MSP state machines and 64 SNCP state machines; The MSP state machine inputs the SDH port value and the switching result to the state machine coordinator, and the SNCP state machine inputs the SDH port value, the corresponding VC4 time slot, and the switching result to the state machine coordinator; When MSP and SNCP superimpose protection and protection switching occurs, the state machine coordinator obtains the VC4 time slot alarms under the SDH ports of the two MSP state machines and outputs them to the SNCP state machine of the SNCP protection group; otherwise, it outputs 64 VC4 time slot alarms from the alarm bus to the SNCP state machine of the SNCP protection group.

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