CGRA mapping method for multi-task fusion execution
By generating scheduling patterns and screening the optimal schedule, the problem of unbalanced node distribution in CGRA resource allocation is solved, tile utilization and throughput are improved, and resource optimization in the time dimension is achieved.
Patent Information
- Application Number
- CN202510715624.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-19
AI Technical Summary
The traditional CGRA resource allocation method lacks scheduling constraints, resulting in an unbalanced distribution of different task nodes in the module cycle within the startup interval. As a result, the utilization of the tiles in the fusion execution mode in the time dimension cannot be improved, which reduces the throughput.
By obtaining the multi-task data flow graph and the target CGRA architecture parameters, the scheduling mode of each task in the data flow graph is generated, the tile utilization when the scheduling is combined is calculated, and the optimal scheduling is screened through differential measurement, and finally the CGRA configuration that drives the multi-task fusion execution is generated.
It effectively reduces the startup interval, reduces tile resource conflicts in the time dimension, ensures balanced node distribution, and improves tile utilization and the throughput of the fusion execution mode.
Smart Images
Figure CN120670110A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a CGRA mapping method for multi-task fusion execution, belonging to the technical field of CGRA resource allocation. Background Art
[0002] A coarse-grained reconfigurable architecture (CGRA) is a computing platform that combines an array of programmable computing units with dynamically interconnected resources. Its core capability lies in enabling the parallel execution of heterogeneous tasks through spatial isolation. By statically or dynamically partitioning the tile array into independent regions, this architecture enables different tasks (such as perception, decision-making, and communication) to run in a physically isolated environment, effectively eliminating interference between tasks. In real-time scenarios such as autonomous systems, this hardware-level isolation not only ensures the latency requirements of critical tasks, but also significantly improves energy efficiency by reducing synchronous operations, making it an ideal choice for low-power multi-tasking systems.
[0003] Existing CGRA resource allocation research focuses on two approaches: static and dynamic. Static allocation divides fixed computational regions based on offline task analysis, which simplifies resource configuration but can easily lead to resource fragmentation. Dynamic allocation adjusts tile layout to optimize pipeline balance by monitoring input data in real time, but both approaches are limited to fine-grained optimization in the spatial dimension. Notably, neither effectively addresses the issue of idle resources in the temporal dimension—for example, idle cycles caused by data dependencies or pipeline bubbles, which lead to underutilization of allocated tiles on the timeline.
[0004] Inspired by GPU core fusion technology, emerging research proposes a solution that breaks through the limitations of traditional spatial partitioning: sharing the entire tile array between tasks to achieve resource reuse in the temporal dimension. Unlike static allocation, where a single task exclusively occupies a portion of the tile, this fusion model allows all tasks to dynamically occupy all computing resources during time slice rotations, significantly improving hardware utilization in the temporal dimension and opening up new avenues for multi-task performance optimization. However, this approach introduces a new challenge for the CGRA mapper: independent dataflow graphs (DFGs) from multiple tasks require coordinated scheduling constraints. Traditional CGRAs lack this mechanism, resulting in an unbalanced distribution of nodes from different tasks across modular cycles within the initiation interval (II). Consequently, tile utilization in the temporal dimension cannot be improved under fused mapping, hindering the throughput advantage of the fused execution model. Summary of the Invention
[0005] The present invention aims to solve the problem in the existing CGRA resource allocation method that, due to the lack of coordinated scheduling constraints in traditional CGRA, nodes from different tasks are unbalancedly distributed in the modular cycle period within the startup interval. As a result, under fusion mapping, the utilization of tiles in the time dimension cannot be improved, which reduces the throughput of the fusion execution mode. A CGRA mapping method for multi-task fusion execution is proposed.
[0006] The technical solution adopted by the present invention to solve the above problems is: the present invention comprises the following steps:
[0007] Step 1: Obtain the multi-task data flow graph DFGs and target CGRA architecture parameters, and obtain the initial startup interval II based on the multi-task data flow graph DFGs and target CGRA architecture parameters;
[0008] Step 2: Generate all scheduling modes of each task in the data flow graph through mathematical rotation operation according to the current initial start interval II;
[0009] Step 3: Calculate the utilization of all tiles within the module cycle when all the scheduling of each task is combined to obtain the scheduling candidate. Combined with the differential metric, all the scheduling modes of each task are screened to obtain the optimal schedule.
[0010] Step 4: Combined with the optimal scheduling, map the nodes in the multi-task data flow graph DFGs to the tiles in the target CGRA architecture. After all nodes are successfully mapped, the CGRA configuration that drives the multi-task fusion execution is generated by analyzing the MRRG function.
[0011] Furthermore, step 1 specifically includes:
[0012] ResMII is determined based on the total number of nodes in the multi-task data flow graph DFGs and the number of CGRAtiles in the multi-task data flow graph DFGs. Recursive analysis is performed on a single DFG to obtain RecMII, where ResMII is the minimum startup interval for resource constraints and RecMII is the minimum startup interval for dependency constraints. ResMII and ResMII are compared, and the maximum value is taken as the initial startup interval II.
[0013] Furthermore, step 2 specifically includes:
[0014] Extract the node schedule for each clock cycle under start interval II and store it in the two-dimensional array schedNodeCnts`. Calculate all cyclic shifts of the corresponding node schedule under start interval II and store them in the `circShiftVal` array. Generate all scheduling patterns for each task in the data flow graph through mathematical rotation operations.
[0015] Furthermore, step 3 specifically includes:
[0016] Step 3.1: Calculate the utilization of all tiles within the module cycle when the scheduling of each task is combined and use them as scheduling candidates;
[0017] Step 3.2: Traverse all scheduling modes and tasks. For scheduling mode i and task j in the data flow graph, perform a cyclic shift on the node scheduling of task j according to the cyclic shift value of scheduling mode i.
[0018] Step 3.3: Calculate the total number of nodes after cyclic shift of all tasks in scheduling mode i, calculate the difference between adjacent nodes, and calculate the average difference value based on the difference in the number of adjacent nodes;
[0019] Step 3.4: Output the candidate schedule with the smallest average difference value as the optimal schedule.
[0020] Furthermore, step 4 specifically includes:
[0021] Construct a modular routing resource graph based on the current startup interval II and the target CGRA architecture parameters, evaluate the layout cost of each tile in the target CGRA architecture through each DFG node, traverse each tile in the target CGRA architecture, calculate the cost of mapping the node to each tile, and select the tile with the minimum cost for layout. Repeat steps 2-3 to obtain the optimal schedule under the current startup interval II, and perform routing based on the optimal schedule. If routing is unsuccessful, the current startup interval II mapping fails, and the current startup interval II is incremented. Repeat steps 2-3 to obtain the optimal schedule under the incremented startup interval II, and restart mapping until all nodes are successfully mapped. Generate the CGRA configuration that drives multi-task fusion execution by analyzing the MRRG function.
[0022] The beneficial effects of the present invention are:
[0023] 1. Compared with the traditional CGRA resource allocation technology, this invention introduces additional scheduling optimization, increases the mapping time, effectively reduces the startup interval, minimizes tile resource conflicts in the time dimension, and ensures the balanced distribution of nodes by calculating the average difference value between adjacent nodes.
[0024] 2. The present invention interweaves derivative calculations with overlapping filter windows, effectively utilizing idle tiles during memory miss stalls, and flexibly partitioning CGRA resources in the time dimension to ensure high tile utilization while avoiding pipeline bubbles and guaranteeing the throughput advantage of the fused execution mode. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1A schematic diagram of a flow chart of a CGRA mapping method for multi-task fusion execution provided by the present invention;
[0026] Figure 2 Schematic diagram comparing the mapping quality and mapping time of the present invention and the traditional CGRA mapper;
[0027] Figure 3 This is a flow chart of the present invention's integrated execution of two 4-node tasks on a 2×2 CGRA;
[0028] Figure 4 A code flow chart of the scheduling-aware heuristic mapping algorithm for multi-task fusion mapping provided by the present invention;
[0029] Figure 5 This is a code flow chart of the optimal scheduling algorithm between data flow graphs for multi-task fusion mapping provided by the present invention. DETAILED DESCRIPTION
[0030] Specific implementation method 1: Figure 1 As shown, the process of a CGRA mapping method for multi-task fusion execution described in this embodiment includes:
[0031] S1: Obtain multi-task data flow graphs DFGs and target CGRA architecture parameters, and obtain the initial startup interval II based on the multi-task data flow graphs DFGs and target CGRA architecture parameters;
[0032] In this embodiment, the pseudo codes of S1 and S4 are as follows: Figure 4 As shown, first, this embodiment processes the multi-task data flow graphs DFGs and the target CGRA architecture parameters to generate the configuration required for CGRA multi-task execution through the mapper. The mapper first calculates the key scheduling constraints: it first determines ResMII based on the total number of nodes in the DFGs and the number of available CGRA tiles (line 1), and then calculates RecMII through recursive analysis of a single DFG (line 2). The initial launch interval II is selected as the maximum of these two values, laying the foundation for subsequent scheduling exploration (line 3). This initialization phase ensures that the algorithm starts from the theoretically achievable lower bound while respecting hardware limitations and computational dependencies.
[0033] S2: Generate all scheduling modes of each task in the data flow graph through mathematical rotation operations according to the current initial start interval II;
[0034] In this embodiment, the pseudo codes of S2 and S3 are as follows: Figure 5As shown, this implementation utilizes loop permutation to balance the computational load across clock cycles of each modular loop. By analyzing the dependencies of multiple input data flow graphs (DFGs), the algorithm extracts node schedules for each clock cycle under initiation interval II (schedNodeCnts, line 1) and systematically evaluates all possible loop shifts of these schedules under a given II. Through mathematical rotation operations, it generates all possible scheduling patterns for each task (shiftedShedNodeCnts, line 4).
[0035] S3: Calculate the scheduling of each task and combine it with the utilization of all tiles in the module cycle to obtain the scheduling candidate. Combined with the differential metric, all scheduling modes of each task are screened to obtain the optimal schedule.
[0036] When calculating the schedules of individual tasks together, all possible tile utilizations within the modular cycle (schedTotalNodeCnt, line 5) are considered as scheduling candidates. A new differential metric (avgDiff, line 6) quantifies the uniformity of node distribution within the modular cycle, enabling quantitative comparison between scheduling candidates (lines 7-14). Finally, the algorithm automatically selects the scheduling candidate with the minimum avgDiff as the optimal schedule (lines 15-16), ensuring optimal resource utilization over time.
[0037] S4: Combined with optimal scheduling, the nodes in the multi-task data flow graph DFGs are mapped to the tiles in the target CGRA architecture. After all nodes are successfully mapped, the CGRA configuration that drives the multi-task fusion execution is generated by analyzing the MRRG function.
[0038] Mapper calls Figure 4 The algorithm in
[15] is used to generate the optimal schedule between DFGs under the current II (line 5), and then a modular routing resource graph MRRG is constructed based on the current II and CGRA architecture parameters (line 6). Considering the spatial proximity and routing complexity, each DFG node will evaluate the layout cost of each tile in the CGRA and select the tile with the minimum cost for layout (lines 7-12). The scheduling function of the mapper strictly implements the Figure 1 The algorithm derives the optimal schedule and attempts to complete routing. If routing is unsuccessful, it indicates that the mapping failed under the current II, and the II is incremented (lines 13-14). The optimal schedule is then regenerated based on the new II (line 5), and mapping is restarted. After all nodes are successfully mapped, the CGRA configurations for the multi-task fusion execution are generated by analyzing the MRRG (line 18). Tile is the basic unit module that can independently execute computing tasks.
[0039] Example 1
[0040] In order to verify the technical effect of the present invention, this embodiment adopts the following test. The test tasks are shown in Table 1. First, a typical embedded scenario for verifying the effect of the invention is introduced. As a real-time data acquisition and analysis device, the storage recorder can synchronously record multi-channel electrical signals and physical quantity data, and is widely used in industrial testing and scientific research monitoring. The waveform calculation function equipped with this device supports users to customize multiple calculation channels for real-time signal processing and analysis. Based on the user manual of the commercial MR-6000 storage recorder, this study selected 16 basic computing tasks (see Table 1) and constructed 48 groups of multi-task verification scenarios by combining adjacent tasks of different scales: in 4×4 CGRA, two groups of adjacent tasks are combined to form 16 scenarios; in 5×5 CGRA, three groups of adjacent tasks are combined to generate 16 scenarios; in 6×6 CGRA, four groups of adjacent tasks are combined to form 16 scenarios. The number of computing nodes and interconnected edges corresponding to each scenario is detailed in Table 2.
[0041] Table 1
[0042]
[0043] Table 2
[0044]
[0045]
[0046] The comparison objects include MapperBase and FexMo-Mapper. MapperBase is the traditional CGRA mapper. FexMo-Mapper is the invention. The mapping quality and mapping time are as follows: Figure 2 shown.
[0047] Depend on Figure 2Experimental results in
[15] demonstrate that FexMo-Mapper achieves significant improvements in mapping quality, measured by initiation interval (II), while also improving mapping time due to its additional scheduling optimizations. Across all 48 cases, FexMo reduces II by an average of 29.3% compared to MapperBase, achieving near-optimal scheduling through its inter-DFG co-scheduling strategy. For example, in a 4×4 CGRA multitasking scenario, FexMo reduces II from 12 to 8 by strategically allocating memory-intensive FFT operations and XY matrix computations across different modulo clock cycles, minimizing tile resource conflicts in the temporal dimension. Similarly, in a 5×5 CGRA, II improves from 11 to 7 because FexMo interleaves derivative computations with overlapping filter windows, effectively utilizing idle tiles during memory miss stalls. FexMo flexibly partitions CGRA resources in the temporal dimension, ensuring high tile utilization while avoiding pipeline bubbles. In summary, the proposed inter-DFG optimal scheduling algorithm proves particularly effective in CGRA multitasking fusion mapping.
[0048] Figure 2 Experimental results in
[15] demonstrate that FexMo-Mapper achieves significant improvements in mapping quality, measured by initiation interval (II), while also improving mapping time due to its additional scheduling optimizations. Across all 48 cases, FexMo reduces II by an average of 29.3% compared to MapperBase, achieving near-optimal scheduling through its inter-DFG co-scheduling strategy. For example, in a 4×4 CGRA multitasking scenario, FexMo reduces II from 12 to 8 by strategically allocating memory-intensive FFT operations and XY matrix computations across different modulo clock cycles, minimizing tile resource conflicts in the temporal dimension. Similarly, in a 5×5 CGRA, II improves from 11 to 7 because FexMo interleaves derivative computations with overlapping filter windows, effectively utilizing idle tiles during memory miss stalls. FexMo flexibly partitions CGRA resources in the temporal dimension, ensuring high tile utilization while avoiding pipeline bubbles. In summary, the proposed inter-DFG optimal scheduling algorithm proves particularly effective in CGRA multitasking fusion mapping.
[0049] Example 2
[0050] like Figure 3As shown, this embodiment integrates two 4-node tasks on a 2×2 CGRA with II = 2. Unshifted scheduling results in severe node imbalance (adjacent modular clock cycles Modulo cycle 0 has 6 nodes, Modulo cycle 1 has 2 nodes, corresponding to avgDiff of 6-2=4). Using a single cyclic shift for task 2 achieves perfect load balancing (each Modulo cycle has 4 nodes, corresponding to avgDiff of 4-4=0). Figure 4 The algorithm will automatically select the optimal schedule with the smallest avgDiff and provide it to Figure 5 The algorithm ensures the most balanced resource allocation in the time dimension, thereby improving the mapping quality. Figure 4 The algorithm will strictly follow the optimal schedule. For example, nodes A / B of task 1 / 2 will be strictly scheduled on different modular clock cycles regardless of which tile they are placed on, even if they have no dependencies.
[0051] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.
Claims
1. A CGRA mapping method for multi-task fusion execution, characterized in that: include: Step 1: Obtain multi-task data flow graphs DFGs and target CGRA architecture parameters, and obtain the initial startup interval II based on the multi-task data flow graphs DFGs and target CGRA architecture parameters; Step 2: Generate all scheduling modes of each task in the data flow graph through mathematical rotation operation according to the current initial start interval II; Step 3: Calculate the utilization of all tiles within the module cycle when all the scheduling of each task is combined to obtain the scheduling candidate. Combined with the differential metric, all the scheduling modes of each task are screened to obtain the optimal schedule. Step 4: Combined with the optimal scheduling, map the nodes in the multi-task data flow graph DFGs to the tiles in the target CGRA architecture. After all nodes are successfully mapped, the CGRA configuration that drives the multi-task fusion execution is generated by analyzing the MRRG function.
2. The CGRA mapping method for multi-task fusion execution according to claim 1, characterized in that: Step 1 specifically includes: ResMII is determined based on the total number of nodes in the multi-task data flow graph DFGs and the number of CGRAtiles in the multi-task data flow graph DFGs. Recursive analysis is performed on a single DFG to obtain RecMII, where ResMII is the minimum startup interval for resource constraints and RecMII is the minimum startup interval for dependency constraints. ResMII and ResMII are compared, and the maximum value is taken as the initial startup interval II.
3. The CGRA mapping method for multi-task fusion execution according to claim 1, characterized in that: Step 2 specifically includes: Extract the node schedule for each clock cycle under start interval II and store it in the two-dimensional array schedNodeCnts`. Calculate all cyclic shifts of the corresponding node schedule under start interval II and store them in the `circShiftVal` array. Generate all scheduling patterns for each task in the data flow graph through mathematical rotation operations.
4. The CGRA mapping method for multi-task fusion execution according to claim 1, characterized in that: Step 3 specifically includes: Step 3.1: Calculate the utilization of all tiles within the module cycle when the scheduling of each task is combined and use them as scheduling candidates; Step 3.2: Traverse all scheduling modes and tasks. For scheduling mode i and task j in the data flow graph, perform a cyclic shift on the node scheduling of task j according to the cyclic shift value of scheduling mode i. Step 3.3: Calculate the total number of nodes after cyclic shift of all tasks in scheduling mode i, calculate the difference between adjacent nodes, and calculate the average difference value based on the difference in the number of adjacent nodes; Step 3.4: Output the candidate schedule with the smallest average difference value as the optimal schedule.
5. The CGRA mapping method for multi-task fusion execution according to claim 1, characterized in that: Step 4 specifically includes: Construct a modular routing resource graph based on the current startup interval II and the target CGRA architecture parameters, evaluate the layout cost of each tile in the target CGRA architecture through each DFG node, traverse each tile in the target CGRA architecture, calculate the cost of mapping the node to each tile, and select the tile with the minimum cost for layout. Repeat steps 2-3 to obtain the optimal schedule under the current startup interval II, and perform routing based on the optimal schedule. If routing is unsuccessful, the current startup interval II mapping fails, and the current startup interval II is incremented. Repeat steps 2-3 to obtain the optimal schedule under the incremented startup interval II, and restart mapping until all nodes are successfully mapped. Generate the CGRA configuration that drives multi-task fusion execution by analyzing the MRRG function.