Computing task processing method and device, medium and product

Abstract

The invention discloses a computing task processing method and device, a medium and a product, and relates to the technical field of integrated circuits. According to the scheme, an FMA unit is designed by adopting a hardware description language, and the direct scheduling capability of hardware is supported; when a plurality of calculation requests are received, storing each corresponding calculation task into a hardware queue, and respectively determining scheduling information of each calculation task; the scheduling information comprises hardware scheduling and software scheduling, that is, the scheme supports two scheduling modes of software and hardware; when the scheduling information of the calculation task is hardware scheduling, the target FMA unit is determined according to the hardware resource use condition of each FMA unit, and the calculation task is distributed to the target FMA unit, so that the target FMA unit executes the calculation task, task balancing based on FMA unit resources is realized, and the calculation efficiency and the FMA resource utilization rate are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a computing task processing method, device, medium and product. Background Art

[0002] Hardware schedulers are crucial in high-performance computing systems, responsible for efficiently managing computing resources to optimize task execution and system throughput. With the prevalence of heterogeneous computing resources, modern hardware schedulers employ pipeline architectures, priority arbitration mechanisms, and intelligent prediction algorithms to adapt to real-time, parallel, and distributed computing requirements, while also integrating hardware acceleration technologies to enhance performance.

[0003] However, current hardware scheduling solutions primarily rely on software task dispatching, performing task allocation and scheduling at the software level. Hardware serves solely as a data transmission channel, lacking direct hardware-level scheduling capabilities, limiting scheduling efficiency and responsiveness. Furthermore, existing solutions use system tasks as the scheduling unit, rather than scheduling based on the actual resource availability of Fused Multiply-Add (FMA) units. This results in an inability to fundamentally balance the power consumption and performance load of electronic devices, impacting the overall energy efficiency and performance optimization of the system.

[0004] In view of the above problems, how to solve the current problem that hardware scheduling relies on software scheduling, lacks direct hardware scheduling capabilities, and does not balance tasks based on FMA unit resources is an urgent problem that needs to be solved by technical personnel in this field. Summary of the Invention

[0005] The present invention provides a computing task processing method, device, medium and product to at least solve the problem that current hardware scheduling relies on software scheduling, lacks hardware direct scheduling capabilities, and does not balance tasks based on FMA unit resources.

[0006] The present invention provides a computing task processing method, comprising: When multiple computing requests are received, computing data corresponding to each computing request is obtained, and each computing request is combined with the corresponding computing data to generate a computing task; Storing each computing task in a hardware queue and determining scheduling information for each computing task; wherein the scheduling information includes hardware scheduling and software scheduling; When the scheduling information of the computing task is hardware scheduling, the target fused multiply-add operation unit is determined according to the hardware resource usage of each fused multiply-add operation unit; wherein the fused multiply-add operation unit is a computing unit constructed based on a hardware description language and supporting scheduling; A mapping relationship between a computing task and a target fused multiply-add operation unit is established, and the computing task is dispatched to the target fused multiply-add operation unit so that the target fused multiply-add operation unit can execute the computing task.

[0007] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned computing task processing methods when executing the computer program.

[0008] The present invention also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the above-mentioned computing task processing methods are implemented.

[0009] The present invention also provides a computer program product, comprising a computer program, which implements the steps of any of the above-mentioned computing task processing methods when executed by a processor.

[0010] The beneficial effects of the present invention are that the FMA unit is designed using a hardware description language to support hardware direct scheduling capabilities; when multiple computing requests are received, the corresponding computing tasks are stored in a hardware queue, and the scheduling information of each computing task is determined separately; the scheduling information includes hardware scheduling and software scheduling, that is, the present solution supports both hardware and software scheduling methods; when the scheduling information of the computing task is hardware scheduling, the target FMA unit is determined according to the hardware resource usage of each FMA unit, and the computing task is dispatched to the target FMA unit so that the target FMA unit can execute the computing task, thereby realizing task balancing based on FMA unit resources and improving computing efficiency and FMA resource utilization.

[0011] In addition, the present invention also provides a computing task processing device, medium and product, with the same effects as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A flowchart of a computing task processing method provided by an embodiment of the present invention; Figure 2 A diagram illustrating the architecture of a schedulable fused multiply-add unit according to an embodiment of the present invention; Figure 3 A diagram of a parallel multiplication-addition scheduling architecture provided by an embodiment of the present invention; Figure 4 A scheduling flow chart of the hardware pipeline scheduler provided in an embodiment of the present invention; Figure 5 A schematic diagram of a hardware queue structure provided by an embodiment of the present invention; Figure 6 A multiplier-accumulator scheduling timing diagram provided by an embodiment of the present invention; Figure 7 A flowchart of the hardware scheduling calculation unit provided in an embodiment of the present invention; Figure 8 A schematic diagram of a computing task processing device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0015] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0016] In order to enable those skilled in the art to better understand the solutions of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0017] The current hardware scheduling scheme mainly relies on software task dispatching, and performs task allocation and scheduling at the software level. The hardware only serves as a data transmission channel and lacks direct scheduling capabilities at the hardware level, which limits the scheduling efficiency and response speed. In addition, the existing scheme uses system tasks as the scheduling unit, rather than scheduling based on the actual resource conditions of the FMA unit, resulting in the inability to fundamentally balance the power consumption and performance load of electronic devices, affecting the overall energy efficiency and performance optimization of the system. In order to solve the above problems, the present invention provides a computing task processing method. It should be noted that the method provided by the present invention can be specifically applied to processors, system on chip (SoC) or other units with computing and storage functions, depending on the specific implementation situation.

[0018] Figure 1 Flowchart of a computing task processing method provided by an embodiment of the present invention. Figure 1 As shown, the method includes: S10: When multiple computing requests are received, computing data corresponding to each computing request is obtained, and each computing request is combined with the corresponding computing data to generate a computing task.

[0019] Figure 2 The following is a diagram of the schedulable fused multiplication-addition unit architecture provided by an embodiment of the present invention. Figure 2 As shown, when multiple computation requests are received, the data acquisition module obtains computation data corresponding to each computation request, such as floating-point computation data, from memory or other storage media, and combines each computation request with the corresponding computation data to generate a computation task. It should be noted that the specific manner in which computation requests and computation data are combined is not limited in this embodiment and depends on the specific implementation.

[0020] S11: storing each computing task in a hardware queue and determining scheduling information for each computing task; wherein the scheduling information includes hardware scheduling and software scheduling.

[0021] It should be noted that if Figure 2 As shown, the parallel scheduling module is a hardware-implemented parallel scheduler (ParallelScheduler), a technology for efficiently managing computing resources. It supports up to 16 FMAs and dynamically allocates computational data and tasks to multiple FMA computing units to maximize resource utilization and performance. The parallel scheduler implements scheduling logic using dedicated circuits (such as state machines, pipelines, and lookup tables). Compared to software scheduling, it offers higher efficiency and lower latency. It assigns tasks to idle FMAs, ensuring even load distribution across all computing units and avoiding resource waste. It also dynamically adjusts the scheduling order based on task priority to address resource contention. In this embodiment, the parallel scheduling module utilizes a pipelined scheduler to divide the scheduling process into multiple stages to improve throughput. It also employs a lookup table (LUT) to store scheduling policies and task mappings, and a hardware queue to store pending tasks, supporting efficient task enqueueing and dequeueing.

[0022] Figure 3 This is a diagram of the parallel multiplication and addition scheduling architecture provided by an embodiment of the present invention. Figure 3 As shown, the parallel scheduler provided by the present invention supports both hardware and software scheduling. Therefore, in this embodiment, each computing task is specifically stored in the hardware queue of the parallel scheduling module, and scheduling information is determined for each computing task. The scheduling information includes both hardware and software scheduling, so the specific processing method for the current computing task can be determined based on the specific content of the scheduling information. The specific process for determining the scheduling information is not limited in this embodiment and depends on the specific implementation.

[0023] S12: When the scheduling information of the computing task is hardware scheduling, determine the target fused multiply-add operation unit according to the hardware resource usage of each fused multiply-add operation unit; wherein the fused multiply-add operation unit is a computing unit constructed based on a hardware description language and supports scheduling.

[0024] Furthermore, when it is confirmed that the scheduling information of the computing task is hardware scheduling, the hardware scheduling of the computing task is performed, and the target FMA unit is determined according to the hardware resource usage of each FMA unit.

[0025] It should be noted that FMA is a hardware computational unit designed to efficiently perform combined multiplication and addition operations, namely, calculating the expression A×B+C. Its structure primarily consists of a multiplier, an adder, an intermediate result processing module, and a rounding and normalization module. Its operating principle is divided into six stages: input, multiplication, intermediate processing, addition, rounding and normalization, and output. First, it receives operands A, B, and C. The multiplier calculates the product of A×B. The intermediate result processing module aligns the product with C to preserve high precision. The adder adds the two to generate the final result. The rounding and normalization module ensures that the result conforms to floating-point standards, and finally, the result is output. By fusing operations, FMA avoids rounding errors in intermediate results, reduces the number of instructions and computational latency, and significantly improves computational accuracy, performance, and energy efficiency.

[0026] It should also be noted that the FMA unit in this embodiment is a computing unit built based on a hardware description language (HDL) and supports scheduling. This embodiment does not limit the specific hardware description language used, for example, Verilog can be used.

[0027] In addition, this embodiment does not limit the specific process of determining the target FMA unit based on the hardware resource usage of each FMA unit. In order to improve resource utilization and computing efficiency, an idle FMA unit should be selected as the target FMA.

[0028] S13: Establish a mapping relationship between the computing task and the target fused multiplication-addition operation unit, and dispatch the computing task to the target fused multiplication-addition operation unit so that the target fused multiplication-addition operation unit can execute the computing task.

[0029] Finally, a mapping relationship between the computing task and the target FMA unit is established, and the computing task is dispatched to the target FMA unit so that the target FMA unit can execute the computing task. In this embodiment, the specific process of establishing the mapping relationship is not limited and depends on the specific implementation situation.

[0030] In this embodiment, the FMA unit is designed using a hardware description language to support direct hardware scheduling capabilities; when multiple computing requests are received, the corresponding computing tasks are stored in a hardware queue, and the scheduling information of each computing task is determined separately; the scheduling information includes hardware scheduling and software scheduling, that is, this solution supports both hardware and software scheduling methods; when the scheduling information of the computing task is hardware scheduling, the target FMA unit is determined according to the hardware resource usage of each FMA unit, and the computing task is dispatched to the target FMA unit so that the target FMA unit can execute the computing task, thereby realizing task balancing based on FMA unit resources and improving computing efficiency and FMA resource utilization.

[0031] Based on the above embodiments, in some embodiments, each computing request is combined with corresponding computing data to generate a computing task, including: S101: Acquire urgency information and task number in a calculation request.

[0032] S102: Combine the urgency information, the task number, and the calculation data corresponding to the calculation request to generate a calculation task.

[0033] In order to generate a computing task, in a specific implementation, the urgency information and task number in the computing request are first obtained. It should be noted that the urgency information represents the urgency of the computing task. For example, when the data size of the urgency information is 2 bits, there are four types of urgency information, 0, 1, 2, and 3, and the urgency increases in sequence. The task number represents the order in which the computing tasks are received, and the data size is generally 6 bits. Finally, the urgency information, the task number, and the computing data corresponding to the computing request are combined to generate the computing task. Among them, the size of the computing data is generally 64 bits. In this way, the complete generation of the computing task is achieved, which is convenient for subsequent task storage and processing.

[0034] Based on the above embodiments, in some embodiments, respectively determining the scheduling information of each computing task includes: S111: Determine configuration bit information of a preset 32-bit register.

[0035] Among them, the lower 16 bits in the configuration bit information represent software scheduling, and each bit in the lower 16 bits is mapped to the corresponding fused multiplication and addition operation unit; the upper 16 bits in the configuration bit information represent hardware scheduling, and each bit in the lower 16 bits is mapped to the corresponding fused multiplication and addition operation unit.

[0036] S112: Obtain the target configuration bit indicated by the user, and determine the scheduling information of the computing task according to the target configuration bit and the configuration bit information.

[0037] In order to determine the scheduling information of each computing task, it is first necessary to determine the configuration bit information of the preset 32-bit register of the pipeline scheduler.

[0038] Table 1 Configuration bit information table As shown in Table 1, the lower 16 bits in the configuration bit information represent software scheduling, and each bit in the lower 16 bits is mapped to a corresponding FMA unit; the upper 16 bits in the configuration bit information represent hardware scheduling, and each bit in the lower 16 bits is mapped to a corresponding FMA unit.

[0039] It should be noted that, as can be seen from the above embodiment, the parallel scheduling module supports a maximum of 16 FMA units, so the number of FMA units supporting software and hardware scheduling in Table 1 is also 16, that is, each FMA unit can support both hardware scheduling and software scheduling. In order to clarify which scheduling method is to be adopted, it is necessary to obtain the target configuration bit indicated by the user, and determine the scheduling information of the computing task based on the target configuration bit and the configuration bit information. For example, if the user indicates that the target configuration bit is 8 bits, it is confirmed that software scheduling is adopted, and the FMA unit used subsequently is an 8-bit mapped FMA unit; if the user indicates that the target configuration bit is 21 bits, it is confirmed that hardware scheduling is adopted, and the FMA unit used subsequently is a 21-bit mapped FMA unit.

[0040] In this embodiment, scheduling selection is achieved through the configuration bit information of the preset 32-bit register of the pipeline scheduler, which supports software and hardware scheduling and improves the flexibility of computing task execution.

[0041] Figure 4 The scheduling flow chart of the hardware pipeline scheduler provided by the embodiment of the present invention. Figure 4 As shown, the dotted line portion is the hardware scheduling task implementation portion, and the solid line portion is the software and hardware combined scheduling implementation portion. Therefore, based on the above embodiment, in some embodiments, the target fused multiply-add operation unit is determined based on the hardware resource usage of each fused multiply-add operation unit, including: S121: Obtain the resource allocation and resource release status of each fused multiplication-addition operation unit.

[0042] S122: Determine the idle status of the corresponding fused multiplication-addition operation unit according to the allocation status and release status of each resource.

[0043] S123: Establishing a mapping priority of each fused multiply-add operation unit according to each idle situation; wherein the mapping priority of the fused multiply-add operation unit is positively correlated with the corresponding idle situation.

[0044] S124: Determine a target fused multiply-add operation unit in each fused multiply-add operation unit according to each mapping priority.

[0045] Among them, the number of target fusion multiplication and addition units is equal to the number of computing tasks.

[0046] After determining to use hardware scheduling for the computing task, it is necessary to determine the target FMA unit. Specifically, the resource allocation and resource release status of each FMA unit are obtained. It can be understood that the resource allocation status of the FMA unit refers to which tasks or resources are currently assigned to the FMA unit, and the occupancy status of these tasks or resources; while the resource release status of the FMA unit refers to which resources are released after the FMA unit completes the task, and the current available status of these resources. The two together reflect the load and resource utilization status of the FMA unit.

[0047] Furthermore, by analyzing the resource allocation and release status of the FMA unit, we can determine the current idle status of the FMA unit, that is, evaluate whether it has the ability to execute new tasks or the resource availability. This helps to perform effective task scheduling and load balancing.

[0048] Subsequently, the mapping priority of each FMA unit is established according to the idle situation. It should be noted that the mapping priority of the FMA unit is positively correlated with the corresponding idle situation, that is, the idler an FMA unit is, the higher its mapping priority is, and the more priority it has in establishing mapping with computing tasks. In other words, in the specific implementation, computing tasks are preferentially mapped to idle or nearly idle FMAs and resource allocation is refreshed, and tasks are dispatched to the FMAs after the mapping is established.

[0049] Finally, the target FMA unit is determined in each FMA unit according to each mapping priority. In this embodiment, there is no restriction on the specific number of target FMA units, but it is necessary to ensure that the number of target FMA units is equal to the number of computing tasks. For example, when there are 3 computing tasks, the number of target FMA units is also 3, and the 3 target FMA units should be the highest mapping priority among all available FMA units.

[0050] In this embodiment, by determining the idle status of the FMA unit, the mapping priority of each FMA unit is established according to each idle status, so that the idle or nearly idle target FMA unit is determined according to each mapping priority to process the computing task, thereby improving the task processing efficiency and resource utilization, and realizing the load balancing of the FMA unit.

[0051] Based on the above embodiments, in some embodiments, establishing a mapping relationship between a computing task and a target fused multiply-add operation unit includes: S131: Determine the allocation priority of each computing task according to the urgency information of each computing task.

[0052] S132: According to the mapping priority of each target fused multiplication-addition operation unit and the allocation priority of each computing task, a mapping relationship between each computing task and each target fused multiplication-addition operation unit is established in a priority order isomorphic manner.

[0053] Among them, each computing task corresponds one-to-one to each target fusion multiplication and addition operation unit.

[0054] In order to establish the mapping relationship between computing tasks and FMA, the urgency of the computing tasks must be considered in addition to the load of the FMA unit. Specifically, the allocation priority of each computing task is first determined based on the urgency information of each computing task. Subsequently, based on the mapping priority of each target FMA unit and the allocation priority of each computing task, the mapping relationship between each computing task and each target FMA unit is established in a priority order isomorphic manner.

[0055] It should be noted that the priority order is isomorphic, that is, each computing task is mapped one-to-one to each target FMA unit according to the priority order. For example, there are 3 computing tasks, the allocation priority of computing task 1 is greater than the allocation priority of computing task 2, and the allocation priority of computing task 2 is greater than the allocation priority of computing task 3; there are 3 target FMA units, the mapping priority of target FMA unit 1 is greater than the mapping priority of target FMA unit 2, and the mapping priority of target FMA unit 2 is greater than the mapping priority of target FMA unit 3. When mapping computing tasks to target FMA units, a mapping relationship between computing task 1 and target FMA unit 1 is specifically established, a mapping relationship between computing task 2 and target FMA unit 2 is established, and a mapping relationship between computing task 3 and target FMA unit 3 is established. In this way, it can be ensured that computing tasks with higher urgency are processed first by idle FMA units, greatly improving task processing efficiency.

[0056] The following is a detailed description of the specific process of determining the allocation priority of each computing task: Figure 5 Schematic diagram of the hardware queue structure provided by the embodiment of the present invention. Figure 5 As shown in the figure, the hardware queue is implemented using an enhanced First In, First Out (FIFO), which adds an extra layer of design outside the Dual Port Random Access Memory (DPRAM) inside the general FIFO. Specifically, the priority of each computing task is determined based on its urgency, including: S141: Divide each computing task into multiple task types according to the urgency information of each computing task; wherein the urgency information of each computing task in the same task type is the same.

[0057] S142: Determine whether there is a target task type with a corresponding number of computing tasks of 3 among each task type; if so, proceed to step S143; if not, proceed to step S145.

[0058] S143: Setting the allocation priority of each computing task in the target task type to be higher than the allocation priority of each computing task in other task types; wherein the allocation priority of each computing task in the target task type is the same.

[0059] S144: Determine the allocation priority of each computing task in the remaining task types according to the numerical value of the corresponding urgency information.

[0060] S145: Determine the allocation priority of each computing task in each task type according to the numerical value of the corresponding urgency information.

[0061] First, each computing task is divided into multiple task types based on the urgency information of each computing task. As can be seen from the above embodiment, the data size of the urgency information is 2 bits, and there are four types of urgency information, namely urgency 0, urgency 1, urgency 2, and urgency 3, with the urgency increasing in sequence. Based on the corresponding urgency information, the computing tasks can also be divided into four task types. It can be understood that the urgency information of each computing task in the same task type is the same. Subsequently, it is determined whether there is a target task type with a corresponding number of computing tasks of 3 in each task type, that is, whether the number of computing tasks in each task type is 3.

[0062] If it is confirmed that the number of computing tasks in the task type is 3, then the allocation priority of each computing task in the target task type is set higher than the allocation priority of each computing task in the remaining task types, regardless of the relationship between the urgency of each computing task in the target task type and the urgency of each computing task in the remaining task types. It should also be noted that the allocation priority of each computing task in the target task type is the same. For each computing task in the remaining task types, the allocation priority of each computing task in the remaining task types needs to be determined based on the numerical value of the corresponding urgency information.

[0063] For example, if the number of computing tasks with urgency level 2 reaches 3, the allocation priority of computing tasks with urgency level 2 is greater than the allocation priority of computing tasks with urgency levels 0, 1, and 3; the allocation priority of the three computing tasks with urgency level 2 is equal. The allocation priority of computing tasks with urgency levels 0, 1, and 3 depends on the numerical value of the corresponding urgency information, that is, the allocation priority of computing tasks with urgency level 3 is greater than the allocation priority of computing tasks with urgency level 1, and the allocation priority of computing tasks with urgency level 1 is greater than the allocation priority of computing tasks with urgency level 0.

[0064] If it is confirmed that the number of computing tasks in any task type is 3, the default FIFO design is followed, and the allocation priority of each computing task in each task type is determined based on the numerical value of the corresponding urgency information. For example, the allocation priority of a computing task with urgency 3 is higher than the allocation priority of a computing task with urgency 2, the allocation priority of a computing task with urgency 2 is higher than the allocation priority of a computing task with urgency 1, and the allocation priority of a computing task with urgency 1 is higher than the allocation priority of a computing task with urgency 0.

[0065] In this way, computing tasks with the same urgency reaching the threshold can be mapped and processed first, thereby improving the processing efficiency of computing tasks.

[0066] It should also be noted that when each computing task is divided into multiple task types, the number of computing tasks in multiple task types may reach 3, that is, there may be multiple target task types; or even the number of computing tasks in all task types may reach 3, that is, all task types are target task types. To cope with this situation, based on the above embodiment, in some embodiments, after confirming the existence of the target task type, the following is further included: S151: Determine whether there are multiple target task types; if not, proceed to step S143; if so, proceed to step S152.

[0067] S152: Determine the allocation priority of each computing task in all target task types according to the numerical value of the corresponding urgency information, and proceed to step S144.

[0068] Specifically, after confirming the existence of the target task type, the number of target task types is verified to determine whether there are multiple target task types. If it is confirmed that there is only one target task type, the process of the above embodiment can be followed to enter the step of setting the allocation priority of each computing task in the target task type to be higher than the allocation priority of each computing task in the remaining task types.

[0069] If it is confirmed that there are multiple target task types, the allocation priority of each computing task in all target task types is determined based on the numerical values ​​of the corresponding urgency information. The subsequent process can be processed according to the process of the above embodiment, and the step of determining the allocation priority of each computing task in the remaining task types based on the numerical values ​​of the corresponding urgency information is entered. It will be understood that when all task types are target task types, it is not necessary to enter the step of determining the allocation priority of each computing task in the remaining task types based on the numerical values ​​of the corresponding urgency information.

[0070] In this way, the accuracy and rationality of the process of determining the allocation priority of computing tasks are guaranteed.

[0071] As can be seen from the above embodiments, this solution supports software scheduling in addition to hardware scheduling. Therefore, in some embodiments, when the scheduling information of the computing task is software scheduling, it also includes: S161: Obtain a pre-built lookup table; wherein the lookup table includes a mapping relationship between task numbers in the hardware queue and dual-port random access memory addresses.

[0072] S162: Determine the corresponding target dual-port random access memory address in the lookup table according to the task number in the calculation request.

[0073] S163: Read the computing task under the target dual-port random access memory address and go to step S13.

[0074] First, get the pre-built lookup table.

[0075] Table 2 Lookup table As shown in Table 2, the lookup table contains the mapping between task numbers in the hardware queue and DPRAM addresses. Because floating-point data (calculation data) in the hardware queue is 32 bits, a typical FMA calculation requires 96 bits (three floating-point data entries) encoded in 8 bits, resulting in an address span of 12 in decimal. Software can use the task number to locate the specific address of floating-point data in the DPRAM of the hardware queue and thus pre-load the calculation tasks in the hardware queue.

[0076] Therefore, if the user selects software scheduling and the software determines that a task requires pre-processing, it first retrieves a pre-built lookup table and determines the corresponding target DPRAM address based on the task number in the compute request. The hardware queue's DPRAM interface reads the compute task from the target DPRAM and then proceeds to establish a mapping between the compute task and the target FMA unit. This enables software scheduling of FMA compute tasks, supporting the prioritization of specific compute tasks.

[0077] Figure 6 The multiplier-adder scheduling timing diagram provided by an embodiment of the present invention. Based on the above embodiment, in some embodiments, after dispatching the computing task to the target fused multiply-add unit, the following is further included: S171: Obtain the estimated multiplication-addition clock cycle of the target fused multiplication-addition operation unit for processing the computing task, and obtain the current multiplication-addition clock cycle executed by the target fused multiplication-addition operation unit in real time.

[0078] S172: Monitor the completion of the target fused multiplication-addition operation unit in processing the computing task based on the estimated multiplication-addition clock cycle and the real-time current multiplication-addition clock cycle.

[0079] like Figure 6 As shown, computation requests and computation data enter the hardware queue through the bus interface. The hardware queue then sends the task and data to the hardware scheduler / software scheduler (i.e., the parallel scheduler). After the task is dequeued and before it is scheduled, the resource map refreshes the current resource status. The scheduler obtains resource usage information from the resource map, selects the FMA hardware computation resources that can be requested, and then dispatches the task to the FMA unit.

[0080] On this basis, in order to be able to determine the completion progress of each computing task, in this embodiment, the estimated multiplication and addition clock cycle of the target FMA unit for processing the computing task can be obtained, and the current multiplication and addition clock cycle executed by the target FMA unit can be obtained in real time. Based on the estimated multiplication and addition clock cycle and the real-time current multiplication and addition clock cycle, the completion degree of the target FMA unit processing the computing task is monitored. For example, for a computing task, the estimated multiplication and addition clock cycle of the target FMA unit for processing the computing task is 32 clock cycles, and the current multiplication and addition clock cycle is 28 clock cycles. Then, the completion degree of the computing task is 28 / 30, and there are still 4 cycles of workload. During the FMA calculation process, the FMA unit notifies the resource mapping module of the current calculation completion degree through a feedback signal.

[0081] Finally, after the computation task is completed, a feedback signal is sent to the resource mapping module to update the resource status. The resource mapping module updates the resource status of each FMA in the FMA computation resource pool and feeds the latest status back to the scheduler. Through these steps, the completion level of each computation task is clearly defined. This entire process ensures efficient task scheduling and dynamic resource management, thereby realizing the system's parallel computing capabilities.

[0082] After multiple FMA computing tasks are completed, different FMA units are assigned different computing tasks and data, and thus different computing times. In order to monitor the execution status of each computing task in real time and ensure that the computing results are output in an orderly manner, based on the above embodiments, in some embodiments, before dispatching the computing task to the target fused multiply-add computing unit, after establishing the mapping relationship between the computing task and the target fused multiply-add computing unit, the following steps are further included: S181: Construct a hardware circular queue containing multiple entries.

[0083] S182: Allocate a corresponding entry to each computing task based on the hardware circular queue and the corresponding task number.

[0084] S183: Monitor the execution status of each computing task according to the status bit of each entry.

[0085] Specifically, this embodiment also provides a data reordering cache module. This module is a hardware structure used to support out-of-order execution. Its core function is to ensure that the order in which tasks are submitted is consistent with the order in which execution results are returned, while allowing computing tasks to be executed out of order during the process to improve performance.

[0086] The data reorder cache module is built on a hardware circular queue (Circular Buffer). The hardware circular queue contains multiple entries, each corresponding to a task. The status bits of the entries in the circular queue include the initialization bit, allocation bit, completion bit, and submission bit.

[0087] When a task is dispatched to an FMA unit, an entry is assigned to the task based on the task number. This entry is the entry before execution. Since the status bit of each entry changes during task execution, the execution status of each task can be monitored based on the status bit of each entry to determine whether the task has been assigned, completed, or submitted.

[0088] At the same time, based on the hardware circular queue, the corresponding calculation results after the calculation task is completed can be reordered according to the task number and status bit when it is dequeued. Specifically, after the target fused multiplication and addition unit completes the calculation task, it also includes: S184: Obtain the calculation results corresponding to each calculation task.

[0089] S185: Control the blocking movement of the read pointer according to each status bit, and control each calculation result to be output in sequence according to the task number of the corresponding calculation task.

[0090] Specifically, if the computation task is completed, the status bit of the corresponding entry will be refreshed. At this time, the hardware circular queue will be dequeued in the order of the entries before execution; if the execution is not completed, the circular queue will continue to refresh in a loop until the computation task that should be completed (that is, the previous queue status bit in the order of the entry has the submission bit valid) completes the output, and then it is submitted uniformly according to the order of the input queue. The following example illustrates: Suppose the hardware circular queue has three entries, all initially in the initialized state. Compute tasks A, B, and C are submitted sequentially, with the corresponding task numbers representing the order of the tasks. When compute task A arrives, entry 0 is assigned, and the corresponding status bit is updated from the initialized bit to the allocated bit. When compute task B arrives, entry 1 is assigned, and the corresponding status bit is updated from the initialized bit to the allocated bit. When compute task C arrives, entry 2 is assigned, and the corresponding status bit is updated from the initialized bit to the allocated bit. During the execution of the three compute tasks, if compute task A completes, the status bit of entry 0 switches from the allocated bit to the completed bit. If compute task B does not complete, entry 1 remains in the allocated bit. If compute task C completes, the status bit of entry 2 switches from the allocated bit to the completed bit. The queue then attempts to submit the results sequentially. However, because compute task B has not completed, the entire process is blocked at entry 1, and submission is not allowed even after compute tasks A and C complete. When compute task B completes, the status bit of entry 1 switches from the allocated bit to the completed bit. The hardware circular queue detects the change, updates the status bits of all entries to the committed bit, and outputs the corresponding results in the order (task numbers) of the input tasks A, B, and C. Eventually all entries return to their initial state and can receive new tasks.

[0091] In this embodiment, the status bit of the hardware circular queue is used to control the blocking movement of the read pointer, forcing the calculation results of each task to be output in sequence according to the input order of its corresponding entries in the queue, thereby ensuring the orderliness of the calculation result output.

[0092] Based on the above embodiment, in some embodiments, after controlling the output of each calculation result, the method further includes: S191: Write each calculation result back to the storage address specified by the corresponding calculation task.

[0093] Specifically, after controlling the output of each calculation result, each calculation result is written back to a specified storage address such as a register or memory to ensure the final storage of the calculation task execution result and the correct data dependency of subsequent tasks. Its role is to maintain data consistency and program correctness.

[0094] In addition, in the process of obtaining the calculation results corresponding to each computing task, result verification and error checking are required to ensure the correctness and consistency of the data. Specifically, verification methods include checksums, hash values, and redundant calculations: the checksum generates a fixed-length value through mathematical operations, which is used to compare whether the data is damaged; the hash value uses a hash function to generate a unique identifier to ensure that the data has not been tampered with; the redundant calculation calculates the same data multiple times and compares the results to confirm the correctness. If errors are found during verification, error detection codes such as parity checks and cyclic redundancy checks can be used to identify errors, or error correction codes such as erasure codes can be used to automatically correct errors within a certain range. These methods effectively ensure the reliability and consistency of data, which are crucial for fields such as high-performance computing, distributed systems, and data storage, and improve the stability of the system and the credibility of the data.

[0095] In order to make those skilled in the art better understand this solution, Figure 7 The specific process of this program is described as follows: Figure 7 The following is a flowchart of the hardware scheduling calculation unit provided in the embodiment of the present invention. Figure 7 As shown in the figure, the hardware scheduling calculation process is mainly divided into the scheduling phase and the calculation phase. The scheduling phase is mainly led by the parallel scheduler. Specifically, when a request is received, the data acquisition module obtains floating-point data from memory or other storage, combines the calculation request with the calculation data, and stores it in the hardware queue. After entering the hardware queue, the soft or hard scheduling method is selected. The scheduling strategy and resource mapping determine the computing unit for the load calculation task, and then the task is dispatched. After the FMA parallel calculation, data reordering is performed, and then data submission and data writeback are completed, completing the entire calculation process.

[0096] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0097] Figure 8 Schematic diagram of a computing task processing device provided by an embodiment of the present invention. Figure 8 As shown, the device includes: The acquisition module 10 is configured to, when receiving multiple computing requests, acquire computing data corresponding to each computing request, and combine each computing request with the corresponding computing data to generate a computing task.

[0098] The first determining module 11 is used to store each computing task in a hardware queue and determine the scheduling information of each computing task respectively; wherein the scheduling information includes hardware scheduling and software scheduling.

[0099] The second determination module 12 is used to determine the target fused multiply-add operation unit according to the hardware resource usage of each fused multiply-add operation unit when the scheduling information of the computing task is hardware scheduling; wherein the fused multiply-add operation unit is a computing unit constructed based on a hardware description language and supports scheduling.

[0100] The task dispatching module 13 is used to establish a mapping relationship between the computing task and the target fused multiplication-addition operation unit, and dispatch the computing task to the target fused multiplication-addition operation unit so that the target fused multiplication-addition operation unit can execute the computing task.

[0101] In some embodiments, the acquisition module 10 includes: The first acquisition submodule is used to obtain the urgency information and task number in the calculation request; The combining submodule is used to combine the urgency information, the task number and the computing data corresponding to the computing request to generate a computing task.

[0102] In some embodiments, the first determining module 11 includes: a configuration bit information determination module, configured to determine configuration bit information of a preset 32-bit register; wherein the lower 16 bits of the configuration bit information represent software scheduling, and each bit of the lower 16 bits is mapped to a corresponding fused multiply-add operation unit; and the upper 16 bits of the configuration bit information represent hardware scheduling, and each bit of the lower 16 bits is mapped to a corresponding fused multiply-add operation unit; The target configuration bit acquisition module is used to obtain the target configuration bit indicated by the user and determine the scheduling information of the computing task based on the target configuration bit and the configuration bit information.

[0103] In some embodiments, the second determining module 12 includes: Resource information acquisition module, used to obtain the resource allocation and resource release status of each fused multiplication and addition operation unit; An idle status determination module, configured to determine the idle status of the corresponding fused multiplication-addition operation unit according to the allocation status and release status of each resource; A mapping priority establishment module, configured to establish a mapping priority of each fused multiply-add operation unit according to each idle condition; wherein the mapping priority of the fused multiply-add operation unit is positively correlated with the corresponding idle condition; a target fused multiply-add operation unit determination module, configured to determine a target fused multiply-add operation unit in each fused multiply-add operation unit according to each mapping priority; Among them, the number of target fusion multiplication and addition units is equal to the number of computing tasks.

[0104] In some embodiments, the task dispatching module 13 includes: An allocation priority determination module, configured to determine the allocation priority of each computing task according to the urgency information of each computing task; A mapping relationship establishment module is used to establish a mapping relationship between each computing task and each target fused multiplication-addition computing unit according to the mapping priority of each target fused multiplication-addition computing unit and the allocation priority of each computing task in a priority order isomorphic manner; Among them, each computing task corresponds one-to-one to each target fusion multiplication and addition operation unit.

[0105] In some embodiments, the allocation priority determination module includes: A task type determination module is used to classify each computing task into multiple task types according to the urgency information of each computing task; wherein the urgency information of each computing task in the same task type is the same; The first judgment module is used to determine whether there is a target task type with a corresponding number of computing tasks of 3 in each task type; if so, the allocation priority of each computing task in the target task type is set to be higher than the allocation priority of each computing task in the remaining task types; wherein the allocation priority of each computing task in the target task type is the same; the allocation priority of each computing task in the remaining task types is determined according to the numerical value of the corresponding urgency information; if not, the allocation priority of each computing task in each task type is determined according to the numerical value of the corresponding urgency information.

[0106] In some embodiments, further comprising: The second judgment module is used to judge whether there are multiple target task types; if not, the step of setting the allocation priority of each computing task in the target task type to be higher than the allocation priority of each computing task in the remaining task types is entered; if so, the allocation priority of each computing task in all target task types is determined according to the numerical size of the corresponding urgency information, and the step of determining the allocation priority of each computing task in the remaining task types according to the numerical size of the corresponding urgency information is entered.

[0107] In some embodiments, further comprising: A lookup table acquisition module is used to obtain a pre-built lookup table; wherein the lookup table contains a mapping relationship between task numbers in the hardware queue and dual-port random access memory addresses; A storage address determination module is used to determine the corresponding target dual-port random access memory address in a lookup table according to the task number in the calculation request; The reading module is used to read the computing task under the target dual-port random access memory address and enter the step of establishing a mapping relationship between the computing task and the target fused multiplication and addition operation unit.

[0108] In some embodiments, further comprising: A multiplication-addition clock cycle acquisition module is used to obtain the estimated multiplication-addition clock cycle of the target fused multiplication-addition operation unit for processing the computing task, and to obtain the current multiplication-addition clock cycle executed by the target fused multiplication-addition operation unit in real time; The completion monitoring module is used to monitor the completion of the target fused multiplication-addition operation unit processing the computing task based on the estimated multiplication-addition clock cycle and the real-time current multiplication-addition clock cycle.

[0109] In some embodiments, further comprising: A hardware circular queue construction module, used to construct a hardware circular queue containing multiple entries; An entry allocation module is used to allocate a corresponding entry to each computing task based on the hardware circular queue and the corresponding task number; The execution status monitoring module is used to monitor the execution status of each computing task according to the status bit of each entry.

[0110] In some embodiments, further comprising: The calculation result acquisition module is used to obtain the calculation results corresponding to each calculation task; The calculation result output module is used to control the blocking movement of the read pointer according to each status bit, and control the output of each calculation result in sequence according to the task number of the corresponding calculation task.

[0111] In some embodiments, further comprising: The write-back module is used to write each calculation result back to the storage address specified by the corresponding calculation task.

[0112] For the description of the features in the embodiment corresponding to the computing task processing device, please refer to the relevant description of the embodiment corresponding to the computing task processing method, and no further details will be given here.

[0113] An embodiment of the present invention further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above-mentioned computing task processing method embodiments.

[0114] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any one of the above-mentioned computing task processing method embodiments when running.

[0115] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0116] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any one of the above-mentioned computing task processing method embodiments are implemented.

[0117] An embodiment of the present invention also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned computing task processing method embodiments.

[0118] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0119] The above is a detailed introduction to a computing task processing method, device, medium and product provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A computing task processing method, characterized in that: include: When receiving multiple computing requests, obtaining computing data corresponding to each computing request, and combining each computing request with the corresponding computing data to generate a computing task; Storing each of the computing tasks in a hardware queue and determining scheduling information for each of the computing tasks; wherein the scheduling information includes hardware scheduling and software scheduling; When the scheduling information of the computing task is the hardware scheduling, determining a target fused multiply-add operation unit according to the hardware resource usage of each fused multiply-add operation unit; wherein the fused multiply-add operation unit is a computing unit constructed based on a hardware description language and supporting scheduling; A mapping relationship between the computing task and the target fused multiply-add operation unit is established, and the computing task is dispatched to the target fused multiply-add operation unit so that the target fused multiply-add operation unit executes the computing task.

2. The computing task processing method according to claim 1, characterized in that: Combining each of the computing requests with the corresponding computing data to generate a computing task includes: Obtaining urgency information and a task number from the computing request; The urgency information, the task number, and the calculation data corresponding to the calculation request are combined to generate the calculation task.

3. The computing task processing method according to claim 1, wherein: Determining scheduling information for each of the computing tasks separately includes: Determine configuration bit information of a preset 32-bit register; wherein the lower 16 bits of the configuration bit information represent software scheduling, and each bit of the lower 16 bits is respectively mapped to the corresponding fused multiply-add operation unit; the upper 16 bits of the configuration bit information represent hardware scheduling, and each bit of the lower 16 bits is respectively mapped to the corresponding fused multiply-add operation unit; Acquire a target configuration bit indicated by a user, and determine scheduling information of the computing task according to the target configuration bit and the configuration bit information.

4. The computing task processing method according to claim 1, wherein: The target fused multiply-add operation unit is determined based on the hardware resource usage of each fused multiply-add operation unit, including: Obtaining resource allocation and resource release status of each of the fused multiplication-addition operation units; Determining the idle state of the corresponding fused multiplication-addition operation unit according to each of the resource allocation conditions and each of the resource release conditions; Establishing a mapping priority of each of the fused multiply-add operation units according to each of the idle conditions; wherein the mapping priority of the fused multiply-add operation unit is positively correlated with the corresponding idle condition; Determining the target fused multiply-add operation unit in each of the fused multiply-add operation units according to each of the mapping priorities; The number of the target fused multiplication-addition operation units is equal to the number of the computing tasks.

5. The computing task processing method according to claim 4, characterized in that: Establishing a mapping relationship between the computing task and the target fused multiplication-addition operation unit includes: Determining the allocation priority of each computing task according to the urgency information of each computing task; According to the mapping priority of each target fused multiply-add operation unit and the allocation priority of each computing task, establishing the mapping relationship between each computing task and each target fused multiply-add operation unit in a priority order isomorphic manner; Among them, each of the computing tasks corresponds one-to-one to each of the target fusion multiplication and addition operation units.

6. The computing task processing method according to claim 5, characterized in that: Determining the allocation priority of each computing task according to the urgency information of each computing task includes: According to the urgency information of each computing task, each computing task is divided into multiple task types; wherein the urgency information of each computing task in the same task type is the same; Determine whether there is a target task type with a number of 3 corresponding computing tasks in each of the task types; If so, setting the allocation priority of each computing task in the target task type to be higher than the allocation priority of each computing task in the remaining task types; wherein the allocation priority of each computing task in the target task type is the same; determining the allocation priority of each of the computing tasks in the remaining task types according to the numerical value corresponding to the urgency information; If not, the allocation priority of each computing task in each task type is determined according to the numerical value corresponding to the urgency information.

7. The computing task processing method according to claim 6, characterized in that: After confirming the existence of the target task type, the following steps are also included: Determine whether there are multiple target task types. If not, proceeding to the step of setting the allocation priority of each computing task in the target task type to be higher than the allocation priority of each computing task in the remaining task types; If so, the allocation priority of each computing task in all the target task types is determined according to the numerical value corresponding to the urgency information, and the step of determining the allocation priority of each computing task in the remaining task types according to the numerical value corresponding to the urgency information is entered.

8. The computing task processing method according to claim 1, wherein: When the scheduling information of the computing task is software scheduling, the method further includes: Obtaining a pre-built lookup table; wherein the lookup table includes a mapping relationship between task numbers in the hardware queue and dual-port random access memory addresses; Determine, in the lookup table, a corresponding target dual-port random access memory address according to the task number in the computing request; The computing task under the target dual-port random access memory address is read, and a step of establishing a mapping relationship between the computing task and the target fused multiplication-addition operation unit is entered.

9. The computing task processing method according to claim 1, characterized in that: After dispatching the computing task to the target fused multiply-add operation unit, the method further includes: Obtaining an estimated multiplication-addition clock cycle of the target fused multiplication-addition operation unit for processing the computing task, and obtaining in real time a current multiplication-addition clock cycle executed by the target fused multiplication-addition operation unit; The completion degree of the target fused multiply-add operation unit in processing the computing task is monitored based on the estimated multiply-add clock cycle and the current multiply-add clock cycle in real time.

10. The computing task processing method according to any one of claims 1 to 9, characterized in that: Before dispatching the computing task to the target fused multiply-add computing unit, after establishing a mapping relationship between the computing task and the target fused multiply-add computing unit, the method further includes: Build a hardware circular queue containing multiple entries; Allocating a corresponding entry to each of the computing tasks based on the hardware circular queue and the corresponding task number; The execution status of each computing task is monitored according to the status bit of each entry.

11. The computing task processing method according to claim 10, characterized in that: After the target fused multiply-add operation unit completes the computing task, the method further includes: Obtaining calculation results corresponding to each of the calculation tasks; The blocking movement of the read pointer is controlled according to each of the status bits, and the calculation results are controlled to be output in sequence according to the task numbers corresponding to the calculation tasks.

12. The computing task processing method according to claim 11, characterized in that: After controlling the output of each of the calculation results, the method further includes: Each of the calculation results is written back to the storage address specified by the corresponding calculation task.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the computing task processing method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the computing task processing method according to any one of claims 1 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the computing task processing method according to any one of claims 1 to 12 are implemented.

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