An FPGA signal observation method, system, device, equipment and storage medium

Abstract

The application relates to the field of FPGA debugging technology and discloses an FPGA signal observation method, system, device, equipment and storage medium, wherein the method comprises the following steps: setting a unique identifier for a to-be-observed FPGA function module where a target observation signal is located, and setting the same identifier in an FPGA top-level module; constructing a signal transmission link between the function module and the top-level module based on the identifier, so that the target observation signal is transmitted to the top-level module; and transmitting the signal to a debugging interface through the top-level module to complete online observation. The method solves the problems that the signals need to be repeatedly and manually connected and the observation target cannot be dynamically switched in the prior art through identifier matching and link construction, and the debugging efficiency is significantly improved.

Description

Technical Field

[0001] This application relates to the field of FPGA debugging technology, specifically to an FPGA signal observation method, system, device, equipment, and storage medium. Background Technology

[0002] In the field of FPGA debugging, existing observation methods require manually exporting the target signal from the functional module to the debugging interface after synthesis, and specifying the clock domain for each signal. This process has significant drawbacks. First, users must wait for the time-consuming synthesis process to finish before they can operate, which can lead to debugging interruptions due to the long synthesis time of large projects. Second, when the same functional module is instantiated multiple times, signals must be manually connected repeatedly for each instance, making it impossible to dynamically switch observation targets. Finally, if the code level of the functional module changes, it is necessary to resynthesize and rebuild the signal connection links, greatly increasing the debugging complexity.

[0003] Therefore, there is an urgent need for an FPGA signal observation method that can avoid synthesis waiting time, support dynamic switching of observation targets, and adapt to changes in code level, so as to solve the problems of low debugging efficiency and poor flexibility of existing technologies. Summary of the Invention

[0004] In view of this, this application provides an FPGA signal observation method, system, device, equipment, and storage medium to solve the problems of low debugging efficiency and poor flexibility in the prior art.

[0005] In a first aspect, this application provides an FPGA signal observation method, the method comprising:

[0006] Set a unique identifier for the FPGA functional module where the target observation signal is located, and set the same unique identifier in the top-level module of the FPGA;

[0007] Based on a unique identifier, a signal transmission link is constructed between the FPGA functional module to be observed and the FPGA top-level module; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module;

[0008] The target measurement signal is transmitted to the debugging interface through the FPGA top-level module for signal observation.

[0009] The FPGA signal observation method provided in this application achieves automatic matching of target signal groups by setting the same unique identifier for the FPGA functional module to be observed and the FPGA top-level module, eliminating the need for manual signal mapping operations. By constructing a signal transmission link based on the unique identifier, the link is predefined before synthesis, avoiding the need to manually extract signals after synthesis. By having the FPGA top-level module uniformly transmit signals to the debugging interface, it supports switching observation targets by only modifying the identifier in multiple instances of the same functional module. This directly solves the problems of cumbersome manual operation, long synthesis waiting time, and inflexible switching of observation targets in existing FPGA debugging, significantly improving debugging efficiency and adaptability.

[0010] In one alternative implementation, the unique identifier includes a bit width parameter of the target observation signal and an identifier name parameter.

[0011] The FPGA signal observation method provided in this application explicitly defines the physical width of the signal through the bit width parameter, avoiding observation errors caused by signal truncation or bit width mismatch; and provides a globally unique name through the identifier name parameter, ensuring that the synthesis tool accurately identifies the target signal group and preventing mismatch.

[0012] In one alternative implementation, a signal transmission link is constructed between the FPGA functional module to be observed and the FPGA top-level module, including:

[0013] Parse the hash index value of the unique identifier; generate the signal transmission link between the observed FPGA functional module and the FPGA top-level module based on the mapping relationship indicated by the hash index value.

[0014] The FPGA signal observation method provided in this application converts identifiers into efficient hash values ​​through hash index parsing, thereby accelerating the matching and generation speed of signal links; the mapping relationship generation directly locates the physical path through hash values, reducing the complexity and resource overhead of link construction.

[0015] In one alternative implementation, constructing a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module further includes:

[0016] Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debug interface to achieve timing synchronization.

[0017] The FPGA signal observation method provided in this application drives clock synchronization to eliminate timing risks across clock domains (such as metastability) and ensures the accuracy of signal capture; multiplexing clock sources avoids the design of additional synchronization circuits and simplifies the debugging interface configuration process.

[0018] In one alternative implementation, the target measurement signal is transmitted to the debugging interface via the FPGA top-level module, including:

[0019] The unique identifier is identified using FPGA synthesis tools, and the physical connection from the target observation signal to the debug interface is completed during the placement and routing stage.

[0020] The FPGA signal observation method provided in this application directly calls the built-in functions of the manufacturer's tools to ensure the reliability of the link connection; no manual intervention is required for physical implementation.

[0021] In one alternative implementation, the method further includes:

[0022] When the FPGA function module to be observed is called multiple times, the value of the unique identifier is modified to switch the observation signal.

[0023] The FPGA signal observation method provided in this application only requires modifying the identifier value and does not require rebuilding the signal transmission link; it can instantly switch between different instances of the same module, improving debugging flexibility.

[0024] In summary, the FPGA signal observation method provided in this application achieves accurate identification and misalignment prevention of target signal groups by setting unique identifiers with bit width and names for functional modules and top-level modules; furthermore, it constructs transmission links based on identifier hash indexes, significantly improving link generation efficiency and reducing resource consumption; simultaneously, it synchronizes and drives the clock for the top-level module, eliminating timing risks; and then, it automatically completes physical connections during the placement and routing stage using FPGA synthesis tools, seamlessly integrating with standard development processes; finally, it supports dynamically switching observation targets by modifying identifier values. Each technical feature is progressively enhanced: the identifier, as the core link, drives link construction, clock synchronization, and tool automation to achieve a dynamic debugging closed loop, solving the problems of cumbersome manual operations, long waiting times, and inflexible switching between multiple instances in traditional FPGA debugging, achieving highly efficient and automated observation throughout the entire process.

[0025] Secondly, this application provides an FPGA signal observation system, which includes an FPGA functional module to be observed and an FPGA top-level module;

[0026] The FPGA functional module to be observed has a signal marking module with a unique identifier; the input of the signal marking module is connected to the target observation signal in the FPGA functional module to be observed.

[0027] The FPGA top-level module has a signal output module with the same unique identifier; the output of the signal output module is connected to the debug interface.

[0028] A signal transmission link is provided between the signal marking module and the signal output module; the signal transmission link is constructed based on a unique identifier;

[0029] The signal output module is used to receive target observation signals through a signal transmission link and transmit them to the debugging interface.

[0030] Thirdly, this application provides an FPGA signal observation device, which includes:

[0031] The marking module is used to set a unique identifier for the FPGA functional module where the target observation signal is located, and to set the same unique identifier in the top-level module of the FPGA.

[0032] The building module is used to construct a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module based on a unique identifier; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module.

[0033] The output module is used to transmit the target measurement signal to the debugging interface through the FPGA top-level module for signal observation.

[0034] In one alternative implementation, the building module is specifically used for:

[0035] Parse the hash index value of the unique identifier; generate the signal transmission link between the observed FPGA functional module and the FPGA top-level module based on the mapping relationship indicated by the hash index value.

[0036] In one alternative implementation, the building module is further configured to:

[0037] Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debug interface to achieve timing synchronization.

[0038] In one alternative implementation, the output module is specifically used for:

[0039] The unique identifier is identified using FPGA synthesis tools, and the physical connection from the target observation signal to the debug interface is completed during the placement and routing stage.

[0040] In one alternative embodiment, the device further includes:

[0041] The modification module is used to change the value of the unique identifier to switch the observation signal when the FPGA function module to be observed is called multiple times.

[0042] Fourthly, this application provides a computer device, including: a memory and a processor, which are communicatively connected to each other. The memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA signal observation method of the first aspect or any corresponding embodiment described above.

[0043] Fifthly, this application provides a computer-readable storage medium storing computer instructions for causing a computer to execute the FPGA signal observation method of the first aspect or any corresponding embodiment described above.

[0044] In a sixth aspect, this application provides a computer program product, including computer instructions for causing a computer to execute the FPGA signal observation method of the first aspect or any corresponding embodiment described above. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a flowchart illustrating an FPGA signal observation method according to an embodiment of this application;

[0047] Figure 2 This is a structural block diagram of an FPGA signal observation device according to an embodiment of this application;

[0048] Figure 3 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of this application. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] In FPGA debugging, observing internal signals requires manual operation after synthesis. Users must first add anti-optimization flags to the signals to be observed in the code. After the synthesis tool completes the time-consuming circuit conversion, the signals are manually brought out to the debugging interface (such as a logic analyzer), and their clock domains are specified one by one. This method has serious drawbacks. First, large-scale engineering synthesis can take hours or even days, and users must wait for synthesis to finish before they can operate, causing the debugging process to be interrupted (e.g., engineers need to start over the next day). Second, when the same functional module is called multiple times (e.g., module A is instantiated 3 times), signals must be manually connected repeatedly for each instance, making it impossible to switch observation targets in real time. Third, if code structure adjustments cause changes in module hierarchy, resynthesis and reconstruction of signal links are required, greatly increasing debugging complexity.

[0051] Therefore, there is an urgent need for an FPGA signal observation method that can eliminate synthesis latency, support dynamic switching of multiple instance targets, and adapt to changes in code hierarchy, in order to solve the problems of low debugging efficiency and insufficient flexibility of existing technologies.

[0052] This application provides an FPGA signal observation method. Figure 1 This is a flowchart of an FPGA signal observation method according to an embodiment of this application, such as... Figure 1 As shown, the process includes the following steps:

[0053] S101. Set a unique identifier for the FPGA functional module where the target observation signal is located, and set the same unique identifier in the top-level module of the FPGA.

[0054] Specifically, in step S101, the target observation signal is essentially a key logic signal that needs to be monitored in real time within the FPGA functional module. The signal types of the target observation signal include, but are not limited to, register values, state machine flags, and data buses; the signal has a defined bit width, clock domain affiliation, and physical location (logical coordinates within the FPGA chip).

[0055] An observed FPGA functional module is an independent logic unit in an FPGA design that implements a specific function. It is instantiated as a sub-module by the top-level module and can contain combinational logic, sequential logic, or IP core integration.

[0056] The unique identifier is a globally unique signal group matching label. It can be a custom string, but must be unique throughout the entire design. Its main function is to mark the target signal group in the functional module and declare the receiving target in the top-level module through the same identifier. This replaces the traditional manual signal mapping and realizes automated matching.

[0057] The FPGA top-level module is the highest-level container in FPGA design. It is used to instantiate all sub-modules (including the functional modules to be observed); it is also used to manage the signal interconnections between sub-modules; and it serves as the endpoint of the signal transmission link and the starting point of the debug interface.

[0058] S102. Based on the unique identifier, construct the signal transmission link between the FPGA functional module to be observed and the FPGA top-level module.

[0059] Specifically, in step S102, the signal transmission link is a logical channel automatically constructed based on a unique identifier. This link is used to transmit the target observation signal to the top-level module of the FPGA. During the synthesis phase, it is converted into internal routing resources within the FPGA.

[0060] S103. The target measurement signal is transmitted to the debugging interface through the FPGA top-level module for signal observation.

[0061] Specifically, in step S103, the debugging interface is the terminal for signal observation, used to capture signal waveforms in real time, trigger specific events, and store and analyze data.

[0062] Optionally, the unique identifier includes the bit width parameter and the identifier name parameter of the target observed signal. The bit width parameter explicitly defines the physical width of the signal, avoiding observation errors caused by signal truncation or bit width mismatch; the identifier name parameter provides a globally unique name, ensuring that the synthesis tools accurately identify the target signal group and preventing mismatches.

[0063] Optionally, a signal transmission link is constructed between the observed FPGA functional module and the FPGA top-level module, including: parsing the hash index value of the unique identifier; and generating the signal transmission link between the observed FPGA functional module and the FPGA top-level module based on the mapping relationship indicated by the hash index value. Hash index parsing converts the identifier into an efficient hash value, accelerating the matching and generation speed of the signal link; mapping relationship generation directly locates the physical path through the hash value, reducing the complexity and resource overhead of link construction.

[0064] Optionally, constructing a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module also includes: setting the same driving clock signal for the FPGA top-level module as the target observed signal, and using the driving clock signal for signal sampling through the debug interface to achieve timing synchronization. Driving clock synchronization eliminates timing risks across clock domains (such as metastability) and ensures the accuracy of signal acquisition; reusing clock sources avoids the design of additional synchronization circuits and simplifies the debug interface configuration process.

[0065] Optionally, the target observation signal can be transmitted to the debug interface via the FPGA top-level module. This includes identifying a unique identifier using FPGA synthesis tools and completing the physical connection between the target observation signal and the debug interface during the placement and routing phase. This directly invokes the built-in functions of the vendor's tools, ensuring the reliability of the link connection; no manual intervention is required in the physical implementation. The FPGA synthesis tool must be selected based on the specific FPGA model and design requirements, such as Vivado, Synplify / Compiler, etc.

[0066] Optionally, the method further includes: when the FPGA functional module to be observed is called multiple times, modifying the value of the unique identifier to switch the observed signal. Only the identifier value needs to be modified, without rebuilding the signal transmission link; different instances of the same module can be switched instantly, improving debugging flexibility.

[0067] In summary, the FPGA signal observation method provided in this application achieves accurate identification and misalignment prevention of target signal groups by setting unique identifiers with bit width and names for functional modules and top-level modules; further, it constructs transmission links based on identifier hash indexes, significantly improving link generation efficiency and reducing resource consumption; simultaneously, it synchronizes and drives the clock for the top-level module, eliminating timing risks; then, it automatically completes physical connections during the placement and routing stage using FPGA synthesis tools, seamlessly integrating standard development processes; and finally, it supports dynamically switching observation targets by modifying identifier values. Each technical feature is progressively enhanced: the identifier, as the core link, drives link construction, clock synchronization, and tool automation to achieve a dynamic debugging closed loop, solving the problems of cumbersome manual operation, long waiting times, and inflexible switching between multiple instances in traditional FPGA debugging, achieving highly efficient and automated observation throughout the entire process.

[0068] Based on the FPGA signal observation method provided in the above embodiments, this application also provides an FPGA signal observation system, which includes:

[0069] The FPGA functional modules and the top-level FPGA module to be observed;

[0070] The FPGA functional module to be observed has a signal marking module with a unique identifier; the input of the signal marking module is connected to the target observation signal in the FPGA functional module to be observed.

[0071] The FPGA top-level module has a signal output module with the same unique identifier; the output of the signal output module is connected to the debug interface.

[0072] A signal transmission link is provided between the signal marking module and the signal output module; the signal transmission link is constructed based on a unique identifier;

[0073] The signal output module is used to receive target observation signals through a signal transmission link and transmit them to the debugging interface.

[0074] In the above FPGA signal observation system, the construction method of the signal tagging module can be exemplarily referred to in the following code:

[0075] PROBE_IN#(

[0076] parameter integer width = 1,

[0077] parameter tag="" ) (

[0080] input[width-1:0]probe_in );

[0082] This code indicates that the signals to be observed within the FPGA functional module to be observed are directed to the PROBE_IN module, which is the signal marking module.

[0083] Where width is the total bit width of the target observation signal to be referenced, tag is the signal group name of these referenced signals, which is a unique identifier; probe_in is the target observation signal to be referenced.

[0084] The signal output module can be constructed by referring to the following code as an example:

[0085] PROBE_OUT#(

[0086] parameter integer width = 1,

[0087] parameter tag="" ) (

[0090] Input clk_in,

[0091] output[width-1:0]probe_out );

[0093] This code indicates that the target observation signal will be output to the corresponding debugging interface.

[0094] Here, width is the total width of the signals to be connected to probe_in, tag is the unique identifier tag of the probe_in to be connected (based on this unique identifier tag, it can be determined which probe_in to connect to), clk_in is connected to the clock of the clock domain where the referenced signal is located, and probe_out is connected to the signal referenced by probe_in.

[0095] This FPGA signal observation system eliminates the need to wait until synthesis is complete before extracting the signals to be observed. During the code writing phase, a dedicated module can be called to extract the signals to be observed. After the signals are extracted, the project can be run (synthesis, placement and routing, etc.). The software can determine which probe_in signal to extract for observation based on the unique identifier.

[0096] When the module containing the signal to be observed is called multiple times (let's say named module_name_a, module_name_b, module_name_c), and you only need to observe the signal in one of the modules (e.g., module_name_a), you only need to fill the probe_out tag with the probe_in tag from module_name_a, and you only need to connect clk_in to the clock of the clock domain where the signal is located, without having to specify the clock domain for each signal individually; if you want to observe module_name_b later, you only need to fill the tag with the probe_in tag name from module_name_b.

[0097] When the module containing the signal to be observed undergoes a hierarchical change in the overall code structure, it is not necessary to wait until synthesis is completed and then re-import the signal; the project (synthesis, placement and routing, etc.) can be run directly.

[0098] This embodiment also provides an FPGA signal observation device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0099] This embodiment provides an FPGA signal observation device, such as... Figure 2 As shown, it includes:

[0100] The marking module 201 is used to set a unique identifier for the FPGA functional module to be observed where the target observation signal is located, and to set the same unique identifier in the top-level module of the FPGA.

[0101] Module 202 is used to construct a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module based on a unique identifier; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module.

[0102] Output module 203 is used to transmit the target measurement signal to the debugging interface through the FPGA top-level module for signal observation.

[0103] In one alternative implementation, the construction module 202 is specifically used for:

[0104] Parse the hash index value of the unique identifier; generate the signal transmission link between the observed FPGA functional module and the FPGA top-level module based on the mapping relationship indicated by the hash index value.

[0105] In an alternative implementation, the construction module 202 is further configured to:

[0106] Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debug interface to achieve timing synchronization.

[0107] In one alternative implementation, the output module 203 is specifically used for:

[0108] The unique identifier is identified using FPGA synthesis tools, and the physical connection from the target observation signal to the debug interface is completed during the placement and routing stage.

[0109] In one alternative embodiment, the device further includes:

[0110] Modify module 204 to switch the observation signal by modifying the value of the unique identifier when the FPGA function module to be observed is called multiple times.

[0111] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0112] In this embodiment, the FPGA signal observation device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0113] This application also provides a computer device having the above-described features. Figure 2 The FPGA signal observation device shown.

[0114] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 3 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 3 Take a processor 10 as an example.

[0115] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0116] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0117] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0118] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0119] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0120] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0121] A portion of this application can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to this application through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0122] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. An FPGA signal observation method, characterized in that, The method includes: A unique identifier is set for the FPGA functional module where the target observation signal is located, and the same unique identifier is set in the top-level module of the FPGA; the unique identifier includes the bit width parameter and the identifier name parameter of the target observation signal; Based on the unique identifier, a signal transmission link is constructed between the FPGA functional module to be observed and the FPGA top-level module; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module. The target measurement signal is transmitted to the debugging interface through the FPGA top-level module for signal observation; The step of setting a unique identifier for the FPGA functional module to be observed where the target observation signal is located includes: calling a dedicated module during the code writing stage to extract the target observation signal; The transmission of target measurement signals to the debugging interface via the FPGA top-level module includes: The unique identifier is identified using FPGA synthesis tools, and the physical connection from the target observation signal to the debug interface is completed during the placement and routing stage.

2. The method according to claim 1, characterized in that, The construction of the signal transmission link between the FPGA functional module to be observed and the FPGA top-level module includes: Parse the hash index value of the unique identifier; The signal transmission link between the observed FPGA functional module and the FPGA top-level module is generated based on the mapping relationship indicated by the hash index value.

3. The method according to claim 2, characterized in that, The construction of the signal transmission link between the FPGA functional module to be observed and the FPGA top-level module also includes: Set the same driving clock signal as the target observation signal for the FPGA top-level module, and use the driving clock signal to sample the signal through the debugging interface to synchronize the timing.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: When the FPGA function module to be observed is called multiple times, the value of the unique identifier is modified to switch the observation signal.

5. An FPGA signal observation system, characterized in that, The system includes the FPGA functional module to be observed and the FPGA top-level module; wherein, In the FPGA functional module to be observed, there is a signal marking module with a unique identifier for the target observation signal; the signal marking module calls a dedicated module during the code writing stage to extract the target observation signal; the input terminal of the signal marking module is connected to the target observation signal in the FPGA functional module to be observed; the unique identifier includes the bit width parameter and the identifier name parameter of the target observation signal; The FPGA top-level module is equipped with a signal output module that has the same unique identifier; the output terminal of the signal output module is connected to the debug interface. A signal transmission link is provided between the signal marking module and the signal output module; the signal transmission link is constructed based on the unique identifier; the signal transmission link identifies the unique identifier through FPGA synthesis tools and completes the physical connection from the target observation signal to the debug interface during the placement and routing stage; The signal output module is used to receive target observation signals through a signal transmission link and transmit them to the debugging interface.

6. An FPGA signal observation device, characterized in that, The device includes: The marking module is used to set a unique identifier for the FPGA functional module to be observed where the target observation signal is located, and to set the same unique identifier in the top-level module of the FPGA; the unique identifier includes the bit width parameter and the identifier name parameter of the target observation signal; A construction module is used to construct a signal transmission link between the FPGA functional module to be observed and the FPGA top-level module based on the unique identifier; the signal transmission link is used to transmit the target observation signal to the FPGA top-level module; The output module is used to transmit the target measurement signal to the debugging interface through the FPGA top-level module for signal observation. The marking module is used to: call a dedicated module during the code writing phase to extract the target observation signal; The output module is used for: The unique identifier is identified using FPGA synthesis tools, and the physical connection from the target observation signal to the debug interface is completed during the placement and routing stage.

7. A computer device, characterized in that, include: A memory and a processor are interconnected, the memory storing computer instructions, and the processor executing the computer instructions to perform the FPGA signal observation method according to any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the FPGA signal observation method according to any one of claims 1 to 4.

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