A method and system for rapid configuration of XDMA IP for PCIe modules in FPGA chips based on network ports

Abstract

This invention discloses a method and system for rapid configuration of the PCIe module XDMA IP in an FPGA chip based on a network interface. Using this method, a host computer can configure and monitor the status of the FPGA's internal DMA register space by using a selected network protocol as the transmission medium through the network interface. Users can not only meet the need for multiple consecutive configurations in a short period of time, but also perform remote debugging and maintenance when direct operation of the device is inconvenient, significantly improving system development efficiency and application flexibility.

Description

Technical Field

[0001] This invention relates to the field of communication and network configuration technology, and in particular to a method and system for rapid configuration of PCIe module XDMA IP in an FPGA chip based on network interface. Background Technology

[0002] PCIe is a high-performance, high-speed serial computer expansion bus standard used to connect high-performance devices in computer systems. With its advantages of high bandwidth and low latency, it has been widely used in various application scenarios. Especially in embedded systems and programmable logic devices such as FPGAs, the PCIe interface is often used to achieve efficient high-speed data transmission and system expansion.

[0003] Xilinx's XDMA IP is a high-performance, configurable SG-mode DMA for PCIe 2.0 and PCIe 3.0, suitable for asynchronous large-volume data transfers and low-latency data streaming. The XDMA IP provides a user-selectable AXI-LiteSlave interface for transmitting configuration and control commands via the bus. This interface conforms to the AXI-Lite protocol specification and can be used to configure the DMA register space within the XDMA IP core.

[0004] Existing FPGA chips integrate Ethernet and PCIe interfaces to enable efficient data transmission and system expansion. However, in practical applications, rapid configuration of the DMA register space of the XDMA IP core in the PCIe module still faces the following challenges: First, traditional configuration methods rely on physical contact or specialized tools, which are often difficult to implement in situations requiring remote management (e.g., remote device deployment). Second, configuration efficiency is low; in certain application scenarios, especially those requiring multiple consecutive configurations of the DMA register space within a short period, existing configuration methods may not meet real-time requirements. Furthermore, when the FPGA board is deployed on a remote device or cannot be physically accessed (e.g., the device is mounted at a high location or in a hazardous area), developers often find it difficult to complete DMA configuration or troubleshooting.

[0005] Therefore, how to achieve fast and efficient configuration of the DMA register space in the PCIe module through network transmission has become an urgent technical problem to be solved. Summary of the Invention

[0006] In view of this, one objective of the present invention is to provide a fast configuration method for XDMAIP of PCIe modules in FPGA chips based on Ethernet ports, which enables fast and efficient configuration of the DMA register space in the PCIe module. A second objective of the present invention is to provide a fast configuration system for XDMAIP of PCIe modules in FPGA chips based on Ethernet ports.

[0007] One of the objectives of this invention is achieved through the following technical solution:

[0008] A method for rapid configuration of PCIe module XDMA IP in an FPGA chip based on network interface is characterized in that: the method includes downlink operation and uplink operation. The downlink operation is to package the configuration content of the register into a UDP protocol data packet by the host computer and transmit it to the FPGA chip through the network. After receiving the data, the internal logic of the FPGA decodes the data, extracts the corresponding configuration content, and thus completes the read and write operation of the DMA register area.

[0009] The uplink operation is that when the host computer needs to obtain the FPGA's operating status, it initiates a read request to the status register, and the FPGA transmits the response data in the register back to the host computer via the network.

[0010] Furthermore, the specific steps include:

[0011] Step S1: Use the host computer to generate a sequence of instructions containing register configuration content. The configuration content includes the target address, operation type and configuration data. Encapsulate the instruction sequence into a UDP protocol data packet and add a sequence number. Send it to the FPGA's buffer through the network interface.

[0012] Step S2: After the data enters the FPGA, the received UDP protocol data packets are parsed and split into data packets;

[0013] Step S3: The FPGA's encoding and decoding module further processes the data packets to adapt to specific requirements. During downlink operations, it parses the data packets to extract configuration content in order to complete the register write operation. During uplink operations, it responds to read requests, obtains the operation results encapsulated in the register as response data packets, and uploads them to the host computer via the FPGA.

[0014] Furthermore, in step S3, during downlink operation, the target address and configuration data signals are converted into AXI-lite standard protocol signals using the interface conversion module, and the configuration information is sent to the DMA register space of the IP core.

[0015] Furthermore, the decomposition of UDP protocol packets adopts a specific format, with tags including head, addr, data, wr_en, enable, Reserved, and odd_parity in sequence; the meanings of each tag are as follows:

[0016] `head` is a fixed frame header of 0xAA, `addr` is a 16-bit DMA register space configuration address, and `data` is a 32-bit DMA register space data. `wr_en` high indicates writing to the register via the network interface, and low indicates reading from the register. `enable` valid indicates that the current read / write request is valid; otherwise, the FPGA can ignore it and not respond. `odd_parity` is the parity value of the first 63 bits of data, used to determine if the data packet has errors.

[0017] The second objective of this invention is achieved through the following technical solution:

[0018] A rapid configuration system for PCIe module XDMA IP in an FPGA chip based on network interface, the system comprising:

[0019] The host computer unit is used to encapsulate DMA register operation instructions into configuration data packets conforming to the UDP protocol;

[0020] The network transmission unit implements downlink transmission of configuration data packets and uplink return transmission of response data packets through the Ethernet physical layer;

[0021] The FPGA unit parses the configuration data packet to extract the configuration content during downlink operations in order to complete the register write operation; during uplink operations, it responds to read requests, obtains the operation result encapsulated in the register as a response data packet, and sends it back to the host computer.

[0022] Furthermore, the FPGA unit includes:

[0023] The protocol parsing module is used to parse and split received UDP protocol packets into packets;

[0024] The encoding / decoding module is used to parse the destination register address, operation type, and configuration data of data packets; during downlink operations, it outputs the configuration content to the interface conversion module; during uplink operations, it responds to read requests, obtains the status information stored in the destination register transmitted by the interface conversion module, and encodes the data into standardized UDP data packets according to a specific format.

[0025] The interface conversion module converts the target address and configuration data signals into AXI-lite standard protocol signals during downlink operations and sends the configuration information to the DMA register space of the IP core; during uplink operations, it sends the DMA register status value back to the encoding / decoding module.

[0026] Furthermore, the decomposition of the configuration data packet adopts a specific format, with tags including head, addr, data, wr_en, enable, Reserved, and odd_parity in sequence; the meanings of each tag are as follows:

[0027] `head` is a fixed frame header of 0xAA, `addr` is a 16-bit DMA register space configuration address, and `data` is a 32-bit DMA register space data. `wr_en` high indicates writing to the register via the network interface, and low indicates reading from the register. `enable` valid indicates that the current read / write request is valid; otherwise, the FPGA can ignore it and not respond. `odd_parity` is the parity value of the first 63 bits of data, used to determine if the data packet has errors.

[0028] The beneficial effects of this invention are:

[0029] This invention fully utilizes the high-performance characteristics of Ethernet interfaces and combines the advantages of UDP over TCP network protocols in terms of simplicity and efficiency. It proposes a fast configuration method for the DMA register space of the PCIe module XDMA IP core in FPGA chips that is efficient, flexible and easy to implement. With this method, users can not only meet the needs of multiple consecutive configurations in a short period of time, but also perform remote debugging and maintenance when it is inconvenient to directly operate the device, which significantly improves the system development efficiency and application flexibility.

[0030] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained from the following description and the foregoing claims. Attached Figure Description

[0031] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein:

[0032] Figure 1 This is a schematic diagram of the method flow of the present invention;

[0033] Figure 2 Schematic diagram of configuring XDAM PCIe IP cores for PCs;

[0034] Figure 3 This is a schematic diagram of the specific format of the 64-bit data packet protocol used in this invention. Detailed Implementation

[0035] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the preferred embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0036] This invention proposes a specific implementation scheme for data communication and register configuration between an XDMA module and a host computer in an FPGA based on a network interface. The core idea is to use the UDP protocol as a transmission carrier through a network interface to achieve configuration and status monitoring of the DMA register space within the FPGA. This method includes downlink and uplink operations. Downlink operations (write operations) involve the host computer packaging the register configuration content into UDP protocol data packets and transmitting them to the FPGA chip via the network. Upon receiving the data, the FPGA's internal logic decodes the data, extracts the corresponding configuration content, and thus completes the read / write operation of the DMA register area. Uplink operations (read operations) occur when the host computer initiates a read request for the status register to obtain the FPGA's operating status. The FPGA then transmits the response data from the register back to the host computer via the network. At the network layer, the UDP protocol is selected as the primary data transmission protocol. The FPGA involved in this embodiment includes a gigabit network module, an encoding / decoding module, an interface conversion module, and the XDMA module to be configured. Its design block diagram is attached. Figure 2 As shown.

[0037] like Figure 1 As shown in the flowchart, the specific implementation plan is as follows:

[0038] Step S1: Use the host computer to generate a sequence of instructions containing register configuration content. The configuration content includes the target address, operation type and configuration data. Encapsulate the instruction sequence into a UDP protocol data packet and add a sequence number. Send it to the FPGA's receive buffer through the network interface.

[0039] At the network layer, UDP is a connectionless transport protocol characterized by low latency and high efficiency, making it ideal for applications with high real-time requirements. Its data segments can contain 46 to 1500 bytes of data and can simultaneously transmit configuration information for multiple XDMA registers. Through the UDP protocol, the host computer can send control commands to the FPGA or obtain status information from the FPGA; simultaneously, the FPGA can also transmit acquired data back to the host computer via UDP. This communication method eliminates the need to maintain complex connection states, reducing protocol overhead and thus improving communication efficiency.

[0040] It should be noted that in this embodiment, the FPGA communicates with the host computer's network card via the RGMII interface. The RGMII interface not only supports data transmission rates up to 1Gbps, but also ensures the stability and reliability of signals during long-distance transmission. In this way, the FPGA can establish a direct network connection with the host computer without the need for additional protocol conversion or external devices.

[0041] Step S2: After the data enters the FPGA, the received UDP protocol data packets are parsed and split into data packets;

[0042] In this embodiment, this step is implemented using the gigabit network module of the FPGA. The main functions of the gigabit network module include the encapsulation and parsing of network data packets. After the network packet enters the FPGA, the gigabit network module splits the valid data into 64-bit data packets, or frames the 64-bit status feedback information and sends it to the host computer. To ensure the accuracy and integrity of data transmission, a specific format is used for the decomposition of UDP data packets, as shown in the attached figure. Figure 3 As shown, the labels include head, addr, data, wr_en, enable, Reserved, and odd_parity in sequence. The meanings of each label are as follows: head is the fixed frame header 0xAA, addr is the 16-bit DMA register space configuration address, and data is the 32-bit DMA register space data; a high wr_en indicates writing to the register through the network interface, while a low wr_en indicates reading from the register; an enabled wr_en indicates that the current read / write request is valid, otherwise the FPGA can ignore it and not respond; odd_parity is the parity value of the first 63 bits of data, used to determine whether the data packet has errors.

[0043] For example, in a write operation, the host computer generates a data packet containing the target configuration address and target configuration data, and sends it to the FPGA via the UDP protocol. The gigabit network module splits the configuration data of multiple registers, with each 64-bit data packet representing the configuration data for a single register in the XDMA. In a read operation, a corresponding read request is generated, which is responded to by the FPGA and returns status information. The gigabit network module is responsible for framing the received multiple 64-bit data packets according to the UDP communication protocol, and finally transmitting them to the host computer through the RGMII interface.

[0044] Step S3: The FPGA's encoding and decoding module further processes the data packets to adapt to specific requirements. During downlink operations, it parses the data packets to extract configuration content in order to complete the register write operation. During uplink operations, it responds to read requests, obtains the operation results encapsulated in the register as response data packets, and uploads them to the host computer via the FPGA.

[0045] In the downlink (write operation), the module first parses the 64-bit UDP data packet, extracting the address of the target register, the data to be written, and relevant control parameters, such as read / write type. This decoded information is then passed to the corresponding register for processing to complete the data write operation. In the uplink (read operation), when the host computer initiates a read request for a specific status register via the network, the encoding / decoding module obtains the information stored in the target address register transmitted by the interface conversion module. It then encodes this data into standardized 64-bit UDP data packets according to a predetermined format, adds port number, packet length, checksum, etc., and frames them into complete network upload data frames, which are then transmitted to the host computer for further processing.

[0046] Since the DMA register space configuration in the XDMA IP requires a standard AXI-lite interface, and the configuration data output by the codec module does not directly interface with this interface, effective signal adaptation is necessary to ensure that the configuration data can be successfully transmitted to the target AXI-lite interface. In this process, an interface conversion module converts the configuration address and configuration data signals into AXI-lite standard protocol signals and sends the configuration information to the IP core's DMA register space. In other words, the interface conversion module converts the configuration data output by the codec module into AXI-lite interface signals, or converts AXI-lite interface signals read from the XDMA IP into the data format required by the codec module.

[0047] Based on the design concept of the above method, this invention also provides a rapid configuration system for PCIe module XDMA IP in an FPGA chip based on a network interface. The system architecture includes:

[0048] (1) The host computer unit is used to encapsulate DMA register operation instructions into configuration data packets that conform to the UDP protocol;

[0049] (2) Network transmission unit, which realizes downlink transmission of configuration data packets and uplink back transmission of response data packets through the Ethernet physical layer;

[0050] (3) FPGA unit: During downlink operation, it parses the configuration data packet to extract the configuration content in order to complete the register write operation; during uplink operation, it responds to the read request, obtains the operation result encapsulated in the register as a response data packet and sends it back to the host computer.

[0051] Specifically, the FPGA unit includes:

[0052] 1) Protocol parsing module, used to parse and split received UDP protocol packets into packets;

[0053] 2) Encoding / decoding module, used to parse the destination register address, operation type and configuration data of data packets; output configuration content to the interface conversion module during downlink operation, respond to read requests during uplink operation, obtain the status information stored in the destination register transmitted by the interface conversion module, and encode the data into standardized UDP data packets according to a specific format;

[0054] 3) The interface conversion module converts the target address and configuration data signals into AXI-lite standard protocol signals during downlink operations and sends the configuration information to the DMA register space of the IP core; during uplink operations, it sends the DMA register status information back to the encoding and decoding module.

[0055] In general, the downlink data flow of this invention is (from host computer to FPGA): the host computer sends UDP data packets to the RGMII interface via network transmission, and finally transmits them to the FPGA; the uplink data flow is (from FPGA to host computer): after the FPGA finishes processing, it transmits the data back to the host computer via the same network path.

[0056] The internal processing flow of the FPGA is as follows: After the data enters the FPGA, it is first parsed by the gigabit network module. At this time, the received network data packet is processed according to the standard network protocol and the effective data is decomposed into a fixed-width data format of data[63:0]. The encoding and decoding module further processes the above data.

[0057] In the downlink (write operation) direction, the encoding and decoding module extracts the address of the read and write register, the data to be written, and related control information (such as the read and write operation type) from the 64-bit UDP data. Subsequently, the interface conversion module converts the configuration address and configuration data signals into AXI-lite standard protocol signals and sends the configuration information to the DMA register space of the IP core.

[0058] In the uplink (read operation), when the host computer initiates a read request to the status register, the encoding and decoding module encodes the read address, data and other information into a 64-bit UDP data packet, and finally completes the framing and sends it to the host computer through the FPGA's upload path.

[0059] This invention aims to overcome the limitations of traditional debugging methods by leveraging network transmission capabilities, providing users with a more flexible and convenient operating method. It utilizes the network port and the AXI-Lite Slave interface of the XDMA IP for continuous, rapid, and remote configuration of PCIe modules.

[0060] In practical applications, users can package the register configuration contents into UDP protocol data packets via a host computer and transmit them to the FPGA chip over the network. Upon receiving the data, the FPGA's internal logic decodes it, extracting the corresponding read / write address, operation type, and target data, thereby completing the read / write operation on the DMA register area. Simultaneously, when it is necessary to obtain the FPGA's operating status, the FPGA can also transmit the data in its status register back to the host computer via the network.

[0061] Furthermore, this invention provides a novel approach to remote configuration and debugging. In traditional scenarios, when FPGA boards are deployed on remote devices or cannot be physically accessed (e.g., the device is mounted at a high position or in a hazardous area), developers often find it difficult to complete DMA configuration or troubleshooting. However, with the network port transmission channel provided by this invention, users can establish a connection between the remote host's network interface and the FPGA's network port, thereby enabling rapid debugging and register operations on the PCIe module's XDMA IP core. This innovative method not only effectively solves the problem of inconvenient device maintenance but also provides real-time debugging capabilities when errors occur in PCIe data transmission, significantly improving system reliability and maintainability.

[0062] It should be recognized that embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can be implemented using standard programming techniques—including a non-transitory computer-readable storage medium configured with a computer program, wherein such a storage medium causes the computer to operate in a specific and predefined manner—according to the methods and drawings described in the specific embodiments. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if desired, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0063] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for rapid configuration of PCIe module XDMA IP in an FPGA chip based on network interface, characterized in that: The method includes downlink operations and uplink operations. The downlink operation involves the host computer packaging the configuration content of the registers into UDP protocol data packets and transmitting them to the FPGA chip via the network. After receiving the data, the internal logic of the FPGA decodes the data, extracts the corresponding configuration content, and thus completes the read and write operations of the DMA register area. The uplink operation is that when it is necessary to obtain the operating status of the FPGA chip, the host computer initiates a read request to the status register, and the FPGA chip transmits the response result data in the register back to the host computer through the network. The specific steps include: Step S1: Use the host computer to generate a sequence of instructions containing register configuration content. The configuration content includes the target address, operation type and configuration data. Encapsulate the instruction sequence into a UDP protocol data packet and add a sequence number. Send it to the receive buffer inside the FPGA chip through the network interface. Step S2: After the data enters the FPGA chip, the received UDP protocol data packets are parsed and split into data packets; Step S3: The FPGA's encoding and decoding module further processes the data packets to adapt to specific requirements. During downlink operations, it parses the data packets to extract configuration content in order to complete the register write operation. During uplink operations, it responds to read requests, obtains the operation results encapsulated in the register as response data packets, and uploads them to the host computer through the FPGA chip.

2. The method for rapid configuration of PCIe module XDMA IP in an FPGA chip based on network interface as described in claim 1, characterized in that: In step S3, during downlink operation, the target address and configuration data signals are converted into AXI-lite standard protocol signals using the interface conversion module, and the configuration information is sent to the DMA register space of the IP core.

3. The method for rapid configuration of PCIe module XDMA IP in a network-based FPGA chip according to claim 1 or 2, characterized in that: The decomposition of UDP protocol packets uses a specific format, with tags including, in order: head, addr, data, wr_en, enable, Reserved, and odd_parity; the meanings of each tag are as follows: `head` is a fixed frame header of 0xAA, `addr` is a 16-bit DMA register space configuration address, and `data` is a 32-bit DMA register space data. `wr_en` high indicates writing to the register via the network interface, and low indicates reading from the register. `enable` valid indicates that the current read / write request is valid; otherwise, the FPGA can ignore it and not respond. `odd_parity` is the parity value of the first 63 bits of data, used to determine if the data packet has errors.

4. A rapid configuration system for PCIe module XDMA IP in an FPGA chip based on network interface, characterized in that: The system includes The host computer unit is used to encapsulate DMA register operation instructions into configuration data packets conforming to the UDP protocol; The network transmission unit implements downlink transmission of configuration data packets and uplink return transmission of response data packets through the Ethernet physical layer; The FPGA unit, during downlink operations, parses configuration data packets to extract configuration content for register write operations; during uplink operations, it responds to read requests, obtains the operation results encapsulated as response data packets in the registers, and sends them back to the host computer. The FPGA unit includes: The protocol parsing module is used to parse and split received UDP protocol packets into packets; The encoding / decoding module is used to parse the destination register address, operation type, and configuration data of data packets; during downlink operations, it outputs the configuration content to the interface conversion module; during uplink operations, it responds to read requests, obtains the status information stored in the destination register transmitted by the interface conversion module, and encodes the data into standardized UDP data packets according to a specific format. The interface conversion module converts the target address and configuration data signals into AXI-lite standard protocol signals during downlink operations and sends the configuration information to the DMA register space of the IP core; during uplink operations, it sends the DMA register status information back to the encoding / decoding module.

5. The PCIe module XDMA IP fast configuration system in an FPGA chip based on a network interface as described in claim 4, characterized in that: The configuration data packet is decomposed in a specific format, with tags including head, addr, data, wr_en, enable, Reserved, and odd_parity in sequence. The meanings of each tag are as follows: head is a fixed frame header of 0xAA, addr is a 16-bit DMA reg space configuration address, and data is 32-bit DMA reg space data; a high wr_en indicates writing to the register via the network interface, while a low wr_en indicates reading from the register; an enabled wiping request indicates that the current read / write request is valid, otherwise the FPGA can ignore it and not respond; odd_parity is the parity value of the first 63 bits of data, used to determine if the data packet has errors.

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