PCB layout optimization method and device, electronic equipment, storage medium and product

Abstract

The invention discloses a PCB layout optimization method and device, electronic equipment, a storage medium and a product. The method comprises the steps of obtaining PCB design data and a current PCB layout in response to triggering of a PCB layout optimization event; inputting the PCB design data into a pre-constructed multi-modal large model, and obtaining multi-modal fusion feature information output by the multi-modal large model; inputting the multi-modal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model, and obtaining a target PCB layout scheme output by the PCB layout reinforcement learning model; and performing PCB layout adjustment on the current PCB layout based on the target PCB layout scheme. According to the scheme, multi-mode data related to PCB design can be effectively processed and understood, PCB layout design capable of meeting various performance requirements is achieved, and the quality and efficiency of PCB layout are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board design, and in particular to a PCB layout optimization method, device, electronic equipment, storage medium and product. Background Art

[0002] As electronic products rapidly evolve toward higher performance, higher integration, and smaller form factors, the complexity of printed circuit board (PCB) design continues to increase. Traditional PCB layout methods rely primarily on the designer's experience, resulting in inefficiencies and inconsistent quality during the design of complex systems. Designers must simultaneously balance multiple performance metrics, such as electrical performance, thermal performance, and space utilization, to find the optimal solution within a vast design space. This experience-based, manual layout approach is no longer sufficient to meet the design demands of modern electronic products.

[0003] Current automated layout technologies primarily rely on heuristic algorithms, such as simulated annealing and genetic algorithms. While these methods can achieve automated layout optimization to a certain extent, they often struggle to effectively handle complex constraints. Rule-based expert systems, while able to leverage design experience, suffer from high rule base maintenance costs and poor adaptability. Traditional machine learning methods also face significant challenges in handling the multimodal data and complex decision-making problems inherent in PCB design. There is an urgent need for a PCB layout optimization method that can intelligently understand design specifications, automatically optimize layout solutions, and effectively balance multiple performance metrics. Summary of the Invention

[0004] The present invention provides a PCB layout optimization method, device, electronic device, storage medium, and product, which can effectively process and understand multimodal data related to PCB design, realize PCB layout design that can meet multiple performance requirements, and effectively improve the quality and efficiency of PCB layout.

[0005] According to one aspect of the present invention, a PCB layout optimization method is provided, comprising:

[0006] In response to a PCB layout optimization event being triggered, obtaining PCB design data and current PCB layout;

[0007] Inputting the PCB design data into a pre-built multimodal large model to obtain multimodal fusion feature information output by the multimodal large model;

[0008] Inputting the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model;

[0009] PCB layout adjustment is performed on the current PCB layout based on the target PCB layout solution.

[0010] According to another aspect of the present invention, a PCB layout optimization device is provided, comprising:

[0011] a PCB design data acquisition module, configured to acquire PCB design data and current PCB layout in response to a PCB layout optimization event being triggered;

[0012] A multimodal fusion feature information acquisition module is used to input the PCB design data into a pre-built multimodal large model and obtain the multimodal fusion feature information output by the multimodal large model;

[0013] a target PCB layout solution acquisition module, configured to input the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model, and acquire a target PCB layout solution output by the PCB layout reinforcement learning model;

[0014] The PCB layout adjustment module is configured to adjust the current PCB layout based on the target PCB layout solution.

[0015] According to another aspect of the present invention, an electronic device is provided, comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the PCB layout optimization method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the PCB layout optimization method described in any embodiment of the present invention when executed.

[0020] According to another aspect of the present invention, a computer program product is provided. The computer program product includes a computer program. When the computer program is executed by a processor, the computer program implements the PCB layout optimization method according to any embodiment of the present invention.

[0021] The PCB layout optimization solution of an embodiment of the present invention, in response to a PCB layout optimization event being triggered, obtains PCB design data and the current PCB layout; inputs the PCB design data into a pre-built multimodal large model to obtain multimodal fusion feature information output by the multimodal large model; inputs the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model; and adjusts the current PCB layout based on the target PCB layout solution. The technical solution provided by the embodiment of the present invention can effectively process and understand multimodal data related to PCB design, achieve PCB layout design that can meet multiple performance requirements, effectively improve the quality and efficiency of PCB layout, and promote the development of PCB design automation technology for electronic products.

[0022] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 A flowchart of a PCB layout optimization method provided by an embodiment of the present invention;

[0025] Figure 2 A schematic diagram of the structure of a multimodal large model provided by an embodiment of the present invention;

[0026] Figure 3 A schematic diagram of a multimodal fusion feature information acquisition process provided by an embodiment of the present invention;

[0027] Figure 4 A schematic diagram of the structure of a PCB layout reinforcement learning model provided by an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of performance evaluation provided by an embodiment of the present invention;

[0029] Figure 6 A schematic diagram of a PCB layout optimization process provided by an embodiment of the present invention;

[0030] Figure 7A schematic diagram of a dynamic adjustment process of an optimization strategy provided by an embodiment of the present invention;

[0031] Figure 8 A comparison diagram before and after PCB layout optimization provided by an embodiment of the present invention;

[0032] Figure 9 A schematic structural diagram of a PCB layout optimization device provided by an embodiment of the present invention;

[0033] Figure 10 A schematic structural diagram of an electronic device for implementing the PCB layout optimization method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] Figure 1 This is a flow chart of a PCB layout optimization method provided by an embodiment of the present invention. This embodiment is applicable to the case of optimizing PCB layout. The method can be executed by a PCB layout optimization device. The PCB layout optimization device can be implemented in the form of hardware and / or software. The PCB layout optimization device can be configured in an electronic device. Figure 1 As shown, the method includes:

[0037] S110 : In response to a PCB layout optimization event being triggered, obtaining PCB design data and current PCB layout.

[0038] In an embodiment of the present invention, upon receiving a PCB layout adjustment instruction input by a user, a PCB layout optimization event is determined to be triggered. In response to the PCB layout optimization event being triggered, PCB design data and a current PCB layout are acquired. The PCB design data may include relevant data such as a text description of PCB design specifications, circuit component parameter descriptions, PCB layout design rules, and circuit schematic images. The current PCB layout can be understood as the PCB layout that requires optimization.

[0039] S120: Input the PCB design data into a pre-built multimodal large model to obtain multimodal fusion feature information output by the multimodal large model.

[0040] In an embodiment of the present invention, a pre-built multimodal large model is obtained. The multimodal large model is used to perform multimodal analysis on PCB design data to determine the multimodal characteristics of the PCB. The PCB design data is input into the multimodal large model, and multimodal fusion feature information output by the multimodal large model is obtained. The multimodal large model can be trained end-to-end, using a combination of cross-entropy loss and contrastive learning loss to optimize the objective.

[0041] Optionally, the PCB design data includes a PCB design specification text description, circuit component parameters, and a circuit schematic diagram; the multimodal large model includes a text processing module, an image processing module, a graph structure processing module, and a multimodal feature fusion module; the PCB design data is input into the pre-built multimodal large model to obtain multimodal fusion feature information output by the multimodal large model, including: inputting the PCB design specification text description into the text processing module to obtain layout constraints output by the text processing module; inputting the circuit schematic diagram into the image processing module to obtain netlist connection relationships output by the image processing module; inputting the circuit component parameters into the graph structure processing module to obtain circuit topology output by the graph structure processing module; and inputting the layout constraints, netlist connection relationships, and circuit topology into the multimodal feature fusion module to obtain multimodal fusion feature information output by the multimodal feature fusion module. The advantage of this configuration is that the multimodal large model can be used to conduct in-depth analysis of the multimodal data of the PCB design and quickly obtain multimodal fusion feature information including layout constraints, netlist connection relationships, and circuit topology.

[0042] For example, Figure 2 This is a schematic diagram of the structure of a multimodal large model provided by an embodiment of the present invention. Figure 2As shown, the multimodal large model includes a text processing module, an image processing module, a graph structure processing module, and a multimodal feature fusion module. The text processing module may include a Transformer encoder, a self-attention layer, and a feature extraction layer. The Transformer encoder may adopt a twelve-layer Transformer encoder structure, with each layer having a word embedding dimension of 768 and equipped with twelve attention heads. The input layer uses positional encoding enhancement. The text processing module is specifically designed to process text information such as design specifications and component parameters. The text processing module in the multimodal large model can be pre-trained based on millions of text data in the PCB field to enable it to understand PCB professional terminology. The image processing module may include a CNN backbone network layer, a spatial attention layer, and a feature extraction layer. The CNN backbone network layer may be based on a ResNet-50 backbone network. The graph structure processing module may include a graph attention network layer, a message passing layer, and a feature aggregation layer. The graph attention network layer may adopt a six-layer graph attention network, with each layer containing 128 hidden units to effectively capture the connectivity between components. In an embodiment of the present invention, a text description of the PCB design specification is input into a text processing module to obtain the layout constraints output by the text processing module, that is, the text processing module is used to convert the PCB design specification text description into quantifiable constraints; wherein, the layout constraints may include component spacing requirements, key signal wiring rules, power integrity requirements, and heat dissipation design specifications and other related information. A circuit schematic is input into an image processing module to obtain the netlist connection relationship output by the image processing module, that is, the image processing module performs computer vision processing on the circuit schematic to identify component symbols, pin positions, and connection relationships; wherein, the netlist connection relationship may include information such as the electrical connection method between components, signal flow direction, power supply and ground distribution, etc. Circuit component parameters are input into a graph structure processing module to obtain the circuit topology output by the graph structure processing module, that is, the graph structure processing module converts the electrical parameters, physical characteristics, and other information of the components into a structured vector representation. The layout constraints output by the text processing module, the netlist connection relationship output by the image processing module, and the circuit topology structure output by the graph structure processing module are input into the multimodal feature fusion module. The alignment and fusion of the above features are achieved through the cross-modal attention layer in the multimodal feature fusion module, and a unified knowledge representation (i.e., multimodal fusion feature information) is generated through the fully connected layer in the multimodal feature fusion module. Figure 3 A schematic diagram of a multimodal fusion feature information acquisition process provided by an embodiment of the present invention.

[0043] Optionally, when acquiring multimodal fusion feature information based on a large multimodal model, the text processing module can employ a specific preprocessing strategy. Specifically, the text description of the PCB design specification can be segmented and standardized to establish a specialized PCB domain vocabulary containing common component names, electrical characteristic parameters, and design specification terminology. Byte Pair Encoding (BPE) can be used for text encoding, with a vocabulary size of 50,000. Furthermore, to handle specialized terminology, specific rules can be incorporated into the segmentation algorithm to ensure the integrity of the terminology. The CNN backbone network layer in the image processing module can be modified based on ResNet-50, such as adding a channel-wise attention mechanism after the convolutional layer and using a Squeeze-and-Excitation module to extract inter-channel dependencies. The spatial attention layer in the image processing module can employ a non-local neural network architecture to capture long-range spatial dependencies. Furthermore, to improve the recognition accuracy of PCB drawings, data augmentation techniques, including rotation, scaling, and noise addition, can be employed during training to enhance the robustness of the image processing module. The graph attention network layer in the graph structure processing module is optimized for PCB topology characteristics. For example, each attention layer contains eight attention heads, each with an output dimension of 16. Node features include information such as component type, electrical parameters, and physical dimensions, while edge features include information such as connection type, signal type, and timing requirements. The message passing layer uses a message passing mechanism to effectively transmit and aggregate global information.

[0044] The multimodal feature fusion module can adopt a hierarchical fusion strategy in the process of feature fusion of layout constraints, netlist connection relationships and circuit topology structures. For example, intra-modal feature fusion can be performed in the first layer, using the self-attention mechanism to integrate different features within the same modality; inter-modal feature fusion can be performed in the second layer, and the alignment and integration of different modal information can be achieved through the cross-modal attention network; global feature fusion can be performed in the third layer, using the gating mechanism to selectively fuse the features of each layer to generate the final multimodal fusion feature information. The advantage of this setting is that by designing a hierarchical feature fusion mechanism, a unified representation of multimodal information is achieved, and a transferable knowledge base system is established, which can continuously accumulate and update design experience and continuously improve the optimization effect.

[0045] S130: Input the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model.

[0046] The PCB layout reinforcement learning model can be a model constructed using an improved PPO algorithm for determining a PCB layout solution. In this embodiment of the present invention, the multimodal fusion feature information and the current PCB layout are input into the PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model. The target PCB layout solution is a PCB layout solution used to optimize the current PCB layout.

[0047] Optionally, the PCB layout reinforcement learning model includes a state encoder, an action generation module, and a value assessment module; inputting the multimodal fusion feature information and the current PCB layout into the PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model includes: inputting the current PCB layout into the state encoder to obtain state information of the current PCB layout output by the state encoder; inputting the multimodal fusion feature information and the state information into the action generation module to obtain a layout adjustment operation output by the action generation module; inputting the layout adjustment operation into the value assessment module to obtain various performance indicators of a new PCB layout solution after executing the layout adjustment operation, output by the value assessment module; and when it is determined that the various performance indicators have converged, using the new PCB layout solution as the target PCB layout solution output by the PCB layout reinforcement learning model.

[0048] For example, Figure 4 This is a structural diagram of a PCB layout reinforcement learning model provided by an embodiment of the present invention. Figure 4As shown, the PCB layout reinforcement learning model consists of a state encoder, an action generation module, and a value assessment module. The state encoder can use a three-layer graph convolutional network to convert the layout state into a 384-dimensional feature vector. The action generation module can output an action probability distribution using a three-layer fully connected network (with dimensions of 384, 256, and 128, respectively). The value assessment module uses a similar structure to the action generation module to output a state value estimate. The state encoder, also known as the state space analysis module, is used to analyze the state information of the current PCB layout. Electrical performance parameters in the state space include signal integrity indicators on signal transmission lines (including signal crosstalk, reflection coefficient, and transmission delay), power integrity parameters of the power distribution network (including power supply noise, IR drop, and decoupling effectiveness), system-level electromagnetic compatibility indicators (including radiated interference level and immunity), and timing parameters of key signals (including signal rise time, propagation delay, and clock skew). The action generation module determines the layout adjustments that can be performed on the current PCB layout, and the value assessment module performs a comprehensive evaluation of the new PCB layout resulting from these adjustments. Specifically, the current PCB layout is input into a state encoder, and state information of the current PCB layout outputted by the state encoder is obtained. The state information of the current PCB layout may include state variables such as component position distribution and performance indicators. Exemplarily, the state information includes the two-dimensional coordinate position information of all components, the actual connection lengths between components, performance parameters of key signals (such as crosstalk and delay), temperature distribution across PCB regions, board space occupancy distribution, the number and distribution of vias used, and the degree to which the current layout plan complies with manufacturing rules. The multimodal fusion feature information and state information are input into an action generation module, and the action generation module outputs a layout adjustment action. Specifically, the action generation module determines a layout adjustment action for the current PCB layout based on an existing strategy network. The layout adjustment action may include at least one of controlling the translation of components on the PCB plane (in any direction and distance), rotating components at different angles, rerouting key signal routing (including adjusting line width, spacing, and corners), allocating and adjusting signal lines between different signal layers, and adjusting the location and number of vias. The layout adjustment operation is input into the value assessment module. The performance indicators of the new PCB layout scheme after the layout adjustment operation are obtained from the value assessment module. It is then determined whether the performance indicators have converged. If so, it means that the performance indicators of the new PCB layout scheme meet the requirements. At this time, the new PCB layout scheme can be used as the target PCB layout scheme output by the PCB layout reinforcement learning model.Among them, various performance indicators may include signal integrity (considering crosstalk, reflection, and delay), power integrity (considering power supply noise and voltage drop), thermal performance (considering hotspot temperature and temperature uniformity), space utilization (considering component density and wiring congestion), and manufacturability (considering assembly difficulty and test feasibility).

[0049] Optionally, the various performance indicators include electrical performance indicators, thermal performance indicators, space utilization indicators and manufacturability indicators; determining the convergence of the various performance indicators includes: calculating the comprehensive reward score of the various performance indicators through a comprehensive reward function, and when the comprehensive reward score is greater than a preset score threshold, determining that the various performance indicators converge. In an embodiment of the present invention, the various performance indicators under the new PCB layout scheme after the layout adjustment operation are determined by a value assessment module, wherein the various performance indicators may include electrical performance indicators, thermal performance indicators, space utilization indicators and manufacturability indicators. For example, electrical performance indicators may include signal integrity (accounting for 30%), power integrity (accounting for 20%) and EMC characteristics (accounting for 20%). Thermal performance indicators may mainly consider temperature distribution uniformity (accounting for 15%). Space utilization indicators may include layout density and routing feasibility (accounting for 10%). Manufacturability indicators may include the degree of satisfaction of assembly process requirements (accounting for 5%). The weights of each indicator are dynamically adjusted through an adaptive mechanism. Exemplary, Figure 5 A performance evaluation diagram provided by an embodiment of the present invention. Figure 5 As shown, a new PCB layout solution can be evaluated for electrical performance, thermal performance, space utilization, and manufacturability to determine a score. Electromagnetic field simulation software can be used to verify signal transmission characteristics and power integrity; thermal analysis tools can be used to assess the PCB's temperature distribution; the layout's density distribution and space utilization can be calculated and evaluated; and the layout's manufacturability can be evaluated against manufacturing specifications. A weighted summation of the scores corresponding to each performance indicator is then performed based on a comprehensive reward function to obtain a comprehensive reward score. The comprehensive reward score is then determined to be greater than a preset threshold. If so, the performance indicators are considered converged.

[0050] Optionally, the method further includes: if the performance indicators have not converged, updating the network parameters of the PCB layout reinforcement learning model based on the current interactive experience information, updating the current PCB layout based on the PCB layout corresponding to the new PCB layout solution, and returning to execute inputting the current PCB layout into the state encoder until the performance indicators converge; wherein the current interactive experience information includes the state information of the current PCB layout, the layout adjustment operation, the comprehensive reward score, and the new PCB layout solution.

[0051] In an embodiment of the present invention, if the various performance indicators under the new PCB layout scheme after the layout adjustment operation is performed have not converged, it means that the new PCB layout scheme generated after the layout adjustment operation is performed on the current PCB layout still needs to be further optimized. At this time, the current interactive experience information (the status information of the current PCB layout, the layout adjustment operation, the comprehensive reward score and the new PCB layout scheme) is stored in the experience replay pool and used to update the network parameters of the PCB layout reinforcement learning model, so that by adjusting the network parameters, the model is more inclined to choose a layout adjustment operation that can balance various performance indicators in subsequent decisions. The current PCB layout is updated based on the PCB layout corresponding to the new PCB layout scheme, and the execution returns to input the current PCB layout into the state encoder, that is, the above-mentioned iterative process is continuously executed until the various performance indicators of the layout scheme converge and the optimal balance state is reached between the various indicators. At this time, the target PCB layout scheme is output. It can be understood that the target PCB layout scheme is a fully optimized PCB layout scheme. Exemplarily, Figure 6 A schematic diagram of a PCB layout optimization process provided by an embodiment of the present invention. During the iterative optimization process, the weight coefficients of various performance indicators can be dynamically adjusted based on the optimization progress. The optimal layout solution that emerges during the optimization process can also be continuously recorded and updated. Multi-dimensional convergence judgment criteria can be set, including the degree of improvement in performance indicators and the number of iterations. A manual intervention interface can also be reserved, allowing design experts to adjust the solution based on their experience.

[0052] In an embodiment of the present invention, a multi-level optimization strategy may be used in the layout optimization process. For example, Figure 7 Schematic diagram of a dynamic adjustment process of an optimization strategy provided by an embodiment of the present invention. Figure 7 As shown in the figure, in the global optimization phase, a preliminary layout of functional blocks can be performed, overall performance indicators can be comprehensively evaluated, and a priority system for key constraints can be established. Next, the local optimization phase is carried out to fine-tune component positions, focusing on optimizing critical signal paths and improving the distribution of hotspots. Finally, the refined optimization phase (detail refinement) further optimizes via distribution, adjusts routing paths, and improves overall space utilization. This multi-layered optimization strategy ensures the effectiveness and reliability of the optimization process.

[0053] It should be noted that training strategies for PCB layout reinforcement learning models can include: dynamically adjusting the exploration-exploration balance factor, increasing the exploration ratio in the early stages of training and the utilization ratio in the later stages; maintaining an experience replay buffer to store historical optimization experiences and randomly sample them for training; implementing a priority-based sampling method to prioritize learning important optimization experiences; and incorporating manually summarized PCB layout expert knowledge to guide model training. Parameters of the PCB layout reinforcement learning model, such as the model structure, optimization algorithm parameters, and evaluation metric weights, can be flexibly configured and optimized as needed by those skilled in the art.

[0054] S140: Adjust the current PCB layout based on the target PCB layout solution.

[0055] In an embodiment of the present invention, the current PCB layout is optimized and adjusted based on the target PCB layout solution to generate the target PCB layout. For example, Figure 8 This figure shows a comparison of the PCB layout before and after optimization according to an embodiment of the present invention. Experiments have shown that, compared to traditional methods, the PCB optimization method provided by an embodiment of the present invention can reduce PCB layout time by 60%, improve signal integrity by 25%, and enhance thermal uniformity by 30%, significantly enhancing overall performance in a multi-layer PCB design containing 500 components.

[0056] The PCB layout optimization solution provided by the embodiment of the present invention can be applied to multiple fields and has a wide range of applicability. For example, for the PCB design of high-speed communication equipment, it can focus on optimizing the transmission path of high-speed signals to ensure signal integrity and timing requirements; when processing the PCB design of analog and digital mixed circuits, the device layout can be reasonably planned to reduce mutual interference. For the PCB design of power circuits, special attention can be paid to heat distribution and power integrity to achieve better heat dissipation. In addition, in the PCB design of complex systems, the intelligent characteristics of the solution provided by the embodiment of the present invention can significantly improve design efficiency, automatically understand and apply design specifications, and convert expert knowledge into executable optimization strategies. Through continuous learning and experience accumulation, the system can continuously improve the optimization effect and adapt to different types of PCB design requirements. The multi-objective optimization mechanism ensures that while meeting various technical indicators, the manufacturability and cost factors of the design are taken into account.

[0057] The technical solution provided by the embodiment of the present invention also shows unique advantages in special application scenarios. In the design of flexible circuit boards, the component layout can be optimized according to the deformation characteristics of the product; for high-density interconnection boards, the wiring space can be reasonably planned to improve space utilization; when dealing with industrial and medical equipment PCBs with high reliability requirements, it can ensure that the design solution meets strict safety and reliability standards. In the production and manufacturing process, the adaptive optimization characteristics of the present invention can improve production efficiency. It can automatically adjust the design rules and layout constraints according to the characteristics of different manufacturing processes to improve the manufacturability of the design solution. This intelligent optimization method can effectively reduce design rework and accelerate the product development process.

[0058] The PCB layout optimization method of an embodiment of the present invention, in response to a PCB layout optimization event being triggered, obtains PCB design data and the current PCB layout; inputs the PCB design data into a pre-built multimodal large model to obtain multimodal fusion feature information output by the multimodal large model; inputs the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model; and adjusts the current PCB layout based on the target PCB layout solution. The technical solution provided by the embodiment of the present invention can effectively process and understand multimodal data related to PCB design, achieve PCB layout design that can meet various performance requirements, effectively improve the quality and efficiency of PCB layout, and promote the development of PCB design automation technology for electronic products.

[0059] Figure 9 A schematic diagram of the structure of a PCB layout optimization device provided by an embodiment of the present invention. Figure 9 As shown, the device includes:

[0060] PCB design data acquisition module 910, for acquiring PCB design data and current PCB layout in response to a PCB layout optimization event being triggered;

[0061] The multimodal fusion feature information acquisition module 920 is used to input the PCB design data into a pre-built multimodal large model and obtain the multimodal fusion feature information output by the multimodal large model;

[0062] A target PCB layout solution acquisition module 930 is configured to input the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model;

[0063] The PCB layout adjustment module 940 is configured to adjust the current PCB layout based on the target PCB layout solution.

[0064] Optionally, the PCB design data includes a text description of PCB design specifications, circuit component parameters, and circuit schematics; the multimodal large model includes a text processing module, an image processing module, a graph structure processing module, and a multimodal feature fusion module;

[0065] The multimodal fusion feature information acquisition module is used to:

[0066] Inputting the PCB design specification text description into the text processing module, and obtaining the layout constraint conditions output by the text processing module;

[0067] Inputting the circuit schematic into the image processing module to obtain the netlist connection relationship output by the image processing module;

[0068] Inputting the circuit element parameters into the graph structure processing module to obtain the circuit topology output by the graph structure processing module;

[0069] The layout constraint conditions, the netlist connection relationship and the circuit topology structure are input into the multimodal feature fusion module to obtain the multimodal fusion feature information output by the multimodal feature fusion module.

[0070] Optionally, the PCB layout reinforcement learning model includes a state encoder, an action generation module and a value assessment module;

[0071] The target PCB layout scheme acquisition module includes:

[0072] a state information acquiring unit, configured to input the current PCB layout into the state encoder and acquire state information of the current PCB layout output by the state encoder;

[0073] a layout adjustment operation acquiring unit, configured to input the multimodal fusion feature information and the state information into the action generation module, and acquire the layout adjustment operation output by the action generation module;

[0074] The target PCB layout scheme determining unit is configured to input the layout adjustment operation into the value assessment module, obtain various performance indicators of a new PCB layout scheme after executing the layout adjustment operation, output by the value assessment module, and, when it is determined that the various performance indicators have converged, use the new PCB layout scheme as the target PCB layout scheme output by the PCB layout reinforcement learning model.

[0075] Optionally, the various performance indicators include electrical performance indicators, thermal performance indicators, space utilization indicators and manufacturability indicators;

[0076] The target PCB layout scheme determining unit is used to:

[0077] The comprehensive reward score of each performance indicator is calculated by a comprehensive reward function, and when the comprehensive reward score is greater than a preset score threshold, it is determined that each performance indicator has converged.

[0078] Optionally, also include:

[0079] an iterative optimization module configured to, if the performance indicators have not converged, update the network parameters of the PCB layout reinforcement learning model based on current interactive experience information, update the current PCB layout based on the PCB layout corresponding to the new PCB layout solution, and return to execute input of the current PCB layout into the state encoder until the performance indicators converge; wherein the current interactive experience information includes state information of the current PCB layout, the layout adjustment operation, the comprehensive reward score, and the new PCB layout solution.

[0080] Optionally, the layout adjustment operation includes: controlling the translational movement of components on the PCB plane, rotating components at different angles, replanning routing paths for key signals, allocating and adjusting signal lines between different signal layers, and adjusting at least one of the position and number of vias.

[0081] The PCB layout optimization device provided in the embodiment of the present invention can execute the PCB layout optimization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0082] Figure 10 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0083] like Figure 10As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0084] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0085] The processor 11 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors that run machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the PCB layout optimization method.

[0086] In some embodiments, the PCB layout optimization method can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the PCB layout optimization method described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the PCB layout optimization method in any other suitable manner (e.g., via firmware).

[0087] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0088] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0089] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0090] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0091] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0092] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0093] A computer program product is further provided in an embodiment of the present invention. The computer program product includes a computer program. When the computer program is executed by a processor, the computer program implements the PCB layout optimization method described in any embodiment of the present invention.

[0094] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0095] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A PCB layout optimization method, characterized in that: include: In response to a PCB layout optimization event being triggered, obtaining PCB design data and current PCB layout; Inputting the PCB design data into a pre-built multimodal large model to obtain multimodal fusion feature information output by the multimodal large model; Inputting the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model to obtain a target PCB layout solution output by the PCB layout reinforcement learning model; PCB layout adjustment is performed on the current PCB layout based on the target PCB layout solution.

2. The method according to claim 1, characterized in that The PCB design data includes a text description of the PCB design specification, circuit component parameters, and a circuit schematic diagram; the multimodal large model includes a text processing module, an image processing module, a graph structure processing module, and a multimodal feature fusion module; Inputting the PCB design data into a pre-built multimodal large model and obtaining multimodal fusion feature information output by the multimodal large model includes: Inputting the PCB design specification text description into the text processing module, and obtaining the layout constraint conditions output by the text processing module; Inputting the circuit schematic into the image processing module to obtain the netlist connection relationship output by the image processing module; Inputting the circuit element parameters into the graph structure processing module to obtain the circuit topology output by the graph structure processing module; The layout constraint conditions, the netlist connection relationship and the circuit topology structure are input into the multimodal feature fusion module to obtain the multimodal fusion feature information output by the multimodal feature fusion module.

3. The method according to claim 1, characterized in that The PCB layout reinforcement learning model includes a state encoder, an action generation module and a value assessment module; Inputting the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model, and obtaining a target PCB layout solution output by the PCB layout reinforcement learning model, including: Inputting the current PCB layout into the state encoder, and obtaining state information of the current PCB layout output by the state encoder; Inputting the multimodal fusion feature information and the state information into the action generation module, and obtaining the layout adjustment operation output by the action generation module; The layout adjustment operation is input into the value assessment module, and various performance indicators of a new PCB layout solution after executing the layout adjustment operation, which is output by the value assessment module, are obtained. When it is determined that the various performance indicators have converged, the new PCB layout solution is used as the target PCB layout solution output by the PCB layout reinforcement learning model.

4. The method according to claim 3, characterized in that The various performance indicators include electrical performance indicators, thermal performance indicators, space utilization indicators and manufacturability indicators; Confirming the convergence of the various performance indicators includes: The comprehensive reward score of each performance indicator is calculated by a comprehensive reward function, and when the comprehensive reward score is greater than a preset score threshold, it is determined that each performance indicator has converged.

5. The method according to claim 4, characterized in that Also includes: If the performance indicators have not converged, network parameters of the PCB layout reinforcement learning model are updated based on the current interactive experience information, the current PCB layout is updated based on the PCB layout corresponding to the new PCB layout solution, and the process returns to inputting the current PCB layout into the state encoder until the performance indicators converge. The current interactive experience information includes state information of the current PCB layout, the layout adjustment operation, the comprehensive reward score, and the new PCB layout solution.

6. The method according to claim 3, characterized in that The layout adjustment operation includes: controlling the translation movement of components on the PCB plane, rotating components at different angles, replanning routing paths for key signals, allocating and adjusting signal lines between different signal layers, and adjusting the position and number of vias.

7. A PCB layout optimization device, characterized in that: include: a PCB design data acquisition module, configured to acquire PCB design data and current PCB layout in response to a PCB layout optimization event being triggered; A multimodal fusion feature information acquisition module is used to input the PCB design data into a pre-built multimodal large model and obtain the multimodal fusion feature information output by the multimodal large model; a target PCB layout solution acquisition module, configured to input the multimodal fusion feature information and the current PCB layout into a PCB layout reinforcement learning model, and acquire a target PCB layout solution output by the PCB layout reinforcement learning model; The PCB layout adjustment module is configured to adjust the current PCB layout based on the target PCB layout solution.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the PCB layout optimization method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the PCB layout optimization method according to any one of claims 1 to 6 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the PCB layout optimization method according to any one of claims 1 to 6.

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