Method for verifying programmable memory configuration result, electronic device and storage medium

Abstract

The present application relates to the technical field of chip design, in particular to a programmable memory configuration result verification method, electronic equipment and storage medium, which obtains a standard file of standard signal values stored in a programmable memory and a configuration file thereof, and includes index information of each signal in the configuration file; obtains actual signal values of the signals configured according to the standard file, and stores the actual signal values of K signals in sequence as a row of configuration result sequence according to the index information of the signals in the configuration file, obtains a configuration result file, processes the standard signal values in the standard file into a row of standard sequence, and compares and verifies the configuration result sequence and the standard sequence, thereby reducing the workload, avoiding compilation errors, greatly improving the efficiency, and shortening the verification period.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip design technical field, in particular to a programmable memory configuration result verification method, an electronic device and a storage medium. BACKGROUND

[0002] The programmable memory is a one-time programmable memory, based on semiconductor technology, can be programmed through a specific electrical signal, the information is not lost after power off, can be used for storing data, such as configuration parameters and user data, etc., some can also protect the elements of the circuit when the circuit is abnormal, such as overcurrent and overvoltage. In the system on a chip (SOC), after the chip is powered on, the boot code will initialize and configure each module in the chip, and one of the important tasks is to use the configuration value stored in the programmable memory to set each module, and these configuration values are equivalent to the standard value (golden value) of the original input. In order to ensure the correctness of the configuration, a set of checking mechanism is needed in the IC verification link, that is, after the boot code completes the configuration, it is checked whether the configuration result of each intellectual property core (IP) is consistent with the reference file (hex) of the fuse. Assuming that the file is a 32bitx1536 row array. The original checking mechanism is to manually extract the signal value after configuration and splice it into a 32bitx1536 row array. However, since the signal bit width is various, some are 1bit or 2bit, some are 8bit or dozens of bits, and the splicing of each row requires 32bit, so there will be a line change problem in the splicing process. If when splicing to 30bit, if the next signal is 8bit, it needs to be line changed, and the 8bit data is stored by two lines, but because there are many signals, it is difficult to determine when the signal of the first several bits is spliced to the signal, and there is no unified rule.

[0003] This situation leads to two obvious defects: first, because the line change signal cannot be determined, there is no unified calculation formula for the script processing, and it can only rely on manual splicing, which increases the labor cost and time cost of verification, and is easy to introduce human error; second, if a new signal is added, the signal that needs to be line changed before will no longer be line changed, which will cause the original splicing writing to appear a compilation error, reducing the stability and maintainability of the verification process. SUMMARY

[0004] In view of the above technical problems, the technical scheme adopted by the present application is: a programmable memory configuration result verification method, the method comprising the following steps:

[0005] Obtain the standard file of the standard signal value stored in the programmable memory, the standard file includes M rows of data composed of K standard signal values, and each row of data includes N bits of data.

[0006] obtaining a configuration file of the standard file, the configuration file including index positions of the K signals, wherein the index position of each signal includes a row index index, a row offset and a data bit width size of a standard signal value of a current signal in the standard file.

[0007] obtaining actual signal values, the actual signal values being signal values obtained according to a standard file configuration signal; and storing the actual signal values of the K signals in sequence as a row of configuration result sequences according to the index information of the signals in the configuration file, to obtain a configuration result file; wherein the step of storing the actual signal value of the jth signal into the configuration result sequence includes: determining a target index position of the jth signal in the configuration result sequence according to the row index index j , the row offset offset j and the data bit width size size j of the jth signal, and storing the actual signal value of the jth signal into the target index position.

[0008] splicing the M rows of data in the standard file into a row of standard sequences.

[0009] comparing and verifying the configuration result sequences and the standard sequences.

[0010] In addition, the application further provides a non-transitory computer readable storage medium, the storage medium storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by a processor to implement the above method.

[0011] In addition, the application further provides an electronic device, including a processor and the above non-transitory computer readable storage medium.

[0012] The application has at least the following beneficial effects:

[0013] The application provides a programmable memory configuration result verification method, an electronic device and a storage medium, which stores all actual signal values of configuration in sequence as a row of configuration result sequences according to index positions of signals in a configuration file, processes standard signal values in a standard file into a row of standard sequences, compares and verifies the configuration result sequences and the standard sequences, thereby reducing workload, avoiding compilation error problems, greatly improving efficiency, shortening verification period, and improving stability and maintainability of a verification process. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments description. Obviously, the drawings in the following description only show some of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on these drawings are within the protection scope of the present application.

[0015] Figure 1 A verification method flow chart of programmable memory configuration result is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0016] The technical solutions in the embodiments of the present application will be clearly and completely described in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present application.

[0017] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present application have the same meanings as commonly understood by those skilled in the art.

[0018] Please refer to Figure 1 The verification method of programmable memory configuration result comprises the following steps:

[0019] S100, obtaining a standard file of standard signal values stored in a programmable memory, the standard file comprising M rows of data composed of K standard signal values of signals, each row of data comprising N bits of data.

[0020] The programmable memory is a one-time programmable memory based on semiconductor technology, which can be programmed by a specific electrical signal and the information is not lost after power off. The programmable memory can be used to store data such as configuration parameters and user data, and some of them can also protect the elements of the circuit when the circuit is abnormal, such as overcurrent and overvoltage.

[0021] In an embodiment, the programmable memory is Efuse or Flash Memory, and other types of programmable memories also fall within the protection scope of the present application. In a chip, the capacity of Efuse is usually very small, and the Efuse of some chips is only 128 bits.

[0022] It should be noted that each row of data comprises at least one signal value of a signal. A row of data can comprise at least one signal value of a signal, and the signal value of a signal can span two rows, that is, a part of the signal value of the signal is at the end of the previous row and another part of the signal value is at the head of the next row.

[0023] As an example, a line of data information is 32 bits, the signal value of signal A1 is 8 bits, the signal value of signal A2 is 16 bits, the signal value of signal A3 is 16 bits, and it is assumed that the signal values of A1, A2 and A3 are stored in the first line in turn from low to high. Since the signal value of A3 is longer, only 8 bits can be stored in the first line, and the remaining 8 bits of A3 are stored in the low 8 bits of the second line.

[0024] S200, obtaining a configuration file of the standard file, the configuration file including index positions of the K signals, wherein the index position of each signal includes a line index index, a line offset and a data bit width size of a standard signal value of a current signal in the standard file.

[0025] It should be noted that the line index can be used to locate the line in which the signal value of the current signal is located in the standard file, the line offset can be used to locate the bit in which the signal value of the current signal starts from the line in the standard file, and the data bit width can be used to determine the data width of the signal value of the current signal. The data that can be directly obtained in the configuration file is the starting address of signal storage, the line offset and the data bit width. The line index index needs to be obtained by a formula.

[0026] In an embodiment, the index satisfies: index = starting address / R, wherein R is the number of bytes of address alignment. The starting address is the storage address configured for the current signal in the configuration file. For R, byte alignment is a memory management strategy which stipulates that the starting address of data storage must be an integer multiple of R. The purpose of this is to improve the efficiency of data access, because hardware is faster when accessing aligned data. For example, if R = 4, the starting address of data must be a multiple of 4.

[0027] S300, obtaining an actual signal value, the actual signal value being a signal value obtained according to the standard file; and storing the actual signal values of the K signals in sequence as a line of configuration result sequence according to the index information of the signals in the configuration file, to obtain a configuration result file; wherein the step of storing the actual signal value of the jth signal in the configuration result sequence includes: determining a target index position of the jth signal in the configuration result sequence according to the line index index j , the line offset offset j and the data bit width size j of the jth signal, and storing the actual signal value of the jth signal in the target index position.

[0028] After allocating the standard signal value stored in the programmable memory to each signal, an actual signal value is obtained, and it is necessary to verify whether the configured actual signal value is the same as the standard signal value stored in the programmable memory.

[0029] In one embodiment, the target index position includes a starting position fuse_index and a stored data width stored in the configuration result sequence, the stored data width is configured as the size, and the fuse_index is configured as index×N+offset.

[0030] As an example, when each line has 32 bits of data and R = 4 bytes, the starting address of the jth signal is 0 according to the configuration file, and the row offset is j 4, data bit width size j When it is 12, it indicates that the starting position of the j-th signal stored in the configuration result sequence is fuse_index=index+offset=0 / 4×32+4=4, that is, the starting position of the j-th signal stored in the configuration result sequence is the 4th bit, and the stored data width is 12 bits, that is, the target index position for storing the actual signal value of the j-th signal is from the 4th bit to the 15th bit.

[0031] It should be noted that there is no line break data in the configuration result sequence.

[0032] S400: splicing the M lines of data in the standard file into a line of standard sequence.

[0033] In one embodiment, the splicing step includes: reading the data in the standard file line by line, storing each line of data in a list in order; and connecting the data lines in the list in order to form a continuous line of standard sequence.

[0034] It should be noted that there is no line break data in the standard sequence.

[0035] S500: Compare and verify the configuration result sequence with the standard sequence.

[0036] It should be noted that since both the configuration result sequence and the standard sequence contain single-line data and do not contain line-wrapped data, they can be directly compared.

[0037] In an embodiment, since the amount of signals that need to be configured by programmable memory in a chip is huge, the workload of manually writing code to store the signal value of each signal into the configuration result sequence is also huge. To solve the problem of manually writing code, the present application further automatically writes this part of code through a script, so the method further comprises: S310, automatically generating K splicing functions corresponding to the K signals, each splicing function being used to store the signal value of the current signal into the configuration result sequence; wherein the steps of automatically generating the splicing function of the jth signal by the script comprise:

[0038] S311, obtaining the declared splicing function, the splicing function comprising a function name and a parameter list, the parameter list comprising a first input parameter and a second input parameter.

[0039] As an example, the splicing function is uvm_model_read(A1, fuse_data_dut[A2]), wherein uvm_model_read is the function name, A1 is the first input parameter, and fuse_data_dut[A2] is the second input parameter. The first input parameter is the signal name of the signal to be read. The second input parameter is the target index position where the read result is stored, wherein fuse_data_dut is the array name.

[0040] S312, obtaining the index of the jth signal according to the configuration file j , offset j and size j .

[0041] S313, splicing the second input parameter in the splicing function according to the index j , offset j and size j .

[0042] In an embodiment, the second input parameter is fuse_data_dut[A21:A22], wherein fuse_data_dut[A21:A22] is the target index position where the read result is stored, fuse_data_dut is the array name, A21 is index j ×N+offset j +size j , representing the high address index of the target index position, and A22 is index j ×N+offset j , representing the low address index of the target index position. In an embodiment, index j = start address / R.

[0043] S314, obtaining a signal file, the signal file comprising signal names of K signals.

[0044] S315, matching the signal file with signal names of the second input parameter, and when the matching is successful, generating the first input parameter in the splicing function according to the matched signal name.

[0045] In an embodiment, the matching of the signal name is text matching.

[0046] In an embodiment, the signal name is a hierarchical name of the signal. The hierarchical name of the signal is a naming method for accurately identifying the position of the signal in a complex circuit system, and reflects the hierarchical relationship of the module where the signal is located.

[0047] The method for automatically generating the splicing function provided by S311-S315 improves the generation efficiency of the splicing function.

[0048] In summary, the application provides a verification method for programmable memory configuration results, which stores all actual signal values of the configuration in a configuration result sequence in order through the index positions of the signals in the configuration file, processes the standard signal values in a standard file into a standard sequence, and compares and verifies the configuration result sequence and the standard sequence, thereby reducing the workload, avoiding compilation errors, greatly improving the efficiency, and shortening the verification period.

[0049] The embodiment of the application further provides a non-transitory computer readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a method in the method embodiment, and the at least one instruction or the at least one program is loaded and executed by the processor to realize the method provided by the above embodiment.

[0050] The embodiment of the application further provides an electronic device, which comprises a processor and the aforementioned non-transitory computer readable storage medium.

[0051] The embodiment of the application further provides a computer program product, which comprises program code, and when the program product is run on an electronic device, the program code is used to make the electronic device execute the steps in the method according to various exemplary embodiments of the application described in the specification.

[0052] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the above-described functions.

[0053] While certain specific embodiments of the application have been described in detail herein for the purposes of exemplification, it will be understood by those skilled in the art that numerous modifications can be made thereto without departing from the scope and spirit of the application. The scope of the present application is limited only by the claims that follow.

Claims

1. A method of verifying a programmable memory configuration result, characterized by, The method comprises the following steps: obtaining a standard file of standard signal values stored in a programmable memory, the standard file comprising M rows of data composed of standard signal values of K signals, each row of data comprising N bits of data; obtaining a configuration file of the standard file, the configuration file comprising index information of the K signals, wherein the index information of each signal comprises a row index index, a row offset offset and a data bit width size of the standard signal value of the current signal in the standard file; The actual signal value is obtained according to the signal value of the standard file configuration signal, and the actual signal values of the K signals are stored in sequence as a configuration result sequence according to the index information of the signal in the configuration file to obtain a configuration result file; wherein the step of storing the actual signal value of the jth signal into the configuration result sequence comprises: determining the target index position of the jth signal in the configuration result sequence according to the row index index j , row offset offset j and data bit width size j of the jth signal, and storing the actual signal value of the jth signal into the target index position. splicing the M rows of data in the standard file into a row of standard sequences; comparing and verifying the configuration result sequence with the standard sequence.

2. The method of claim 1, wherein, The target index position comprises a stored start position fuse_index in the configuration result sequence and a stored data width, the stored data width being configured as the size, and the fuse_index being configured as index×N+offset.

3. The method of claim 1, wherein, The index satisfies: index=starting address / R, wherein R is the number of bytes of address alignment.

4. The method of claim 1, wherein, The method further comprises automatically generating, by a script, K splicing functions corresponding to the signals, each of the splicing functions being used to store actual signal values of a current signal into the configuration result sequence.

5. The method of claim 4, wherein, The step of automatically generating, by a script, the splicing function of the jth signal comprises: obtaining a declared splicing function, the splicing function comprising a function name and a parameter list, the parameter list comprising a first input parameter and a second input parameter; According to the configuration file, acquire the index of the jth signal j , offset j , and size j ; According to the index j , offset j and size j splicing to generate the second input parameter in the splicing function; obtaining a signal file, the signal file comprising signal names of the K signals; matching the signal file with the signal name of the second input parameter, and generating the first input parameter in the splicing function according to the matched signal name when the matching is successful.

6. The method of claim 5, wherein, The second input parameter is fuse_data_dut[A21:A22], wherein fuse_data_dut[A21:A22] is a target index position for storing a read result, fuse_data_dut is an array name, A21 is index j ×N+offset j +size j , which represents a high-bit address index of the target index position; A22 is index j ×N+offset j , which represents a low-bit address index of the target index position.

7. The method of claim 1, wherein, The splicing step comprises reading data in the standard file row by row, and storing each row of data in a list in order; and sequentially connecting the data rows in the list to form a continuous row of standard sequences.

8. The method of claim 1, wherein, The programmable memory is an Efuse. 9.A non-transitory computer-readable storage medium having stored therein at least one instruction or at least one piece of program, characterized in that, The at least one instruction or the at least one program is loaded and executed by the processor to implement the method of any one of claims 1-8.

10. An electronic device, comprising: The non-transitory computer readable storage medium of claim 9 is included in a processor. The non-transitory computer readable storage medium of claim 9 is included in a processor.

Images