Multilayer ceramic capacitor

Abstract

Provided is a multilayer ceramic capacitor in which the occurrence of layer peeling when a mechanical stress is applied is suppressed. In the multilayer ceramic capacitor (1), the segregation amount of silicon and magnesium on the outer layer side (711) of the outermost internal electrode layer (301) is greater than the segregation amount of silicon and magnesium on the inner layer side (712) of the outermost internal electrode layer (301). When a first region (340) is defined as a region defined by a region (320) in which the outermost internal electrode layer (301) is present and a segregation region (330) of silicon and magnesium present in contact with the outermost internal electrode layer (301), the line edge roughness (A) of the outer layer side (711) of the first region (340) is greater than the line edge roughness (B) of the inner layer side (712) of the first region (340).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] For example, the multilayer ceramic capacitor described in Patent Document 1 includes a capacitor body comprising a ceramic sintered body composed of a dielectric such as barium titanate. Internal electrode layers composed of precious metals such as silver or a silver-palladium alloy, or base metals such as nickel, are arranged within the capacitor body, sandwiching a ceramic layer serving as the dielectric layer. The internal electrode layers are alternately extended to one end face and the other end face of the capacitor body. The alternating internal electrode layers are electrically connected to external electrodes at different potentials.

[0003] The multilayer capacitor described in Patent Document 1 has internal electrode layers made of a metal material, and external electrodes made of multiple metal components, including the same metal as or alloyable with the internal electrode layers, and a glass component. The external electrodes are bonded to the wiring substrate via a conductive resin adhesive. The area of ​​the metal component relative to the cross-sectional area of ​​the external electrode ranges from 60% to 95%. As a result, the multilayer capacitor described in Patent Document 1 can be mounted on the wiring substrate at low cost and with high reliability without the use of solder.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2001-237137

[0007] Furthermore, the laminated body of a typical multilayer ceramic capacitor as described above has an inner layer portion and an outer layer portion in the height direction. The inner layer portion is the portion where the dielectric layer and internal electrode layer are stacked. The outer layer portion is the portion where only the dielectric layer is arranged without the internal electrode layer. Conventionally, the mechanical bonding strength between the inner and outer layers was not high. Therefore, when mechanical stress is applied to the multilayer ceramic capacitor, there is a problem of delamination between the inner and outer layers. Summary of the Invention

[0008] Problems to be solved by the invention

[0009] Therefore, an object of the present invention is to provide a multilayer ceramic capacitor that suppresses the occurrence of layer separation when mechanical stress is applied.

[0010] Technical solutions to solve problems

[0011] The multilayer ceramic capacitor of the present invention comprises: a laminated body including a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, comprising a first main surface and a second main surface opposite to each other in the height direction, a first side surface and a second side surface opposite to each other in the width direction perpendicular to the height direction, and a first end surface and a second end surface opposite to each other in the length direction perpendicular to the height direction and the width direction, and comprising an inner layer portion and an outer layer portion, wherein the inner layer portion is formed by alternately laminating the dielectric layers and the internal electrode layers, and the outer layer portion is arranged so as to sandwich the inner layer portion from the first main surface side and the second main surface side; a first external electrode is arranged on the inner layer portion; on the first end face; and a second external electrode arranged on the second end face, wherein, when the internal electrode layer arranged closest to the outer layer portion is set as the outermost internal electrode layer, the segregation amount of silicon and magnesium on the outer layer side of the outermost internal electrode layer is greater than the segregation amount of silicon and magnesium on the inner layer side of the outermost internal electrode layer, and when the area defined by the area where the outermost internal electrode layer exists and the segregation area of ​​silicon and magnesium existing in contact with the outermost internal electrode layer is set as the first area, the line edge roughness A on the outer layer side of the first area is greater than the line edge roughness B on the inner layer side of the first area.

[0012] Effects of the Invention

[0013] According to the present invention, it is possible to provide a multilayer ceramic capacitor in which the occurrence of layer separation when mechanical stress is applied is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a perspective view of the appearance of a multilayer ceramic capacitor according to one embodiment of the present disclosure.

[0015] Figure 2 yes Figure 1 101-101 cross-sectional view.

[0016] Figure 3 yes Figure 2 102-102 cross-sectional view.

[0017] Figure 4 yes Figure 2 103-103 cross-sectional view.

[0018] Figure 5 yes Figure 2 104-104 cross-sectional view.

[0019] Figure 6 yes Figure 1 101-101 cross-sectional view.

[0020] Figure 7 is equivalent to Figure 6 A portion of the enclosing box 110 is shown enlarged in the figure.

[0021] Figure 8 is equivalent to Figure 6 A portion of the enclosing box 110 is shown enlarged in the figure.

[0022] Figure 9 This is a diagram for explaining line edge roughness.

[0023] Figure 10 It is a graph showing the evaluation results of Examples and Comparative Examples.

[0024] Description of Reference Numerals

[0025] 1: Multilayer ceramic capacitor;

[0026] 2: laminate;

[0027] 3: The first main surface;

[0028] 4: The second main side;

[0029] 5: 1st side;

[0030] 6: 2nd side;

[0031] 7: 1st end face;

[0032] 8: Second end face;

[0033] 10: inner layer;

[0034] 11: outer layer portion on the main surface side;

[0035] 14: electrode opposing portion;

[0036] 20: dielectric layer;

[0037] 21: inner dielectric layer;

[0038] 22: outer dielectric layer;

[0039] 30: internal electrode layer;

[0040] 40: external electrode;

[0041] 41: 1st external electrode;

[0042] 42: second external electrode;

[0043] 50: base electrode layer;

[0044] 80: Segregation of silicon and magnesium;

[0045] 301: outermost internal electrode layer;

[0046] 311: outer surface;

[0047] 312: Inner plane;

[0048] 320: The area where the outermost internal electrode layer exists;

[0049] 330: silicon and magnesium segregation area;

[0050] 340: Area 1;

[0051] 341: outer lateral line in region 1;

[0052] 342: Inner lateral line of region 1;

[0053] 701: thickness of the internal electrode layer;

[0054] 711: outer side;

[0055] 712: inner side;

[0056] 721: Area of ​​the outer side of region 1;

[0057] 722: Area of ​​the outer side of the second region;

[0058] L: length direction;

[0059] T: height direction;

[0060] W: width direction. DETAILED DESCRIPTION

[0061] (Multilayer Ceramic Capacitors)

[0062] A multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described with reference to the drawings. Figure 1 This is a perspective view of the appearance of a multilayer ceramic capacitor 1 according to one embodiment of the present disclosure. Figure 2 yes Figure 1 101-101 cross-sectional view. Figure 3 yes Figure 2 102-102 cross-sectional view. Figure 4 yes Figure 2 103-103 cross-sectional view. Figure 5 yes Figure 2 104-104 cross-sectional view.

[0063] like Figure 1 As shown, the multilayer ceramic capacitor 1 is in a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a multilayer body 2 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the multilayer body 2 so as to be spaced apart from each other.

[0064] exist Figure 1In FIG. 1 , arrow T indicates the height direction of the multilayer ceramic capacitor 1 and the multilayer body 2. The height direction T is also the thickness direction and the stacking direction of the multilayer ceramic capacitor 1 and the multilayer body 2. Figure 1 In FIG. 1 , arrow L indicates the longitudinal direction of the multilayer ceramic capacitor 1 and the multilayer body 2, which is perpendicular to the height direction T. Figure 1 In FIG. 1 , arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 2 , which is perpendicular to the height direction T and the length direction L. The pair of external electrodes 40 are respectively arranged at one end and the other end of the laminate 2 in the length direction L.

[0065] Figure 2 The section shown is called the LT section. Figure 3 The cross section shown is called the WT cross section. Figure 4 The cross-section shown and Figure 5 The cross section shown is called the LW cross section.

[0066] (Laminated body)

[0067] The two surfaces of the laminate 2 that are opposite to each other in the height direction T are referred to as the first main surface 3 and the second main surface 4. The two surfaces of the laminate that are opposite to each other in the length direction L that is perpendicular to the height direction T are referred to as the first end surface 7 and the second end surface 8. The two surfaces of the laminate 2 that are opposite to each other in the width direction W that is perpendicular to the height direction T and the length direction L are referred to as the first side surface 5 and the second side surface 6.

[0068] like Figure 1 As shown, the shape of the laminate 2 is a substantially rectangular parallelepiped. The length of the laminate 2 in the longitudinal direction L may not be longer than the length in the width direction W. The corners and ridges of the laminate 2 are preferably rounded. A corner is where three sides of the laminate intersect. A ridge is where two sides of the laminate intersect. Part or all of the surface of the laminate 2 may also have a concave-convex shape.

[0069] The size of the laminate 2 is not limited. The preferred length of the laminate 2 in the longitudinal direction L is 0.2 mm to 6 mm. The preferred length of the laminate 2 in the height direction T is 0.05 mm to 5 mm. The preferred length of the laminate 2 in the width direction W is 0.1 mm to 5 mm.

[0070] (Division in the height direction)

[0071] like Figure 2 as well as Figure 3As shown, the laminate 2 is divided into an inner layer portion 10 and a main surface side outer layer portion 11 in the height direction T. The main surface side outer layer portion 11 includes a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13. The first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 are located so as to sandwich the inner layer portion 10 in the height direction T. In other words, the laminate 2 is divided into the first main surface side outer layer portion 12, the inner layer portion 10, and the second main surface side outer layer portion 13.

[0072] (Dielectric layer)

[0073] The inner layer portion 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the height direction T. The inner layer portion 10 includes the internal electrode layer 30 located closest to the first principal surface 3 in the height direction T to the internal electrode layer 30 located closest to the second principal surface 4. In the inner layer portion 10, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layers 20 interposed therebetween. The inner layer portion 10 is the portion that generates electrostatic capacitance and essentially functions as a capacitor. The dielectric layers 20 included in the inner layer portion 10 are referred to as inner dielectric layers 21. The dielectric layers 20 included in the outer layer portion 12 on the first principal surface side and the dielectric layers 20 included in the outer layer portion 13 on the second principal surface side are referred to as outer dielectric layers 22.

[0074] The plurality of dielectric layers 20 are formed from a dielectric material. Examples of dielectric materials include dielectric ceramics containing components such as barium titanate, calcium titanate, strontium titanate, or calcium zirconate. Alternatively, the dielectric material may be a material containing these main components with minor components such as manganese compounds, iron compounds, copper compounds, cobalt compounds, and nickel compounds added thereto. A preferred dielectric material is one containing barium titanate as a main component.

[0075] The preferred thickness of dielectric layer 20 is 0.2 μm to 10 μm. The preferred number of laminated dielectric layers 20 is 15 to 1200. The number of dielectric layers 20 is the sum of the number of inner dielectric layers 21 and the number of outer dielectric layers 22.

[0076] (Internal electrode layer)

[0077] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the height direction T with the dielectric layer 20 interposed therebetween. The first internal electrode layers 31 extend toward the first end surface 7, and the second internal electrode layers 32 extend toward the second end surface 8.

[0078] like Figure 4As shown, the first internal electrode layer 31 is divided into a first opposing portion 33 and a first lead portion 35. The first opposing portion 33 is a portion that faces the second internal electrode layer 32 with the dielectric layer 20 interposed therebetween. The first lead portion 35 is a portion that extends from the first opposing portion 33 toward the first end surface 7. The first lead portion 35 is exposed at the first end surface 7.

[0079] like Figure 5 As shown, the second internal electrode layer 32 is divided into a second opposing portion 34 and a second lead portion 36. The second opposing portion 34 is a portion that faces the first internal electrode layer 31 with the dielectric layer 20 interposed therebetween. The second lead portion 36 is a portion that extends from the second opposing portion 34 toward the second end surface 8. The second lead portion 36 is exposed at the second end surface 8.

[0080] In the multilayer ceramic capacitor 1 , the first opposing portion 33 and the second opposing portion 34 face each other via the dielectric layer 20 , thereby forming capacitance. As a result, the multilayer ceramic capacitor 1 exhibits capacitor characteristics.

[0081] The shapes of the first opposing portion 33 and the second opposing portion 34 are not limited. Preferred shapes for the first opposing portion 33 and the second opposing portion 34 are rectangular. Similarly, the shapes of the first lead portion 35 and the second lead portion 36 are not limited. Preferred shapes for the first lead portion 35 and the second lead portion 36 are rectangular. In the aforementioned rectangular shape, the corners of the rectangle may be rounded. The corners of the rectangle may also be inclined.

[0082] The length of the first opposing portion 33 in the width direction W and the length of the first lead portion 35 in the width direction W may be the same. The length of the first opposing portion 33 in the width direction W and the length of the first lead portion 35 in the width direction W may be shorter. The length of the second opposing portion 34 in the width direction W and the length of the second lead portion 36 in the width direction W may be the same. The length of the second opposing portion 34 in the width direction W and the length of the second lead portion 36 in the width direction W may be shorter.

[0083] Examples of materials for the first and second internal electrode layers 31, 32 include metals such as nickel, copper, silver, palladium, and gold, and conductive materials such as alloys containing at least one of these metals. When alloys are used, examples of materials for the first and second internal electrode layers 31, 32 include alloys of silver and palladium.

[0084] The preferred thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is 0.2 μm to 2.0 μm. The preferred total number of first internal electrode layers 31 and second internal electrode layers 32 is 15 to 1000.

[0085] (Main surface side outer layer)

[0086] like Figure 2 as well as Figure 3 As shown, the portion comprising the aggregate of the plurality of dielectric layers 20 located between the first principal surface 3 and the internal electrode layer 30 closest to the first principal surface 3 is referred to as the first principal surface-side outer layer portion 12. The first principal surface-side outer layer portion 12 is located on the first principal surface 3 side of the laminate 2. The portion comprising the aggregate of the plurality of dielectric layers 20 located between the second principal surface 4 and the internal electrode layer 30 closest to the second principal surface 4 is referred to as the second principal surface-side outer layer portion 13. The second principal surface-side outer layer portion 13 is located on the second principal surface 4 side of the laminate 2. The dielectric layers 20 used in both the first principal surface-side outer layer portion 12 and the second principal surface-side outer layer portion 13 can be the same dielectric layers as the dielectric layers 20 used in the inner layer portion 10. The material of the inner dielectric layer 21 and the material of the outer dielectric layer 22 can be the same.

[0087] (Electrode facing portion)

[0088] The portion where the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 face each other is referred to as an electrode opposing portion 14. The electrode opposing portion 14 is a portion of the inner layer portion 10. Figure 4 as well as Figure 5 , the range of the electrode opposing portion 14 in the width direction W and the length direction L is shown. The electrode opposing portion 14 is also referred to as a capacitor effective portion.

[0089] (Division in the width direction W)

[0090] The laminate 2 is divided into a first side outer layer portion 15, an electrode opposing portion 14, and a second side outer layer portion 16 in the width direction W. The first side outer layer portion 15 is a portion including the dielectric layer 20 located between the electrode opposing portion 14 and the first side 5. The second side outer layer portion 16 is a portion including the dielectric layer 20 located between the electrode opposing portion 14 and the second side 6. Figure 3 、 Figure 4 as well as Figure 5 , the ranges of the first side outer layer portion 15, the electrode opposing portion 14, and the second side outer layer portion 16 in the width direction W are shown. The first side outer layer portion 15 and the second side outer layer portion 16 are referred to as a W interval or a side interval.

[0091] (Division in the length direction L)

[0092] The stack 2 is divided into a first end face side outer layer portion 17, an electrode opposing portion 14, and a second end face side outer layer portion 18 in the longitudinal direction L. The first end face side outer layer portion 17 is a portion including the dielectric layer 20 and the first lead portion 35 located between the electrode opposing portion 14 and the first end face 7. The first end face side outer layer portion 17 is a collection of the portions of the multilayer dielectric layer 20 on the first end face 7 side and the multilayer first lead portion 35. The second end face side outer layer portion 18 is a portion including the dielectric layer 20 and the second lead portion 36 located between the electrode opposing portion 14 and the second end face 8. The second end face side outer layer portion 18 is a collection of the portions of the multilayer dielectric layer 20 on the second end face 8 side and the multilayer second lead portion 36. Figure 2 、 Figure 4 as well as Figure 5 , the ranges of the first end surface side outer layer portion 17, the electrode opposing portion 14, and the second end surface side outer layer portion 18 in the longitudinal direction L are shown. The first end surface side outer layer portion 17 and the second end surface side outer layer portion 18 are referred to as an L interval or an end interval.

[0093] (External electrode)

[0094] The external electrodes 40 include a first external electrode 41 and a second external electrode 42. The first external electrode 41 is disposed on the first end face 7 side of the stacked body 2. The second external electrode 42 is disposed on the second end face 8 side of the stacked body 2.

[0095] The first external electrode 41 and the second external electrode 42 have the same basic structure and have shapes that are substantially plane-symmetrical with respect to a WT cross section at the center in the longitudinal direction L of the multilayer ceramic capacitor 1 .

[0096] The first external electrode 41 is disposed on the first end surface 7. The first external electrode 41 contacts the first lead portion 35 of each of the plurality of first internal electrode layers 31 exposed on the first end surface 7. The first external electrode 41 is electrically connected to the plurality of first internal electrode layers 31. The first external electrode 41 may also be disposed on a portion of the first principal surface 3, a portion of the second principal surface 4, a portion of the first side surface 5, and a portion of the second side surface 6. In this embodiment, the first external electrode 41 is formed to extend from the first end surface 7 to a portion of the first principal surface 3, a portion of the second principal surface 4, a portion of the first side surface 5, and a portion of the second side surface 6.

[0097] The second external electrode 42 is disposed on the second end surface 8. The second external electrode 42 contacts the second lead portion 36 of each of the plurality of second internal electrode layers 32 exposed on the second end surface 8. The second external electrode 42 is electrically connected to the plurality of second internal electrode layers 32. The second external electrode 42 may also be disposed on a portion of the first principal surface 3, a portion of the second principal surface 4, a portion of the first side surface 5, and a portion of the second side surface 6. In this embodiment, the second external electrode 42 is formed so as to extend from the second end surface 8 to a portion of the first principal surface 3, a portion of the second principal surface 4, a portion of the first side surface 5, and a portion of the second side surface 6.

[0098] Within the laminate 2, the first opposing portion 33 of the first internal electrode layer 31 and the second opposing portion 34 of the second internal electrode layer 32 oppose each other via the dielectric layer 20, thereby forming a capacitor. Consequently, capacitor characteristics are exhibited between the first external electrode 41 connected to the first internal electrode layer 31 and the second external electrode 42 connected to the second internal electrode layer 32.

[0099] (Base electrode layer)

[0100] like Figure 2 、 Figure 4 as well as Figure 5 As shown, the first external electrode 41 includes a first foundation electrode layer 51 and a first plating layer 71. The first plating layer 71 is disposed on the first foundation electrode layer 51. The second external electrode 42 includes a second foundation electrode layer 52 and a second plating layer 72. The second plating layer 72 is disposed on the second foundation electrode layer 52.

[0101] The first foundation electrode layer 51 is disposed on the first end surface 7. The first foundation electrode layer 51 is in contact with the first lead portion 35 of each of the plurality of first internal electrode layers 31 exposed on the first end surface 7. The first foundation electrode layer 51 is formed so as to extend from the first end surface 7 to a portion of the first principal surface 3, a portion of the second principal surface 4, a portion of the first side surface 5, and a portion of the second side surface 6.

[0102] The second foundation electrode layer 52 is disposed on the second end surface 8. The second foundation electrode layer 52 is in contact with the second lead portion 36 of each of the plurality of second internal electrode layers 32 exposed on the second end surface 8. The second foundation electrode layer 52 is formed so as to extend from the second end surface 8 to a portion of the first principal surface 3, a portion of the second principal surface 4, a portion of the first side surface 5, and a portion of the second side surface 6.

[0103] The first base electrode layer 51 and the second base electrode layer 52 are sintered layers. The sintered layers preferably contain a metal component. In addition to the metal component, the sintered layers preferably also contain at least one of a glass component and a ceramic component. The metal component, for example, includes at least one selected from copper, nickel, silver, palladium, an alloy of silver and palladium, gold, etc. The glass component, for example, includes at least one selected from boron, silicon, barium, magnesium, aluminum, lithium, etc. The ceramic component can be the same type of ceramic material as the dielectric layer 20. The ceramic component can also be a different type of ceramic material from the dielectric layer 20. The ceramic component, for example, includes at least one selected from barium titanate, calcium titanate, a mixed crystal material in which a portion of the barium in barium titanate is replaced with calcium, strontium titanate, calcium zirconate, etc.

[0104] An example of a sintered layer is a layer formed by applying a conductive paste containing glass and metal to a laminate and sintering it. The sintered layer is formed by simultaneously sintering a pre-sintered laminated sheet containing multiple internal electrode layers and multiple dielectric layers, which is the raw material of the laminate, and the conductive paste applied to the laminated sheet. Alternatively, the sintered layer is formed by sintering the laminated sheet to obtain a laminate, and then applying a conductive paste to the laminate and sintering it. In the case where the conductive paste is sintered after the laminate is obtained, the sintered layer is preferably formed by sintering a conductive paste to which a ceramic material has been added instead of the glass component. When a conductive paste to which a ceramic material has been added is used, the added ceramic material is preferably a ceramic material of the same type as the dielectric layer. The sintered layer can also be multilayered.

[0105] As an example of a preferred thickness of the first foundation electrode layer 51 in the longitudinal direction L on the first end face 7 , the central portion in the height direction T and the width direction W of the first foundation electrode layer 51 is approximately 10 μm to 200 μm.

[0106] As an example of a preferred thickness of the second foundation electrode layer 52 in the longitudinal direction L on the second end surface 8 , the central portion in the height direction T and the width direction W of the second foundation electrode layer 52 is approximately 10 μm to 200 μm.

[0107] In the case where the first base electrode layer 51 is also provided on a portion of at least one of the first main surface 3 or the second main surface 4, as an example of a preferred thickness in the height direction T of the first base electrode layer 51 provided in the portion, the central portion in the length direction L and the width direction W of the first base electrode layer 51 provided in the portion is greater than 3 μm and less than 40 μm.

[0108] In the case where the first base electrode layer 51 is also provided on a portion of at least one surface of the first side surface 5 or the second side surface 6, as an example of a preferred thickness in the width direction W of the first base electrode layer 51 provided in the portion, the central portion in the length direction L and the height direction T of the first base electrode layer 51 provided in the portion is greater than 3 μm and less than 40 μm.

[0109] In the case where the second base electrode layer 52 is also provided on a portion of at least one of the first main surface 3 or the second main surface 4, as an example of a preferred thickness in the height direction T of the second base electrode layer 52 provided in the portion, the central portion in the length direction L and the width direction W of the second base electrode layer 52 provided in the portion is greater than 3 μm and less than 40 μm.

[0110] In the case where the second base electrode layer 52 is also provided on a portion of at least one surface of the first side surface 5 or the second side surface 6, as an example of a preferred thickness in the width direction W of the second base electrode layer 52 provided in the portion, the central portion in the length direction L and the height direction T of the second base electrode layer 52 provided in the portion is greater than 3 μm and less than 40 μm.

[0111] The first plating layer 71 is arranged to cover the first foundation electrode layer 51 . The second plating layer 72 is arranged to cover the second foundation electrode layer 52 .

[0112] The first plating layer 71 and the second plating layer 72 may include, for example, at least one selected from copper, nickel, tin, silver, palladium, an alloy of silver and palladium, gold, and the like. The first plating layer 71 and the second plating layer 72 may each be formed of multiple layers. A preferred structure of the first plating layer 71 and the second plating layer 72 is a two-layer structure in which a tin plating layer is formed on a nickel plating layer.

[0113] The first plating layer 71 is arranged to cover the first base electrode layer 51. In this embodiment, the first plating layer 71 includes a first nickel plating layer 73 and a first tin plating layer 75. The first tin plating layer 75 is located on the first nickel plating layer 73.

[0114] The second plating layer 72 is arranged to cover the second base electrode layer 52. In this embodiment, the second plating layer 72 includes a second nickel plating layer 74 and a second tin plating layer 76. The second tin plating layer 76 is located on the second nickel plating layer 74.

[0115] The nickel plating layer prevents the first and second base electrode layers 51 and 52 from being corroded by solder when mounting the multilayer ceramic capacitor 1. The tin plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. The tin plating layer facilitates mounting the multilayer ceramic capacitor 1. The first nickel plating layer 73, the first tin plating layer 75, the second nickel plating layer 74, and the second tin plating layer 76 each preferably have a thickness of 2 μm or more and 10 μm or less.

[0116] The external electrode 40 may also include a conductive resin layer containing conductive particles and a thermosetting resin. When the external electrode 40 includes a conductive resin layer, the conductive resin layer may be arranged to cover the sintered layer. When the conductive resin layer is arranged to cover the sintered layer, the conductive resin layer is arranged between the sintered layer and the plated layer. The sintered layer corresponds to the first base electrode layer 51 and the second base electrode layer 52. The plated layer corresponds to the first plated layer 71 and the second plated layer 72. The conductive resin layer may completely cover the sintered layer. Alternatively, the conductive resin layer may cover a portion of the sintered layer.

[0117] A conductive resin layer composed of a thermosetting resin is more flexible than a conductive layer composed of a plated film or a fired product of a conductive paste. Therefore, when a multilayer ceramic capacitor is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer. Consequently, the conductive resin layer suppresses cracks in the multilayer ceramic capacitor.

[0118] Examples of metals that constitute the conductive particles include silver, copper, nickel, tin, bismuth, or alloys containing at least two of these metals. The conductive particles preferably contain silver. An example of conductive particles is silver metal powder. Silver has the lowest resistivity among metals. Silver is suitable for electrode materials. Silver is a precious metal. Silver is not easily oxidized. Silver has high weather resistance. For these reasons, silver metal powder is suitable as the conductive particles.

[0119] The conductive particles may also be metal powder coated with silver. When using conductive particles coated with silver, the metal powder is preferably copper, nickel, tin, bismuth, or an alloy thereof. To ensure the properties of silver while reducing the cost of the base metal, silver-coated metal powder is preferably used.

[0120] The conductive particles may also be copper or nickel particles subjected to an oxidation prevention treatment. Alternatively, the conductive particles may be metal powders coated with tin, nickel, or copper. When using metal powders coated with tin, nickel, or copper, the metal powders are preferably silver, copper, nickel, tin, bismuth, or alloy powders containing at least two of these metals.

[0121] The shape of the conductive particles is not limited. Examples of the conductive particle shape include spherical and flat shapes. It is preferable to use a mixture of spherical metal powder and flat metal powder.

[0122] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. The plurality of conductive particles are in contact with each other, thereby forming a current path inside the conductive resin layer.

[0123] Examples of the resin constituting the conductive resin layer may include at least one selected from various well-known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is particularly suitable. Epoxy resin has excellent heat resistance, moisture resistance, and adhesion. The resin of the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may also be various well-known compounds such as phenols, amines, acid anhydrides, imidazoles, active esters, and amide-imides.

[0124] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest portion of the conductive resin layer is preferably 10 μm to 150 μm.

[0125] The above is the basic structure of the multilayer ceramic capacitor 1. The preferred length of the multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 40, in the longitudinal direction L is 0.2 mm to 6 mm. The preferred length of the multilayer ceramic capacitor 1 in the height direction T is 0.05 mm to 5 mm. The preferred length of the multilayer ceramic capacitor 1 in the width direction W is 0.1 mm to 5 mm.

[0126] (Segregation and segregation areas of silicon and magnesium)

[0127] In the multilayer ceramic capacitor 1 of this embodiment, there is a portion where silicon or magnesium is segregated in the laminate 2. This portion is referred to as a segregation portion 80. The segregation portion 80 is not uniform in the laminate 2 but is uneven. Figure 6 Provide explanation. Figure 6 yes Figure 1 However, in Figure 6 In the same way Figure 1 101-101 cross-sectional view Figure 2 In contrast, each part is omitted. Figure 6 In FIG, the segregation portion 80 is emphasized.

[0128] (Outermost internal electrode layer)

[0129] The internal electrode layer 30 closest to the main surface side outer layer portion 11 (outer layer portion) among the internal electrode layers 30 is referred to as the outermost internal electrode layer 301. The distribution of the segregation portion 80 near the outermost internal electrode layer 301 will be described. Figure 6 , two outermost internal electrode layers 301 are shown: the outermost internal electrode layer 301 near the first principal surface-side outer layer portion 12 and the outermost internal electrode layer 301 near the second principal surface-side outer layer portion 13. In the following description, the outermost internal electrode layer 301 near the first principal surface-side outer layer portion 12 is used as an example to describe the outermost internal electrode layer 301. The following description also applies to the other outermost internal electrode layer 301.

[0130] (Outer and inner sides of the outermost internal electrode layer)

[0131] In the multilayer ceramic capacitor 1 of the present embodiment, the amount of silicon and magnesium segregated on the outer layer side 711 of the outermost internal electrode layer 301 is greater than the amount of silicon and magnesium segregated on the inner layer side 712 of the outermost internal electrode layer 301 .

[0132] Here, the outer layer side 711 of the outermost internal electrode layer 301 refers to the side of the outermost internal electrode layer 301 that is in contact with the main surface side outer layer portion 11 , and the inner layer side 712 of the outermost internal electrode layer 301 refers to the side opposite to the outer layer side 711 .

[0133] (Outer and inner surfaces of the outermost internal electrode layer)

[0134] Of the two surfaces of the outermost internal electrode layer 301 parallel to the longitudinal direction L, the surface on the outer layer side 711 is the outer layer surface 311 . Of the two surfaces of the outermost internal electrode layer 301 parallel to the longitudinal direction L, the surface on the inner layer side 712 is the inner layer surface 312 .

[0135] The amount of silicon and magnesium segregation on the outer layer side 711 of the outermost internal electrode layer 301 refers to the amount of the segregated portion 80 protruding from the outer surface layer 311 toward the outer layer side 711. On the other hand, the amount of silicon and magnesium segregation on the inner layer side 712 of the outermost internal electrode layer 301 refers to the amount of the segregated portion 80 protruding from the inner surface layer 312 toward the inner layer side 712. In other words, the amount of silicon and magnesium segregation includes at least a portion of the segregated portion 80 that is in contact with the outermost internal electrode layer 301.

[0136] like Figure 6 As shown, in the multilayer ceramic capacitor 1 of this embodiment, the amount of silicon and magnesium segregated on the outer layer side 711 of the outermost internal electrode layer 301 is greater than the amount of silicon and magnesium segregated on the inner layer side 712 of the outermost internal electrode layer 301 .

[0137] (Evaluation of segregation amount)

[0138] The amount of segregation can be evaluated by observing the cross section of the laminate 2. Figure 7 as well as Figure 8 Provide explanation. Figure 7 as well as Figure 8 are equivalent to Figure 6 A portion of the enclosing box 110 is shown enlarged in the figure. Figure 7 as well as Figure 8 All are reflection electron microscope images. Figure 7 The black portion in the figure is the segregation portion 80. The amount of segregation can be evaluated based on the area of ​​the segregation portion 80.

[0139] like Figure 8 As shown, the amount of silicon and magnesium segregated on the outer side 711 of the outermost internal electrode layer 301 is greater than the amount of silicon and magnesium segregated on the inner side 712 of the outermost internal electrode layer 301. The segregated portion 80 will be described in more detail below.

[0140] (Area where the outermost internal electrode layer exists)

[0141] In the outermost internal electrode layer 301, the region where the material for the internal electrode layer 30 constituting the outermost internal electrode layer 301 exists is referred to as the region 320 where the outermost internal electrode layer 301 exists. The region 320 where the outermost internal electrode layer 301 exists corresponds to Figure 6 The area sandwiched between the outer layer 311 and the inner layer 312 in the LT cross section is shown.

[0142] (Segregation area of ​​silicon and magnesium)

[0143] The region formed by the entire segregation portion 80 existing in contact with the outermost internal electrode layer 301 is referred to as a silicon and magnesium segregation region 330. Figures 6 to 8 , a reference numeral is given to a portion of the segregation region 330. The segregation region 330 is not necessarily continuous in the longitudinal direction L.

[0144] (Region 1)

[0145] The combined area of ​​the region 320 where the outermost internal electrode layer 301 exists and the region 330 where silicon and magnesium are segregated is referred to as a first region 340 .

[0146] (Line edge roughness)

[0147] The line edge roughness of the first region 340 will be described. Line edge roughness refers to the positional variation of the line edge. In the multilayer ceramic capacitor 1 of this embodiment, the line edge roughness of the end portion on the outer layer side 711 of the first region 340 is greater than the line edge roughness of the end portion on the inner layer side 712 of the first region 340.

[0148] Reference Figure 9 Line edge roughness is explained below. Line edge roughness is calculated in the following two steps.

[0149] (1) The coordinates of the edge points of the measurement line are determined, and an approximate straight line is calculated based on these coordinates. The edge points are set at intervals of 16 nm in the direction perpendicular to the thickness direction (horizontal direction).

[0150] (2) The deviation between the calculated approximate straight line and the edge point is calculated as the line edge roughness.

[0151] Figure 9 is a diagram for explaining the calculation method of line edge roughness. Figure 9 2 shows two measurement lines, a measurement line 501 and a measurement line 502. However, the calculation method of the approximate straight line and the calculation method of the line edge roughness are the same for the measurement line 501 and the measurement line 502.

[0152] Figure 9 Figure 601 on the left shows a method for finding approximate lines. Solid circles 511 through 515 on measurement line 501 and solid circles 521 through 525 on measurement line 502 represent the edge points of the measurement lines. To calculate line edge roughness, approximate lines are first found for the edge points of the measurement lines. The approximate lines found are approximate lines 531 and 532.

[0153] Next, as indicated by arrow 600 , the process proceeds to calculation of line edge roughness based on the obtained approximate straight line 531 and the approximate straight line 532 . Figure 9 Figure 602 on the right shows a method for calculating edge roughness. Edge roughness refers to the deviation of each edge point from an approximate straight line. Solid circles 516 through 519 on measurement line 501 and solid circles 526 through 529 on measurement line 502 represent the edge points of the measurement line. For example, the deviation between edge point 516 on measurement line 501 and approximate straight line 531 is the amount indicated by arrow 541. Hereinafter, the amount indicated by arrow 541 will be referred to as edge roughness 541.

[0154] Next, a specific method for calculating line edge roughness will be described. For measurement line 501, the edge roughness 541 of edge point 516, the edge roughness 542 of edge point 517, the edge roughness 543 of edge point 518, and the edge roughness of edge point 519 are averaged. This average value is defined as the line edge roughness. Furthermore, edge point 519 lies on approximate straight line 531. Therefore, the edge roughness of edge point 519 is 0. For measurement line 502, the line edge roughness can be calculated in the same manner as for measurement line 501.

[0155] In the multilayer ceramic capacitor 1 of the present embodiment, the line edge roughness was determined according to the following standards.

[0156] Image analysis / measurement software: WinROOF (trade name)

[0157] Measurement magnification: 10000 times

[0158] Image: Reflected electron image

[0159] Field of view: average of 5 fields of view

[0160] Specifically, under the aforementioned specifications, the internal electrode layer 30 within the field of view is divided into 624 sections along the longitudinal direction L. The average edge roughness of each section is then defined as the line edge roughness. In other words, the average edge roughness of n = 624 is defined as the line edge roughness.

[0161] The line edge roughness of each of the five viewing fields is calculated, and the average value of the five calculated line edge roughnesses is set as the line edge roughness of the present disclosure.

[0162] (Line edge roughness on the outer layer side and line edge roughness on the inner layer side)

[0163] In the multilayer ceramic capacitor 1 of the present embodiment, the line edge roughness (LER) A on the outer layer side 711 of the first region 340 is greater than the line edge roughness (LER) B on the inner layer side 712 of the first region 340 .

[0164] exist Figure 8 , the contour line of the outer layer side 711 of the first region 340 is shown as the first region outer layer line 341. Similarly, the contour line of the inner layer side 712 of the first region 340 is shown as the first region inner layer line 342. The line edge roughness A of the first region outer layer line 341 is greater than the line edge roughness B of the first region inner layer line 342.

[0165] The multilayer ceramic capacitor 1 of this embodiment, with the above-described structure, can provide a multilayer ceramic capacitor 1 that suppresses delamination when mechanical stress is applied. In particular, a multilayer ceramic capacitor 1 can provide a multilayer ceramic capacitor 1 that suppresses delamination between the inner layer portion 10 and the main surface-side outer layer portion 11.

[0166] According to the above-described structure, the line edge roughness (ie, surface irregularities) increases only on the outer layer side 711 of the outermost internal electrode layer 301 .

[0167] Therefore, the mechanical bonding between the inner layer portion 10 and the main surface side outer layer portion 13 is enhanced, and layer separation can be suppressed.

[0168] Furthermore, according to the above-described structure, the inner layer side 712 of the outermost internal electrode layer 301 is smooth. Therefore, the reliability of the multilayer ceramic capacitor 1 is less likely to decrease.

[0169] (Thickness and line edge roughness of internal electrode layers)

[0170] A more preferable range of line edge roughness will be described. Figure 6 The thickness 701 of the internal electrode layer 30 is shown, and its average thickness is denoted as C. The value obtained by dividing the line edge roughness A of the outer layer side 711 of the first region 340 described above by the average thickness C of the internal electrode layer 30 (i.e., the ratio (A / C)) is denoted as D. The value D is preferably not less than 0.093 and not more than 0.341.

[0171] When the value D is less than 0.093, the outer layer side 711 of the outermost internal electrode layer 301 has insufficient irregularities relative to the thickness of the internal electrode layer 30. Therefore, layer separation may be insufficiently suppressed.

[0172] On the other hand, when the value D exceeds 0.341, the unevenness becomes too large, and the mechanical bonding between the inner layer portion 10 and the main surface side outer layer portion 13 is weakened. Therefore, the suppression of delamination may become insufficient.

[0173] (Line edge roughness on the outer layer side and line edge roughness on the inner layer side)

[0174] The ratio (A / B) of the line edge roughness A on the outer side 711 of the first region 340 to the line edge roughness B on the inner side 712 of the first region 340 described above is set to value E. The value E is preferably 1.23 or more and 6.70 or less.

[0175] By setting the values ​​D and E within the above ranges, the line edge roughness can be increased only on the outer layer side 711 of the outermost internal electrode layer 301, thereby increasing the unevenness. This further strengthens the mechanical bond between the inner layer portion 10 and the main surface-side outer layer portion 11. Consequently, delamination can be further suppressed.

[0176] (Area ratio of outer layer side to inner layer side)

[0177] The areas of the outer layer side 711 and the inner layer side 712 in the first region 340 will be described. Figure 8 7 shows an area 721 of the outer side 711 of the first region 340 and an area 722 of the inner side 712 of the first region 340. The ratio of the area 721 of the outer side 711 of the first region 340 to the area 722 of the inner side 712 of the first region 340 is set to F. The value F is preferably greater than or equal to 1.1 and less than or equal to 3.30.

[0178] With this structure, only the outer layer side 711 of the outermost internal electrode layer 301 has increased line-edge roughness, and the unevenness is also increased. This further strengthens the mechanical bond between the inner layer portion 10 and the main surface-side outer layer portion 11. As a result, delamination can be significantly suppressed.

[0179] Furthermore, a value F exceeding 1 indicates that the segregation amounts of silicon and magnesium on the outer layer side 711 of the outermost internal electrode layer 301 are greater than the segregation amounts of silicon and magnesium on the inner layer side 712 of the outermost internal electrode layer 301 .

[0180] (Area measurement method)

[0181] Reference Figure 7 as well as Figure 8 , a method for measuring the area in the first region 340 is described.

[0182] (1) First, outer wires are drawn out from both side ends in the height direction T of a region where a metal material (eg, nickel) constituting the internal electrode layer 30 exists. Figure 7 as well as Figure 8 The lines 401 and 403 shown are outer lines.

[0183] (2) Next, a center line is drawn at the center in the height direction T between the line 401 and the line 403 . Figure 7 as well as Figure 8 The line 402 shown is a center line. The center line 402 is defined as the center in the height direction T of the internal electrode layer 30 .

[0184] (3) Next, the areas on both sides of the center line 402 in the first region 340 are calculated. The area of ​​the portion enclosed by the center line 402 and the outer side line 341 of the first region 340 is the area 721 of the outer side 711 of the first region 340. The area of ​​the portion enclosed by the center line 402 and the inner side line 342 of the first region 340 is the area 722 of the inner side 712 of the first region 340.

[0185] (4) Next, the ratio of the obtained area 721 to the area 722 is calculated.

[0186] In addition, when calculating the area, magnesium segregation and magnesium present together with nickel were also included in the area measurement.

[0187] (Examples and Comparative Examples)

[0188] Reference Figure 10 The evaluation results of Examples and Comparative Examples will be described. Figure 10 1 and 2 are graphs showing evaluation results of Examples and Comparative Examples. First, the samples used for evaluation will be described.

[0189] (Sample)

[0190] Dimensions of the multilayer ceramic capacitor: Dimensions in the longitudinal direction L × dimensions in the width direction W × dimensions in the height direction T = 3.15 mm × 1.65 mm × 1.65 mm

[0191] Ceramic material: barium titanate

[0192] Electrostatic capacitance: 10μF

[0193] Internal electrode material: Nickel

[0194] Samples with varying wire edge roughness were produced in batches using the manufacturing method described below, adjusting the manufacturing conditions. These samples served as examples 1 to 22 and comparative examples 1 to 3. The samples within each batch were produced under the same manufacturing conditions. For each example and comparative example, three samples (n = 3) were prepared from the same batch for measuring wire edge roughness and internal electrode layer thickness, and 100 samples were prepared for evaluating layer delamination. The average value of the three measurements was used for measuring wire edge roughness and internal electrode layer thickness.

[0195] (Evaluation method for layer peeling)

[0196] The fired laminate was inspected for appearance by mechanical external screening to confirm the presence or absence of separation between the inner layer portion and the outer layer portion (n=100 pieces).

[0197] (Judgment Criteria)

[0198] The determination was made based on the number of peeled pieces per 100 pieces.

[0199] 0 or more and less than 10: ◎

[0200] 11 or more and less than 30: ○

[0201] 31 or more and less than 70: △

[0202] More than 71 and less than 100: ×

[0203] (Evaluation results)

[0204] In such Figure 9 As shown, when the line edge roughness A on the outer layer side of the first region is larger than the line edge roughness B on the inner layer side of the first region, the layer peeling judgment after firing is any of ⊚, ∘, or Δ.

[0205] When the ratio D of the line edge roughness A on the outer layer side of the first region to the average thickness C of the internal electrode layer is greater than 0.093 and less than 0.341, and the ratio E of the line edge roughness A on the outer layer side of the first region to the line edge roughness B on the inner layer side of the first region is greater than 1.23 and less than 6.70, the layer peeling judgment after firing is either ◎ or 0.

[0206] (Method for Manufacturing Multilayer Ceramic Capacitors)

[0207] A method for manufacturing a multilayer ceramic capacitor will be described. Note that the method for manufacturing a multilayer ceramic capacitor is not limited to the following method.

[0208] A dielectric sheet for dielectric layer 20 and a conductive paste for internal electrode layer 30 are prepared. Both the dielectric sheet for dielectric layer 20 and the conductive paste for internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known binders and solvents. An example of a paste made of a conductive material is one in which an organic binder and an organic solvent are added to metal powder.

[0209] Conductive paste for the internal electrode layer 30 is printed on the dielectric sheet using a printing plate designed to form the shape of the internal electrode layer 30. Examples of printing methods include screen printing and gravure printing. This prepares a dielectric sheet with a pattern for the first internal electrode layer 31 and a dielectric sheet with a pattern for the second internal electrode layer 32.

[0210] A predetermined number of dielectric sheets without a pattern of the internal electrode layer 30 printed thereon are stacked to form a portion that will become the first principal surface side outer layer portion 12 on the first principal surface 3 side. Dielectric sheets with a pattern of the first internal electrode layer 31 printed thereon and dielectric sheets with a pattern of the second internal electrode layer 32 printed thereon are then alternately stacked thereon to form a portion that will become the inner layer portion 10. A predetermined number of dielectric sheets without a pattern of the internal electrode layer 30 printed thereon are then stacked to form a portion that will become the second principal surface side outer layer portion 13 on the second principal surface 4 side. This results in a laminated sheet.

[0211] Here, by increasing the concentrations of silicon and magnesium in the dielectric sheet corresponding to the outer layer portion on the main surface side, silicon and magnesium can be selectively segregated on the outer layer side of the outermost internal electrode layer. Furthermore, by adding a magnesium compound having a large particle size to the dielectric sheet corresponding to the outer layer portion on the main surface side, magnesium can also be selectively segregated on the outer layer side of the outermost internal electrode layer.

[0212] Next, the laminated sheets are pressed in the height direction by isostatic pressing or the like, thereby producing a laminated block.

[0213] Next, the stacked block is cut into pieces of a predetermined size to obtain a plurality of stacked small pieces. The stacked small pieces may then be polished by barrel polishing or the like to round off the corners and ridges.

[0214] Next, the stacked small pieces are fired. This firing produces a stacked body. The preferred firing temperature is 900° C. or higher and 1400° C. or lower. The firing temperature can be varied depending on the materials of the dielectric and internal electrode layers.

[0215] A conductive paste, which will become the base electrode layer 50, is applied to both end surfaces of the laminate 2. In this embodiment, the base electrode layer 50 is a sintered layer. The sintered layer can be formed by applying a conductive paste containing a glass component and a metal to the laminate 2 by a method such as dipping, followed by sintering. The sintering temperature is preferably between 700°C and 900°C.

[0216] Alternatively, the pre-fired laminated pieces and the conductive paste applied to the laminated pieces may be fired simultaneously. In this case, the sintered layer is preferably formed by sintering a conductive paste to which a ceramic material has been added in place of the glass component. In this case, the added ceramic material is preferably the same type as that used for dielectric layer 20. In this case, the conductive paste is applied to the pre-fired laminated pieces, and the laminated pieces and the conductive paste applied to the laminated pieces are sintered simultaneously to form a laminate 2 having a sintered layer formed thereon.

[0217] Then, a plating layer is formed on the surface of the base electrode layer 50 consisting of a sintered layer. In the present embodiment, a first plating layer 71 is formed on the surface of the first base electrode layer 51. A second plating layer 72 is formed on the surface of the second base electrode layer 52. In the present embodiment, a nickel plating layer and a tin plating layer are formed as plating layers. When performing the plating process, either electrolytic plating or electroless plating can be adopted. However, with respect to electroless plating, in order to increase the plating deposition speed, it is necessary to perform pretreatment using a catalyst, etc., and therefore there is a disadvantage of complicating the process. Therefore, electrolytic plating is generally preferred. The nickel plating layer and the tin plating layer are formed sequentially, for example, by drum plating.

[0218] When a conductive resin layer is provided, it can also be configured to cover the sintered layer. When a conductive resin layer is provided, a conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer and then heat-treated at a temperature of 250 to 550°C or higher. This heat-cures the thermosetting resin to form the conductive resin layer. The heat treatment atmosphere is preferably an N2 atmosphere. To prevent scattering of the resin and oxidation of the various metal components, the oxygen concentration is preferably below 100 ppm.

[0219] According to the above-described manufacturing steps, the multilayer ceramic capacitor 1 can be manufactured.

[0220] The present invention is not limited to the configuration of the above embodiment, and can be applied with appropriate modifications within the scope of the present invention. Combinations of two or more of the preferred configurations described in the above embodiment also constitute the present invention.

Claims

1. A multilayer ceramic capacitor comprising: A laminate comprising a plurality of laminated dielectric layers and a plurality of laminated internal electrode layers, the laminate comprising a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction, the laminate comprising an inner layer portion and an outer layer portion, the inner layer portion being formed by alternately laminating the dielectric layers and the internal electrode layers, and the outer layer portion being arranged so as to sandwich the inner layer portion from the first main surface side and the second main surface side; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface; in, When the internal electrode layer disposed closest to the outer layer portion is defined as the outermost internal electrode layer, the segregation amounts of silicon and magnesium on the outer layer side of the outermost internal electrode layer are greater than the segregation amounts of silicon and magnesium on the inner layer side of the outermost internal electrode layer. When a region defined by the region where the outermost internal electrode layer exists and the segregation region of silicon and magnesium existing in contact with the outermost internal electrode layer is defined as a first region, The line edge roughness A on the outer layer side of the first region is greater than the line edge roughness B on the inner layer side of the first region.

2. The multilayer ceramic capacitor according to claim 1, wherein If the ratio A / C of the line edge roughness A on the outer layer side of the first region to the average thickness C of the internal electrode layer is set to D, and the ratio A / B of the line edge roughness A on the outer layer side of the first region to the line edge roughness B on the inner layer side of the first region is set to E, then D is 0.093 or more and 0.341 or less, E is 1.23 or more and 6.70 or less.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein: If the ratio of the area of ​​the outer layer side of the first region to the area of ​​the inner layer side of the first region is F, then F is 1.1 or more and 3.30 or less.

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