Multilayer ceramic electronic component

Abstract

A multilayer ceramic capacitor (1), wherein a first external electrode (40A) and a second external electrode (40B) have first grooves (72A3, 72B3) extending in a layer stacking direction (T). In the first grooves (72A3, 72B3), a first base electrode layer (50A) and a second base electrode layer (50B) are directly connected to a first plating layer (70A) and to a second plating layer (70B). One end of each of the first grooves (72A3, 72B3) is open on a first main surface (TS1) side, and the other end of each of the first grooves (72A3, 72B3) terminates within a first end face (LS1) or within a second end face (LS2).

Description

Multilayer ceramic electronic components

[0001] This invention relates to multilayer ceramic electronic components.

[0002] In recent years, multilayer ceramic electronic components, such as multilayer ceramic capacitors, have been required to withstand harsh environments, including flexural stress due to thermal expansion. To address this, a technology using thermosetting conductive resin paste for the external electrodes of multilayer ceramic electronic components has been developed. Patent Document 1 is an example of this type of technology. Patent Document 1 describes a multilayer ceramic capacitor having an external electrode with a layered structure in which an electrode layer coated by dipping and baking a conductive paste, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially laminated.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] In the case of the multilayer ceramic capacitor described in Patent Document 1, the occurrence of cracks in the laminate can be suppressed by sacrificial fracture and stress relaxation due to deformation of the resin layer. On the other hand, a challenge for multilayer ceramic capacitors having such a resin layer is ensuring highly reliable electrical and mechanical connections.

[0005] The present invention aims to provide a multilayer ceramic electronic component that can ensure highly reliable electrical and mechanical bonding while suppressing the occurrence of cracks in the laminate.

[0006] The multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, a first external electrode disposed on the first end surface, and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface side external electrode disposed on the first end surface, and the second external electrode is disposed on the second end surface The first and second end-face external electrodes are provided, and each of the first and second end-face external electrodes comprises an end-face base electrode layer, an end-face conductive resin layer disposed on the end-face base electrode layer, and an end-face plating layer disposed to cover the end-face conductive resin layer, the first and second end-face external electrodes have a first groove extending in the lamination direction, the end-face base electrode layer and the end-face plating layer are directly connected in the first groove, one end of the first groove is open to the first main surface, and the other end of the first groove is terminated within the first end face or the second end face.

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can ensure highly reliable electrical and mechanical bonding while suppressing the occurrence of cracks in the laminate.

[0008] This is an external perspective view of a multilayer ceramic capacitor according to the first embodiment of the present invention. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line III-III. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line V-V. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. This is a view of the multilayer ceramic capacitor shown in Figure 2 from the direction of arrow V, and is a side view showing the end face of the ceramic capacitor. This is a cross-sectional view of a multilayer ceramic capacitor according to the second embodiment. This is a schematic diagram showing an example of the configuration of a double-gang multilayer ceramic capacitor. This is a schematic diagram showing an example of the configuration of a triple-gang multilayer ceramic capacitor. This is a schematic diagram showing an example of the configuration of a quadruple-gang multilayer ceramic capacitor.

[0009] (First Embodiment) A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to the first embodiment of the present disclosure will be described with reference to Figures 1 to 6. Figure 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line III-III. Figure 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of Figure 2 along the line IV-IV. Figure 5 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line V-V. Figure 6 is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 2 along the line IV-IV. Note that Figure 2 is a cross-sectional view of the grooves 72A3 and 72B3 (described later), and Figure 3 is a cross-sectional view of a position other than the grooves 72A3 and 72B3 (described later).

[0010] The multilayer ceramic capacitor 1 comprises a laminate 10 and an external electrode 40.

[0011] Figures 1 to 4 show the XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T, which is the height direction of the multilayer ceramic capacitor 1 and the laminate 10, corresponds to the Z direction. Here, the cross-sections shown in Figures 2 and 3 are also called LT cross-sections. The cross-section shown in Figure 4 is also called WT cross-sections. The cross-sections shown in Figures 5 and 6 are also called LW cross-sections.

[0012] As shown in Figures 1 to 6, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W. The mounting surface of the multilayer ceramic capacitor 1 is the first main surface TS1. The mounting surface is the surface that faces the wiring board when the multilayer ceramic capacitor 1 is mounted on a wiring board or the like.

[0013] As shown in Figure 1, the laminate 10 has a substantially rectangular parallelepiped shape. The length L dimension of the laminate 10 is not necessarily longer than the width W dimension. It is preferable that the corners and edges of the laminate 10 are rounded. The corners are the parts where three faces of the laminate intersect, and the edges are the parts where two faces of the laminate intersect. Some or all of the surfaces constituting the laminate 10 may have irregularities or bumps formed on them.

[0014] The dimensions of the laminate 10 are not particularly limited, but if the dimension in the length direction L of the laminate 10 is denoted as dimension L, then it is preferable that dimension L is 0.2 mm or more and 10 mm or less. If the dimension in the stacking direction T of the laminate 10 is denoted as dimension T, then it is preferable that dimension T is 0.1 mm or more and 10 mm or less. If the dimension in the width direction W of the laminate 10 is denoted as dimension W, then it is preferable that dimension W is 0.1 mm or more and 10 mm or less.

[0015] As shown in Figures 2 and 3, the laminate 10 has an inner layer 11 and a first main surface-side outer layer 12A and a second main surface-side outer layer 12B, which are arranged to sandwich the inner layer 11 in the lamination direction T.

[0016] The inner layer 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The inner layer 11 includes the internal electrode layer 30 located on the first main surface TS1 side to the internal electrode layer 30 located on the second main surface TS2 side in the stacking direction T. In the inner layer 11, the plurality of internal electrode layers 30 are arranged facing each other via the dielectric layers 20. The inner layer 11 is the part that generates capacitance and functions substantially as a capacitor.

[0017] Multiple dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, BaTiO ３ CaTiO ３ SrTiO ３ , or CaZrO ３ The dielectric ceramic may contain components such as those mentioned above. Furthermore, the dielectric material may be obtained by adding minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds to these main components.

[0018] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of dielectric layers 20 to be stacked is preferably 10 or more and 700 or less. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer portion 11 and the number of dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0019] The plurality of internal electrode layers 30 have a plurality of first internal electrode layers 31 as a plurality of first internal conductor layers and a plurality of second internal electrode layers 32 as a plurality of second internal conductor layers. The plurality of first internal electrode layers 31 are arranged on a plurality of dielectric layers 20. The plurality of second internal electrode layers 32 are arranged on a plurality of dielectric layers 20. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10 via the dielectric layers 20. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20.

[0020] The first internal electrode layer 31 has a first opposing portion 31A that faces the second internal electrode layer 32, and a first leading portion 31B that is drawn out from the first opposing portion 31A to the first end face LS1. The first leading portion 31B is exposed to the first end face LS1.

[0021] The second internal electrode layer 32 has a second opposing portion 32A that faces the first internal electrode layer 31, and a second leading portion 32B that is drawn out from the second opposing portion 32A to the second end face LS2. The second leading portion 32B is exposed to the second end face LS2.

[0022] In this embodiment, capacitance is formed when the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, and the characteristics of a capacitor are exhibited.

[0023] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle.

[0024] The widthwise dimension W of the first opposing portion 31A and the widthwise dimension W of the first drawer portion 31B may be the same, or one of them may be smaller. The widthwise dimension W of the second opposing portion 32A and the widthwise dimension W of the second drawer portion 32B may be the same, or one of them may be narrower.

[0025] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, Au, or alloys containing at least one of these metals. When using an alloy, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0026] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably 10 or more and 700 or less.

[0027] The first main surface-side outer layer 12A is located on the second main surface TS2 side of the laminate 10. The first main surface-side outer layer 12A is an aggregate of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface-side outer layer 12A may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0028] The second main surface-side outer layer 12B is located on the first main surface TS1 side of the laminate 10. The second main surface-side outer layer 12B is an aggregate of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the second main surface-side outer layer 12B may be the same as the dielectric layers 20 used in the inner layer 11, or they may be dielectric layers made of different materials.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is the portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as part of the inner layer portion 11. Figures 5 and 6 show the width direction W and length direction L of the counter electrode portion 11E. The counter electrode portion 11E is also called the capacitor effective portion.

[0030] The laminate 10 has a side outer layer. The side outer layer has a first side outer layer WG1 and a second side outer layer WG2. The first side outer layer WG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. The second side outer layer WG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. Figures 4 to 6 show the width direction W range of the first side outer layer WG1 and the second side outer layer WG2. The side outer layer is also called a W gap or side gap.

[0031] The laminate 10 has an end-face outer layer. The end-face outer layer has a first end-face outer layer LG1 and a second end-face outer layer LG2. The first end-face outer layer LG1 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the first end face LS1. The second end-face outer layer LG2 is a portion that includes a dielectric layer 20 located between the opposing electrode portion 11E and the second end face LS2. Figures 2, 3, 5, and 6 show the range L in the longitudinal direction of the first end-face outer layer LG1 and the second end-face outer layer LG2. The end-face outer layer is also called an L gap or end gap.

[0032] The external electrode 40 includes a first external electrode 40A positioned on the first end face LS1 side and a second external electrode 40B positioned on the second end face LS2 side.

[0033] The first external electrode 40A is positioned on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed extending from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0034] The second external electrode 40B is positioned on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be positioned on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed extending from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as on a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] As described above, within the laminate 10, capacitance is formed by the opposition of the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 via the dielectric layer 20. Therefore, capacitor characteristics are exhibited between the first external electrode 40A to which the first internal electrode layer 31 is connected and the second external electrode 40B to which the second internal electrode layer 32 is connected.

[0036] The first external electrode 40A includes a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A. The first plating layer 70A includes a first Ni plating layer 71A as an under-plating layer and a first Sn plating layer 72A as an over-plating layer.

[0037] The second external electrode 40B includes a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B. The second plating layer 70B includes a second Ni plating layer 71B as an under-plating layer and a second Sn plating layer 72B as an over-plating layer.

[0038] As shown in Figures 2 to 6, the first Ni plating layer 71A has a first end face Ni plating layer 71A1 and a first side face Ni plating layer 71A2. The first end of the first Ni plating layer 71A refers to the portion of the first Ni plating layer 71A that is on the second end face LS2 side of the first conductive resin layer 60A in the longitudinal direction L.

[0039] As shown in Figures 2 to 6, the second Ni plating layer 71B has a second end face Ni plating layer 71B1 and a second side face Ni plating layer 71B2. The second end of the second Ni plating layer 71B refers to the portion of the second Ni plating layer 71B that is on the first end face LS1 side of the second conductive resin layer 60B in the length direction L.

[0040] Here, the basic configurations of the respective layers constituting the first external electrode 40A and the second external electrode 40B are the same. Also, the first external electrode 40A and the second external electrode 40B are substantially plane-symmetric with respect to the LW cross-section at the center in the length direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to particularly distinguish between the first external electrode 40A and the second external electrode 40B for explanation, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrode 40. Also, when there is no need to particularly distinguish between the first base electrode layer 50A and the second base electrode layer 50B for explanation, the first base electrode layer 50A and the second base electrode layer 50B may be collectively referred to as the base electrode layer 50. Also, when there is no need to particularly distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B for explanation, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60. Also, when there is no need to particularly distinguish between the first plating layer 70A and the second plating layer 70B for explanation, the first plating layer 70A and the second plating layer 70B may be collectively referred to as the plating layer 70. Also, when there is no need to particularly distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B for explanation, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as the Ni plating layer 71. Also, when there is no need to particularly distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B for explanation, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as the Sn plating layer 72.

[0041] The base electrode layer 50 has a first base electrode layer 50A and a second base electrode layer 50B.

[0042] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. Further, the first base electrode layer 50A may also be disposed on a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2. In the present embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0043] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. Further, the second base electrode layer 50B may also be disposed on a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2. In the present embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a part of the first main surface TS1, a part of the second main surface TS2, a part of the first side surface WS1, and a part of the second side surface WS2.

[0044] The first base electrode layer 50A and the second base electrode layer 50B of the present embodiment are baking layers. The baking layer preferably contains either a metal component and a glass component or a ceramic component, or both. Thereby, the adhesion between the laminate 10 and the base electrode layer can be improved. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. When there is a glass component, it can assist the sintering of the metal component in the base electrode layer and promote the sintering. The ceramic component may be the same type of ceramic material as the dielectric layer 20 or a different type of ceramic material. The ceramic component is, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３It includes at least one selected from the following.

[0045] The baked layer is, for example, formed by applying a conductive paste containing glass and metal to a laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, or by firing a laminated chip having internal electrodes and a dielectric layer to obtain a laminate, and then applying the conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrodes and a dielectric layer and the conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a material with a ceramic component added instead of glass. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may consist of multiple layers.

[0046] The longitudinal thickness of the first base electrode layer 50A located at the first end face LS1 is preferably, for example, 2 μm to 220 μm at the center of the first base electrode layer 50A in the lamination direction T and width direction W. Furthermore, the thickness of the first base electrode layer 50A is preferably 4 μm to 40 μm in areas other than the first end face LS1.

[0047] The longitudinal thickness of the second base electrode layer 50B located at the second end face LS2 is preferably, for example, 2 μm to 220 μm at the center of the second base electrode layer 50B in the lamination direction T and width direction W. Furthermore, the thickness of the second base electrode layer 50B is preferably 4 μm to 40 μm in areas other than the first end face LS1.

[0048] When the first base electrode layer 50A is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A in the lamination direction provided in this part is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this part.

[0049] When the first base electrode layer 50A is provided on a part of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness of the first base electrode layer 50A in the width direction provided in this portion is, for example, 4 μm or more and 40 μm or less at the center of the first base electrode layer 50A in the length direction L and the lamination direction T.

[0050] When a second base electrode layer 50B is provided on a part of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided in this portion in the lamination direction is, for example, 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided in this portion.

[0051] When a second base electrode layer 50B is provided on at least one of the surfaces of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B in the width direction provided in this portion is preferably, for example, 4 μm or more and 40 μm or less at the center of the second base electrode layer 50B in the length direction L and the lamination direction T.

[0052] The external electrode 40 has a conductive resin layer 60 containing resin and metal components, which is placed on the base electrode layer 50. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0053] The first conductive resin layer 60A is arranged to cover the first base electrode layer 50A. Preferably, the end of the first conductive resin layer 60A is in contact with the laminate 10. The end of the first conductive resin layer 60A refers to the portion of the first conductive resin layer 60A that is on the second end face LS2 side of the first base electrode layer 50A in the length direction L. The second conductive resin layer 60B is arranged to cover the second base electrode layer 50B. Preferably, the end of the second conductive resin layer 60B is in contact with the laminate 10. The end of the second conductive resin layer 60B refers to the portion of the second conductive resin layer 60B that is on the first end face LS1 side of the second base electrode layer 50B in the length direction L.

[0054] The longitudinal thickness of the first conductive resin layer 60A located on the first end face LS1 side is preferably, for example, 10 μm to 200 μm at the center of the first conductive resin layer 60A in the lamination direction T and width direction W. Furthermore, the thickness of the first conductive resin layer 60A is preferably 10 μm to 200 μm in areas other than the first end face LS1.

[0055] The longitudinal thickness of the second conductive resin layer 60B located on the second end face LS2 side is preferably, for example, 10 μm to 200 μm at the center of the second conductive resin layer 60B in the lamination direction T and width direction W. Furthermore, the thickness of the second conductive resin layer 60B is preferably 10 μm to 200 μm in areas other than the second end face LS2.

[0056] When the first conductive resin layer 60A is also provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the first conductive resin layer 60A in the lamination direction T provided in these portions is preferably, for example, 10 μm or more and 200 μm or less at the center of the length direction L and width direction W of the first conductive resin layer 60A provided in these portions.

[0057] When the first conductive resin layer 60A is also provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, it is preferable that the thickness of the first conductive resin layer 60A in the width direction W provided on this portion is, for example, 10 μm or more and 200 μm or less at the center of the first conductive resin layer 60A in the length direction L and the lamination direction T provided on this portion.

[0058] When a second conductive resin layer 60B is provided on a portion of the first main surface TS1 and a portion of the second main surface TS2, the thickness of the second conductive resin layer 60B provided in this portion in the lamination direction T is preferably, for example, 10 μm to 200 μm at the center of the length direction L and width direction W of the second conductive resin layer 60B provided in this portion.

[0059] When a second conductive resin layer 60B is provided on a portion of the first side surface WS1 and a portion of the second side surface WS2, the thickness of the second conductive resin layer 60B in the width direction W provided on this portion is preferably, for example, 10 μm or more and 200 μm or less at the center of the second conductive resin layer 60B in the length direction L and the lamination direction T.

[0060] The conductive resin layer 60 is placed on the underlying electrode layer 50. The plating layer 70 is then placed so as to cover the conductive resin layer 60. The plating layer 70 has a Ni plating layer 71 and a Sn plating layer 72.

[0061] The conductive resin layer 60 has a resin portion and a conductive filler dispersed within the resin portion.

[0062] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, it is preferable that the resin portion of the conductive resin layer 60 contains a curing agent together with the thermosetting resin. When epoxy resin is used as the base resin, the curing agent for the epoxy resin may be various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0063] Because the conductive resin layer 60 includes such resin components, it is more flexible than, for example, the base electrode layer 50 which consists of a plated film or a fired product of metal and glass components. Therefore, even when the multilayer ceramic capacitor 1 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer 60 functions as a buffer layer. Thus, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0064] The conductive filler is dispersed within the resin portion in a substantially uniform distribution. The conductive filler is primarily responsible for the conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed inside the conductive resin layer 60, and electrical conductivity is established between the base electrode layer 50 and the plating layer 70.

[0065] The metal constituting the conductive filler may be pure silver (Ag), an alloy containing Ag, or a metal powder with an Ag coating on its surface. Ag has the lowest resistivity among metals, making it suitable for electrode materials. Furthermore, as a noble metal, Ag is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as a conductive filler. When using a metal powder with an Ag coating on its surface, it is preferable to use Cu, Ni, Sn, Bi, or alloy powders containing these metals.

[0066] Furthermore, the conductive filler may be Cu or Ni that has been treated to prevent oxidation. Alternatively, the conductive filler may be metal powder coated with Sn, Ni, or Cu on its surface. When using metal powder coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy of these.

[0067] The shape of the conductive filler is not particularly limited. Conductive fillers can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0068] The average particle size of the conductive filler may be, for example, 0.3 μm or more and 10 μm or less.

[0069] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated using the laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0070] The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0071] The first plating layer 70A is arranged to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2. More specifically, the first plating layer 70A is arranged such that the first end face Ni plating layer 71A1 described above is arranged on the first end face LS1, and the first side surface Ni plating layer 71A2 described above extends from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2.

[0072] The second plating layer 70B is arranged to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is arranged to extend from the first end face LS1 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2. More specifically, the second plating layer 70B is arranged such that the second end face Ni plating layer 71B1 described above is arranged on the second end face LS2, and the second side surface Ni plating layer 71B2 described above extends from the second end face LS2 to a part of the first main surface TS1 and a part of the second main surface TS2, as well as to a part of the first side surface WS1 and a part of the second side surface WS2.

[0073] The plating layer 70 preferably has a two-layer structure consisting of a Ni plating layer 71 and a Sn plating layer 72. Preferably, the first Sn plating layer 72A is placed on the first Ni plating layer 71A, and preferably the second Sn plating layer 72B is placed on the second Ni plating layer 71B. The Ni plating layer 71 prevents the underlying electrode layer 50 and the conductive resin layer 60 from being corroded by the solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. This facilitates the mounting of the multilayer ceramic capacitor 1.

[0074] In the first Sn plating layer 72A, the first end-face side Sn plating layer 72A1 is positioned on the first end-face side Ni plating layer 71A1, and the second side-side Sn plating layer 72A2 is formed on the first side-side Ni plating layer 71A2.

[0075] In the second Sn plating layer 72B, the second end-face side Sn plating layer 72B1 is formed on the second end-face side Ni plating layer 71B1, and the second side-side Sn plating layer 72B2 is formed on the second side-side Ni plating layer 71B2.

[0076] The thickness of the first Ni plating layer 71A and the first Sn plating layer 72A are preferably 1 μm or more and 15 μm or less.

[0077] The thickness of the second Ni plating layer 71B and the second Sn plating layer 72B are preferably 1 μm or more and 15 μm or less.

[0078] Furthermore, if the lengthwise dimension of the multilayer ceramic capacitor 1, including the laminated body 10 and the external electrodes 40, is denoted as dimension L, then it is preferable that dimension L is between 0.2 mm and 10 mm. Also, if the dimension in the stacking direction of the multilayer ceramic capacitor 1 is denoted as dimension T, then it is preferable that dimension T is between 0.1 mm and 10 mm. Furthermore, if the widthwise dimension of the multilayer ceramic capacitor 1 is denoted as dimension W, then it is preferable that dimension W is between 0.1 mm and 10 mm.

[0079] The first external electrode 40 and the second external electrode 40B each have grooves 72A3 and 72B3 extending in the stacking direction T. Specifically, the first Sn plating layer 72A has grooves 72A3 extending in the stacking direction T. The second Sn plating layer 72B has grooves 72B3 extending in the stacking direction T. The grooves 72A3 and 72B3 will be described in detail below with reference to Figures 1, 2, 5, and 7. Figure 7 is a view of the multilayer ceramic capacitor shown in Figure 2 from the direction of arrow V, and is a side view showing the end face of the ceramic capacitor.

[0080] The groove 72A3 is formed as part of the first end face side Sn plating layer 72A1 of the first Sn plating layer 72A. The groove 72A3 is recessed in the longitudinal direction L of the laminate 10 and extends linearly along the lamination direction T.

[0081] As shown in Figures 1, 2, and 7, one end of the groove 72A3 is open to the first main surface TS1, and the other end of the groove 72A3 terminates within the first end surface LS1. In other words, the groove 72A3 has one end at a position on the first end surface LS1 that is separated from the first main surface TS1 by a predetermined distance T in the stacking direction.

[0082] The groove 72B3 is formed as part of the second end face side Sn plating layer 72B1 of the second Sn plating layer 72B. The groove 72B3 is recessed in the longitudinal direction L of the laminate 10 and extends linearly along the lamination direction T.

[0083] As shown in Figure 2, one end of the groove 72B3 is open to the first main surface TS1, and the other end of the groove 72B3 terminates within the second end surface LS2. In other words, the groove 72B3 has one end at a position on the second end surface LS2 that is separated from the second main surface TS2 by a predetermined distance T in the stacking direction.

[0084] Multiple grooves (three in this embodiment) are arranged in the width direction W of each groove 72A3 and groove 72B3. Preferably, the number of grooves 72A3 and groove 72B3 is three or more each. This increases the area in which the plating layer 70 and the under electrode layer 50 are directly connected without the conductive resin layer 60, thereby reducing resistance.

[0085] The grooves 72A3 and 72B3 are arranged evenly and in a balanced manner in the width direction W. This allows for reduced resistance while ensuring mechanical joint strength through soldering. However, the grooves 72A3 and 72B3 may be arranged at unequal intervals in the width direction W.

[0086] More specifically, as shown in Figure 7, when viewed in the longitudinal direction L, the grooves 72A3 and 72B3 are arranged to intersect with the multiple internal electrode layers 30. Specifically, they are orthogonal to each other. This allows for a reduction in resistance.

[0087] More specifically, as shown in Figure 7, when viewed in the longitudinal direction L, the grooves 72A3 and 72B3 are arranged to straddle the boundary between the second main surface outer layer 12B and the inner layer 11 of the laminate 10.

[0088] Next, the structure for realizing the grooves 72A3 and 72B3 will be described in detail. As shown in Figures 2 and 5, the first conductive resin layer 60A has three slits 61A extending in the lamination direction T. As shown in Figures 2 and 5, the second conductive resin layer 60B has three slits 61B extending in the lamination direction T.

[0089] One end of slit 61A is open to the first main surface TS1, and the other end of slit 61A terminates within the first end surface LS1. One end of slit 61B is open to the first main surface TS1, and the other end of slit 61B terminates within the second end surface LS2.

[0090] The first Ni plating layer 71A has three grooves 71A3. The grooves 71A3 are portions that extend into the slit 61A. In this way, the first underlay electrode layer 50A and the first plating layer 70A are directly connected via the slit 61A.

[0091] The aforementioned groove 72A3 is the portion that extends into the slit 61A and is formed in correspondence with the groove 71A3.

[0092] The second Ni plating layer 71B has three grooves 71B3. The grooves 71B3 are portions that extend into the slit 61B. In this way, the second underlay electrode layer 50B and the second plating layer 70B are directly connected via the slit 61B.

[0093] The aforementioned groove 72B3 is the portion that extends into the slit 61B and is formed in accordance with the groove 71B3.

[0094] Next, the effects of grooves 72A3 and 72B3 will be explained. Because one end of grooves 72A3 and 72B3 is open to the first main surface TS1, solder can be effectively attracted during mounting. In other words, the solder joints to the first base electrode layer 50A and the second base electrode layer 50B can be strengthened. In particular, by soldering the slits 61A and 62A of the conductive resin layer 60 to the base electrode layer, the Ni plating layer, and the Sn plating layer, highly reliable electrical and mechanical joints can be ensured.

[0095] The ends of grooves 71A3 and 72B3 on the second main surface TS1 side terminate within the first end face LS1 and the second end face LS2, allowing for adjustment of the solder wetting amount. Generally, excessive solder wetting can cause stress loads on the laminate, potentially leading to cracking. However, with the configuration of this embodiment, the solder wetting amount can be appropriately adjusted.

[0096] As described above, it is possible to ensure highly reliable electrical and mechanical bonding while suppressing the occurrence of cracks in the laminate 10.

[0097] More specifically, in the longitudinal direction L, the total area of ​​grooves 72A3 and 72B3 is 10% to 40% of the area of ​​the first external electrode 40A or the second external electrode 40B. This allows for reduced resistance while ensuring mechanical bonding strength through soldering. As described above, the remaining conductive resin layer on the end face makes it less likely for solder cracks to form on the end face during thermal shock cycles, resulting in improved long-term bonding reliability.

[0098] The length of the grooves 72A3 and 72B3 in the stacking direction T is preferably half or more of the length of the external electrode 40 in the stacking direction T. That is, the other end portions of the grooves 72A3 and 72B3 are preferably located on the second main surface TS2 side of the center of the external electrode 40 in the stacking direction T. This ensures mechanical bonding strength through soldering.

[0099] The multilayer ceramic capacitor 1 of this embodiment provides the following effects.

[0100] (1) The multilayer ceramic capacitor 1 includes a plurality of stacked dielectric layers 20 and a plurality of internal electrode layers 3, and has a laminate 10 having a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing the width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing the length direction L perpendicular to the stacking direction T and the width direction W, and a first external electrode 40A disposed on the first end surface LS1 and a second external electrode 40B disposed on the second end surface LS2. The first external electrode 40A is disposed on the first end surface LS1. The second external electrode 40B is disposed on the second end surface LS2. Each of the first external electrode 40A and the second external electrode 40B comprises a first base electrode layer 50A and a second base electrode layer 50B, a first conductive resin layer 60A and a second conductive resin layer 60B disposed on the first base electrode layer 50A and the second base electrode layer 50B, and a first plating layer 70A and a second plating layer 70B disposed to cover the first conductive resin layer 60A and the second conductive resin layer 60B. The first external electrode 40A and the second external electrode 40B have grooves 72A3 and grooves 72B3 extending in the lamination direction. In grooves 72A3 and grooves 72B3, the first base electrode layer 50A and the second base electrode layer 50B are directly connected to the first plating layer 70A and the second plating layer 70B. One end of grooves 72A3 and 72B3 is open to the first main surface TS1, while the other end of grooves 72A3 and 72B3 terminates within the first end surface LS1 or the second end surface LS2.

[0101] This results in a multilayer ceramic capacitor 1 that can ensure highly reliable electrical and mechanical connections while suppressing the occurrence of cracks in the laminate 10.

[0102] (2) Multiple grooves 72A3 and grooves 72B3 are arranged side by side in the width direction W.

[0103] This increases the area in which the plating layer 70 and the underlay electrode layer 50 are directly connected without the conductive resin layer 60, thereby reducing resistance.

[0104] (3) When viewed in the length direction L, the grooves 72A3 and 72B3 are arranged to intersect with the multiple internal electrode layers 30.

[0105] This reduces the resistance of the multilayer chip capacitor 1. (4) In the longitudinal direction L, the grooves 72A3 and 72B3 are arranged to straddle the boundary between the second main surface outer layer 12B and the inner layer 11 of the laminate 10.

[0106] This makes it possible to reduce the resistance of the multilayer chip capacitor 1.

[0107] Next, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment will be described. The manufacturing method of the multilayer ceramic capacitor of this embodiment is not limited as long as the above requirements are satisfied. However, a preferred manufacturing method comprises the following steps. The details of each step are described below.

[0108] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and solvent may be known substances.

[0109] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern for the first internal electrode layer 31 formed on it, and a dielectric sheet with the pattern for the second internal electrode layer 32 formed on it.

[0110] A predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first main surface outer layer portion 12A on the first main surface TS1 side. On top of this, dielectric sheets with printed patterns for the first internal electrode layer 31 and dielectric sheets with printed patterns for the second internal electrode layer 32 are sequentially stacked to form the inner layer portion 11. On top of this inner layer portion 11, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the second main surface outer layer portion 12B on the second main surface TS2 side. This completes the production of the laminated sheet.

[0111] Laminated sheets are pressed in the lamination direction by means of hydrostatic pressing or other methods to produce laminated blocks.

[0112] The laminated block is cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0113] The laminated chips are fired to produce the laminated body 10. The firing temperature depends on the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably between 900°C and 1400°C.

[0114] A conductive paste, which will become the base electrode layer 50, is applied to both end faces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing glass components and metal is applied to the laminate 10 by a method such as dipping. After that, a baking process is performed to form the base electrode layer 50. The temperature of this baking process is preferably 700°C to 950°C.

[0115] Next, a conductive resin layer 60 is formed. The conductive resin layer 60 may be formed on the surface of the underlying electrode layer 50, or it may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 60 is formed on the surface of the underlying electrode layer 50.

[0116] First, a conductive resin paste is prepared by dispersing a conductive filler in a thermosetting resin, which serves as the base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive filler. Therefore, the conductive filler is uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, a silver (Ag) metal powder.

[0117] Subsequently, the conductive resin paste is applied to the base electrode layer 50 using a dipping method, and heat treatment is performed at a temperature of 200°C to 550°C. This causes the resin to heat-cur, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the scattering of resin and the oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0118] After heat curing, a portion of the conductive resin layer 60 is removed by laser processing to form slits 61A and 61B extending in the lamination direction T. The slits 61A and 61B are formed such that one end is open to the first main surface TS1 and the other end terminates within the first end surface LS1 or the second end surface LS2.

[0119] It is preferable to use a pulsed laser. By adjusting the laser conditions, only a portion of the conductive resin layer 60 is removed while leaving the underlying electrode layer 50 intact. This ultimately forms the conductive resin layer 60 of this embodiment.

[0120] Subsequently, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electroplating method. For example, barrel plating is preferred as the plating method.

[0121] In this case, since the plating layer 70 is formed with a substantially uniform thickness, grooves 72A3 and 72B3 are formed on the surface of the external electrode, i.e., the plating layer, corresponding to the slits 61A and 61B formed in the conductive resin layer 60.

[0122] In grooves 72A3 and 72B3, the first base electrode layer 50A and the second base electrode layer 50B are directly connected to the first plating layer 70A and the second plating layer 70B, respectively.

[0123] A multilayer ceramic capacitor 1 is manufactured using the above manufacturing method.

[0124] (Second Embodiment) The shape, number, and position of the grooves in the Sn plating layer are not limited to the first embodiment.

[0125] A second embodiment will be described using Figure 8. Figure 8 is a cross-sectional view of a multilayer ceramic capacitor according to the second embodiment. Since the basic structure of the second embodiment is the same as that of the first embodiment, the following description will focus on the differences. In addition, only the first Sn plating layer 72A will be described, but since the structure of the second Sn plating layer 72B is the same as that of the first Sn plating layer 72A, the description of the second Sn plating layer 72B will be omitted.

[0126] The first Sn plating layer 72A has a first groove 72A3 extending in the lamination direction T and a second groove 72A4 extending in the width direction W.

[0127] The first groove 72A3 is formed as part of the first end face side Sn plating layer 72A1 of the first Sn plating layer 72A. The first groove 72A3 is recessed in the longitudinal direction L of the laminate 10 and extends linearly along the lamination direction T.

[0128] The second groove 72A4 is formed as part of the first end face side Sn plating layer 72A1 of the first Sn plating layer 72A. The second groove 72A4 is recessed in the length direction L of the laminate 10 and extends linearly along the width direction W.

[0129] As shown in Figure 8, the first groove 72A3 and the second groove 72A4 intersect, specifically, are perpendicular to each other.

[0130] The first groove 72A3 enhances solder wetting and reduces resistance.

[0131] The second groove 72A4 further increases the area in which the plating layer 70 and the underlay electrode layer 50 are directly connected without the conductive resin layer 60, thereby reducing resistance.

[0132] As shown in Figure 8, one end of the first groove 72A3 is open to the first main surface TS1, and the other end of the groove 72A3 terminates within the first end surface LS1. In other words, the first groove 72A3 has one end at a position on the first end surface LS1 that is separated from the second main surface TS2 by a predetermined distance T in the stacking direction.

[0133] As shown in Figure 8, one end of the second groove 72A4 terminates within the first end face LS1, and the other end of the second groove 72A4 terminates within the first end face LS1. In other words, the second groove 72A4 has both ends located on the first end face LS1 at a predetermined distance in the width direction W from the first side surface WS1 and the second side surface WS2.

[0134] Multiple first grooves 72A3 are arranged in the width direction W (in this embodiment, three). It is preferable that the number of first grooves 72A3 be three or more.

[0135] The first grooves 72A3 are arranged evenly and in a balanced manner in the width direction W. This allows for reduced resistance while ensuring mechanical bonding strength through soldering. However, the first grooves 72A3 may be arranged at unequal intervals in the width direction W.

[0136] Multiple (three in this embodiment) second grooves 72A4 are arranged in the stacking direction T. It is preferable that the number of second grooves 72A4 be three or more.

[0137] The second grooves 72A4 are arranged evenly and in a balanced manner in the stacking direction T. This allows for reduced resistance while ensuring mechanical bonding strength through soldering. The second grooves 72A4 may also be arranged at unequal intervals in the width direction W.

[0138] (Other configurations of multilayer ceramic capacitors) The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 8. For example, the multilayer ceramic capacitor 1 may be a double-gang, triple-gang, or quadruple-gang multilayer ceramic capacitor as shown in Figures 9, 10, and 11.

[0139] The multilayer ceramic capacitor 1 shown in Figure 9 is a double-gang multilayer ceramic capacitor 1, and as an internal electrode layer 30, it includes a first internal electrode layer 33 and a second internal electrode layer 34, as well as a floating internal electrode layer 35 that is not led out to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in Figure 10 is a triple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in Figure 11 is a quadruple-gang multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as floating internal electrode layers 35. In this way, by providing floating internal electrode layers 35 as internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. Therefore, the voltage applied to each capacitor component becomes lower, and the voltage rating of the multilayer ceramic capacitor 1 can be increased. It goes without saying that the multilayer ceramic capacitor 1 in this embodiment may also have a multi-gang structure of four or more units.

[0140] The multilayer ceramic capacitor 1 may be a two-terminal type with two external electrodes, or a multi-terminal type with multiple external electrodes.

[0141] In the embodiments described above, a multilayer ceramic capacitor was given as an example in which a dielectric layer 20 made of dielectric ceramic is used as the ceramic layer. However, the multilayer ceramic electronic components of this disclosure are not limited to this. For example, the ceramic electronic components of this disclosure can also be applied to various multilayer ceramic electronic components such as piezoelectric components using piezoelectric ceramic as the ceramic layer, thermistors using semiconductor ceramic as the ceramic layer, and inductors using magnetic ceramic as the ceramic layer. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ferrite and other ceramics.

[0142] <1> A laminate comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end surface-side external electrode disposed on the first end surface, the second external electrode comprises a second end surface-side external electrode disposed on the second end surface, and each of the first end surface-side external electrode and the second end surface-side external electrode comprises an end surface-side base electrode layer, an end surface-side conductive resin layer disposed on the end surface-side base electrode layer, and an end surface-side plating layer disposed to cover the end surface-side conductive resin layer. A multilayer ceramic electronic component wherein the first end-face side external electrode and the second end-face side external electrode have a first groove extending in the stacking direction, the end-face side base electrode layer and the end-face side plating layer are directly connected in the groove, one end of the first groove is open to the first main surface, and the other end of the groove is terminated within the first end face or the second end face.

[0143] <2> The multilayer ceramic electronic component according to <1>, wherein the first grooves are arranged in a plurality in the width direction.

[0144] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein, when viewed in the longitudinal direction, the first groove is arranged to intersect with the plurality of internal conductor layers.

[0145] <4> The multilayer ceramic electronic component according to any one of <1> to <3>, wherein, when viewed in the longitudinal direction, the first groove is arranged to straddle the boundary between the outer layer and the inner layer of the laminate.

[0146] <5> The multilayer ceramic electronic component according to any one of <1> to <4>, wherein the first end-face side external electrode and the second end-face side external electrode have a second groove extending in the width direction, and the first groove and the second groove intersect.

[0147] <6> The multilayer ceramic electronic component according to any one of <1> to <5>, wherein, viewed in the longitudinal direction, the total area of ​​the first groove is 10% or more and 40% or less of the area of ​​the first external electrode or the second external electrode.

[0148] The present invention is not limited to the configuration of the above embodiments, and can be modified and applied as appropriate without altering the essence of the invention. Furthermore, a combination of two or more of the desirable configurations described in the above embodiments also constitutes the present invention.

[0149] 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 40A First external electrode (first end-face side external electrode) 40B Second external electrode (second end-face side external electrode) 50A First base electrode layer (end-face side base electrode layer) 50B Second base electrode layer (end-face side base electrode layer) 60A First conductive resin layer (end-face side conductive resin layer) 60B Second conductive resin layer (end-face side conductive resin layer) 70A First plating layer (end-face side plating layer) 70B Second plating layer (end-face side plating layer) 72A3 Groove (first groove) 72B3 Groove (first groove) T Lamination direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side WS2 Second side L Length direction LS1 First end face LS2 Second end face

Claims

1. A laminate comprising a plurality of stacked ceramic layers and a plurality of internal conductor layers, having a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, wherein the first external electrode comprises a first end-face side external electrode disposed on the first end surface, the second external electrode comprises a second end-face side external electrode disposed on the second end surface, and each of the first end-face side external electrode and the second end-face side external electrode comprises an end-face side base electrode layer, an end-face side conductive resin layer disposed on the end-face side base electrode layer, and an end-face side plating layer disposed to cover the end-face side conductive resin layer. A multilayer ceramic electronic component wherein the first end-face side external electrode and the second end-face side external electrode each have a first groove extending in the stacking direction, the end-face side base electrode layer and the end-face side plating layer are directly connected in the first groove, one end of the first groove is open to the first main surface, and the other end of the first groove terminates within the first end face or the second end face.

2. The multilayer ceramic electronic component according to claim 1, wherein the first grooves are arranged in a plurality in the width direction.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein, in view of the longitudinal direction, the first groove is arranged to intersect with the plurality of internal conductor layers.

4. The multilayer ceramic electronic component according to claim 1 or 2, wherein, in view in the longitudinal direction, the first groove is arranged to straddle the boundary between the outer layer and the inner layer of the laminate.

5. The multilayer ceramic electronic component according to claim 1 or 2, wherein the first end-face side external electrode and the second end-face side external electrode have a second groove extending in the width direction, and the first groove and the second groove intersect.

6. The multilayer ceramic electronic component according to claim 1 or 2, wherein, viewed in the longitudinal direction, the total area of ​​the first groove is 10% or more and 40% or less of the area of ​​the first external electrode or the second external electrode.

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