Preparation method of semiconductor structure and semiconductor structure
By using atomic layer deposition technology to form an oxide layer in the semiconductor structure and reducing the content of target elements in the oxide layer, the performance degradation problem caused by the inverse narrow channel effect is solved, achieving performance improvement and cost reduction.
Patent Information
- Application Number
- CN202510803640.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-16
- Publication Date
- 2025-09-19
AI Technical Summary
The inverse narrow channel effect causes performance degradation in semiconductor devices, and existing technologies are unable to effectively solve this problem.
The oxide layer is formed by atomic layer deposition process, which reduces the content of target elements in the oxide layer, thereby weakening the migration of dopants to the isolation layer and increasing the concentration of dopants in the active area.
The anti-narrow channel effect is improved, the performance of semiconductor devices is enhanced, the process flow is simplified, and the cost is reduced.
Smart Images
Figure CN120674303A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and the semiconductor structure. Background Art
[0002] In the field of semiconductor manufacturing technology, the inverse narrow channel effect generally refers to the fact that as the channel width becomes narrower, the performance or characteristics of the semiconductor device show changes that are opposite to traditional expectations. For example, when the channel size becomes narrower, the current density, leakage current, short channel effect, etc. of the semiconductor device deteriorate.
[0003] Therefore, how to reduce the impact of the anti-narrow channel effect becomes an urgent problem to be solved. Summary of the Invention
[0004] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0005] According to some embodiments, the present application provides a method for preparing a semiconductor structure, the method comprising:
[0006] Providing a substrate, wherein an isolation trench and an active area are formed in the substrate;
[0007] forming a first dielectric layer and a second dielectric layer stacked in a direction perpendicular to the substrate, wherein the first dielectric layer is located on the top surface of the active area;
[0008] An oxide layer is formed by a preset process, the oxide layer covering the sidewalls of the isolation trench, the exposed outer surface of the first dielectric layer, and the exposed outer surface of the second dielectric layer, wherein the content of the target element in the oxide layer is less than the content of the target element in the film layer prepared by the wet oxidation process;
[0009] An isolation layer is formed, and the isolation layer covers the oxide layer.
[0010] In the method for preparing the semiconductor structure of the above embodiment, the content of the target element in the oxide layer formed by the preset process is less than the content of the target element in the film layer prepared by the wet oxidation process. In order to reduce the anti-narrow channel effect, it is necessary to ensure the concentration of the dopant in the active area, and the content of the target element in the oxide layer can affect the migration of the dopant in the active area to the isolation layer. For example, the lower the content of the target element in the oxide layer, the weaker the migration of the dopant in the active area to the isolation layer, so that the concentration of the dopant in the active area increases. In this way, the oxide layer is formed by the preset process, which can reduce the content of the target element in the oxide layer, which is conducive to improving the anti-narrow channel effect, thereby improving the performance of the semiconductor device. In addition, the preparation method in the above embodiment does not require additional masking process and / or ion implantation process, which can simplify the process flow and thus reduce costs.
[0011] In some embodiments, the predetermined process includes an atomic layer deposition process.
[0012] In some embodiments, a portion of the active region located at a top of the isolation trench has a sharp corner; before forming the oxide layer using a predetermined process, the method further includes:
[0013] A sacrificial layer is formed by a dry oxidation process to round the sharp corners of the active area. The sacrificial layer covers the sidewalls of the isolation trench and the sharp corners of the active area.
[0014] The sacrificial layer is removed.
[0015] In some embodiments, forming a first dielectric layer and a second dielectric layer stacked in a direction perpendicular to the substrate includes:
[0016] forming a first dielectric material layer and a second dielectric material layer stacked in a direction perpendicular to the substrate, wherein the first dielectric material layer is located on the top surface of the active area, and the first dielectric material layer and the second dielectric material layer are flush with the sidewalls of the isolation trench;
[0017] A portion of the first dielectric material layer and a portion of the second dielectric material layer are removed to expose the sharp corner of the active area. The remaining first dielectric material layer constitutes a first dielectric layer, and the remaining second dielectric material layer constitutes a second dielectric layer.
[0018] In some embodiments, forming an isolation layer includes:
[0019] The isolation layer is formed by a high-density plasma chemical vapor deposition process.
[0020] In some embodiments, the temperature range of the atomic layer deposition process includes 600° C. to 750° C.;
[0021] In some embodiments, the precursor for the atomic layer deposition process includes silicon chloride;
[0022] In some embodiments, the reducing agent of the atomic layer deposition process includes hydrogen;
[0023] In some embodiments, the oxidant of the atomic layer deposition process includes oxygen;
[0024] In some embodiments, the gas flow ratio range of the precursor, reducing agent, and oxidizing agent in the atomic layer deposition process includes 1: (3-5): (2-3);
[0025] In some embodiments, the thickness of the oxide layer formed using the atomic layer deposition process ranges from 60 Å to 100 Å.
[0026] In some embodiments, the temperature range of the dry oxidation process includes 800° C. to 1100° C.;
[0027] In some embodiments, the oxidizing medium of the dry oxidation process includes oxygen;
[0028] In some embodiments, the flow rate of the oxidizing medium in the dry oxidation process ranges from 7 L / min to 12 L / min;
[0029] In some embodiments, the sacrificial layer formed using the dry oxidation process has a thickness ranging from 30 Å to 50 Å.
[0030] In some embodiments, after forming the oxide layer using a predetermined process and before forming the isolation layer, the method further includes:
[0031] The oxide layer is treated by an in-situ thermal annealing process.
[0032] In some embodiments, the temperature range of the in-situ thermal annealing process includes 700° C. to 750° C.;
[0033] In some embodiments, the atmosphere of the in-situ thermal annealing process includes nitrogen;
[0034] In some embodiments, the in-situ thermal annealing process may take 30 minutes to 60 minutes.
[0035] According to some embodiments, the present application further provides a semiconductor structure, which is prepared using the method for preparing the semiconductor structure in any of the above embodiments.
[0036] In the semiconductor structure of the above embodiment, the content of the target element in the oxide layer is less than the content of the target element in the film layer obtained by the wet oxidation process, which can weaken the migration of dopants in the active area to the isolation layer, thereby increasing the concentration of dopants in the active area to improve the anti-narrow channel effect, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0038] Figure 2 A schematic cross-sectional view of a structure obtained from steps S10 to S31 in a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0039] Figure 3 A schematic cross-sectional view of a structure obtained in step S32 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0040] Figure 4 A schematic cross-sectional view of a structure obtained in step S41 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0041] Figure 5A schematic cross-sectional view of a structure obtained in step S42 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0042] Figure 6 This is a schematic cross-sectional view of a structure obtained in step S50 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0043] Figure 7 This is a schematic cross-sectional view of a structure obtained in step S70 in a method for preparing a semiconductor structure provided in one embodiment of the present application.
[0044] Explanation of the reference numerals: 10, substrate; 11, isolation trench; 12, active area; 21, first dielectric layer; 211, first dielectric material layer; 22, second dielectric layer; 221, second dielectric material layer; 30, sacrificial layer; 40, oxide layer; 50, isolation layer. DETAILED DESCRIPTION
[0045] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.
[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0047] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.
[0048] In addition, to clearly illustrate the multiple layers and regions in the drawings, the thickness of each layer and each region are exaggerated to clearly illustrate the relative positions of the layers and the distribution of the regions. When a portion of a layer, film, region, plate, etc. is described as being "on one side" of another portion, this description includes not only the case where it is "directly above" the other portion, but also the case where there are other layers between them. Furthermore, it should be understood that when a portion of a layer, film, region, plate, etc. is described as being "on one side" of another portion, this generally refers to the side directly above the other portion.
[0049] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.
[0050] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0051] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.
[0052] The inverse narrow channel effect is often associated with dopant migration within the active region, which in turn is related to the concentration of certain elements in the oxide film surrounding it. In semiconductor devices with shallow trench isolation structures, boron (B) is often used as a dopant element in the source and well regions to achieve threshold voltage control. However, because boron has a much higher solubility in silicon dioxide than in silicon, it migrates out of the silicon dioxide more easily, resulting in a low boron concentration in the active region. This significantly affects narrow channel devices, reducing their turn-on voltage and causing the inverse narrow channel effect.
[0053] In a traditional process flow, after the front-end process is completed, a trench linear oxide layer is typically grown using in-situ steam generation (ISSG). However, because the ISSG process is inherently a wet process, the grown oxide layer may contain some hydrogen-related defects, such as silicon-hydrogen (Si-H) bonds and / or silicon-hydroxyl (Si-OH) bonds. It is understood that hydrogen can promote the precipitation of boron in silicon oxide. Furthermore, after the subsequent deposition process, the dense isolation structure formed hinders the release of hydrogen in the oxide layer during annealing. This is particularly true for NMOS devices, which have low well concentrations. As a result, the boron in the low-concentration wells of the device is affected by hydrogen and precipitates more, resulting in a significant anti-narrow channel effect and affecting device performance.
[0054] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0055] See also Figure 1 , the present application provides a method for preparing a semiconductor structure, and the method for preparing a semiconductor structure includes the following steps.
[0056] Step S10: providing a substrate, wherein an isolation trench and an active area are formed in the substrate;
[0057] Step S30: forming a first dielectric layer and a second dielectric layer stacked in a direction perpendicular to the substrate, wherein the first dielectric layer is located on the top surface of the active area;
[0058] Step S50: forming an oxide layer using a preset process, the oxide layer covering the sidewalls of the isolation trench, the exposed outer surface of the first dielectric layer, and the exposed outer surface of the second dielectric layer, wherein the content of the target element in the oxide layer is less than the content of the target element in the film layer obtained by the wet oxidation process;
[0059] Step S70: forming an isolation layer, where the isolation layer covers the oxide layer.
[0060] In the method for preparing the semiconductor structure of the above embodiment, the content of the target element in the oxide layer formed by the preset process is less than the content of the target element in the film layer prepared by the wet oxidation process. In order to reduce the anti-narrow channel effect, it is necessary to ensure the concentration of the dopant in the active area, and the content of the target element in the oxide layer can affect the migration of the dopant in the active area to the isolation layer. For example, the lower the content of the target element in the oxide layer, the weaker the migration of the dopant in the active area to the isolation layer, so that the concentration of the dopant in the active area increases. In this way, the oxide layer is formed by the preset process, which can reduce the content of the target element in the oxide layer, which is conducive to improving the anti-narrow channel effect, thereby improving the performance of the semiconductor device. In addition, the preparation method in the above embodiment does not require additional masking process and / or ion implantation process, which can simplify the process flow and thus reduce costs.
[0061] In some embodiments, a portion of the active region located at a top of the isolation trench has a sharp corner; before step S50, forming the oxide layer using a predetermined process, the method further includes:
[0062] Step S41: forming a sacrificial layer by a dry oxidation process to round the sharp corners of the active area, wherein the sacrificial layer covers the sidewalls of the isolation trench and the sharp corners of the active area;
[0063] Step S52: removing the sacrificial layer.
[0064] In some embodiments, step S30, forming a first dielectric layer and a second dielectric layer stacked in a direction perpendicular to the substrate, includes:
[0065] Step S31: forming a first dielectric material layer and a second dielectric material layer stacked in a direction perpendicular to the substrate, wherein the first dielectric material layer is located on the top surface of the active area, and the first dielectric material layer and the second dielectric material layer are flush with the sidewalls of the isolation trench;
[0066] Step S32 : removing a portion of the first dielectric material layer and a portion of the second dielectric material layer to expose the sharp corner of the active area. The remaining first dielectric material layer constitutes the first dielectric layer, and the remaining second dielectric material layer constitutes the second dielectric layer.
[0067] In some embodiments, the temperature range of the dry oxidation process includes 800° C. to 1100° C.;
[0068] In some embodiments, the oxidizing medium of the dry oxidation process includes oxygen;
[0069] In some embodiments, the flow rate of the oxidizing medium in the dry oxidation process ranges from 7 L / min to 12 L / min;
[0070] In some embodiments, the sacrificial layer formed using the dry oxidation process has a thickness ranging from 30 Å to 50 Å.
[0071] In some embodiments, the predetermined process includes an atomic layer deposition process.
[0072] In some embodiments, the temperature range of the atomic layer deposition process includes 600° C. to 750° C.;
[0073] In some embodiments, the precursor for the atomic layer deposition process includes silicon chloride;
[0074] In some embodiments, the reducing agent of the atomic layer deposition process includes hydrogen;
[0075] In some embodiments, the oxidant of the atomic layer deposition process includes oxygen;
[0076] In some embodiments, the gas flow ratio range of the precursor, reducing agent, and oxidizing agent in the atomic layer deposition process includes 1: (3-5): (2-3);
[0077] In some embodiments, the thickness of the oxide layer formed using the atomic layer deposition process ranges from 60 Å to 100 Å.
[0078] In some embodiments, after step S50, forming the oxide layer using a predetermined process, and before step S70, forming the isolation layer, the method further includes:
[0079] Step S60: treating the oxide layer with an in-situ thermal annealing process.
[0080] In some embodiments, the temperature range of the in-situ thermal annealing process includes 700° C. to 750° C.;
[0081] In some embodiments, the atmosphere of the in-situ thermal annealing process includes nitrogen;
[0082] In some embodiments, the in-situ thermal annealing process may take 30 minutes to 60 minutes.
[0083] In some embodiments, step S70, forming an isolation layer, includes:
[0084] Step S71 : forming an isolation layer by using a high-density plasma chemical vapor deposition process.
[0085] In the above embodiments of the present disclosure, unless otherwise specified herein, there is no strict order restriction for the execution of the steps in the method. These steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a portion of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.
[0086] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figures 2 to 7 The method is described in detail.
[0087] like Figure 2 As shown, in step S10, a substrate 10 is provided, in which an isolation trench 11 and an active area 12 are formed. As an example, in the embodiments of the present disclosure, the substrate 10 can be made of a semiconductor material, an insulating material, a conductive material, or any combination of these materials. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including, for example, a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI), or a silicon-germanium-on-insulator (SiGe). Those skilled in the art may select the type of substrate 10 according to the type of transistors formed on the substrate 10 , and thus the type of substrate 10 should not limit the protection scope of the present disclosure.
[0088] In some embodiments, a portion of the active region 12 located at the top of the isolation trench 11 has a sharp corner. In step S10 , the isolation trench 11 and the active region 12 may be formed by removing a portion of the substrate 10 .
[0089] like Figure 2 As shown, in step S30 , a first dielectric layer 21 and a second dielectric layer 22 are formed and stacked in a direction perpendicular to the substrate 10 . The first dielectric layer 21 is located on the top surface of the active region 12 .
[0090] It can be understood that the direction perpendicular to the substrate 10 is Figure 2 Y direction shown.
[0091] Illustratively, the first dielectric layer 21 includes a silicon nitride layer.
[0092] Illustratively, the second dielectric layer 22 includes a silicon oxide layer.
[0093] Please combine Figure 2 and Figure 3 It is understood that, in some embodiments, step S30, forming the first dielectric layer 21 and the second dielectric layer 22 stacked in a direction perpendicular to the substrate 10, includes the following steps S31 and S32.
[0094] Step S31: Figure 2 As shown, a first dielectric material layer 211 and a second dielectric material layer 221 are formed and stacked in a direction perpendicular to the substrate 10 . The first dielectric material layer 211 is located on the top surface of the active area 12 , and the first dielectric material layer 211 and the second dielectric material layer 221 are flush with the sidewalls of the isolation trench 11 .
[0095] For example, in step S31, the first dielectric material layer 211 and the second dielectric material layer 221 may be formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes. The CVD process may include one or more of atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD), or plasma-enhanced CVD (PECVD).
[0096] Step S32: Figure 3 As shown, part of the first dielectric material layer 211 and part of the second dielectric material layer 221 are removed to expose the sharp corners of the active region 12 . The remaining first dielectric material layer 211 constitutes the first dielectric layer 21 , and the remaining second dielectric material layer 221 constitutes the second dielectric layer 22 .
[0097] For example, in step S32, an etching process may be used to remove a portion of the first dielectric material layer 211 and a portion of the second dielectric material layer 221. For example, this step may employ anisotropic etching for back etching. Anisotropic etching can selectively etch material in a predetermined crystal orientation or crystal plane direction, while leaving little or no etching marks in other directions. Using anisotropic etching for back etching in this step can make the morphology of the resulting structure more precise and controllable.
[0098] Please combine Figure 4 and Figure 5 It is understood that in some embodiments, before step S50 , in which the oxide layer 40 is formed using a predetermined process, the method further includes the following steps S41 and S42 .
[0099] Step S41: Figure 4 As shown, a dry oxidation process is used to form a sacrificial layer 30 to round the sharp corners of the active area 12 . The sacrificial layer 30 covers the sidewalls of the isolation trench 11 and the sharp corners of the active area 12 .
[0100] Illustratively, the sacrificial layer 30 includes a silicon oxide layer.
[0101] In step S41 , the sacrificial layer 30 formed by the dry oxidation process can round the sharp corners of the active area 12 to avoid the risk of tip leakage, and can repair structural damage caused by the front-end etching process when forming the sacrificial layer 30 .
[0102] In some embodiments, the temperature range of the dry oxidation process includes 800° C. to 1100° C. For example, the temperature range of the dry oxidation process may be 800° C., 900° C., 1000° C., or 1100° C., etc.
[0103] In some embodiments, the oxidizing medium of the dry oxidation process includes oxygen. For example, the oxidizing medium of the dry oxidation process is only oxygen.
[0104] In some embodiments, the flow rate of the oxidizing medium in the dry oxidation process ranges from 7 L / min to 12 L / min. For example, the flow rate of the oxidizing medium in the dry oxidation process can be 7 L / min, 8 L / min, 9 L / min, 10 L / min, 11 L / min, or 12 L / min.
[0105] In some embodiments, the thickness of the sacrificial layer 30 formed by the dry oxidation process ranges from 30 Å to 50 Å. For example, the thickness of the sacrificial layer 30 can be 30 Å, 35 Å, 40 Å, 45 Å, or 50 Å.
[0106] In the above embodiment, compared with the wet oxidation process using water vapor as the oxidizing medium, the dry oxidation process using oxygen as the oxidizing medium to form the sacrificial layer 30 is advantageous in avoiding the generation of defects related to hydrogen.
[0107] Step S52 : removing the sacrificial layer 30 .
[0108] In step S52 , the sacrificial layer 30 may be removed by using a dry etching process or a wet etching process. For example, the sacrificial layer 30 may be removed by using a plasma etching process.
[0109] like Figure 6As shown, in step S50, an oxide layer 40 is formed by a preset process, and the oxide layer 40 covers the sidewalls of the isolation trench 11, the exposed outer surface of the first dielectric layer 21, and the exposed outer surface of the second dielectric layer 22. The content of the target element in the oxide layer 40 is less than the content of the target element in the film layer obtained by the wet oxidation process.
[0110] In some embodiments, the target element is hydrogen. In step S50, the content of hydrogen in the oxide layer 40 formed by the preset process is less than the content of hydrogen in the film layer obtained by the wet oxidation process. In order to reduce the anti-narrow channel effect, it is necessary to ensure the concentration of the dopant in the active area 12. The content of hydrogen in the oxide layer 40 can affect the migration of the dopant in the active area 12 to the isolation layer 50. For example, the lower the content of hydrogen in the oxide layer 40, the weaker the migration of the dopant in the active area 12 to the isolation layer 50, thereby increasing the concentration of the dopant in the active area 12. In this way, forming the oxide layer 40 by the preset process can reduce the content of hydrogen in the oxide layer 40, which is beneficial to improving the anti-narrow channel effect, thereby improving the performance of the semiconductor device.
[0111] Illustratively, the oxide layer 40 is a silicon oxide layer.
[0112] In some embodiments, the preset process includes an atomic layer deposition process. It is understood that atomic layer deposition is a technology that forms a deposited film by alternately passing a gaseous precursor pulse into a reactor and chemically adsorbing and reacting on a deposition substrate. When the precursor reaches the surface of the deposition substrate, it will chemically adsorb on its surface and react on the surface. The surface reaction of atomic layer deposition is self-limiting. The required structure is formed by repeatedly repeating the self-limiting reaction in atomic layer deposition. Compared with traditional solution chemical deposition technology and physical deposition technologies such as sputtering or evaporation, due to the lack of surface control or the existence of sputtering shadow areas, the effect of deposition on the surface of three-dimensional complex structures is better. However, the atomic layer deposition technology is based on surface self-limitation and self-saturated adsorption reaction, so it has surface controllability. The prepared structure has excellent three-dimensional conformality and large-area uniformity, and is more adaptable to complex high-aspect-ratio surface deposition processes. At the same time, the atomic layer deposition process can produce a smooth surface morphology that fits tightly to the original film layer, thereby reducing the stress generated by the deposition process. Therefore, according to the characteristics of the atomic layer deposition process itself, the atomic layer deposition process is used to form the oxide layer 40, which can improve the density of the oxide layer 40 and reduce the content of hydrogen in the oxide layer 40, which helps to improve the anti-narrow channel effect.
[0113] In some embodiments, the temperature range of the atomic layer deposition process includes 600° C. to 750° C. For example, the temperature of the atomic layer deposition process can be 600° C., 650° C., or 700° C.
[0114] In some embodiments, the precursor for the atomic layer deposition process includes silicon chloride.
[0115] In some embodiments, the reducing agent of the atomic layer deposition process includes hydrogen.
[0116] In some embodiments, the oxidant of the atomic layer deposition process includes oxygen.
[0117] In some embodiments, the ratio of the gas flow rates of the precursor, the reducing agent, and the oxidizing agent in the atomic layer deposition process ranges from 1:(3-5):(2-3). For example, the ratio of the gas flow rates of the precursor, the reducing agent, and the oxidizing agent in the atomic layer deposition process can be 1:3:2, 1:4:2, 1:5:2, 1:3:3, 1:4:3, or 1:5:3, etc.
[0118] In some embodiments, the thickness of the oxide layer 40 formed by the atomic layer deposition process ranges from 60 Å to 100 Å. For example, the thickness of the oxide layer 40 can be 60 Å, 70 Å, 80 Å, 90 Å, or 100 Å.
[0119] In some embodiments, after step S50, forming the oxide layer 40 using a predetermined process, and before step S70, forming the isolation layer 50, the method further includes:
[0120] Step S60 , treating the oxide layer 40 by an in-situ thermal annealing process.
[0121] In step S60, the oxide layer 40 is treated with an in-situ thermal annealing process, which can improve the stress state of the oxide layer 40 interface and / or the oxide layer 40 material, thereby stabilizing the material structure, reducing defect density, and reducing defects and impurities in the oxide layer 40, thereby improving electrical performance.
[0122] In some embodiments, the temperature range of the in-situ thermal annealing process includes 700° C. to 750° C. For example, the temperature of the in-situ thermal annealing process is 700° C., 710° C., 720° C., 730° C., 740° C., or 750° C.
[0123] In some embodiments, the atmosphere of the in-situ thermal annealing process includes nitrogen.
[0124] In some embodiments, the in-situ thermal annealing process may last from 30 minutes to 60 minutes. For example, the in-situ thermal annealing process may last for 30 minutes, 45 minutes, or 60 minutes.
[0125] like Figure 7As shown, in step S71, a high-density plasma chemical vapor deposition process is used to form an isolation layer 50, which covers the oxide layer 40 and is at least located in the isolation trench 11. For example, at least a portion of the isolation layer 50 can be used to form a shallow trench isolation structure.
[0126] Illustratively, the isolation layer 50 includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.
[0127] In the method for preparing the semiconductor structure of the above embodiment, the content of the target element in the oxide layer 40 formed by the preset process is less than the content of the target element in the film layer prepared by the wet oxidation process. In order to reduce the anti-narrow channel effect, it is necessary to ensure the concentration of the dopant in the active area 12, and the content of the target element in the oxide layer 40 can affect the migration of the dopant in the active area 12 to the isolation layer 50. For example, the lower the content of the target element in the oxide layer 40, the weaker the migration of the dopant in the active area 12 to the isolation layer 50, so that the concentration of the dopant in the active area 12 increases. In this way, forming the oxide layer 40 by the preset process can reduce the content of the target element in the oxide layer 40, which is conducive to improving the anti-narrow channel effect, thereby improving the performance of the semiconductor device. In addition, the preparation method in the above embodiment does not require additional masking process and / or ion implantation process, which can simplify the process flow and thus reduce costs.
[0128] See also Figure 7 According to some embodiments, the present application further provides a semiconductor structure fabricated using the method for fabricating a semiconductor structure in any of the aforementioned embodiments. Because the semiconductor structure is fabricated using a superior fabrication method, the beneficial effects of the aforementioned method for fabricating a semiconductor structure are also achieved by the semiconductor structure in the embodiments of the present application and are not further elaborated herein.
[0129] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0130] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein an isolation trench and an active area are formed in the substrate; forming a first dielectric layer and a second dielectric layer stacked in a direction perpendicular to the substrate, wherein the first dielectric layer is located on a top surface of the active area; forming an oxide layer using a preset process, the oxide layer covering the sidewalls of the isolation trench, the exposed outer surface of the first dielectric layer, and the exposed outer surface of the second dielectric layer, wherein the content of the target element in the oxide layer is less than the content of the target element in the film layer produced by the wet oxidation process; An isolation layer is formed, wherein the isolation layer covers the oxide layer.
2. The method for preparing a semiconductor structure according to claim 1, wherein: The preset process includes an atomic layer deposition process.
3. The method for preparing a semiconductor structure according to claim 2, wherein: The portion of the active region located at the top of the isolation trench has a sharp corner; Before forming the oxide layer using a preset process, the method further includes: forming a sacrificial layer by a dry oxidation process to round the sharp corners of the active area, wherein the sacrificial layer covers the sidewalls of the isolation trench and the sharp corners of the active area; The sacrificial layer is removed.
4. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of the first dielectric layer and the second dielectric layer stacked in a direction perpendicular to the substrate includes: forming a first dielectric material layer and a second dielectric material layer stacked in a direction perpendicular to the substrate, wherein the first dielectric material layer is located on a top surface of the active area, and the first dielectric material layer and the second dielectric material layer are flush with sidewalls of the isolation trench; A portion of the first dielectric material layer and a portion of the second dielectric material layer are removed to expose the sharp corner of the active area. The remaining first dielectric material layer constitutes the first dielectric layer, and the remaining second dielectric material layer constitutes the second dielectric layer.
5. The method for preparing a semiconductor structure according to any one of claims 2 to 4, wherein: The forming of the isolation layer comprises: The isolation layer is formed by a high-density plasma chemical vapor deposition process.
6. The method for preparing a semiconductor structure according to claim 2, wherein: The parameters of the atomic layer deposition process include at least one of the following characteristics: The temperature range of the atomic layer deposition process includes 600° C. to 750° C.; The precursors for the atomic layer deposition process include silicon chloride; The reducing agent of the atomic layer deposition process includes hydrogen; The oxidant of the atomic layer deposition process includes oxygen; The gas flow ratio range of the precursor, reducing agent and oxidizing agent in the atomic layer deposition process includes 1: (3-5): (2-3); The thickness of the oxide layer formed by the atomic layer deposition process ranges from 60 Å to 100 Å.
7. The method for preparing a semiconductor structure according to claim 3, wherein: The parameters of the dry oxidation process include at least one of the following characteristics: The temperature range of the dry oxidation process includes 800° C. to 1100° C.; The oxidizing medium of the dry oxidation process includes oxygen; The flow rate of the oxidizing medium in the dry oxidation process ranges from 7 L / min to 12 L / min; The sacrificial layer formed by the dry oxidation process has a thickness ranging from 30 Å to 50 Å.
8. The method for preparing a semiconductor structure according to claim 2 or 6, wherein: After forming the oxide layer using a preset process and before forming the isolation layer, the method further includes: The oxide layer is treated by an in-situ thermal annealing process.
9. The method for preparing a semiconductor structure according to claim 8, wherein: The parameters of the in-situ thermal annealing process include at least one of the following characteristics: The temperature range of the in-situ thermal annealing process includes 700° C. to 750° C.; The atmosphere of the in-situ thermal annealing process includes nitrogen; The in-situ thermal annealing process may take 30 to 60 minutes.
10. A semiconductor structure, characterized in that The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.