Hybrid bonding structure and method for detecting stress of barrier layer in hybrid bonding structure

Abstract

The invention provides a hybrid bonding structure and a method for detecting stress of a barrier layer in the hybrid bonding structure, and belongs to the technical field of hybrid bonding of three-dimensional packaging. A composite barrier layer comprising a high-density barrier layer and a NiTi shape memory alloy stress characterization layer is prepared in a mixed bonding structure. The NiTi shape memory alloy stress characterization layer has excellent thermal-mechanical stress self-regulation performance, and can absorb strain and release stress through reversible phase change of austenite and martensite during mixed bonding and annealing. A mixed bonding structure containing the composite barrier layer is prepared, and the stress of the barrier layer is calculated by detecting the deformation of the NiTi shape memory alloy stress characterization layer and combining a stress-strain curve of the NiTi shape memory alloy stress characterization layer in the mixed bonding and annealing treatment process or after the mixed bonding and annealing treatment is completed. The detection result is accurate, the detection method is simple, and the application prospect is wide.

Description

Technical Field

[0001] The present invention relates to the technical field of hybrid bonding of three-dimensional packaging, and in particular to a hybrid bonding structure containing a composite barrier layer and a method for detecting barrier layer stress in the hybrid bonding structure. Background Art

[0002] Hybrid bonding technology achieves direct electrical and mechanical connections between die or wafers by simultaneously forming dielectric layer bonds and metal pad bonds, resulting in a highly reliable and durable bond interface. Metal pads can reach submicron levels, significantly increasing integration density and effectively reducing parasitic capacitance and resistance, improving thermal conductivity while increasing signal transmission speed and energy efficiency. Furthermore, hybrid bonding technology is compatible with most existing semiconductor manufacturing processes, supporting heterogeneous integration of chips made of different materials and with different functions, facilitating the large-scale production of multifunctional devices.

[0003] During hybrid bonding and annealing, if the dielectric layer and metal pad are in direct contact, the interface resistance is high and chemical reactions are likely to occur. Atoms from the metal pad can easily diffuse into the dielectric layer, leading to undesirable effects such as leakage current and signal crosstalk. Furthermore, the significant difference in thermal expansion coefficients between the dielectric layer and the metal pad can easily generate significant thermal stress during hybrid bonding and annealing, leading to desorption at the interface and warping or cracking of the bonded structure.

[0004] Therefore, by detecting stress changes in the micro-areas of the hybrid bonding structure during hybrid bonding and annealing, the stress compression-tension conversion and abnormal stress fluctuations at the interface between the dielectric layer and the metal pad can be evaluated, as well as the stress concentration and maximum stress tolerance of the hybrid bonding structure. Based on the evaluation results, the structural design, preparation materials, and bonding pretreatment process of the hybrid bonding structure, as well as the bonding time, pressure, and temperature, and the annealing heating and cooling rates, holding temperature, and time are optimized. While improving the quality of the bonding interface, it also avoids undesirable conditions such as cracking, desorption, and delamination at the interface between the dielectric layer and the metal pad, ensuring the reliability of the overall bonding structure.

[0005] Methods for measuring stress in micro-regions of hybrid bonded structures include Raman spectroscopy, X-ray diffraction, and atomic force microscopy. X-ray diffraction calculates stress by analyzing lattice distortion in micro-regions. It has the characteristics of high spatial resolution and non-destructiveness, but it cannot perform real-time continuous monitoring. Raman spectroscopy infers stress by analyzing the peak shift of the micro-region spectrum, but thermal noise interference is significant when measuring above 300°C, and it cannot directly perform in-situ precise measurements of the internal structure of the bond. Atomic force microscopy evaluates the morphology, elasticity, stress, and adhesion of the micro-region through the interaction between the probe and the micro-region, and can draw a force-displacement curve based on the interaction force. However, this method has a slow measurement speed and requires high surface cleanliness of the test micro-region.

[0006] Chinese patent CN118969653A discloses a method for hybrid bonding micro-area stress characterization. This method involves preparing a metal structure containing a stress characterizer on the bonding surface of a chip. After hybrid bonding, the micro-area stress is determined by observing the deformation of the stress characterizer. This method often uses nanospheres made of polymers and memory metals as stress characterizers. Polymer nanospheres are prone to aging and degradation, while uniform distribution of memory metal nanospheres within the metal structure is difficult to achieve, impacting deformation measurement accuracy. Furthermore, metal structures made of copper, twinned copper, or ruthenium are prone to chemical reactions and diffusion with the dielectric layer, which can affect the performance of the bonding structure and stress characterizer, while also reducing deformation measurement accuracy.

[0007] Chinese patent CN119069461A discloses a method for monitoring stress in hybrid bonding micro-areas. This method involves preparing a metal stress characterization structure on the bonding surface of a chip. After hybrid bonding, the deformation of the metal stress characterization structure is observed to determine the micro-area stress. This method, however, creates a metal stress characterization structure on the bonding surface of the chip, which occupies the bonding surface area and can lead to chemical reactions and diffusion between metal atoms and the dielectric layer, among other undesirable phenomena.

[0008] To address this issue, a novel hybrid bonding structure and micro-area stress detection method are needed. This method isolates the dielectric layer and metal pad within the bonding structure and detects stress changes in specific micro-areas or stress-sensitive micro-areas during bonding and annealing. This facilitates subsequent adjustments to the bonding structure and preparation materials, as well as the bonding and annealing processes, to ensure a stable bonding interface and a reliable overall bonding structure. Summary of the Invention

[0009] In hybrid bonded structures, a barrier layer is prepared to isolate the dielectric layer from the metal pad, preventing chemical reactions at the bonding interface and blocking the diffusion of metal atoms into the dielectric layer. This prevents adverse effects such as signal crosstalk, increased leakage current, short circuits in the bonded structure, and severe reliability degradation. WN, TaN, or TiN have a dense structure and high thermal stability, effectively blocking the rapid diffusion of metal atoms into the dielectric layer even at temperatures above 300°C. They can fill micro-defects on the dielectric surface and maintain good adhesion to the dielectric layer, minimizing the incidence of voids, delamination, and delamination at the bonding interface. They also possess excellent chemical inertness, offering strong resistance to the various acid and alkaline solutions used in subsequent chemical mechanical polishing and pickling processes, effectively maintaining their barrier properties.

[0010] In view of the many shortcomings of the background technology and the unique advantages of WN, TaN or TiN mentioned above, the present invention uses WN, TaN or TiN as a high-density barrier layer, which is combined with a stress characterization layer made of NiTi shape memory alloy to form a composite barrier layer. The high-density barrier layer is in direct contact with the dielectric layer, and the NiTi shape memory alloy stress characterization layer is in direct contact with the metal pad. The NiTi shape memory alloy stress characterization layer has excellent thermo-mechanical stress self-regulation performance. During bonding and annealing, it can absorb the strain at the interface between the composite barrier layer and the dielectric layer and the metal pad through the reversible phase transition of austenite (high temperature phase) and martensite (low temperature phase), thereby reducing residual stress. The interface between the NiTi shape memory alloy stress characterization layer and the metal pad is easily oxidized to form a dense NiTiO with a high reaction energy barrier and diffusion activation energy. X The oxide layer effectively blocks the diffusion of oxygen and metal atoms and prevents the stress characterization layer from reacting with the metal pad. Furthermore, the NiTi shape memory alloy stress characterization layer has a thermal expansion coefficient between that of the dielectric layer and the metal pad, buffering the thermal stresses generated during bonding and annealing. During or after bonding and annealing, the barrier layer stress is calculated by detecting the deformation of the NiTi shape memory alloy stress characterization layer and combining it with its stress-strain curve.

[0011] In summary, the present invention provides a hybrid bonded structure containing a composite barrier layer and a method for detecting barrier layer stress in a hybrid bonded structure. To achieve the above objectives, the specific technical solutions of the present invention are as follows:

[0012] In a first aspect, the present invention provides a method for preparing a hybrid bonded structure containing a composite barrier layer, comprising the following steps:

[0013] (1) Plasma activation treatment of the substrate surface to be bonded;

[0014] (2) uniformly coating the surface of the substrate to be bonded with photoresist, covering it with a patterned photolithography mask, and exposing and developing it to form a blind hole pattern on the surface to be bonded;

[0015] (3) preparing a blind hole on the surface to be bonded, removing the photoresist, and preparing a composite barrier layer on the surface of the blind hole; the composite barrier layer includes a high-density barrier layer and a NiTi shape memory alloy stress characterization layer;

[0016] (4) A seed layer and a metal pad are prepared on the surface of the NiTi shape memory alloy stress characterization layer, and hybrid bonding and annealing treatment are performed to obtain a hybrid bonding structure containing a composite barrier layer.

[0017] Furthermore, before the surface of the substrate to be bonded is subjected to plasma activation treatment, the surface of the substrate to be bonded is ultrasonically cleaned with acetone and isopropanol in sequence to remove organic contaminants. Specifically, the present invention sequentially uses acetone and isopropanol to ultrasonically clean the surface of the substrate to be bonded for 5 minutes each, and after cleaning, uses N2 at a pressure of 0.2 MPa for 45 o Blow diagonally for 30 s to dry the surfaces to be bonded.

[0018] Furthermore, the plasma activation treatment includes, but is not limited to, plasma activation of the substrate surface to be bonded using O2 and / or Ar plasma. Specifically, the activation treatment using O2 plasma can form active groups on the surface to be bonded to improve wettability to the photoresist, while the activation treatment using Ar plasma can adjust the roughness of the bonding surface to enhance its mechanical engagement with the photoresist.

[0019] Furthermore, when using O2 and / or Ar plasma to activate the substrate surface to be bonded, the total gas flow rate is 50-200 sccm, the treatment time is 30-180 s, the RF power is 50-300 W, and the substrate temperature is controlled by water cooling at 40-90°C. A mixed gas of O2 and Ar can achieve both chemical activation and physical cleaning. The optimal volume ratio of Ar / O2 is 4:1.

[0020] Furthermore, the substrate is composed of a chip and a SiO2 dielectric layer thereon, with the bonding surface located on the surface of the SiO2 dielectric layer. The chip can be made of materials including, but not limited to, Si wafers, GaN wafers, InP wafers, Ga2O3 wafers, GaAs wafers, or SiC wafers. The chip size includes, but is not limited to, 2 inches, 4 inches, 6 inches, 8 inches, 10 inches, or 12 inches.

[0021] Furthermore, the photoresist coating method includes, but is not limited to, spin coating. Specifically, the spin coating process is as follows: after the photoresist is dropped onto the bonding surface, the spin coating is rotated at a low speed of 400-600 rpm for 3-6 seconds to achieve uniform spreading, and then the spin coating is completed by rotating at a high speed of 1500-3000 rpm for 20-40 seconds.

[0022] After the photoresist is applied, the substrate is baked on a vacuum hot plate at 90-100°C for 30-120 seconds to remove the solvent and improve the stability and adhesion of the photoresist. After aligning the patterned photomask with the wafer, contact exposure is performed using a UV light source. The photoresist in the exposed areas undergoes a photochemical reaction, causing its solubility to change. Development is performed using a spray method for 30-60 seconds. The developer is selected based on the type of photoresist and may include, but is not limited to, organic solvents or alkaline developers.

[0023] Furthermore, reactive ion etching (RIE) was used to prepare blind vias in the SiO2 dielectric layer of the substrate. Specifically, CF4 and CHF3 were used as etching gases, with gas flow rates of 60 sccm and 15 sccm, respectively, and the etching time and RF power were 300 W and 300 s, respectively. The blind vias could be of any shape, such as circular, square, or diamond.

[0024] Furthermore, the photoresist was removed by reacting with O2 plasma, with a reaction gas O2 flow rate of 150 sccm, a reaction time of 3-15 min, and a RF power of 350 W, respectively.

[0025] Furthermore, the high-density barrier layer has a thickness of 10 to 50 nm and includes WN, TiN or TaN. The WN, TiN or TaN high-density barrier layer is prepared by magnetron sputtering technology, using a 99.99% pure high-purity W target, Ti target or Ta target as the target material, and a N2 / Ar mixed gas as the reaction gas, and the sputtering substrate with the substrate is placed for ±30 o Tilt rotation or planetary motion ensures uniform coverage of the high-density barrier layer on the bottom and sidewalls of the blind hole. Specifically, when preparing the high-density barrier layer WN, a high-purity W target with a purity of 99.99% is used as the target material, the volume ratio of N2 in the N2 / Ar reaction gas is 20%-40%, the substrate temperature is 200-300°C, and the sputtering power is 300-500 W. When preparing the high-density barrier layer TiN, a high-purity Ti target with a purity of 99.99% is used as the target material, the volume ratio of N2 in the N2 / Ar reaction gas is 20%-30%, the substrate temperature is 150-250°C, and the sputtering power is 200-300 W. When preparing the high-density TaN barrier layer, a high-purity Ta target with a purity of 99.99% is used as the target material, the volume ratio of N2 in the N2 / Ar reaction gas is 30%~50%, the substrate temperature is 200~350℃, and the sputtering power is 300~400W.

[0026] Furthermore, the NiTi shape memory alloy stress characterization layer has a thickness of 10-200 nm and is deposited using magnetron sputtering or atomic layer deposition. When using magnetron sputtering, the sputtering powers of the 99.99% pure high-purity Ni and Ti targets are 120 W and 80 W, respectively. The flow rate of 99.99% pure high-purity Ar gas is 20-40 sccm, and the substrate temperature is 200-400°C to promote crystallization. When using atomic layer deposition, when the Ni source precursor is Ni(dmamb)2 or Ni(Cp)2, the reducing agent is NH3 plasma; when the Ni source precursor is Ni(hfip)2, the reducing agent is H2 plasma; and when the Ti source precursor is TiCl4, the reducing agent is H2 plasma. Ni and Ti are deposited alternately, followed by annealing to form the NiTi shape memory alloy stress characterization layer.

[0027] Furthermore, a seed layer is prepared on the surface of the NiTi shape memory alloy stress characterization layer by electroplating, magnetron sputtering, or atomic layer deposition. The seed layer has a thickness of 20 to 100 nm and is made of Au, Ag, Cu, Pt, Co, or Ni.

[0028] Furthermore, direct current electroplating technology was used to fill the blind vias to prepare metal pads. Specifically, during the preparation process, the direct current electroplating solution consisted of 0.6-0.9 mol / L CuSO4·5H2O, 30-60 ppm NaCl, 10-20 ml / L H2SO4, 30-60 ppm Gelatin, and ultrapure water. The electroplating solution was electromagnetically stirred at a rate of 300-600 rpm, and the current density and electroplating temperature were 40-60 mA / cm2, respectively. 2 and 25~30 ℃. CuSO4·5H2O provides Cu 2+ Ions, H2SO4 enhance the conductivity of the plating solution and inhibit oxidation, NaCl provides Cl - ions to promote anodic dissolution and grain refinement, electromagnetic stirring to reduce concentration polarization and provide shear force to promote the formation and growth of nanotwins; the electroplating temperature is 25~30 ℃ to stabilize the activity of additives / inhibitors; the inhibitor Gelatin promotes the growth of (111) oriented columnar crystals containing high-density nanotwins and improves the blind hole filling rate.

[0029] Furthermore, after the metal pad is prepared, the bonding surface is subjected to mechanical chemical polishing, pickling and plasma activation treatment in sequence, and then hybrid bonding and annealing treatment are performed.

[0030] In a second aspect, the present invention provides a hybrid bonding structure containing a composite barrier layer prepared by the method.

[0031] In a third aspect, the present invention provides a method for detecting the stress of the barrier layer in the hybrid bonding structure containing the composite barrier layer, comprising the following steps: during or after the hybrid bonding and annealing treatment, detecting the deformation of the NiTi shape memory alloy stress characterization layer, and calculating and obtaining the stress of the barrier layer in combination with the stress-strain curve of the NiTi shape memory alloy stress characterization layer.

[0032] Furthermore, methods for detecting the deformation of the NiTi shape memory alloy stress characterization layer include but are not limited to scanning electron microscopy, atomic force microscopy or transmission electron microscopy.

[0033] Compared with the prior art, the present invention is beneficial in that:

[0034] 1. The composite barrier layer prepared in the present invention comprises a high-density barrier layer of WN, TaN, or TiN and a NiTi shape memory alloy stress characterization layer. The materials and processes used for preparation are relatively simple. The high-density barrier layer exhibits strong thermal stability and chemical inertness, isolating the dielectric layer from the metal pad and preventing metal atoms from diffusing into the dielectric layer. It also withstands various acid and alkaline solutions used in pickling and polishing processes, effectively maintaining its barrier function.

[0035] 2. The NiTi shape memory alloy stress characterization layer prepared by the present invention has excellent thermo-mechanical stress self-regulation performance. It can absorb strain and release stress through the reversible phase transformation of austenite and martensite during bonding and annealing, which can reduce the risk of desorption and peeling between the composite barrier layer and the dielectric layer and the metal pad, as well as the risk of rupture of the composite barrier layer itself.

[0036] 3. The composite barrier layer produced by the present invention combines the unique advantages of a high-density barrier layer and a NiTi shape memory alloy stress characterization layer. By detecting the deformation of the NiTi shape memory alloy stress characterization layer and calculating the barrier layer stress based on its stress-strain curve, the detection method is simple and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Flowchart of a method for preparing a hybrid bonding structure and detecting stress of a barrier layer in a hybrid bonding structure in a specific embodiment of the present invention;

[0038] Figure 2 Schematic diagram of the cross section of the substrate after spin coating photoresist on the surface to be bonded and drying to remove the solvent;

[0039] Figure 3 A schematic cross-sectional view of a substrate after a photomask is covered on a photoresist and exposed and developed to reveal a blind hole pattern;

[0040] Figure 4 The figure is a schematic cross-sectional view of the substrate after patterned blind vias are prepared using reactive ion etching technology and the photoresist is removed;

[0041] Figure 5 A schematic cross-sectional view of the substrate after a high-density barrier layer and a NiTi shape memory alloy stress characterization layer are sequentially prepared on the blind hole surface to form a composite barrier layer;

[0042] Figure 6 Schematic diagram of the cross-section of the substrate after preparing a seed layer on the outer surface of the composite barrier layer, filling the blind hole with electroplating to prepare a metal pad, and sequentially subjecting the bonding surface to mechanical chemical polishing, pickling, and plasma activation treatment;

[0043] Figure 7 is a schematic cross-sectional view of a hybrid bonding structure during hybrid bonding and annealing treatment;

[0044] Figure 8 This is an electron backscatter diffraction pattern of the surface of the metal pad manufactured by the present invention after mechanical chemical polishing, pickling and plasma activation treatment.

[0045] Figure 9 This is the stress-strain curve of the NiTi shape memory alloy stress characterization layer prepared in the present invention.

[0046] Figures 2 to 7 In the figure, A1 represents the chip, A2 represents the SiO2 dielectric layer, A3 represents the photoresist, A4 represents the blind hole located in the SiO2 dielectric layer, A5 represents the high-density barrier layer on the surface of the blind hole, A6 represents the NiTi shape memory alloy stress characterization layer on the surface of the high-density barrier layer, A7 represents the seed layer on the surface of the NiTi shape memory alloy stress characterization layer, and A8 represents the metal pad made by filling the blind hole by electroplating. DETAILED DESCRIPTION

[0047] The technical solutions of the present invention are described clearly and completely below. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0048] In the description of the present disclosure, the terms "upper", "lower", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and do not refer to or imply that the device or element must have a special direction, and should not be understood as limiting the present disclosure. The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, "multiple" means two or more, unless otherwise defined.

[0049] Throughout this disclosure, unless otherwise defined, terms such as "mounted," "connected," "connect," and "fixed" should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections, electrical connections, or communication; direct connections, indirect connections through an intermediary, or internal communication between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0050] It should be noted that, unless otherwise defined, the technical or scientific terms used in the present invention should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0051] Example 1

[0052] Embodiments of the present invention provide a hybrid bonding structure including a composite barrier layer and a method for detecting barrier layer stress in the hybrid bonding structure, which will be described below with reference to the accompanying drawings.

[0053] Figure 1 The following is a flowchart of the preparation of a hybrid bonded structure containing a composite barrier layer and the stress detection of the barrier layer in the hybrid bonded structure in a specific embodiment of the present invention.

[0054] 1. Ultrasonic cleaning of the substrate surface to be bonded was performed using acetone and isopropanol, respectively, to remove organic contaminants. The surface was then activated using O2 and Ar plasma. The O2 and Ar gas flow rates and volume ratios during activation were 100 sccm and 1:4, respectively. The treatment time and RF power were 75 s and 200 W, respectively.

[0055] 2. Spin-coat photoresist on the surface to be bonded, bake to remove the solvent, and then cover with a patterned photolithography mask. After exposure and development, a blind hole pattern appears on the surface to be bonded.

[0056] Figure 2 This is a cross-sectional schematic diagram of the substrate after spin coating photoresist on the surface to be bonded and drying to remove the solvent. In the figure, A1 is the chip, A2 is the SiO2 dielectric layer, and A3 is the photoresist.

[0057] Specifically, the chip is made of a 2-inch Si wafer; the SiO2 dielectric layer above the chip is 30 μm thick; the photoresist model is AZ5214, which is composed of phenolic resin, photosensitizer and solvent; the developer model is AZ400, which is diluted with ultrapure water (ultrapure water:AZ400 = 4:1) during development, and the development time is 45 s.

[0058] Figure 3A schematic cross-sectional view of a substrate after a photomask is covered on the photoresist and exposed and developed to reveal a blind hole pattern. In the figure, A1 is the chip, A2 is the SiO2 dielectric layer, and A3 is the photoresist.

[0059] Specifically, the blind hole pattern is a circle with a diameter of 15 μm, and the blind hole pattern spacing is 150 μm.

[0060] 3. Patterned blind holes are prepared and photoresist is removed by reactive ion etching technology, and a high-density barrier layer and a NiTi shape memory alloy stress characterization layer are prepared on the surface of the blind holes to form a composite barrier layer.

[0061] Figure 4 This is a schematic cross-sectional view of the substrate after patterned blind vias are prepared using reactive ion etching technology and after photoresist removal. In the figure, A1 is the chip, A2 is the SiO2 dielectric layer, and A4 is the blind via located in the SiO2 dielectric layer.

[0062] Specifically, the blind via has a depth of 5µm. The etchant gases CF4 and CHF3 were prepared at flow rates of 60 sccm and 15 sccm, respectively, with an etching time of 90 seconds and a radio frequency power of 300 W. The photoresist was removed by reacting with an O2 plasma to generate volatile products such as CO2, CO, and H2O. The O2 reaction gas flow rate was 150 sccm, and the etching time and radio frequency power were 4 minutes and 350 W, respectively.

[0063] Figure 5 This is a schematic cross-sectional view of the substrate after a high-density barrier layer and a NiTi shape memory alloy stress characterization layer are sequentially prepared on the surface of the blind hole to form a composite barrier layer. In the figure, A1 is the chip, A2 is the SiO2 dielectric layer, A4 is the blind hole located in the SiO2 dielectric layer, A5 is the high-density barrier layer, and A6 is the NiTi shape memory alloy stress characterization layer.

[0064] Specifically, the high-density barrier layer is TaN with a thickness of 20 nm, which is prepared by magnetron sputtering technology. The target material is a high-purity Ta target with a purity of 99.99%, the reaction gas is a N2 / Ar mixed gas with a N2 volume ratio of 30%, the substrate temperature and sputtering power are 250 ° C and 300 W respectively, the bias voltage is -75 V and the substrate is subjected to ± 30 oTilt rotation ensures uniform coverage of the high-density barrier layer at the bottom and sidewalls of the blind hole. The NiTi shape memory alloy stress characterization layer, 50 nm thick, was deposited using atomic layer deposition. The Ni source precursor was Ni(hfip)2, and the deposition process was as follows: a Ni(hfip)2 pulse for 2 s, an Ar purge for 5 s, a reducing H2 plasma pulse for 5 s, and an Ar purge for 10 s. The Ti source precursor was TiCl4, and the deposition process was as follows: a TiCl4 pulse for 3 s, an Ar purge for 8 s, a reducing H2 plasma pulse for 5 s, and an Ar purge for 10 s. Ni and Ti layers were deposited alternately in a 2:3 deposition cycle ratio at 250°C. After deposition, the layer was annealed at 400°C for 1 h in an atomic layer deposition chamber in an Ar atmosphere to promote alloying and the formation of an austenite phase in the NiTi shape memory alloy stress characterization layer.

[0065] 5. Prepare a seed layer on the surface of the composite barrier layer, fill the blind hole with DC electroplating to prepare a metal pad, and perform mechanical chemical polishing, pickling and plasma activation on the bonding surface in sequence, and then perform hybrid bonding and annealing.

[0066] Figure 6 A schematic cross-sectional view of the substrate after preparing a seed layer on the outer surface of the composite barrier layer, filling blind holes by electroplating to prepare metal pads, and sequentially subjecting the bonding surface to mechanical chemical polishing, pickling, and plasma activation treatment. In the figure, A1 is the chip, A2 is the SiO2 dielectric layer, A4 is the blind hole located in the SiO2 dielectric layer, A5 is the high-density barrier layer, A6 is the NiTi shape memory alloy stress characterization layer, A7 is the seed layer, and A8 is the metal pad.

[0067] Specifically, the seed layer has a thickness of 30 nm and is prepared using magnetron sputtering technology. The DC electroplating solution consists of 0.8 mol / L CuSO4·5H2O, 40 ppm NaCl, 40 ppm Gelatin, 20 mL / L H2SO4 and ultrapure water. The current density and electroplating temperature are 45 mA / cm 2 and 30 °C, and the electromagnetic stirring rate was 500 rpm.

[0068] Figure 7 This is a cross-sectional schematic diagram of the substrate to be bonded during the hybrid bonding and annealing process. In the figure, A1 is the chip, A2 is the SiO2 dielectric layer, A4 is the blind hole located in the SiO2 dielectric layer, A5 is the high-density barrier layer, A6 is the NiTi shape memory alloy stress characterization layer, A7 is the seed layer, and A8 is the metal pad.

[0069] Figure 8The electron backscatter diffraction pattern of the metal pad made by the present invention after mechanical chemical polishing, pickling and plasma activation treatment, the left picture is the fringe contrast picture, and the right picture is the fringe contrast + Z direction reverse polarity emitter picture. Figure 8 It can be seen that the grains on the surface of the metal pad have high (111) orientation and high-density nanotwin characteristics. The (111) oriented grain area accounts for 84.2%, and the average size of twins within the grains is about 225.3 nm.

[0070] 6. During or after the hybrid bonding and annealing process, the deformation of the NiTi shape memory alloy stress characterization layer is detected, and the stress of the composite barrier layer is calculated based on its stress-strain curve.

[0071] Figure 9 The stress-strain curve of the stress characterization layer of NiTi shape memory alloy. Figure 9 It can be seen that the ultimate tensile strength and strain of the NiTi shape memory alloy stress characterization layer are 761.4 MPa and 13.6%. At a maximum tensile strain of 5.8%, the NiTi shape memory alloy stress characterization layer can recover its deformation through its superelasticity or reversible phase transformation from martensite to austenite.

[0072] Test Example 1

[0073] The hybrid bonded structure prepared in Example 1 was bonded for 20 minutes in a vacuum environment at 25°C and a bonding pressure of 5 MPa. Annealing was then performed for 90 minutes at 250°C and 300°C, respectively, in a vacuum environment without bonding pressure. After annealing, the NiTi shape memory alloy stress characterization layer was observed using a focused dual-beam plasma beam microscope. Combined with the stress-strain curves of the NiTi shape memory alloy stress characterization layer, the composite barrier layer stresses were 181 MPa and 216 MPa after annealing at 250°C and 300°C, respectively.

[0074] The above specific embodiments describe the implementation of the present invention in detail, but the present invention is not limited to the specific details of the above embodiments. Within the scope of the claims and technical concept of the present invention, various simple modifications and changes can be made to the technical solution of the present invention, and these simple modifications all fall within the scope of protection of the present invention.

Claims

1. A method for preparing a hybrid bonding structure containing a composite barrier layer, characterized in that: The following steps are involved: Plasma activation treatment is performed on the surface of the substrate to be bonded; Evenly coating the surface of the substrate to be bonded with photoresist, covering it with a patterned photolithography mask, and exposing and developing it to reveal a blind hole pattern on the surface to be bonded; Prepare a blind hole on the surface to be bonded, remove the photoresist, and prepare a composite barrier layer on the surface of the blind hole; the composite barrier layer includes a high-density barrier layer and a NiTi shape memory alloy stress characterization layer; A seed layer and a metal pad are prepared on the surface of the NiTi shape memory alloy stress characterization layer, and hybrid bonding and annealing treatment are performed to obtain a hybrid bonding structure containing a composite barrier layer.

2. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 1, characterized in that: The thickness of the high-density barrier layer is 10-50 nm, the thickness of the NiTi shape memory alloy stress characterization layer is 10-200 nm, and the thickness of the seed layer is 20-100 nm.

3. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 2, characterized in that: The NiTi shape memory alloy stress characterization layer is prepared by magnetron sputtering or atomic layer deposition technology.

4. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 2, wherein: The high-density barrier layer includes WN, TiN or TaN.

5. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 4, characterized in that: The high-density barrier layer WN, TiN or TaN is prepared by magnetron sputtering technology.

6. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 2, wherein: The seed layer is prepared from materials including Au, Ag, Cu, Pt, Co or Ni.

7. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 1, characterized in that: Before the surface of the substrate to be bonded is subjected to plasma activation treatment, the surface of the substrate to be bonded is ultrasonically cleaned using acetone and isopropyl alcohol in sequence to remove organic pollutants.

8. The method for preparing a hybrid bonding structure containing a composite barrier layer according to claim 1, characterized in that: The plasma activation treatment of the surface to be bonded of the substrate includes but is not limited to the use of O2 and / or Ar plasma.

9. A hybrid bonded structure comprising a composite barrier layer prepared by the method according to any one of claims 1 to 8.

10. The method for detecting barrier layer stress in a hybrid bonding structure containing a composite barrier layer according to claim 9, characterized in that: The following steps are included: During or after the hybrid bonding and annealing treatment, the barrier layer stress is calculated and obtained by detecting the deformation of the NiTi shape memory alloy stress characterization layer and combining the stress-strain curve of the NiTi shape memory alloy stress characterization layer.

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