Bare chip and crystalline silicon wafer
By setting redundant test holes on the top metal of the bare chip, the problem of difficulty and high cost in making test pin cards caused by small spacing between bare chip functional test holes is solved, thereby achieving the effect of reducing the production cost of test pin cards.
Patent Information
- Application Number
- CN202510810628.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2018-09-18
- Publication Date
- 2025-09-19
AI Technical Summary
In the prior art, the test pin card is difficult to manufacture and has high cost due to the small spacing between the functional test holes on the bare chip.
At least two redundant test holes are set on the top metal of the bare chip. The distance between any two redundant test holes is greater than the distance between the functional test holes connected to them. The redundant test holes are used to replace the functional test holes connected to them and connect to the test pin card.
By adding redundant test holes with larger hole pitch, the spacing between test pins in the test pin card is increased, and the difficulty and cost of manufacturing the test pin card are reduced.
Smart Images
Figure CN120674409A_ABST
Abstract
Description
[0001] This application is a divisional application based on the application date of September 18, 2018, application number 201811086151.8, and invention name “A bare chip and a silicon wafer”. Technical Field
[0002] The embodiments of the present invention relate to the technical field of bare die testing, and in particular to a bare die and a silicon wafer. Background Art
[0003] A bare die is a set of integrated circuits formed by applying semiconductor manufacturing processes such as oxidation, photolithography, diffusion, epitaxy, and aluminum evaporation to a silicon wafer. Generally speaking, tens of thousands of bare die can be produced on a single silicon wafer. Once all the bare die on the silicon wafer are completed, they first undergo functional testing using a test probe card. Only after passing these functional tests can the bare die be packaged.
[0004] Typically, a test pin card is inserted directly into the functional test holes on a die to perform functional testing on the die. Because die are inherently smaller, the spacing between the functional test holes on the die is smaller. Furthermore, with thousands of die densely packed on a single silicon wafer, the test pins on the test pin card are correspondingly densely arranged, with very close spacing between the pins.
[0005] In the process of realizing the present invention, the inventors found that the prior art has the following defects: since the distance between the functional test holes on the bare chip is very short, it is difficult to manufacture the test pin card, thereby increasing the manufacturing cost of the test pin card. Summary of the Invention
[0006] In view of this, an embodiment of the present invention provides a bare die and a silicon wafer to reduce the difficulty of manufacturing a test pin card for the silicon wafer.
[0007] In a first aspect, an embodiment of the present invention provides a bare chip, comprising:
[0008] at least two redundant test holes disposed on the top metal layer of the die and respectively connected to different functional test holes of the die;
[0009] The distance between any two redundant test holes is greater than the distance between the two functional test holes connected thereto, and the redundant test hole is used to replace the functional test hole connected thereto and be connected to the test pin card corresponding to the bare chip.
[0010] In the above bare chip, optionally, the area of the redundant test hole is greater than or equal to the area of the functional test hole connected thereto.
[0011] In the above bare chip, optionally, the functional test hole includes at least two adjacent bonding holes, wherein the bonding holes are used for wire bonding;
[0012] The redundant test holes are not used for bonding.
[0013] In the above bare chip, optionally, the distance between any two of the redundant test holes is greater than a set distance threshold, and the area of the bare chip is greater than a set area threshold, wherein the set distance threshold matches the set area threshold.
[0014] In the above bare chip, optionally, the redundant test hole and the functional test hole connected thereto are connected through the top metal layer.
[0015] In the above bare chip, optionally, at least one of the redundant test holes is provided with a connection point in at least one other layer of metal other than the top layer of metal;
[0016] The redundant test hole and the functional test hole connected thereto are connected through the top metal layer and other metal layers except the top metal layer.
[0017] In a second aspect, an embodiment of the present invention provides a silicon wafer, comprising:
[0018] At least one bare chip according to any embodiment of the present invention.
[0019] An embodiment of the present invention provides a bare chip and a silicon wafer, wherein the bare chip includes at least two redundant test holes arranged on the top metal of the bare chip and respectively connected to different functional test holes of the bare chip, wherein the spacing between any two redundant test holes is greater than the spacing between the two functional test holes connected to them, and the redundant test holes are used to replace the functional test holes connected to them and connect to the test pin card corresponding to the bare chip, thereby solving the technical defects in the prior art that the functional test holes in the bare chip have small spacing, resulting in high difficulty and high production cost of the test pin card. By adding redundant test holes with larger hole spacing on the bare chip, the spacing between the test pins in the test pin card can be increased, thereby reducing the difficulty of producing the test pin card and further reducing the production cost of the test pin card. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a top view of a bare chip provided in the first embodiment of the present invention. DETAILED DESCRIPTION
[0021] In order to make the purpose, technical solutions and advantages of the present invention more clear, the following is a further detailed description of the specific embodiments of the present invention in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention.
[0022] It should also be noted that, for ease of description, only the part relevant to the present invention, rather than all of the content, is shown in the accompanying drawings. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processing or methods depicted as flow charts. Although flow charts describe various operations (or steps) as sequential processing, many operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of various operations can be rearranged. When its operation is completed, the processing can be terminated, but can also have additional steps not included in the accompanying drawings. The processing can correspond to methods, functions, procedures, subroutines, subprograms, etc.
[0023] Example 1
[0024] Figure 1 This is a top view of a die provided in Example 1 of the present invention. The die of this embodiment specifically includes:
[0025] At least two redundant test holes are arranged on the top metal of the bare chip and are respectively connected to different functional test holes of the bare chip, wherein the spacing between any two redundant test holes is greater than the spacing between the two functional test holes connected to them, and the redundant test holes are used to replace the functional test holes connected to them and be connected to the test pin card corresponding to the bare chip.
[0026] like Figure 1 In the bare chip shown, the circular holes numbered 1-11 are functional test holes, the circular holes numbered 12-16 are redundant test holes, the functional test holes numbered 1-7 are pressure welding holes for wire bonding, and the functional test holes numbered 8-11 are holes used only for functional testing. Figure 1 It is exemplarily shown that the bare chip is provided with five redundant test holes, of which three redundant test holes are provided corresponding to three bonding holes (round holes No. 4, 6 and 7) for wire bonding, and two redundant test holes are provided corresponding to holes (round holes No. 9 and 10) used only for functional testing.
[0027] What needs to be explained here is Figure 1 The shapes and positions of the functional test holes, the shapes and positions of the redundant test holes, the positional relationship and area relationship between the functional test holes and the redundant test holes, and the positions and paths of the connecting lines shown in the figure are all exemplary representations and do not impose any restrictions on the bare chip described in this embodiment.
[0028] In this embodiment, a bare die specifically refers to an integrated circuit formed by performing semiconductor manufacturing processes such as oxidation, photolithography, diffusion, epitaxy, and aluminum evaporation on a silicon wafer. Generally, a bare die is not packaged directly after fabrication, but only after passing functional testing.
[0029] Specifically, functional testing is typically performed simultaneously on all dies on a silicon wafer using a test pin card (the test pin card is inserted into all functional test holes on all dies on the wafer). The die have functional test holes on the top metal layer to facilitate functional testing with the test pin card. The functional test holes on a die may include only bonding holes for wire bonding, or they may include both bonding holes and holes used solely for functional testing.
[0030] Understandably, bare chips generally have a high level of integration, and the electronic components within them are densely arranged. Consequently, the placement of the bonding holes within the die is also relatively close, and the spacing between the bonding holes is relatively short. Furthermore, due to limitations on die size and the placement of electronic components within the die, the distances between holes used solely for functional testing, as well as the distances between holes used solely for functional testing and bonding holes, are relatively short.
[0031] Because the spacing between the bonding holes, the distance between the holes used only for functional testing, and the distance between the holes used only for functional testing and the bonding holes are all short, the spacing between the test pins in the test pin card is also short. It is understandable that the shorter the spacing between the test pins in the test pin card, the higher the manufacturing precision required for the test pin card, and thus the higher the manufacturing cost of the test pin card.
[0032] Therefore, in this embodiment, at least two redundant test holes connected to different functional test holes of the bare chip are provided on the top metal layer of the bare chip. The redundant test holes are used to replace the functional test holes connected thereto and connect to the test pin card corresponding to the bare chip. In other words, the positions and sizes of the test pins on the test pin card no longer need to be set completely corresponding to the functional test holes, but can be set to correspond partially or entirely to the redundant test holes. Furthermore, since the spacing between any two redundant test holes is greater than the spacing between the two functional test holes connected thereto (for example, the spacing between the redundant test holes can be greater than 400um), the spacing between some or all of the test pins in the test pin card can be increased accordingly, thereby reducing the manufacturing accuracy and manufacturing cost of the test pin card.
[0033] Furthermore, to further reduce the production cost of the test pin card, redundant test holes can be provided for all functional test holes on the die. However, due to the limitations of the die area, the location of electronic components on the die, and the location of connecting wires on the die, it may not be possible to provide redundant test holes for all functional test holes on some dies. In this case, redundant test holes should be provided for functional test holes with relatively shorter spacing to minimize the production cost of the test pin card.
[0034] In this embodiment, while redundant test vias are provided in the top metal layer, connection points for the redundant test vias can also be provided in other metal layers via connecting wires. It is understandable that, because many connecting wires are interlaced in each metal layer of the die, it is difficult to ensure that all redundant test vias can be connected to the functional test vias through the top metal layer. Therefore, it is sometimes necessary to connect the redundant test vias to the functional test vias in other metal layers. Figure 1 It is merely illustratively shown that all redundant test holes are connected to the functional test holes through the top metal layer.
[0035] An embodiment of the present invention provides a bare chip and a silicon wafer, wherein the bare chip includes at least two redundant test holes arranged on the top metal of the bare chip and respectively connected to different functional test holes of the bare chip, wherein the spacing between any two redundant test holes is greater than the spacing between the two functional test holes connected to them, and the redundant test holes are used to replace the functional test holes connected to them and connect to the test pin card corresponding to the bare chip, thereby solving the technical defects in the prior art that the functional test holes in the bare chip have small spacing, resulting in high difficulty and high production cost of the test pin card. By adding redundant test holes with larger hole spacing on the bare chip, the spacing between the test pins in the test pin card can be increased, thereby reducing the difficulty of producing the test pin card and further reducing the production cost of the test pin card.
[0036] Based on the above embodiment, the area of the redundant test hole may be greater than or equal to the area of the functional test hole connected thereto.
[0037] It is understandable that the thinner the test needles in the test needle card, the higher the production cost of the test needle card. Since the size of the test needle is determined by the area of the functional test hole, the larger the area of the redundant test hole used to replace the functional test hole and connect to the test needle corresponding to the bare chip is set, the larger the test needle can be set accordingly, and the production cost of the test needle card can be further reduced. Of course, the size of the bare chip, the position of the connecting wire in the top metal, and the size and position of the electronic components in the top metal will subject the area of the redundant test hole to certain restrictions. Furthermore, the areas of different redundant test holes can be the same or different.
[0038] Based on the above embodiment, the functional test hole may include at least two adjacent bonding holes, wherein the bonding holes are used for wire bonding; and the redundant test holes are not used for wire bonding.
[0039] Generally speaking, most functional test holes on a die are solder holes used for wire bonding, and the spacing between adjacent solder holes is generally small. A solder hole specifically refers to a hole located on the die that is used to connect to the die's packaged pins. Therefore, in this embodiment, providing two redundant test holes connected to at least two adjacent solder holes (these two redundant test holes are not used for wire bonding, but are only used to connect to a test pin card for functional testing of the die) can more effectively increase the spacing between two adjacent test pins on the test pin card, thereby reducing the production cost of the test pin card.
[0040] Based on the above embodiment, the distance between any two redundant test holes is greater than a set distance threshold, and the area of the die is greater than a set area threshold, wherein the set distance threshold matches the set area threshold.
[0041] It is understood that the spacing and number of redundant test holes cannot be set arbitrarily and must be adapted to the area of the die. In this embodiment, when the distance between any two redundant test holes is greater than a set distance threshold, the area of the die must also be greater than the set area threshold to ensure that the redundant test holes can be effectively arranged within the die with a spacing greater than the set distance threshold.
[0042] Based on the above embodiment, the redundant test hole and the functional test hole connected thereto are connected through the top metal layer.
[0043] In this embodiment, all redundant test holes are connected to the functional test holes through the top layer metal, rather than through other layers of metal other than the top layer metal. This arrangement eliminates the need to set connection points of the redundant test holes in the other layers of metal through connecting wires, thereby reducing the difficulty of making the redundant test holes and further reducing the difficulty of making the bare chip.
[0044] Based on the above embodiment, at least one redundant test hole sets a connection point in at least one other layer of metal other than the top layer of metal; the redundant test hole and the functional test hole connected to it are connected through the top layer of metal and / or through other layers of metal other than the top layer of metal.
[0045] It is understandable that if more redundant test holes are added, for example, a corresponding redundant test hole is added for each functional test hole, then, since some connecting wires and electronic components are already set in the top metal layer, it may be difficult to connect all redundant test holes to the corresponding functional test holes through the top metal layer. In this case, it is necessary to realize the connection between one or more redundant test holes and the functional test holes in other layers of metal other than the top metal layer. Accordingly, it is necessary to set the connection points of the redundant test holes in the above-mentioned other layers of metal through connecting wires. Furthermore, the connection between the redundant test holes and the functional test holes can be realized in multiple different other layers of metal mentioned above. Such a setting can add more redundant test holes to further reduce the production cost of the test pin card.
[0046] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.
Claims
1. A bare chip, characterized in that: include: Redundant test holes and functional test holes; The functional test holes include pressure welding holes for wire bonding and holes used only for functional testing; The functional test holes are arranged on the top metal layer of the die; at least two of the redundant test holes are respectively connected to different functional test holes of the die; The redundant test hole is used to replace the functional test hole connected thereto and is connected to the test pin card corresponding to the bare chip; the test pin card is used to perform a functional test on the bare chip; The area of the redundant test hole is greater than or equal to the area of the functional test hole connected thereto; The redundant test holes are arranged on the top metal layer of the die.
2. The die according to claim 1, wherein: The areas of different redundant test holes are the same, or the areas of different redundant test holes are different.
3. The die according to claim 1, wherein: The redundant test holes correspond to the functional test holes with a relatively shorter connection spacing.
4. The die according to claim 1, wherein: The distance between any two of the redundant test holes is greater than a set distance threshold, and the area of the die is greater than a set area threshold, wherein the set distance threshold matches the set area threshold.
5. The die according to claim 1, wherein: Some of the redundant test holes are connected to different bonding holes of the bare chip used for wire bonding; some of the redundant test holes are connected to different holes of the bare chip used only for functional testing.
6. The die according to claim 1, wherein: The die includes at least two redundant test holes; wherein at least one redundant test hole is connected to a bonding hole of the die for wire bonding; and at least one redundant test hole is connected to a hole of the die used only for functional testing.
7. A silicon wafer, characterized in that: include: At least one die according to any one of claims 1 to 6.
8. A test probe card for performing functional testing on a bare chip according to any one of claims 1 to 6, characterized in that: The positions and sizes of the test pins on the test pin card partially or entirely correspond to the redundant test hole settings of the bare chip.