Device with inverter function and adjustable trigger voltage

Abstract

The invention relates to a device with inverter function and adjustable trigger voltage. A device having an inverter function and an adjustable trigger voltage includes a PFET and an NFET connected in series. The FETs are multi-gate, and at least one FET is a threshold voltage (VT) programmable FET. In some embodiments, both FETs are bigate (i.e., having two gates), where at least one of the two gates is programmable (i.e., configured for VT programmability). In these embodiments, the device includes an input node connected to a primary gate of the FET and an additional node connected to a VT programmable secondary gate of the FET, respectively. Alternatively, the device includes an input node connected to a secondary gate of the FET and an additional node connected to a VT programmable main gate of the FET, respectively. Alternatively, the device includes an input node connected to the primary gate of the FET and another input node connected to the secondary gate of the FET, where the primary gate and / or the secondary gate are programmable.

Description

Technical Field

[0001] The present disclosure relates to inverters and similar devices having inverter functionality. Background Art

[0002] An inverter or a device having an inverter function is a device that is configured such that when the input voltage at the input node switches from a first logic value to a second logic value, the output voltage at the output node switches from a second logic value to a first logic value, and vice versa. A conventional inverter includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET) connected in series between a positive voltage rail (e.g., at a positive supply voltage (VDD)) and a ground rail (e.g., at 0.0 volts (V)). The device has an input node connected to the gates of the PFET and NFET and an output node located at the interconnection between the drain regions of the PFET and NFET. In operation, when the input voltage rises from a low voltage level to at least a trigger voltage (also called a trigger threshold or switching voltage), the output voltage drops to ground potential. Subsequently, when the input voltage drops from a high voltage level to below the threshold trigger voltage, the output voltage rises to VDD. In conventional inverters, the trigger voltage is typically at a fixed level (i.e., not adjustable). Summary of the Invention

[0003] Disclosed herein are embodiments of a device having an inverter function and an adjustable trigger voltage. In the disclosed embodiments, the device may include a first transistor (e.g., a P-channel field effect transistor (PFET)) and a second transistor (e.g., an N-channel field effect transistor (NFET)) connected in series via an interconnect. The first transistor and / or the second transistor may be a threshold voltage (VT) programmable transistor. In addition, the first transistor and the second transistor may have multiple gates. The device may also include an output node located at the interconnect.

[0004] In some embodiments, the device may include a first transistor (e.g., a VT-programmable PFET) and a second transistor (e.g., a VT-programmable NFET) connected in series with the first transistor via an interconnect. The first transistor may include a first main gate and a first sub-gate. Similarly, the second transistor may include a second main gate and a second sub-gate. The device may also include an output node located at the interconnect.

[0005] In some embodiments, the device may include a first transistor (e.g., a VT-programmable PFET) and a second transistor (e.g., a VT-programmable NFET). The first transistor may include a first main gate and a first sub-gate. Similarly, the second transistor may include a second main gate and a second sub-gate. The device may also include a first voltage input node and a second voltage input node, the first voltage input node being connected to the first main gate and the second main gate and also being connected to receive a first input voltage, the second voltage input node being connected to the first sub-gate and the second sub-gate and also being connected to receive a second input voltage. The device may also include: an interconnect connecting a first drain region of the first transistor and a second drain region of the second transistor such that the first transistor and the second transistor are connected in series. The device may also include an output node located at the interconnect.

[0006] It should be noted that all aspects, examples, and features of the disclosed embodiments mentioned in the above summary of the invention can be combined in any technically possible manner. That is, two or more aspects of any disclosed embodiment, including those described in the summary of the invention, can be combined to form an embodiment not specifically described herein. The details of one or more embodiments are set forth in the drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, as well as from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be better understood from the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0008] Figures 1A-1G are schematic diagrams respectively illustrating a device having an inverter function and an adjustable trigger voltage according to an embodiment disclosed herein;

[0009] Figure 2 is shown as a VT programmable field effect transistor incorporated into Figures 1A-1G A cross-sectional view of an example of a ferroelectric field effect transistor (FeFET) in a device;

[0010] Figure 3 is shown as a VT programmable field effect transistor incorporated into Figures 1A-1G A cross-sectional view of an example of a charge trap field effect transistor (CTFET) in a device;

[0011] Figure 4 is shown as a VT programmable field effect transistor incorporated into Figures 1A-1G a cross-sectional view of an example of a floating gate field effect transistor (FGFET) in a device of FIG.

[0012] Figures 5A-5G They are respectively realized in the semiconductor-on-insulator processing technology platform Figures 1A-1G Cross-sectional view of the device. DETAILED DESCRIPTION

[0013] As described above, an inverter or a device having an inverter function is a device that is configured such that when the input voltage at the input node switches from a first logic value to a second logic value, the output voltage at the output node switches from the second logic value to the first logic value, and vice versa. A conventional inverter includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET) connected in series between a positive voltage rail (e.g., at a positive power supply voltage (VDD)) and a ground rail (e.g., at 0.0 volts (V)). The device has an input node connected to the gates of the PFET and the NFET and an output node located at the interconnection between the drain regions of the PFET and the NFET. In operation, when the input voltage rises from a low voltage level to at least a trigger voltage (also called a trigger threshold or switching voltage), the output voltage drops to ground potential. Subsequently, when the input voltage drops from a high voltage level to below the threshold trigger voltage, the output voltage rises to VDD. In conventional inverters, the trigger voltage is typically at a fixed level (i.e., not adjustable).

[0014] In view of the above, embodiments of a device having inverter functionality and an adjustable trigger voltage are disclosed herein. The device may include two field effect transistors (FETs), specifically a P-channel field effect transistor (PFET) and an N-channel field effect transistor (NFET) connected in series between a positive voltage rail and ground. The FETs may be multi-gate, and at least one of the FETs may be a VT-programmable FET (e.g., an FeFET, etc.). In some embodiments, both FETs may be dual-gate (i.e., may have two gates), wherein at least one of the two gates is programmable (i.e., configured for VT programmability). In these embodiments, the device may include: a voltage input node that receives an input voltage and is connected to a VT-programmable or non-VT-programmable main gate (e.g., a front gate) of the FET; and an additional node that receives an independent bias voltage and is respectively connected to a VT-programmable sub-gate (e.g., a back gate) of the FET. Alternatively, the device may include: a voltage input node that receives an input voltage and is connected to a VT-programmable or non-VT-programmable sub-gate (e.g., a back gate) of the FET; and an additional node that receives an independent bias voltage and is respectively connected to a VT-programmable main gate (e.g., a front gate) of the FET. Alternatively, the device may include: a first voltage input node that receives a first input voltage and is connected to a main gate (e.g., a front gate) of a FET; and a second voltage input node that receives a second input voltage and is connected to a secondary gate (e.g., a back gate) of the FET, wherein the main gate and / or the secondary gate are VT programmable. In any case, the device may also include a voltage output node located at the interconnection between the drain regions of the two FETs. In such a device, by selectively adjusting the memory window (MW) of the main gate and / or the secondary gate of the PFET and / or NFET, the trigger voltage at which the output voltage at the voltage output node switches from logic "0" to logic "1" and vice versa can be finely adjusted. Specifically, the position, skew, and rise / fall time of the inverter trigger voltage can be controlled without a static power supply. For example, such a device with inverter functionality and adjustable trigger voltage can be incorporated into a logic device (e.g., an inverter or a NOT gate), a memory cell, etc.

[0015] More specifically, Figures 1A-1G 1 are schematic diagrams respectively illustrating devices 100A-100G having inverter functions and adjustable trigger voltage according to the disclosed embodiments.

[0016] In each of the disclosed embodiments, the device 100A-100G includes a first transistor 110 and a second transistor 120. The first transistor 110 is a P-channel field effect transistor (PFET). Specifically, the PFET 110 has a first source region 111, a first drain region 112, and a first channel region 113 located between the first source region 111 and the first drain region 112. Those skilled in the art will recognize that, typically, a PFET will include a P-type source / drain region (e.g., a P+ source / drain region) having a relatively high conductivity level and an N-type channel region (e.g., an N-channel region) or an intrinsic (i.e., undoped) channel region having a relatively low conductivity level. As discussed in more detail below, the PFET 110 may also include multiple gates adjacent to the first channel region 113. The second transistor 120 is an N-channel field effect transistor (NFET). Specifically, the NFET 120 has a second source region 121, a second drain region 122, and a second channel region 123 located between the second source region 121 and the second drain region 122. Those skilled in the art will recognize that, in general, an NFET will include an N-type source / drain region (e.g., an N+ source / drain region) with a relatively high conductivity level and a P-type channel region (e.g., a P-channel region) or an intrinsic (i.e., undoped) channel region with a relatively low conductivity level. As discussed in more detail below, the NFET 120 may also include multiple gates adjacent to the second channel region 123.

[0017] In each of the disclosed embodiments, the PFET 110 and the NFET 120 are electrically connected in series between a first voltage rail 191 (also referred to herein as the positive voltage rail) at a positive power supply voltage (VDD) level and a second voltage rail 192 (also referred to herein as the ground rail) at a ground potential (e.g., 0.0V). That is, the first source region 111 of the PFET 110 is electrically connected to the first voltage rail 191, and the second source region 121 of the NFET 120 is electrically connected to the second voltage rail 192. Furthermore, the first drain region 112 of the PFET 110 is electrically connected (e.g., via an interconnect) to the second drain region 122 of the NFET 120. For example, the interconnect can be a local interconnect (e.g., a silicide layer) extending through the top surfaces of the immediately adjacent first and second drain regions, a combination of a middle-of-the-line (MOL) contact and a back-end-of-the-line (BEOL) via / line, or any other suitable interconnect for electrically connecting the PFET and the NFET in series.

[0018] In each disclosed embodiment, at least one FET (ie, PFET 110 and / or NFET 120) is a VT programmable FET having at least one programmable gate (ie, configured for VT programmability).

[0019] For the purposes of this disclosure, a VT programmable transistor is a transistor having a gate structure specifically configured to implement VT programming. For example, depending on the bias conditions during the programming operation, the VT programmable transistor may exhibit a low VT or a high VT, or alternatively, any number of different VTs between low VT and high VT. Often, a VT programmable transistor will be used as a memory cell. For example, a VT programmable transistor with a low VT (also referred to herein as an unprogrammed state) can be read as storing a first stored data value (e.g., a logical value of "0"); while a VT programmable transistor with a high VT (also referred to herein as a programmed state) can be read as storing a second stored data value (e.g., a logical value of "1"). The memory window (MW) of a VT programmable transistor refers to the difference between high VT and low VT. The MW can be adjusted (e.g., based on device parameters, programming voltage, etc.); however, it must be large enough to ensure sufficient read margin and minimize read error rate.

[0020] Examples of VT programmable transistors include, but are not limited to, ferroelectric field effect transistors (FeFETs) (see, for example, Figure 2 ), charge trap field effect transistor (CTFET) (see Figure 3 ) and floating gate field effect transistors (FGFETs) (see, for example, Figure 4 ).

[0021] Specifically, Figure 2 is a cross-sectional view illustrating a FeFET 200 including a programmable gate, specifically a FeFET gate (Fe-G). The FeFET may include a channel region (C) located between source / drain (S / D) regions. The FeFET may be a P-channel FeFET. In this case, the S / D regions may have P-type conductivity at a relatively high conductivity level (e.g., they may be P+ source / drain regions). The channel region may have N-type conductivity at a relatively low conductivity level (e.g., it may be an N-channel region). Alternatively, the channel region may be undoped. The FeFET may also be an N-channel FeFET. In this case, the S / D regions may have N-type conductivity at a relatively high conductivity level (e.g., they may be N+ source / drain regions). The channel region may have P-type conductivity at a relatively low conductivity level (e.g., it may be a P-channel region). Alternatively, the channel region may be undoped.

[0022] The FeFET 200 may further include a FeFET gate (Fe-G) adjacent to the channel region. The Fe-G may be a multilayer structure, for example, including a gate dielectric layer 251 located on the channel region, a ferroelectric layer 252 (e.g., a hafnium oxide layer or some other suitable ferroelectric layer) located on the gate dielectric layer 251, and a gate conductor layer 254 located on the ferroelectric layer 252. The Fe-G may be selectively programmed so that the FeFET has a low VT, a high VT, or one or more VTs between low VT and high VT.

[0023] For example, to selectively program the Fe-G of a P-channel FeFET to have a high Vt, a positive voltage pulse (e.g., VDD) can be applied to the Fe-G, and 0.0 V can be applied to the S / D. This causes the polarization vector of the ferroelectric layer 252 to be directed toward the channel region (i.e., this causes the + pole of the di-pole of the ferroelectric layer 252 to be adjacent to the gate dielectric layer 251, and the - pole of the di-pole to be adjacent to the gate conductor layer 254), so that electrons are attracted to the channel region, thereby preventing a conductive region from forming in the channel region between the S / D. To selectively program the Fe-G of a P-channel FeFET to have a low Vt, either (a) a negative voltage pulse can be applied to the Fe-G, and 0.0 V can be applied to the S / D; or (b) 0.0 V can be applied to the Fe-G, and a positive voltage pulse can be applied to the S / D. This causes the direction of the polarization vector of the ferroelectric layer 252 to point toward the gate conductor layer 254 (i.e., this causes the + pole in the bipole of the ferroelectric layer 252 to be adjacent to the gate conductor layer 254, and the - pole in the bipole to be adjacent to the gate dielectric layer 251), so that electrons are repelled from the channel region, and holes are attracted to the channel region, thereby forming a conductive region between S / D.

[0024] To selectively program the Fe-G of an N-channel FeFET to have a low Vt, a positive voltage pulse (e.g., VDD) can be applied to the Fe-G, and 0.0 V can be applied to the S / D. This causes the polarization vector of the ferroelectric layer 252 to be directed toward the channel region (i.e., this causes the + pole of the bipolar portion of the ferroelectric layer 252 to be adjacent to the gate dielectric layer 251, and the - pole of the bipolar portion to be adjacent to the gate conductor layer 254), causing electrons to be attracted to the channel region, thereby forming a conductive region within the channel region between the S / D. To selectively program the Fe-G of an N-channel FeFET to have a high Vt, either (a) a negative voltage pulse can be applied to the Fe-G, and 0.0 V can be applied to the S / D; or (b) 0.0 V can be applied to the Fe-G, and a positive voltage pulse can be applied to the S / D. This causes the direction of the polarization vector of the ferroelectric layer 552 to point toward the gate conductor layer 254 (i.e., this causes the + pole in the bipole of the ferroelectric layer 552 to be adjacent to the gate conductor layer 254, and the - pole in the bipole to be adjacent to the gate dielectric layer 251), so that electrons are repelled from the channel region, thereby eliminating any conductive region between S / D.

[0025] Figure 3 is a cross-sectional view illustrating an example of a CTFET 300 including a programmable gate, specifically a CTFET gate (CT-G). The CTFET 300 may include a channel region (C) located between source / drain (S / D) regions. The CTFET may be a P-channel CTFET. In this case, the S / D regions may have P-type conductivity at a relatively high conductivity level (e.g., they may be P+ source / drain regions). The channel region may have N-type conductivity at a relatively low conductivity level (e.g., it may be an N-channel region). Alternatively, the channel region may be undoped. The CTFET may also include a CTFET gate (CT-G) adjacent to the channel region. The CT-G may be a multilayer structure, for example, including a gate dielectric layer 351 located on the channel region, a charge trap layer 352 (e.g., a silicon nitride layer) located on the gate dielectric layer 351, another gate dielectric layer 353 located on the charge trap layer 353, and a gate conductor layer 354 located on the gate dielectric layer 353. To selectively program the CT-G of the CTFET, a specific voltage is applied to the CT-G and S / D to move electrons into or out of the charge trap layer 352, thereby adjusting the VT.

[0026] Figure 4is a cross-sectional view showing an example of an FGFET 400 including a programmable gate, specifically an FGFET gate (FG). The FGFET 400 may include a channel region (C) located between source / drain (S / D) regions. The FGFET may be a P-channel CTFET. In this case, the S / D regions may have P-type conductivity at a relatively high conductivity level (e.g., they may be P+ source / drain regions). The channel region may have N-type conductivity at a relatively low conductivity level (e.g., it may be an N-channel region). Alternatively, the channel region may be undoped. The FGFET may also include an FGFET gate (FG) adjacent to the channel region. The FG may be a multi-layer structure, for example, including a gate dielectric layer 451 located on the channel region, a floating gate layer 452 (e.g., a polysilicon layer) located on the gate dielectric layer 451, another gate dielectric layer 453 located on the floating gate layer 452, and a gate conductor layer 454 located on the gate dielectric layer 453. To selectively program the FG of the FGFET, a specific voltage is applied to the FG and S / D to move electrons into or out of the floating gate layer 452, thereby adjusting VT.

[0027] Those skilled in the art will recognize that FETs can be single-gate. That is, they can include a single gate structure adjacent to the surface of the semiconductor body in the channel region. Alternatively, FETs can be multi-gate. That is, they can have multiple gates adjacent to different surfaces of the channel. In some multi-gate FETs, the different gates can be isolated from each other and independently biasable. For example, some dual-gate FETs can have two independently biasable gates; some tri-gate FETs can have three independently biasable gates, and so on. In addition, in at least some of these FETs with independently biasable gates, one or more gates may be programmable (i.e., configured for VT programmability), as described above and as Figure 2-4 shown.

[0028] Figures 1A-1GThe devices 100A-100G shown each have a FET including two independently biasable gates. Specifically, the PFET 110 (i.e., the first transistor) has a first main gate 115 and a first sub-gate 117 adjacent to opposite surfaces of the first channel region 113 and electrically isolated from each other. Similarly, the NFET 120 (i.e., the second transistor) has a second main gate 125 and a second sub-gate 127 adjacent to opposite surfaces of the second channel region 123 and electrically isolated from each other. Such a dual-gate FET with independently biasable gates can be used in a variety of different process technology platforms, such as a fully depleted semiconductor-on-insulator process technology platform (e.g., a fully depleted silicon-on-insulator (FDSOI) process technology platform), a non-planar device process technology platform (e.g., a fin field effect transistor (FinFET) process technology platform), etc. It should be understood that any of these process technologies can be used to implement Figures 1A-1G Devices 100A-100G.

[0029] For illustration purposes, Figures 5A-5G Examples of devices 100A-100G implemented in an advanced semiconductor-on-insulator processing technology platform (e.g., an FDSOI processing technology platform) are shown respectively. In this case, the semiconductor-on-insulator structure may include a semiconductor substrate 501. The semiconductor substrate 501 may be, for example, a single crystal silicon substrate, or may be a single crystal substrate of any other suitable semiconductor material (e.g., silicon germanium, etc.). The semiconductor-on-insulator structure may further include an insulator layer 505 located on the semiconductor substrate 501. The insulator layer 505 may include, for example, at least one layer of an insulator material (e.g., silicon dioxide or any other suitable insulator material). Alternatively, the insulator layer 505 may include multiple different insulator material layers. In some cases, as discussed in more detail below, different insulator material layers may be used to achieve back-gate VT programmability. The semiconductor-on-insulator structure may further include a semiconductor layer 508 located on the insulator layer 505. The semiconductor layer 508 may be, for example, a single crystal silicon layer or a layer of any other suitable single crystal semiconductor material (e.g., silicon germanium, etc.).

[0030] PFET 110 and NFET 120 may have respective active device regions in semiconductor layer 508. These active device regions may be laterally surrounded by isolation regions 509 (e.g., shallow trench isolation (STI) regions) extending through semiconductor layer 508 to insulator layer 505. PFET 110 may include a first channel region 113 within its active device region, laterally located between a first source region 111 and a first drain region 112. NFET 120 may include a second channel region 123 within its active device region, laterally located between a second source region 121 and a second drain region 122. Optionally, the source / drain regions may include raised portions (e.g., doped epitaxial semiconductor layers) located on the top surface of semiconductor layer 508. PFET 110 and NFET 120 may also include first and second main gates 115 and 125, respectively, located on the top surface of semiconductor layer 508 above first and second channel regions 113 and 123. The first main gate 115 and the second main gate 125 may be electrically isolated from adjacent source / drain regions by gate sidewall spacers.

[0031] Those skilled in the art will recognize that one advantage of a fully depleted semiconductor-on-insulator technology processing platform (e.g., an FDSOI processing technology platform) is that FETs can be formed on an insulator layer above a well region (e.g., an N-well or P-well) within a semiconductor substrate to implement different types of NFETs or PFETs with different threshold voltages (VT). For the purposes of this disclosure, a well region refers to a doped region of semiconductor material. A P-well is a P-type doped region, while an N-well is an N-type doped region. For ultra-low threshold voltage (SLVT) or low threshold voltage (LVT) devices, the PFET can be located on an insulator layer aligned above the P-well, and the NFET can be located on an insulator layer aligned above the N-well. For normal threshold voltage (RVT) or high threshold voltage (HVT) devices, the PFET can be located on an insulator layer aligned above the N-well, and the NFET can be located on an insulator layer aligned above the P-well. Whether a device is an SLVT or LVT (or, RVT or HVT) device will depend on the design (e.g., device size, etc.) and process specifications (e.g., dopant concentration, etc.). Another advantage of the fully depleted semiconductor-on-insulator (e.g., FDSOI) process technology platform is back biasing. Specifically, in this structure, the portion of the insulator layer and well region aligned below the channel region can effectively serve as the gate dielectric and gate conductor layers of the sub-gate (also called the back gate). The sub-gate can be biased by biasing the well region, which can be used to fine-tune VT. Forward back bias (FBB) refers to a back bias that reduces VT; while reverse back bias (RBB) refers to a bias that increases VT.

[0032] exist Figures 5A-5GIn the devices 100A-100G of FIG. 5 , the PFET 110 may be located on an insulator layer 505 above a P-well 504 within a semiconductor substrate 501, and the NFET 120 may be located on an insulator layer 505 above an N-well 503 within the semiconductor substrate 501. Thus, in this example, the PFET 110 and the NFET 120 would be LVT or SLVT FETs. Alternatively, the positions of the well regions may be swapped so that the PFET 110 and the NFET 120 are RVT or HVT FETs. In any case, a buried N-well 502 may be located within the semiconductor substrate 501 below the P-well 504 to isolate the P-well 203 from the lower portion of the semiconductor substrate 501. Thus, in FIG. Figures 5A-5G In the devices 100A-100G, portions of the insulator layer 505 and the P-well 504 below the first channel region 113 of the PFET 110 effectively serve as the gate dielectric layer and gate conductor layer of the first sub-gate 117, and portions of the insulator layer 505 and the N-well 503 below the second channel region 123 effectively serve as the gate dielectric layer and gate conductor layer of the second sub-gate 127 of the NFET 120.

[0033] Well taps can allow discrete electrical connections to the P-well 504 and the N-well 503, thereby allowing the first sub-gate 117 and the second sub-gate 127 to be biased, respectively. Specifically, a pair of well tap openings can extend vertically through the isolation region 509 and the insulator layer 505 to reach the P-well 504 and the N-well 503, respectively. The P-well tap 507 can be adjacent to the P-well 504 in one well tap opening and can have P+ conductivity. The P-well tap 507 can be an in-situ doped epitaxial semiconductor layer adjacent to the top surface of the semiconductor substrate 501 at the P-well 504. Alternatively, the P-well tap 507 can be a shallow P+ doped region located within the P-well 504. Similarly, the N-well tap 506 can be adjacent to the N-well 503 in another well tap opening and can have N+ conductivity. The N-well tap 506 can be an in-situ doped epitaxial semiconductor layer adjacent to the top surface of the semiconductor substrate 501 at the N-well 503. Alternatively, the N-well tap 506 may be a shallow N+ doped region within the N-well 503 .

[0034] like Figures 1A-1G As shown and also as Figures 5A-5G As shown, the main gates of the PFETs and NFETs and / or the sub-gates of the PFETs and NFETs in devices 100A-100G may be programmable (i.e., configured for VT programmability). Devices 100A-100G differ in that either the main gates or the sub-gates of PFET 110 and NFET 120 are programmable, or both the main gates and the sub-gates are programmable (i.e., configured for VT programmability).

[0035] For illustration purposes, Figures 5A-5G The PFETs 110 and NFETs 120 in the devices 100A-100G are shown as FeFETs, each having at least one ferroelectric gate (Fe-G). Each ferroelectric gate includes a gate dielectric layer 551 (e.g., silicon dioxide or any other suitable gate dielectric material), a gate conductor layer 554 (e.g., a doped semiconductor and / or metal gate conductor material), and a ferroelectric layer 552 (e.g., a layer of hafnium oxide or some other suitable ferroelectric material) located between and adjacent to the gate dielectric layer 551 and the gate conductor layer 554 (see above for details). Figure 2 Detailed discussion of ferroelectric gates of the PFET 110 and NFET 120 is provided below. However, it should be understood that, alternatively, the PFET 110 and NFET 120 may be CTFETs (each having at least one charge trapping gate), FGFETs (each having at least one floating gate), or any other suitable type of VT programmable FET with a programmable gate. In any case, when the PFET 110 and NFET 120 have non-programmable gates, the non-programmable gates are Figure 5A 、 5C , 5E and 5F are shown as including only a gate dielectric layer 551 (e.g., silicon dioxide or any other suitable gate dielectric material) and a gate conductor layer 554 (e.g., a doped semiconductor and / or metal gate conductor material). However, it should be understood that, alternatively, such a non-programmable gate may have any suitable non-programmable gate configuration.

[0036] In the disclosed embodiments, devices 100A-100G also differ in the number and location of input nodes and whether independent bias voltages are applied to any main or secondary gates.

[0037] refer to Figures 1A-1B and Figures 5A-5BIn device 100A, the first main gate 115 of PFET 110 and the second main gate 125 of NFET 120 are non-programmable, while the first sub-gate 117 of PFET 110 and the second sub-gate 127 of NFET 120 are programmable. In this case, the first main gate 115 and the second main gate 125 can be any suitable type of conventional gate structure (e.g., a gate-first polysilicon gate structure, a gate-first high-K metal gate (HKMG) structure, a replacement metal gate (RMG) structure, etc.), including a gate dielectric layer 551 and a gate conductor layer 554 adjacent to the gate dielectric layer 551. The first sub-gate 117 of PFET 110 and the second sub-gate 127 of NFET 120 can be, for example, ferroelectric gates. In device 100B, the first main gate 115, the second main gate 125, the first sub-gate 117, and the second sub-gate 127 are all programmable (i.e., configured for VT programmability). In this case, the first main gate 115, the second main gate 125, the first sub-gate 117, and the second sub-gate 127 can all be, for example, ferroelectric gates. A multi-layer insulator layer 505 can be used to implement the formation of a ferroelectric back gate in the first sub-gate 117 and the second sub-gate 127. For example, the insulator layer 505 can include a layer located below and adjacent to the semiconductor layer 508 (for example, a silicon dioxide layer or other suitable gate dielectric material layer, and used as a gate dielectric layer 551). The insulator layer 505 can also include a second layer located below and adjacent to the first layer (for example, hafnium oxide or some other suitable ferroelectric material for the ferroelectric layer 552).

[0038] In addition, in devices 100A and 100B, a voltage input node 101 can be electrically connected to receive an input voltage (Vin) and can also be electrically connected to a first main gate 115 of the PFET 110 and a second main gate 125 of the NFET 120, thereby applying Vin to these gates. Furthermore, in devices 100A and 100B, a pair of additional input nodes 103-104 can be electrically connected to a first sub-gate 117 and a second sub-gate 127, respectively (e.g., through well taps 507 and 506), and can also be electrically connected to receive independent bias voltages (Vfe1 and Vfe2), thereby applying Vfe1 to the first sub-gate 117 and Vfe2 to the second sub-gate 127.

[0039] refer to Figures 1C-1D and Figures 5C-5DIn device 100C, the first sub-gate 117 of the PFET 110 and the second sub-gate 127 of the NFET 120 are non-programmable, while the first main gate 115 of the PFET 110 and the second main gate 125 of the NFET 120 are programmable. In this case, the first main gate 115 and the second main gate 125 may be, for example, ferroelectric front gates. The first sub-gate 117 and the second sub-gate 127 may be conventional back gates. In device 100D, the first main gate 115, the second main gate 125, the first sub-gate 117, and the second sub-gate 127 may all be programmable. In this case, the first main gate 115, the second main gate 125, the first sub-gate 117, and the second sub-gate 127 may all be, for example, ferroelectric gates. As described above, a multi-layered insulator layer 505 may be used to form a ferroelectric back gate in the first sub-gate 117 and the second sub-gate 127. For example, the insulator layer 505 may include a layer (e.g., a silicon dioxide layer or other suitable gate dielectric material layer, used as the gate dielectric layer 551) located below and adjacent to the semiconductor layer 508. The insulator layer 505 may also include a second layer (e.g., hafnium oxide or some other suitable ferroelectric material, used as the ferroelectric layer 552) located below and adjacent to the first layer.

[0040] Furthermore, in devices 100C and 100D, a voltage input node 101 can be electrically connected to receive an input voltage (Vin) and can also be electrically connected to the first sub-gate 117 of the PFET 110 and the second sub-gate 127 of the NFET 120, thereby applying Vin to these gates. Furthermore, in devices 100C and 100D, a pair of additional input nodes 103-104 can be electrically connected to the first main gate 115 and the second main gate 125, respectively, and can also be electrically connected to receive independent bias voltages (Vfe1 and Vfe2), thereby applying Vfe1 to the first main gate 115 and Vfe2 to the second main gate 125.

[0041] Devices 100A-100D may also include a voltage output node 102 at the interconnection between PFET 110 and NFET 120, respectively, specifically at the interconnection electrically connecting the first drain region 112 of PFET 110 and the second drain region 122 of NFET 120. Devices 100A-100D have inverter functionality and adjustable trigger voltages. By independently adjusting Vfe1 and Vfe2, the position, skew, and rise / fall times of the inverter trigger voltage can be controlled without a static power supply. Vfe1 and Vfe2 can also be used to switch the ferroelectric gate receiving it to avoid destructive interference during readout. Each device 100A-100D can be incorporated into a logic device (e.g., an inverter or a NOT gate), a memory cell, etc. By including such a device in a memory cell, the memory window can be greatly enhanced.

[0042] refer to Figures 1E-1G and Figures 5E-5GIn the device 100E, the first main gate 115 of the PFET 110 and the second main gate 125 of the NFET 120 are non-programmable, while the first sub-gate 117 of the PFET 110 and the second sub-gate 127 of the NFET 120 are programmable. In this case, the first main gate 115 and the second main gate 125 can be any suitable type of conventional gate structure (e.g., a gate-first polysilicon gate structure, a gate-first high-K metal gate (HKMG) structure, a replacement metal gate (RMG) structure, etc.), which includes a gate dielectric layer 551 and a gate conductor layer 554 adjacent to the gate dielectric layer 551. The first sub-gate 117 of the PFET 110 and the second sub-gate 127 of the NFET 120 can be, for example, ferroelectric gates. In device 100F, the first main gate 115 of PFET 110 and the second main gate 125 of NFET 120 are programmable, while the first sub-gate 117 of PFET 110 and the second sub-gate 127 of NFET 120 are non-programmable. In this case, the first main gate 115 of PFET 110 and the second main gate 125 of NFET 120 can be, for example, ferroelectric front gates. The first sub-gate 117 and the second sub-gate 127 can be conventional back gates. In device 100G, the first main gate 115, the second main gate 125, the first sub-gate 117, and the second sub-gate 127 are programmable. In this case, the first main gate 115, the second main gate 125, the first sub-gate 117, and the second sub-gate 127 can all be, for example, ferroelectric gates. As with the devices 100A, 100B, and 100D described above, in the devices 100E and 100G, a multi-layer insulator layer 505 can be used to implement ferroelectric back gate formation in the first sub-gate 117 and the second sub-gate 127. For example, the insulator layer 505 can include a layer located below and immediately adjacent to the semiconductor layer 508 (e.g., a silicon dioxide layer or other suitable gate dielectric material layer, and serving as the gate dielectric layer 551). The insulator layer 505 can also include a second layer located below and immediately adjacent to the first layer (e.g., hafnium oxide or some other suitable ferroelectric material, serving as the ferroelectric layer 552).

[0043] Furthermore, in the devices 100E, 100F, and 100G, the first voltage input node 101 can be electrically connected to receive a first input voltage (Vin1) and can also be electrically connected to the first main gate 115 of the PFET 110 and the second main gate 125 of the NFET 120, thereby applying Vin1 to these gates. Furthermore, in the devices 100E, 100F, and 100G, the second voltage input node 105 can be electrically connected to receive a second input voltage (Vin2) and can also be electrically connected to the first sub-gate 117 of the PFET 110 and the second sub-gate 127 of the NFET 120, thereby applying Vin2 to these gates.

[0044] Devices 100E-100F may also include a voltage output node 102 at the interconnect between PFET 110 and NFET 120, respectively, specifically at the interconnect electrically connecting the first drain region 112 of PFET 110 and the second drain region 122 of NFET 120. Devices 100E-100G have inverter-like functionality (based on the combination of Vin1 and Vin2) and adjustable trigger voltages. The input voltage(s) connected to the ferroelectric gate can be used to control the position, skew, rise / fall time of the inverter trigger voltage in the absence of a static power supply, and can also be used to avoid destructive interference during readout. Each device 100E-100G can be incorporated into a logic device (e.g., an inverter or a NOT gate), a memory cell, etc. By including such a device in a memory cell, the memory window can be greatly enhanced. Furthermore, by selectively adjusting one input voltage connected to one set of ferroelectric gates, different Vout levels can be achieved in response to another input voltage applied to another set of gates (which may or may not be ferroelectric gates as described above).

[0045] It should be understood that Figures 5A-5G Without intending to be limiting, the disclosed devices may alternatively be implemented using any other type of technology processing platform in which a FET comprising two or more independently biasable gates, at least one of which may be programmable (i.e., configured for VT programmability) may be formed. Techniques for forming such FETs in different process technology platforms, such as in a fully depleted semiconductor-on-insulator process technology platform (e.g., an FDSOI process technology platform), as shown, or in a fin field effect transistor (FinFET) process technology platform, are well known in the art. Therefore, details of these techniques are omitted from this specification so that the reader can focus on the salient aspects of the disclosed embodiments involving the connection of the main gate and / or sub-gate of the PFET 110 and NFET 120 to (one or more) input nodes, to additional nodes for receiving bias voltages, etc., for adjusting the trigger voltage.

[0046] It should be understood that in the above methods and structures, semiconductor materials refer to materials whose conductive properties can be changed by doping with impurities. Exemplary semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining Group III elements such as aluminum (Al), gallium (Ga), or indium (In) with Group V elements such as nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). Pure semiconductor materials, more specifically, semiconductor materials that are not doped with impurities to increase conductivity (i.e., undoped semiconductor materials), are referred to in the art as intrinsic semiconductors. Semiconductor materials doped with impurities to increase conductivity (i.e., doped semiconductor materials) are referred to in the art as extrinsic semiconductors and will be more conductive than intrinsic semiconductors made from the same base material. That is, extrinsic silicon is more conductive than intrinsic silicon; extrinsic silicon germanium is more conductive than intrinsic silicon germanium; and so on. In addition, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity), and that the dopants can vary depending on the different semiconductor materials used. For example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, etc.) are typically doped with Group III dopants such as boron (B) or indium (In) to achieve P-type conductivity, while silicon-based semiconductor materials are typically doped with Group V dopants such as arsenic (As), phosphorus (P), or antimony (Sb) to achieve N-type conductivity. Gallium nitride (GaN)-based semiconductor materials are typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that the different levels of conductivity depend on the relative concentration levels of the dopant(s) in a given semiconductor region.

[0047] It should be understood that the terms used herein are used to describe the disclosed structures and methods and are not intended to be limiting. For example, as used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, as used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of a described feature, whole, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof. In addition, as used herein, when oriented and shown in the figures, terms such as "right," "left," "vertical," "horizontal," "top," "bottom," "upper," "lower," "below," "under," "underlying," "above," "overlying," "parallel," "perpendicular," and the like are intended to describe relative positions (unless otherwise indicated), and terms such as "touching," "directly in contact," "adjacent," "directly adjacent," "immediately adjacent," and the like are intended to indicate that at least one element is in physical contact with another element (with no other elements separating the elements). The term "laterally" is used herein to describe the relative positions of elements and, more specifically, to indicate that one element is to the side of another element, as opposed to above or below it, as the elements are oriented and shown in the figures. For example, an element positioned laterally adjacent to another element would be to the side of the other element, an element positioned laterally next to another element would be directly to the side of the other element, and an element laterally surrounding another element would be adjacent to and bordered by an outer sidewall of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the following claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

[0048] The above-described method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as tube cores, or in packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with either or both surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0049] The description of the various disclosed embodiments is provided for the purpose of illustration and is not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications or technical improvements to technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A device comprising: a first transistor comprising a P-channel field effect transistor; a second transistor comprising an N-channel field effect transistor, wherein the first transistor and the second transistor are connected in series by an interconnect and have multiple gates, and wherein at least one of the first transistor and the second transistor is a threshold voltage programmable transistor; and An output node is located at the interconnection.

2. The device according to claim 1, in, the interconnect connecting the first drain region of the first transistor to the second drain region of the second transistor, wherein the first transistor has a first source region connected to a positive voltage rail, and The second transistor has a second source region connected to a ground rail.

3. The device according to claim 1, in, The first transistor includes at least a first main gate and a first sub-gate, and The second transistor at least includes a second main gate and a second sub-gate.

4. The device according to claim 3, in, The first transistor and the second transistor are threshold voltage programmable transistors, and Wherein, the device further includes: a voltage input node connected to the first main gate and the second main gate and further connected to receive an input voltage; and Additional input nodes are connected to the first sub-gate and the second sub-gate, respectively, and are also connected to receive independent bias voltages.

5. The device according to claim 4, wherein The first sub-gate of the first transistor and the second sub-gate of the second transistor are programmable.

6. The device according to claim 4, wherein The first main gate and the first sub-gate of the first transistor and the second main gate and the second sub-gate of the second transistor are programmable.

7. The device according to claim 4, wherein The first transistor and the second transistor are ferroelectric field effect transistors.

8. The device according to claim 4, wherein The first transistor and the second transistor are a semiconductor-on-insulator structure.

9. A device comprising: a first transistor comprising a first main gate and a first sub-gate, wherein the first transistor is a P-channel field effect transistor with programmable threshold voltage; a second transistor including a second main gate and a second sub-gate, wherein the first transistor and the second transistor are connected in series through an interconnect, and wherein the second transistor is an N-channel field effect transistor with programmable threshold voltage; and An output node is located at the interconnection.

10. The device according to claim 9, in, the interconnect connecting a first drain region of the first transistor and a second drain region of the second transistor, wherein the first transistor has a first source region connected to a positive voltage rail, and The second transistor has a second source region connected to a ground rail.

11. The device according to claim 9, further comprising: a voltage input node connected to the first sub-gate and the second sub-gate and further connected to receive an input voltage; as well as Additional input nodes are connected to the first main gate and the second main gate, respectively, and are also connected to receive independent bias voltages.

12. The device according to claim 9, wherein The first main gate of the first transistor and the second main gate of the second transistor are programmable.

13. The device according to claim 9, wherein The first main gate and the first sub-gate of the first transistor and the second main gate and the second sub-gate of the second transistor are programmable.

14. The device according to claim 9, wherein The first transistor and the second transistor are ferroelectric field effect transistors.

15. The device according to claim 9, wherein The first transistor and the second transistor are a semiconductor-on-insulator structure.

16. A device comprising: a first transistor comprising a first main gate and a first sub-gate, wherein the first transistor is a P-channel field effect transistor with programmable threshold voltage; a second transistor comprising a second main gate and a second sub-gate, wherein the second transistor is an N-channel field effect transistor with programmable threshold voltage; a first voltage input node connected to the first main gate and the second main gate and further connected to receive a first input voltage; a second voltage input node connected to the first sub-gate and the second sub-gate and further connected to receive a second input voltage; an interconnect connecting the first drain region of the first transistor to the second drain region of the second transistor; and An output node is located at the interconnection.

17. The device according to claim 16, wherein The first transistor has a first source region connected to a positive voltage rail, and wherein the second transistor has a second source region connected to a ground rail.

18. The device according to claim 16, wherein At least the first main gate of the first transistor and the second main gate of the second transistor are programmable.

19. The device according to claim 16, wherein At least the first sub-gate of the first transistor and the second sub-gate of the second transistor are programmable.

20. The device according to claim 16, wherein The first main gate and the first sub-gate of the first transistor and the second main gate and the second sub-gate of the second transistor are programmable.

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