System and method for high accuracy open loop transconductance amplifier with gain set by output load

Abstract

Some examples of the present disclosure relate to systems and methods for calibrating and operating transconductance amplifiers for high bandwidth applications configured in an open loop configuration. Some examples of the present disclosure relate to setting a gain of the transconductance amplifier based on a value of an output load. Some examples of the present disclosure relate to modifying the bias of a transconductance amplifier using auto-zero circuitry and gain correction circuitry.

Description

Technical Field

[0001] This disclosure generally relates to systems and methods for continuous operation of a transconductance amplifier. Background Art

[0002] Transconductance amplifiers are commonly used to convert voltage to current signals and are often implemented in electronic devices such as switch-mode converters and power supplies. However, conventional transconductance amplifier designs are often unable to support applications requiring high bandwidth and fast transient response without unreasonably expanding the footprint of the circuitry implementing such amplifiers. Therefore, there is a need for transconductance amplifier topologies that reduce circuit board area while supporting both high-bandwidth and high-slew-rate implementations. Summary of the Invention

[0003] This generally relates to devices and / or systems that include transconductance amplifiers configured to support high bandwidth and fast output swing requirements. For example, the transconductance amplifiers can be operated in parallel and configured for use in systems with threshold bandwidth requirements (e.g., bandwidths greater than 10 MHz, 20 MHz, 50 MHz, etc.) and / or with threshold rise time requirements (e.g., less than 0.25, 0.5, 0.75, 1, 1.25, 1.5, or 3 ns). In particular, the plurality of transconductance amplifiers can be configured to (i) convert an input voltage to an output current in a transconductance stage and / or (ii) perform one or more calibration operations in one or more stages including an auto-zero substage and a gain offset correction substage (also referred to herein as a gain correction substage).

[0004] In some embodiments, a dual amplifier architecture is employed. While the first amplifier performs operations associated with (i) transconductance (e.g., converting voltage to current), the second amplifier performs operations associated with (ii) one or more calibration phases. Multiple transconductance amplifiers can be configured in an open-loop configuration and can reduce input offset and modify amplifier gain to support systems requiring threshold bandwidth and / or transient requirements. For example, during a first time period, the first transconductance amplifier is configured to function as a voltage-to-current converter between a shared input and output of the dual amplifier, and the second transconductance amplifier is configured to perform one or more calibration phases (e.g., an auto-zero subphase followed by a gain offset correction subphase) while decoupled from the shared input and output of the dual amplifier. During a second time period, the operations of each amplifier in the dual amplifier are reversed. The first transconductance amplifier is configured to perform one or more calibration phases, while the second transconductance amplifier functions as a voltage-to-current converter between the shared input and output of the dual amplifier. During a first time period and a second time period, a respective one of the first and second transconductance amplifiers is coupled between a first input node and an output node such that the respective one of the first transconductance amplifier or the second transconductance amplifier is configured to perform a transconductance measurement with respect to the same input node and output node while the other amplifier performs one or more calibration phases while being decoupled from the input node and output node of the respective amplifier. In some embodiments, the dual amplifier uses input and output switches to implement calibration (e.g., auto-zeroing and gain offset correction) on every other clock cycle.

[0005] A full description of these examples is provided in the drawings and detailed description, with the understanding that this summary does not limit the scope of the disclosure in any way. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] For a better understanding of the various examples described herein, reference should be made to the following detailed description and the following drawings. Throughout the drawings, like reference numerals generally refer to corresponding parts.

[0007] Figure 1 An example flow chart illustrating a method of configuring a transconductance amplifier for calibration and operation according to an embodiment of the present disclosure is shown.

[0008] Figure 2 A transconductance amplifier topology according to an embodiment of the present disclosure is shown.

[0009] Figure 3 A transconductance amplifier topology according to an embodiment of the present disclosure is shown.

[0010] Figure 4 A timing diagram illustrating a plurality of input switches and a plurality of output switches according to an embodiment of the present disclosure is shown.

[0011] Figure 5 A timing diagram illustrating a transconductance amplifier topology according to an embodiment of the present disclosure.

[0012] Figure 6 Shown is a switch configuration of a transconductance amplifier topology according to an embodiment of the present disclosure.

[0013] Figure 7 Control circuitry for controlling a transconductance amplifier topology according to an embodiment of the present disclosure is shown.

[0014] Figure 8 A transconductance amplifier topology including auto-zero circuitry according to an embodiment of the present disclosure is shown.

[0015] Figure 9 A transconductance amplifier topology including gain correction circuitry according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0016] This generally relates to devices and / or systems that include transconductance amplifiers configured to support high bandwidth and fast output swing requirements. For example, the transconductance amplifiers can be operated in parallel and configured for use in systems with threshold bandwidth requirements (e.g., bandwidths greater than 10 MHz, 20 MHz, 50 MHz, etc.) and / or with threshold rise time requirements (e.g., less than 0.25, 0.5, 0.75, 1, 1.25, 1.5, or 3 ns). In particular, the plurality of transconductance amplifiers can be configured to (i) convert an input voltage to an output current in a transconductance stage and / or (ii) perform one or more calibration operations in one or more stages including an auto-zero substage and a gain offset correction substage (also referred to herein as a gain correction substage).

[0017] In some embodiments, a dual amplifier architecture is employed. While the first amplifier performs operations associated with (i) transconductance (e.g., converting voltage to current), the second amplifier performs operations associated with (ii) one or more calibration phases. Multiple transconductance amplifiers can be configured in an open-loop configuration and can reduce input offset and modify amplifier gain to support systems requiring threshold bandwidth and / or transient requirements. For example, during a first time period, the first transconductance amplifier is configured to function as a voltage-to-current converter between a shared input and output of the dual amplifier, and the second transconductance amplifier is configured to perform one or more calibration phases (e.g., an auto-zero subphase followed by a gain offset correction subphase) while being decoupled from the shared input and output of the dual amplifier. During a second time period, the operations of each amplifier in the dual amplifier are reversed. The first transconductance amplifier is configured to perform one or more calibration phases, while the second transconductance amplifier functions as a voltage-to-current converter between the shared input and output of the dual amplifier. During a first time period and a second time period, a respective one of the first and second transconductance amplifiers is coupled between a first input node and an output node such that the respective one of the first transconductance amplifier or the second transconductance amplifier is configured to perform a transconductance measurement with respect to the same input node and output node while the other amplifier performs one or more calibration phases while being decoupled from the input node and output node of the respective amplifier. In some embodiments, the dual amplifier uses input and output switches to implement calibration (e.g., auto-zeroing and gain offset correction) on every other clock cycle.

[0018] In the embodiments described herein, it will be understood that the singular forms used in the following description (e.g., "a," "an," and "the") are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" used in the following description is intended to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "includes," "including," "comprises," and / or "comprising" used in the following description are intended to specify the presence of stated features, integers, steps, operations, elements, components, and / or units, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, units, and / or groups thereof.

[0019] Certain aspects of the present disclosure include the process steps, operations, and / or instructions described herein. It should be understood that the process steps, instructions, and / or operations of the present disclosure may be embodied in software, firmware, and / or hardware. When embodied in software, the process steps, instructions, and / or operations of the present disclosure may be downloaded to reside on and operate from different platforms used by various operating systems.

[0020] It should be understood that example devices that include the circuit systems described herein and / or communicate with the circuit systems described herein may be envisioned without departing from the scope of the present disclosure. For example, the device is optionally a switch mode power supply, a power management integrated circuit, an application specific integrated circuit, an on-chip solution, a circuit board including various integrated circuits, and / or the like that includes the switching circuit systems, amplifiers, interconnects, and / or passive components described herein. The device may include a logic storage device, such as an electrical, magnetic, and / or optical memory (e.g., including random access memory, cache, hard drive, and / or other non-transitory computer-readable medium). The device may include an interface circuit system to detect, monitor, buffer, and / or store measurements of current, voltage, and the like at various nodes included in the circuit system. In some embodiments, the storage device stores one or more instructions, the one or more instructions including instructions to configure switches, sequence switches, change voltages, change currents, bias the circuit system, route inputs to amplifiers, and route outputs from amplifiers, etc., in order to perform at least reference Figure 1-9 In some embodiments, the circuitry disclosed herein may be at least partially distributed among multiple devices, such as among multiple integrated circuits.

[0021] Figure 1 An example flow chart illustrating a method of configuring a transconductance amplifier to perform calibration and transconductance operations in one or more phases according to an embodiment of the present disclosure is shown. For example, the transconductance amplifier performs one or more calibration phases, including performing an auto-zero operation (102a) during an auto-zero subphase and performing a gain correction operation (102b) during a gain correction subphase. After the one or more calibration operations, the transconductance amplifier performs a transconductance operation (102c) as a run-time measurement. As described herein, it should be understood that conventional transconductance amplifier topologies are typically subject to high current (e.g., 5, 10, 20, 30, 40, or 50A), high speed, and / or high temperature operation (e.g., from -50 ℃ to 200 ℃ Insufficient bandwidth and / or insufficient transient characteristics required to maintain stability. For example, performing one or more of the above-mentioned calibration operations followed by a transconductance operation during a calibration phase reduces the bandwidth and / or requires many switching operations in the signal path that may introduce transients.

[0022] The methods and apparatus described herein relate to a parallel transconductance amplifier topology in which different amplifiers are configured to perform different operations in parallel. This parallel operation enables continuous operation of at least one amplifier for transconductance operation, while calibration of the other amplifier can be performed in parallel without affecting the transconductance operation. For example, for a dual amplifier, during a first time period, the first amplifier performs a transconductance operation in which a measured input voltage is converted to an output current (e.g., the first amplifier is configured to be in an operating mode during the first time period to perform transconductance operation (102c)), while the second amplifier is configured to perform one or more calibration operations (e.g., the second amplifier is configured to be in a calibration mode during the first time period to perform auto-zero operation (102a) and gain correction operation (102b)). During a second time period different from the first time period, the operations of the first and second amplifiers are reversed. The first amplifier is configured to perform one or more calibration operations (auto-zero operation (102a) and gain correction operation (102b)), while the second amplifier is configured to perform transconductance operation (transconductance operation (102c)).

[0023] Figure 1 Thus, the calibration and operation phases of the respective amplifiers of a dual-parallel transconductance amplifier topology are illustrated, but it should be understood that the other amplifier in parallel with the respective amplifier is configured to perform the same operation offset in time (e.g., the other amplifier performs a transconductance operation while the respective amplifier performs one or more calibration operations, or performs one or more calibration operations while the respective amplifier operates). It should be further understood that additional amplifiers (e.g., more than two) may be configured in parallel with the at least one amplifier configured to perform a transconductance operation during the operation phase, with the additional amplifiers performing one or more of the calibration sub-phases described herein in parallel while the operation phase amplifier measures transconductance. For example, for a three-amplifier transconductance amplifier topology, during a first time period, the first amplifier is configured to perform a transconductance operation, the second amplifier is configured to perform an auto-zero operation, and the third amplifier is configured to perform a gain correction operation. During a second time period, the third amplifier is configured to perform a transconductance operation, the first amplifier is configured to perform an auto-zero operation, and the second amplifier is configured to perform a gain correction operation. During a third time period, the second amplifier is configured to perform a transconductance operation, the third amplifier is configured to perform an auto-zero operation, and the first amplifier is configured to perform a gain correction operation. Additionally, it will be appreciated that increasing the number of amplifiers in parallel allows some of the amplifiers to be idle while the others perform Figure 1 Additionally, it will be appreciated that, although described as non-overlapping stages, increasing the number of amplifiers enables some overlap between the auto-zero sub-stages, gain correction sub-stages, and measurement sub-stages applied at the different amplifiers.

[0024] The auto-zero sub-stage is used to mitigate undesirable drift in a transconductance amplifier. For example, a natural offset voltage may exist and / or be generated between the terminals of a transconductance amplifier configured in an open-loop configuration. This offset voltage may undesirably alter or affect one or more characteristics of the transconductance amplifier, such as amplification characteristics. In some embodiments, the auto-zero sub-stage may limit the input offset voltage between the amplifier's input terminals so that the voltage across a load coupled to the amplifier's output is less than a threshold voltage.

[0025] Figure 2-3 A transconductance amplifier topology according to an embodiment of the present disclosure is shown, having a first amplifier configured for transconductance operation and a second amplifier configured for auto-zero operation (in Figure 2 in) or gain correction operation (in Figure 3 The switching circuit system implements the configuration of the first amplifier or the second amplifier for the aforementioned operation. For example, the switching circuit system included in the transconductance amplifier topology (or in the device including the transconductance amplifier topology) is configured to be in a first configuration. In the first configuration, one or more input switches and one or more output switches, such as Figure 2 The input switch 206 and the output switch 208 shown in FIG are arranged to couple the first amplifier 202 between the input and output of the transconductance amplifier topology. IN The input 210 is coupled differentially to the input of amplifier 202 using switches 214 and 216 (e.g., single-pole, dual-rotation switches); OUT The output denoted by 211 is coupled to the output of the amplifier 202 using a switch 222 and is coupled to an output load 226 (Z LOAD ). The first amplifier is kept at Figure 3 In the same configuration shown in .

[0026] like Figure 2 As shown in FIG, during an auto-zero operation, one or more input switches, such as switch 236, are arranged to couple (e.g., short) Figure 2 . Additionally, in the first configuration, one or more output switches included in the switching circuitry may be configured to couple the output of the second amplifier 204 to the auto-zero amplifier. For example, Figure 2 As shown in FIG, the second amplifier 204 is coupled to the auto-zero amplifier 243 (or another auto-zero amplifier, such as the auto-zero amplifier 243 or the auto-zero amplifier 241) and to one or more compensation capacitors (e.g., Figure 8 For ease of explanation, capacitors 260 and 262 in FIG. Figure 2 not shown).

[0027] When the input of the second amplifier 204 is shorted, the auto-zero amplifier operates to automatically zero the output to the operating output voltage of the second amplifier 204. Balancing the auto-zero amplifier allows the compensation capacitor associated with the auto-zero amplifier to store charge through the correction current (CC). For example, Figure 8 A transistor-level circuit schematic diagram of an example amplifier 202 and an example auto-zero amplifier 241 is shown. Figure 8 The capacitor 262 and / or the capacitor 260 shown in FIG. 1 may be shorted together when the inputs of the first amplifier 202 are shorted together (e.g., when Figure 8 The control signal coupled to auto-zero terminal 272 may also enable one or more switches, such as switch 276, switch 278, and / or switch 284. A combination of transistors and / or passive circuitry (e.g., resistors, capacitors), and / or logic gates causes capacitors 260 and 262 to charge as the voltage offset between the inputs of the differential pair decreases (e.g., to 0V, or within a threshold voltage of 0V, such as less than 100nV, 1μV, 500μV, 1mV, etc.). Thus, auto-zero electronics 200 may adjust the bias of the transconductance amplifier until one or more criteria are met, including a criterion that is met when the voltage offset between the inputs of the transconductance amplifier is less than a threshold level. Thus, in this first configuration, the device may determine a correction capacitance (e.g., provided via an auto-zero amplifier coupled to compensation capacitors 260 and / or 262) to minimize (or zero) the input offset of second amplifier 204. After the auto-zero operation is complete, the compensation capacitor is partially decoupled, but the correction voltage is maintained to maintain the input offset at or near zero for gain correction operation. In some embodiments, the auto-zero amplifier is a Class B amplifier, so that the quiescent current is reduced (e.g., to or near zero) while reducing the input offset of the second amplifier 204.

[0028] In some embodiments, the transconductance of the transconductance amplifier may vary from a nominal value due to drift in the amplifier and / or other circuitry that biases the amplifier. To mitigate drift, and optionally after performing an auto-zero calibration subphase, the apparatus performs a gain correction (102b) during a gain correction subphase. The gain correction subphase, included as a subphase of one or more calibration phases, includes modifying the bias of the transconductance amplifier (e.g., current bias I BIAS ), thereby modifying the gain of the amplifier. For example, Figure 3A second configuration is shown for biasing the second amplifier 204 using bias circuitry 232. The switches for the first amplifier 202 remain the same in the second configuration as in the first configuration. In some embodiments, the transconductance amplifier is biased using analog circuitry (e.g., analog circuitry that detects gain offset), and analog feedback is provided to the transconductance amplifier based on operating conditions detected during the closed-loop calibration sub-phase. In some embodiments, the transconductance amplifier is biased using a current source controlled by a controller (e.g., controller 239). The device may configure the switch circuitry to be in a configuration for gain correction (a second configuration) that is different from the configuration required to perform auto-zero calibration. The different configurations may include coupling the input of the second amplifier 204 to a reference voltage (e.g., corresponding to a reference voltage). Figure 2-3 V in cal 212), coupling the output of the transconductance amplifier to an output load (e.g., an attenuation network, such as a network including load 226 and calibration load 228), and measuring the difference between the voltage developed across the output load and the target voltage.

[0029] In some embodiments, V cal 212 and / or resistor 266 represent one or more semiconductor devices (e.g., field effect transistors (FETs), bipolar junction transistors (BJTs), thyristors, etc.) and / or one or more passive devices (e.g., resistors, capacitors, and / or inductors) configured to generate a calibration voltage across the terminals of the second amplifier 204. In some embodiments, V cal 212 and resistor 266 represent an input attenuation network (e.g., a ladder of multiple resistors) that taps a reference voltage (e.g., coupled to a voltage supply rail of the electronic device 200). In some embodiments, V cal 212 corresponds to an input voltage (e.g., 1, 5, 10, 15, 30, or 50 mV) that may be coupled across the terminals of a transconductance amplifier for a gain correction substage (e.g., different from the auto-zero substage) included in the calibration phase, which may be predetermined based on different implementations and / or operating conditions required by the electronic device 200.

[0030] In some embodiments, the device uses a gain correction amplifier (e.g., a current bias amplifier) ​​as a control signal to change the bias point of the transconductance amplifier until the voltage across the calibrated load reaches a target voltage and / or meets one or more criteria, including a criterion that is met when the target voltage is stable within a threshold voltage (e.g., + / - 10 mV) of the target voltage (e.g., 200 mV when a 10 mV offset is applied across the amplifier input). Figure 9 An example shunt transconductance amplifier topology including gain correction circuitry is shown. For example, in Figure 9, amplifier 290 provides a current bias to the first amplifier 202 (from the “iout” terminal), and amplifier 292 provides a current bias to the second amplifier 204 (from the “iout” terminal), based on the voltage measured across the calibration load 228 during the corresponding gain correction sub-phase.

[0031] In some embodiments, the transconductance amplifier topology (or an apparatus including the transconductance amplifier topology) maintains the zero offset and / or current bias of the second amplifier 204 determined during one or more calibration phases (e.g., during the auto-zero and / or gain correction sub-phases) while the second amplifier 204 is later "running" (e.g., performing transconductance measurement (102c)). For example, a voltage stored across a correction capacitor (e.g., determined during the auto-zero sub-phase) and / or by connecting the correction capacitor to a trim terminal and an output stage or input stage of the amplifier to maintain the bias point of the amplifier (e.g., determined during the gain correction sub-phase). For example, Figure 8 The voltage across capacitors 260, 262 shown in FIG is detected and held during the gain correction sub-phase for use in determining a gain correction bias current and / or held during an operation phase of the second amplifier (e.g., or transconductance amplifier 202). Such correction (e.g., auto-zero hold voltage and / or amplifier bias current I BIAS ) can be applied to the second amplifier so that when a voltage is applied to the input of the calibrated amplifier, the amplifier output voltage matches or nearly matches the target voltage (e.g., within a threshold, such as 0.5%, 1%, 2% of the target voltage, or other suitable threshold). After compensating for any input offset and gain drift (e.g., performed during steps 102a and 102b), the amplifier is configured for transconductance operation to convert the voltage input signal into a current output signal.

[0032] As described herein, when the first amplifier 202 performs one or more calibration phases and the second amplifier 204 performs a transconductance operation, the switching circuitry included in the transconductance amplifier topology (or in an apparatus including the transconductance amplifier topology) is configured to be in a third configuration. The third configuration is similar to the first configuration, but the operations of the first amplifier 202 and the second amplifier 204 are swapped. In the third configuration, one or more input switches and one or more output switches are arranged to couple the second amplifier 204 between the input and output of the transconductance amplifier topology. For example, by V IN The input denoted by 210 is differentially coupled to the input of the second amplifier 204 using switches 218 and 220; OUT The output denoted by 211 is coupled to the output of the second amplifier 204 using a switch 224 and is coupled to an output load 226 (Z LOAD ). In some embodiments, V in210 is a voltage source representing the input voltage that the electronic device 200 converts into current. It should be understood that V in 210 is only an example of a voltage that can be sensed, and the input voltage may include circuitry that is different from or greater than the exemplary voltage source. For example, V in 210 optionally corresponds to an output voltage generated by a DC-DC converter, a low dropout regulator, and / or the like coupled to the electronic device 200. Additionally or alternatively, V in 210 optionally corresponds to a voltage developed across a resistor included in the SMPS (eg, a current sensing shunt resistor).

[0033] In a similar way, Figure 2 Mirroring the process, in a third configuration, during an auto-zero operation for the first amplifier, one or more input switches, such as switch 234, are arranged to couple (e.g., short) the input of the first amplifier 202, and one or more output switches included in the switch circuitry can be configured to couple the output of the first amplifier 202 to the auto-zero amplifier 241 and to one or more compensation capacitors (e.g., similar to capacitors 860, 862). For the sake of brevity, the details of auto-zero are not repeated here. Similar to Figure 3 In the fourth configuration, the input of the first amplifier 202 is coupled to the reference voltage V using switches 214 and 216. cal 212, and the output of the transconductance amplifier is coupled to an output load (e.g., an attenuation network, such as including calibration load 228) using switch 222. The details of the gain correction operation are not repeated for first amplifier 202, but instead first amplifier 202 is biased using bias circuitry 230 using a control signal from controller 237. During the fourth configuration, second amplifier 204 remains in a configuration for transconductance operation (e.g., the same as the third configuration, which is not repeated for brevity).

[0034] although Figure 2-3 Separate auto-zero amplifiers 241 and 243 are shown that are dedicated to the first amplifier 202 and the second amplifier 204, respectively, but alternative embodiments may use a single auto-zero amplifier that switches between the first amplifier 202 and the second amplifier 204 depending on which amplifier is configured for auto-zero operation (e.g., a first configuration couples a shared auto-zero amplifier to the second amplifier 204, and a third configuration couples the shared auto-zero amplifier to the first amplifier 202).

[0035] It should be understood that the electronic device 200 can include a greater number of switches, a fewer number of switches, and / or be implemented using switches having a greater number of poles and / or throws or a fewer number of poles and / or throws, such that the transconductance amplifier described herein can be coupled to an input voltage, coupled to a calibration voltage, shorted at the respective inputs, coupled to a calibration load, and / or coupled to an operational load, as further described herein. In some embodiments, the switches are implemented to include field effect transistors (FETs), complementary metal oxide semiconductor field effect transistors (CMOS) switches, multiplexers, and / or other types of switches.

[0036] Figure 4-6 A table and timing diagram showing the configuration and operation of a transconductance amplifier topology according to an embodiment of the present disclosure are shown. Table 400 shows two time periods including a first time period 402 and a second time period 404. During the first time period 402, the Figure 2 and 3 The configuration of the first amplifier 202 in the first time period 402 corresponds to the first amplifier 202 being configured for transconductance operation in the operation phase 406 to convert the input voltage at the input of the transconductance amplifier topology into an output current. Figure 2 and 3 The configuration of the second amplifier 204 in FIG. 4 is configured to be in one or more calibration phases including an auto-zero sub-phase and a gain correction sub-phase. For example, during the first portion of the first time period 402, corresponding to Figure 2 During the second portion of the first time period 402, corresponding to the second amplifier 204 in the configuration of the second amplifier 204, the second amplifier 204 is configured to be in the auto-zero calibration sub-phase 408 to perform the auto-zero operation. Figure 2 , the second amplifier 204 is configured in the gain calibration sub-phase 410 to perform a gain correction operation.

[0037] During the second time period 404, the configurations and phases of the amplifiers are swapped. For example, the first amplifier 202 is configured to perform one or more calibration operations including an auto-zero sub-phase 412 and a gain calibration sub-phase 414. Simultaneously, the second amplifier 204 is configured to be in an operating phase 416 for transconductance operation between the input and output of the transconductance amplifier topology.

[0038] Figure 5 A timing diagram 500 is shown illustrating a transconductance amplifier topology according to an embodiment of the present disclosure. Return to Reference Figure 2-3As described above, the transconductance amplifier topology can include four configurations for the switching circuitry. For example, as described above, during the first time period 402 (between t0 and t2), the first amplifier 202 can be configured in the first and second configurations for the switching circuitry corresponding to the operating phase 406 to perform a transconductance operation between the input and the output. During the second time period 404 (between t2 and t4), the second amplifier 204 can be configured in the third and fourth configurations for the switching circuitry corresponding to the operating phase 416 to perform a transconductance operation between the input and the output. During the first portion of the first time period 402 (between t0 and t1), the second amplifier 204 can be configured in the first configuration for the switching circuitry for the auto-zero calibration subphase 408 to perform an auto-zero operation, and during the second portion of the first time period 402 (between t1 and t2), the second amplifier 204 can be configured in the second configuration for the switching circuitry corresponding to the gain correction subphase 410 to perform a gain correction operation. During a first portion of the second time period 404 (between t2 and t3), the first amplifier 202 may be configured to be in a third configuration for the switching circuit system for the auto-zero calibration sub-stage 412 to perform an auto-zero operation, and during a second portion of the second time period 404 (between t3 and t4), the first amplifier 202 may be configured to be in a fourth configuration for the switching circuit system corresponding to the gain correction sub-stage 414 to perform a gain correction operation.

[0039] In some embodiments, the operating phase is maintained for a time period 402, such as 500 ns. It should be understood that 500 ns is an example, but depending on the speed requirements of the application, the operating phase may optionally be maintained for a time period longer than 500 ns (e.g., 750 ns, 1000 ns, or 1500 ns) or for a shorter time period (e.g., 100 ns, 250 ns, or 400 ns). In some embodiments, the operating phase is maintained for a second time period 404, which may optionally be the same 500 ns period as the first time period 402 (or a different time period, longer or shorter). The duration of the auto-zero subphase and the gain correction subphase together may be the same duration as the duration of the operating phase or shorter than the duration of the operating phase. In some embodiments, the duration of the auto-zero subphase and the gain correction subphase are equal. In some embodiments, the duration of the auto-zero subphase and the gain correction subphase are unequal.

[0040] In some embodiments, the frequency at which the switching configuration of the electronic device 200 changes is based on the switching frequency of related circuitry, such as a switch mode power supply (SMPS) coupled to the input of the electronic device 200. For example, Figure 5In the embodiment, the time period for auto-zero and the time period for gain correction may correspond to the inverse of the switching frequency of the SMPS (eg, every 250 ns, every 500 ns, etc.).

[0041] Figure 6 Table 600 shows a switch configuration including a transconductance amplifier topology according to an embodiment of the present disclosure. For example, Figure 6 Show Figure 2 It should be understood that the second amplifier 204 can also be configured according to Table 600 (switching the operation and calibration phases with the first amplifier 202) by applying the switch settings of the first amplifier 202 in the table to the corresponding switches of the second amplifier 204.

[0042] During operating phase 606 (e.g., corresponding to operating phase 406), e.g. Figure 2 The electronic device 200 and / or transconductance amplifier topology shown in FIG can be configured to obtain a transconductance measurement using the first amplifier 202 by coupling the input node of the input voltage to the terminal of the first amplifier 202 using coupling switch 214 and switch 216. For example, the non-inverting terminal V pos 660 coupled to V in+ , the V in+ The inverting terminal V of the first amplifier 202 is neg 662 coupled to V in- , the V in- The switch 234 remains open to avoid shorting the inverting terminal and the non-inverting terminal of the first amplifier 202. In addition, the operation phase 606 includes switching the output V out 664 is coupled to the load 226 (Z LOAD ).

[0043] During the auto-zero sub-phase 612 (eg, corresponding to the auto-zero sub-phase 412), the non-inverting terminal and the inverting terminal (respectively, the first terminal V pos 660 and the second terminal V neg 662) is shorted with switch 234 and decoupled from the input voltage (and calibration input voltage). The output of the first amplifier 202 is decoupled from the output load 226 and can be terminated, left floating, and / or coupled to the calibration load 228 using switch 222.

[0044] During the gain correction sub-phase 614 (eg, corresponding to the gain correction sub-phase 414 ), the switches 214 and 216 couple the input of the first amplifier 202 to the calibration voltage V cal212. For example, the first terminal V of the first amplifier 202 pos 660 is coupled to a first terminal of the calibration voltage, and a second terminal V of the first amplifier 202 is coupled to a first terminal of the calibration voltage. neg The output of the first amplifier 202 is coupled to the calibration load 228 using the output switch 222 .

[0045] Figure 7 An example controller in communication with a memory device according to an embodiment of the present disclosure is shown. The circuit system 700 may represent a controller 702 including an integrated memory device 704, and / or a controller 702 communicatively coupled to the memory device 704. In some embodiments, the controller 702 executes one or more instructions stored in the memory device 704 (e.g., in a memory) to cause an electronic device (e.g., the electronic device 200) or a transconductance amplifier topology described herein to perform one or more operations. Such operations may include configuring the constituent amplifiers in the transconductance amplifier topology in various operating modes using one or more input switches 206 and / or output switches 208 (e.g., switching a first amplifier and a second amplifier between performing a transconductance operation and one or more calibration operations). For example, the controller 702 optionally corresponds to Figure 2-3 Controllers 237 and / or 239 in the embodiment of the present invention provide control of switches 206 and / or 208. Additionally or alternatively, operations may include controlling connections and control signals (e.g., using controllers 237 and / or 239) to allow auto-zeroing and gain calibration using digital and / or analog circuitry (e.g., auto-zeroing using one or more analog auto-zero amplifiers 241, 243 and correction capacitors 860, 862, biasing using analog bias provided by bias circuitry 230 and / or bias circuitry 232, etc.) to reduce or eliminate input offset and change the bias / gain of such one or more amplifiers. In some embodiments, controller 702 is a hard-wired controller (which may not include storage device 704) or a processor.

[0046] In some example embodiments, these instructions / steps are implemented as functional and software instructions. In other embodiments, the instructions may be implemented using logic gates, dedicated chips, firmware, and other hardware forms.

[0047] When the instructions are implemented as an executable instruction set in a non-transitory computer-readable or computer-usable medium, these instructions are implemented on a computer or machine programmed with and controlled by the executable instructions. The instructions are loaded for execution on a processor (e.g., one or more CPUs). The processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers) or other control or computing device. A processor may refer to a single component or multiple components. The computer-readable or computer-usable storage medium is considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. A non-transitory machine or computer-usable medium as defined herein does not include signals, but such media may be capable of receiving and processing information from signals and / or other transient media.

[0048] Figure 8 A transconductance amplifier including auto-zero circuitry according to an embodiment of the present disclosure is shown. Electronic device 800 includes transconductance amplifier 202 and auto-zero amplifier 241, which may be similar or identical to the amplifiers described with reference to other figures described herein. It should be understood that the description of amplifier 202 is similarly applicable to amplifier 204, and the description of amplifier 241 is similarly applicable to amplifier 243. In some embodiments, amplifier 202 may include input switches 214 and 216 that can switch between a calibration voltage and an input voltage. In some embodiments, a controller, such as controller 237 and / or controller 702, changes the switch configuration and / or coupling of the input and output of amplifier 202. For example, the input of amplifier 202 may be shorted during the auto-zero sub-phase. In some embodiments, amplifier 202 includes an output switch that couples the output stage of amplifier 202 to calibration load 228 and / or load 226. For example, switch 280 may couple the output stage to calibration load 228, and switch 282 may couple the output stage to load 226. It should be understood that the description of the gain correction amplifier and / or circuitry may be coupled to electronic device 800 to change the bias of transconductance amplifier 202, as described with reference to FIG. Figure 9 described.

[0049] In some embodiments, as previously described, electronic device 800 can be configured to be in an auto-zero sub-phase. For example, input switch 214 can couple the first input ("inp") of amplifier 202 to the second input ("inn") of the amplifier via switch 216 and an additional or alternative switch. During the auto-zero sub-phase, auto-zero signal 272 can be asserted, and gain voltage enable signal 274 can remain low (not asserted). Due to the assertion of auto-zero signal 272, switch 284 can be closed, thereby coupling the measurement node ("cc") to compensation capacitor 260. Additionally or alternatively, the assertion of auto-zero signal 272 can enable switches 276 and 278, which can be output switches that allow current to flow through a current mirror included in amplifier 202 via capacitors 262 and / or 260, which can be another compensation capacitor. In some embodiments, auto-zero amplifier 241 facilitates charging current through capacitors 262 and / or 260, thereby changing the bias current applied to amplifier 202 until the voltage difference between the inputs of amplifier 202 is less than a threshold voltage. As previously described, the voltage across capacitors 260 and / or 262 can be the same or nearly the same as the analog voltage and / or current that settles in response to shorting the inputs of amplifier 202.

[0050] In some embodiments, during the auto-zero sub-phase, one or more output switches can be configured to couple amplifier 202 to and / or decouple amplifier 202 from one or more loads. For example, output switch 280 can remain open, and / or a node on the high side of switch 276 or the low side of switch 278 can be coupled to an output calibration node (e.g., "gnv"). In some embodiments, output switch 282 can be asserted based on a logical combination of other signals. For example, when auto-zero signal 272 or gain voltage enable signal 274 is logic high, logic gate 270 (e.g., an XOR gate) can be asserted low. Consequently, switch 282 can be opened, leaving the output voltage node (e.g., "out") floating.

[0051] In some embodiments, after the auto-zero sub-phase, the electronic device 800 may perform a gain correction sub-phase. For example, switches 214 and 216 may couple the input of amplifier 202 to the input voltage node and decouple the input from the calibration voltage node. Additionally, the input of amplifier 202 may be disconnected to prevent shorting of the input used during the auto-zero sub-phase, such as Figure 8 As shown in .

[0052] In some embodiments, during the gain correction sub-phase, auto-zero amplifier 241 is configured differently than during the auto-zero sub-phase. For example, switches 276, 278, and / or 284 may be opened when auto-zero signal 272 is driven to logic low, thereby allowing capacitors 260 and 262 to maintain the voltage established during the auto-zero sub-phase and thereby maintain the bias of amplifier 202.

[0053] In some embodiments, the electronic device 800 couples the output of the amplifier 202 to a gain voltage node. For example, the gain voltage enable signal 274 can be asserted, thereby coupling the calibration output node ("gnv") to a node at the output of the amplifier 202. As described herein, the calibration output node can be coupled to a calibration load, such as a reference load. Figure 2 、 3 and 9, while the gain correction amplifier changes the bias of the amplifier 202 (refer to Figure 9 further described, and at least in part not in Figure 8 ). In some embodiments, the bias, and therefore the transconductance, of amplifier 202 may be changed until a controller in communication with electronic device 800 transitions from a gain correction sub-phase to an operational phase of electronic device 800. For example, the bias may be changed until the output voltage measured across a calibration load coupled to the calibration output node meets one or more criteria (e.g., the output voltage is within a threshold voltage of a target voltage (e.g., 0.01, 0.1, 1, or 5 mV of 10, 50, 100, 150, 200, 300, 500, or 1000 mV).

[0054] In some embodiments, after the auto-zero sub-phase and the gain correction sub-phase are completed, the amplifier of the electronic device 800 is reconfigured to perform the operation phase. For example, the input switches 214 and 216 can be coupled to a node across the input voltage, such as the reference voltage. Figure 2 and 3 As described above. Additionally, the auto-zero signal 272 and the gain voltage enable signal 274 may be driven low by the controller, thereby driving the output of the logic gate 270 to a logic high. Thus, at the output of the electronic device 800, the switch 280 may disconnect the calibration output node from the output stage of the amplifier 202 and may close the operating output node (e.g., "out") via the switch 282. In some embodiments, during the operation phase, the bias determined and applied by the auto-zero amplifier 241 during the auto-zero sub-phase is maintained, and the gain offset correction and / or the bias associated with the gain offset correction during the gain correction sub-phase is maintained. For example, capacitors 262 and 260 continue to maintain a voltage similar to or the same as the voltage established during the auto-zero sub-phase.

[0055] Thus, amplifier 202 can facilitate transconductance measurements during the operation phase based on the bias established during the auto-zero and / or correction sub-phases. In some embodiments, while amplifier 202 is performing auto-zero and / or gain correction, a second amplifier (e.g., amplifier 204) facilitates transconductance measurements. In some embodiments, when amplifier 202 facilitates transconductance measurements, amplifier 204 performs the auto-zero and / or gain correction sub-phases using circuitry similar to or identical to that described with reference to amplifier 202.

[0056] Figure 9 A parallel transconductance amplifier topology including gain correction circuitry is shown. For example, electronic device 900 may include amplifier 202 and amplifier 204, which may alternatively be configured for an operation phase or calibration sub-phase, including auto-zeroing and / or gain correction as described herein. For example, controller 237 may control switches included in electronic device 900 to perform various operations described herein. For example, controller 237 may control the switching of input switch 206A and output switch 208A included in amplifier 202, and may control input switch 206B and / or output switch 208B included in amplifier 204.

[0057] In some embodiments, controller 237 additionally controls the enabling and / or operation of a gain correction amplifier. For example, amplifier 290 may be configured to provide a gain correction amplifier via I bias Terminal 284A changes the bias of amplifier 202 and thereby changes the transconductance of amplifier 202. Similarly, amplifier 292 may be a first gain correction amplifier configured to provide a gain correction signal to amplifier 204 via I bias Terminal 284B changes the bias of amplifier 204. It should be understood that the auto-zero circuitry may be included in amplifiers 202 and 204, or external to but in communication with amplifiers 202 and 204 (for simplicity of illustration, the auto-zero circuitry may be referred to as "auto-zero" in the example of FIG. 2 ). Figure 9 (not shown). In some embodiments, amplifiers 290 and / or 292 are differential amplifiers that measure the difference between the gain voltage outputs of amplifiers 202 and 204, respectively, relative to a reference voltage (e.g., 100 mV, 200 mV, 300 mV, 500 mV, or a 1 V DC reference). In some embodiments, amplifiers 290 and / or 292 convert the differential outputs into current signals that are provided to amplifiers 202 and / or 204, respectively, thereby changing the bias of the receiving amplifier.

[0058] exist Figure 9In FIG. 2 , amplifier 202 is configured to be in the operating phase of operation, and amplifier 204 is configured to be in the gain correction phase of operation. For example, input switch 206A allows coupling of input voltage 210 to the input stage of amplifier 202, and output switch 208A is configured to couple Z load 228 is coupled to the output 288A of the amplifier 202 (but not to the gain voltage output 286A). Meanwhile, the amplifier 204 can be coupled to V cal 212, and an output voltage may be generated across a portion of Zcal 228 via gain voltage output 286B via output switch 208B (but not coupled to output 288B).

[0059] By configuring the transconductance amplifier to perform a calibration phase, the electronic device 200 reduces the need for fine-tuning circuitry required to accommodate potential drift within the amplifier's operating range, thereby reducing manufacturing complexity, board and / or packaging space, and the overall cost associated with the electronic device 200. In some embodiments, the calibration sub-phase may be performed once or periodically. For example, the electronic device 200 may be coupled to a switched-mode power supply (SMPS) and calibration of the corresponding transconductance amplifier may be performed during one or more charge and / or discharge cycles of the SMPS. Thus, calibration may be performed during a time period corresponding to the switching frequency of the SMPS. Additionally or alternatively, the electronic device 200 may perform the calibration sub-phase for the corresponding amplifier in response to initiating a transconductance measurement configuration for another amplifier. Because the calibration may include analog circuitry for adjusting input offset and bias current (e.g., in addition to digital sampling and digitally synthesized signal alternatives), the electronic device 200 may quickly respond to swings in the input signal without occupying excessive real estate on the circuit board and / or package containing the electronic device 200.

[0060] In view of the embodiments described herein, it will be appreciated that devices, systems, and methods can provide significant improvements over conventional transconductance amplification solutions. In particular, the devices described herein can provide system bandwidths exceeding 5, 10, 15, 20, 25, 30, 35, 40, and / or 50 MHz, and can reduce degradation in gain linearity. In contrast to conventional solutions, the embodiments described herein can provide continuous transconductance operation despite rapid fluctuations in the input signal due to switching between a first amplifier and a second amplifier that can receive the input signal, and can provide a continuously accurate solution by quickly performing calibration phases for such amplifiers. Additionally, the embodiments described herein are flexible and may not require excessive circuitry to fine-tune the amplifier.

[0061] In some embodiments, the topologies described herein may differ from those shown. For example, the topologies optionally include a different number, arrangement, and / or type of switches, amplifiers, passive circuitry, and / or some combination thereof. Additionally or alternatively, the auto-zeroing of the transconductance amplifier is optionally performed by one or more amplifiers and / or Figure 8 The topology may also include one or more additional transconductance amplifiers that can perform the calibration phase while another transconductance amplifier performs the operation phase. In such an example, the one or more additional transconductance amplifiers can be configured to be in the operation phase to allow the other transconductance amplifiers to perform the calibration phase.

[0062] Some examples of the present disclosure relate to an electronic device. In some embodiments, the electronic device includes a controller, a plurality of transconductance amplifiers including a first transconductance amplifier and a second transconductance amplifier, and a switching circuit system including one or more first input switches, one or more second input switches, one or more first output switches, and one or more second output switches. In some embodiments, during a first time period, the one or more first input switches are configured by the controller to operate the first transconductance amplifier in a transconductance operation phase by coupling the input of the first transconductance amplifier to an input voltage via the one or more first input switches and coupling the output of the first transconductance amplifier to an output load via the one or more first output switches, and the one or more second input switches are configured by the controller to operate the second transconductance amplifier in one or more calibration phases by decoupling the input of the second transconductance amplifier from the input voltage using the one or more second input switches and decoupling the output of the second transconductance amplifier from the output load via the one or more second output switches.

[0063] Additionally or alternatively, during a second time period different from the first time period, the one or more first input switches are configured by the controller to operate the first transconductance amplifier in one or more calibration phases by decoupling the input of the first transconductance amplifier from the input voltage using the one or more first input switches and by decoupling the output of the first transconductance amplifier from the output load via the one or more first output switches, and the one or more second input switches are configured by the controller to operate the second transconductance amplifier in a transconductance operation phase by coupling the input of the second transconductance amplifier to the input voltage via the one or more second input switches and by coupling the output of the second transconductance amplifier to the output load via the one or more second output switches.

[0064] Additionally or alternatively, the electronic device may further include an auto-zero amplifier. In some embodiments, during a first sub-period of the first time period, the one or more second input switches are configured by the controller to operate the second transconductance amplifier in an auto-zero sub-phase of the one or more calibration phases by shorting a first terminal of the input of the second transconductance amplifier to a second terminal of the input of the second transconductance amplifier and by storing a correction current using a compensation capacitor associated with the auto-zero amplifier.

[0065] Additionally or alternatively, the electronic device may further include a gain correction amplifier. In some embodiments, during a second sub-period of the first time period, the one or more second input switches are configured by the controller to operate the second transconductance amplifier in a gain correction sub-phase of the one or more calibration phases by coupling an input of the second transconductance amplifier to the first calibration voltage and by adjusting a bias of the second transconductance amplifier.

[0066] Additionally or alternatively, the electronic device may further include an input attenuation network, wherein the electronic device is further configured to generate the first calibration voltage by coupling the input attenuation network to a supply voltage of the electronic device.

[0067] Additionally or alternatively, the first calibration voltage may correspond to a reference voltage generated by the electronic device.

[0068] Additionally or alternatively, the electronic device may include an output attenuation network.In some embodiments, the output attenuation network includes a calibration load coupled to the output of the second transconductance amplifier during one or more calibration phases during the first time period.

[0069] Additionally or alternatively, one or more calibration phases during the first time period may include an auto-zero sub-phase followed by a gain correction sub-phase.

[0070] Additionally or alternatively, the auto-zero sub-stage may include adjusting a bias of a second transconductance amplifier generated with the auto-zero amplifier until an output of the second transconductance amplifier satisfies one or more criteria.

[0071] Additionally or alternatively, the gain correction sub-stage may include using gain correction circuitry to supplement a bias current of the second transconductance amplifier based on an adjusted offset of the second transconductance amplifier produced with the auto-zero amplifier.

[0072] Additionally or alternatively, during the first time period, the switch circuitry may be configured to be in the first configuration and the second configuration, and during the second time period, the switch circuitry may be configured to be in the third configuration and the fourth configuration.

[0073] Additionally or alternatively, the first configuration for the switching circuit system may correspond to an auto-zero sub-stage of a transconductance operation phase for the first transconductance amplifier and one or more calibration phases for the second transconductance amplifier, and the second configuration for the switching circuit system may correspond to a transconductance operation phase for the first transconductance amplifier and a gain correction sub-stage of one or more calibration phases for the second transconductance amplifier.

[0074] Additionally or alternatively, the third configuration for the switching circuit system may correspond to an auto-zero sub-stage of a transconductance operation phase for the second transconductance amplifier and one or more calibration phases for the first transconductance amplifier, and the fourth configuration for the switching circuit system may correspond to a transconductance operation phase for the second transconductance amplifier and a gain correction sub-stage of one or more calibration phases for the first transconductance amplifier.

[0075] Additionally or alternatively, during the first time period, the switching circuitry may be configured to be in the first configuration and the second configuration, and during the second time period, the switching circuitry is configured to be in the third configuration and the fourth configuration.

[0076] Additionally or alternatively, the first configuration for the switching circuit system may correspond to an auto-zero sub-stage of a transconductance operation phase for the first transconductance amplifier and one or more calibration phases for the second transconductance amplifier, and the second configuration for the switching circuit system may correspond to a transconductance operation phase for the first transconductance amplifier and a gain correction sub-stage of one or more calibration phases for the second transconductance amplifier.

[0077] Additionally or alternatively, the duration of the first time period may correspond to a switching frequency of a power supply coupled to the electronic device.

[0078] Some embodiments of the present disclosure relate to a method comprising: measuring transconductance using a first transconductance amplifier during a first time period; and calibrating a second transconductance amplifier while measuring the transconductance using the first amplifier during the first time period, wherein the calibration comprises an auto-zero sub-stage and a gain correction sub-stage.

[0079] Additionally or alternatively, the auto-zero sub-phase may include using analog circuitry included in the electronic device to change the bias of the second transconductance amplifier.

[0080] Additionally or alternatively, the method may further include measuring the transconductance using a second transconductance amplifier during the second time period, wherein the transconductance of the second transconductance amplifier corresponds to the bias established during the auto-zero sub-phase; and calibrating the first transconductance amplifier while measuring the transconductance using the second amplifier during the second time period.

[0081] Additionally or alternatively, the gain correction sub-stage may include using circuitry included in the electronic device to vary the gain of the second transconductance amplifier until one or more criteria are met.

[0082] Additionally or alternatively, the one or more criteria may be satisfied when the voltage generated by the second transconductance amplifier is within a threshold voltage of the target voltage.

[0083] Additionally or alternatively, the method may further include calibrating the third transconductance amplifier while measuring transconductance using the first amplifier during the first time period. In some embodiments, the calibration includes an auto-zero sub-phase and a gain correction sub-phase.

[0084] The foregoing description has been described with reference to specific examples. It should be understood that the above illustrative discussion is not intended to be exhaustive, nor is it intended to limit the present disclosure to the specific disclosed examples. In light of the above disclosure, various modifications and variations are possible. The examples are selected and described in order to explain the principles of the present disclosure and its practical application, thereby enabling those skilled in the art to best utilize the present disclosure and the various described examples with various modifications suitable for specific applications.

Claims

1. An electronic device, characterized in that: include: Controller; a plurality of transconductance amplifiers, the plurality of transconductance amplifiers including a first transconductance amplifier and a second transconductance amplifier; as well as Switching circuitry comprising one or more first input switches, one or more second input switches, one or more first output switches, and one or more second output switches, wherein during a first time period: The one or more first input switches are configured by the controller to operate the first transconductance amplifier in a transconductance operation phase by coupling an input of the first transconductance amplifier to an input voltage via the one or more first input switches and by coupling an output of the first transconductance amplifier to an output load via the one or more first output switches, and The one or more second input switches are configured by the controller to operate the second transconductance amplifier in one or more calibration phases by decoupling the input of the second transconductance amplifier from the input voltage using the one or more second input switches and by decoupling the output of the second transconductance amplifier from the output load via the one or more second output switches.

2. The electronic device according to claim 1, wherein: During a second time period different from the first time period: the one or more first input switches are configured by the controller to operate the first transconductance amplifier in the one or more calibration phases by decoupling the input of the first transconductance amplifier from the input voltage using the one or more first input switches and by decoupling the output of the first transconductance amplifier from the output load via the one or more first output switches, and The one or more second input switches are configured by the controller to operate the second transconductance amplifier in the transconductance operation phase by coupling the input of the second transconductance amplifier to the input voltage via the one or more second input switches and by coupling the output of the second transconductance amplifier to the output load via the one or more second output switches.

3. The electronic device according to claim 1, wherein: Additionally included is an auto-zero amplifier, wherein during a first sub-time period of the first time period, the one or more second input switches are configured by the controller to operate the second transconductance amplifier in an auto-zero sub-phase of the one or more calibration phases by shorting a first terminal of the input of the second transconductance amplifier to a second terminal of the input of the second transconductance amplifier and by storing a correction current using a compensation capacitor associated with the auto-zero amplifier.

4. The electronic device according to claim 1, wherein: Also included is a gain correction amplifier, wherein during a second sub-time period of the first time period, the one or more second input switches are configured by the controller to operate the second transconductance amplifier in a gain correction sub-phase of the one or more calibration phases by coupling the input of the second transconductance amplifier to a first calibration voltage and by adjusting a bias of the second transconductance amplifier.

5. The electronic device according to claim 4, wherein: An input attenuation network is additionally included, wherein the electronic device is additionally configured to generate the first calibration voltage by coupling the input attenuation network to a supply voltage of the electronic device.

6. The electronic device according to claim 4, wherein: The first calibration voltage corresponds to a reference voltage generated by the electronic device.

7. The electronic device according to claim 1, wherein: Additionally included is an output attenuation network, wherein the output attenuation network comprises a calibration load coupled to an output of the second transconductance amplifier during the one or more calibration phases during the first time period.

8. The electronic device according to claim 1, wherein: The one or more calibration phases during the first time period include an auto-zero sub-phase followed by a gain correction sub-phase.

9. The electronic device according to claim 1, wherein: During the first time period, the switch circuitry is configured to be in a first configuration and a second configuration, and during the second time period, the switch circuitry is configured to be in a third configuration and a fourth configuration.

10. A method for operating an electronic device, characterized in that: include: During a first time period, measuring transconductance using a first transconductance amplifier, and During the first time period, a second transconductance amplifier is calibrated while measuring the transconductance using the first transconductance amplifier, wherein the calibration includes an auto-zero sub-phase and a gain correction sub-phase.

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