Voltage level shifter

Abstract

The invention provides a voltage level shifter. The voltage level shifter comprises a voltage level shifting circuit and a booster circuit. The voltage level shift circuit includes a first boost input terminal, a second boost input terminal and a shift output terminal, and is operated between a first voltage and a second voltage. The first boost input terminal is configured to receive a first boost voltage, the second boost input terminal is configured to receive a second boost voltage, and the shift output terminal is configured to output a shift voltage. The boost circuit operates between a third voltage and a second voltage and is configured to receive an input signal and provide a first boost voltage and a second boost voltage to the voltage level shift circuit. The boost circuit responds to the input signal and boosts one of the first boost voltage and the second boost voltage according to the third voltage.

Description

Technical Field

[0001] The present invention relates to a voltage conversion circuit, and in particular to a voltage level shifter suitable for operating at a low power supply voltage. Background Art

[0002] In integrated electronic products with multiple functions, voltage level shifters are often required to switch between different operating voltage ranges. For example, memory devices often include voltage level shifters to perform shifting operations between different voltage levels.

[0003] However, to meet energy conservation needs, the supply voltage of electronic products is becoming increasingly smaller. When the supply voltage is low (e.g., below 0.9 volts), when the input signal is converted from a low voltage level to a high voltage level, existing voltage level shifters may not be able to complete the signal transition within the specified time (e.g., 100 nanoseconds), or may even fail to function. This results in not only a slow transition speed but also excessive transition current, which can easily lead to excessive power consumption in the voltage level shifter, thus hindering energy conservation. Summary of the Invention

[0004] The present invention provides a voltage level shifter for avoiding the problems of too slow transition speed, too large transition current and even functional failure when the supply voltage is low.

[0005] The voltage level shifter of the present invention includes a voltage level shift circuit and a boost circuit. The voltage level shift circuit includes a first boost input terminal, a second boost input terminal, and a shift output terminal, and operates between a first voltage and a second voltage. The first boost input terminal is configured to receive a first boosted voltage, the second boost input terminal is configured to receive a second boosted voltage, and the shift output terminal is configured to output the shifted voltage. The boost circuit is coupled to the voltage level shift circuit. The boost circuit operates between a third voltage and the second voltage, is configured to receive an input signal via an input terminal, and provide the first boosted voltage and the second boosted voltage to the voltage level shift circuit via an output terminal. The boost circuit responds to the input signal and boosts one of the first boosted voltage and the second boosted voltage according to the third voltage.

[0006] Based on the above, the voltage level shifter of the present invention can drive the voltage level shift circuit with a voltage greater than the input signal voltage through a boost circuit. This not only improves the transition speed but also reduces the generation of transition current, thereby reducing power consumption and facilitating the application of energy-saving products.

[0007] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram illustrating a voltage level shifter according to an embodiment of the present invention is shown;

[0009] Figure 2 A block diagram illustrating a boost circuit block according to an embodiment of the present invention;

[0010] Figure 3 Show Figure 1 A schematic diagram of the circuit structure of a voltage level shifter according to an embodiment;

[0011] Figure 4 An example of a method for generating an input signal according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0013] Please refer to Figures 1 to 3 The voltage level shifter 100 of this embodiment includes a voltage level shift circuit 110, a boost circuit 120, and a buffer circuit 130. The voltage level shift circuit 110 is coupled to the boost circuit 120 and the buffer circuit 130. In this embodiment, the voltage level shift circuit 110 is, for example, a circuit configuration with a single-ended output and a differential input, and includes a first boost input terminal BIN1, a second boost input terminal BIN2, and a shift output terminal SOUT. The first boost input terminal BIN1 is configured to receive a first boosted voltage VB1, the second boost input terminal BIN2 is configured to receive a second boosted voltage VB2, and the shift output terminal SOUT is configured to output a shifted voltage VSH.

[0014] The voltage level shift circuit 110 operates between a first voltage VPPY and a second voltage VSS. The first voltage VPPY is higher than the second voltage VSS. The first voltage VPPY is, for example, 9-10 volts, and the second voltage VSS is, for example, 0 volts (i.e., ground voltage), but the present invention is not limited thereto.

[0015] like Figure 3As shown, the voltage level shift circuit 110 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 each include a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor M1 is coupled to the first voltage VPPY. The first terminal of the second transistor M2 is coupled to the first voltage VPPY. The first terminal of the third transistor M3 is coupled to the second terminal of the first transistor M1. The second terminal of the third transistor M3 is coupled to the control terminal of the second transistor M2 and the shift output terminal SOUT. The control terminal of the third transistor M3 is coupled to the second boost input terminal BIN2. The first terminal of the fourth transistor M4 is coupled to the second terminal of the second transistor M2. The second terminal of the fourth transistor M4 is coupled to the control terminal of the first transistor M1. The control terminal of the fourth transistor M4 is coupled to the first boost input terminal BIN1. A first terminal of the fifth transistor M5 is coupled to the control terminal of the second transistor M2, the second terminal of the third transistor M3, and the shift output terminal SOUT. A second terminal of the fifth transistor M5 is coupled to the second voltage VSS. The control terminal of the fifth transistor M5 is coupled to the second boost input terminal BIN2. A first terminal of the sixth transistor M6 is coupled to the control terminal of the first transistor M1 and the second terminal of the fourth transistor M4. A second terminal of the sixth transistor M6 is coupled to the second voltage VSS. The control terminal of the sixth transistor M6 is coupled to the first boost input terminal BIN1. In this embodiment, the first to sixth transistors M1 to M6 are high-voltage metal oxide semiconductor field effect transistors.

[0016] Based on the above structure, the voltage level shift circuit 110 can shift the voltage levels of the differential input first boosted voltage VB1 and the second boosted voltage VB2 to the first voltage VPPY to output as the shifted voltage VSH. The first boosted voltage VB1 and the shifted voltage VSH are in phase, and the second boosted voltage VB2 and the shifted voltage VSH are in opposite phase.

[0017] The buffer circuit 130 also operates between the first voltage VPPY and the second voltage VSS. The buffer circuit 130 is configured to receive the shift voltage VSH to provide an output signal YSB.

[0018] The boost circuit 120 operates between a third voltage VDD and a second voltage VSS. The third voltage VDD is lower than the first voltage VPPY and higher than the second voltage VSS. In practical applications, the third voltage VDD is, for example, 0.78 to 1.2 volts. In this embodiment, the third voltage VDD is a supply voltage.

[0019] The boost circuit 120 is configured to receive an input signal SEN and provide a first boost voltage VB1 and a second boost voltage VB2 to the voltage level shift circuit 110. In this embodiment, the boost circuit 120 can respond to the input signal SEN and boost one of the first boost voltage VB1 and the second boost voltage VB2 according to the third voltage VDD.

[0020] like Figure 1 As shown, the boost circuit 120 of one embodiment of the present invention may include a first boost circuit block 122 and a second boost circuit block 124. Figure 2 As shown, each boost circuit block in one embodiment of the present invention includes a boost and charge element 200, a transmission control element 210, a voltage maintenance element 220, a pull-down element 230, and a logic element 240. The boost circuit 120 is configured to receive an input signal SEN via an input terminal IN and provide the input signal SEN to the boost and charge element 200, the voltage maintenance element 220, and the logic element 240. The logic element 240 is configured to generate a control signal Sct to a node N1 based on the input signal SEN. The boost and charge element 200 is configured to charge a node N2 based on the input signal SEN and to boost a node N2 located between the boost and charge element 200 and the transmission control element 210 based on a third voltage VDD. In one embodiment, the boost and charge element 200 is configured to first charge the node N2 based on the input signal SEN and then boost the charged node N2 to raise the voltage of the node N2 to twice the third voltage VDD. The transmission control element 210 and the pull-down element 230 are coupled to the logic element 240 via node N1 to receive a control signal Sct. Furthermore, the transmission control element 210 is coupled to the boost and charge element 200 via node N2 and determines whether to provide the voltage from node N2 to the output terminal OUT based on the control signal Sct. The pull-down element 230 determines whether to pull the output terminal OUT down to the second voltage VSS based on the control signal Sct. The voltage maintenance element 220 is configured to determine whether to provide the third voltage VDD to the output terminal OUT based on the input signal SEN, thereby preventing the output terminal OUT from floating before the pull-down element 230 is enabled. The output terminal OUT is configured to provide either the first boosted voltage VB1 or the second boosted voltage VB2.

[0021] Specifically, the input signal SEN of this embodiment includes a first input signal EN and a second input signal ENb. Figure 3In the embodiment, the first boosting circuit block 122 and the second boosting circuit block 124 are respectively coupled to the first boosting input terminal BIN1 and the second boosting input terminal BIN2 of the voltage level shifting circuit 110 via the output terminal OUT. The first boosting circuit block 122 can receive a first input signal EN via the input terminal IN and provide a first boosted voltage VB1 to the voltage level shifting circuit 110 via the output terminal OUT based on the first input signal EN. The second boosting circuit block 124 can receive a second input signal ENb via the input terminal IN and provide a second boosted voltage VB2 to the voltage level shifting circuit 110 via the output terminal OUT based on the second input signal ENb.

[0022] The first input signal EN and the second input signal ENb are in opposite phases. For example, the voltage level shifter 100 can be applied to a read operation of a memory device. For example, in one embodiment, the voltage level shifter 100 can be used to control a switch between a global bit line and a data line, but the present invention is not limited thereto. Figure 4 As shown, NAND gate 300 receives address signals Ad1-Ad3 and enable signal Bank. Address signals Ad1-Ad3 may, for example, constitute the memory address to be read. When address signals Ad1-Ad3 and enable signal Bank are enabled (become a high voltage level), inverter 310 generates a first input signal EN at a high voltage level, and inverter 320 generates a second input signal ENb at a low voltage level. The memory device may be, for example, a non-volatile memory such as a flash memory, or a volatile memory such as a DRAM, but the present invention is not limited thereto. In this embodiment, the memory device is a NOR flash memory.

[0023] In one embodiment, if Figure 3As shown, the boost and charging component 200 of the first boost circuit block 122 may include a seventh transistor M7 and a first capacitor C1. The transmission control component 210 may include an eighth transistor M8. The logic component 240 may include a first inverter IV1. The pull-down component 230 may include a ninth transistor M9. The voltage maintaining component 220 may include a tenth transistor M10. The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 each include a first terminal, a second terminal, and a control terminal. The first capacitor C1 includes a first terminal and a second terminal. The first inverter IV1 includes an input terminal and an output terminal. The first terminal of the seventh transistor M7 is coupled to the third voltage VDD. The control terminal of the seventh transistor M7 receives a first input signal EN. The first terminal of the first capacitor C1 is coupled to the second terminal of the seventh transistor M7. The second terminal of the first capacitor C1 receives the first input signal EN. The first terminal of the eighth transistor M8 is coupled to the second terminal of the seventh transistor M7 and the first terminal of the first capacitor C1. The second terminal of the eighth transistor M8 is coupled to the first boosted input terminal BIN1 of the voltage level shifting circuit 110 and can output the first boosted voltage VB1 to the voltage level shifting circuit 110. The input terminal of the first inverter IV1 receives the first input signal EN. The output terminal of the first inverter IV1 is coupled to the control terminal of the eighth transistor M8. The first terminal of the ninth transistor M9 is coupled to the second terminal of the eighth transistor M8. The second terminal of the ninth transistor M9 is coupled to the second voltage VSS. The control terminal of the ninth transistor M9 is coupled to the output terminal of the first inverter IV1. The first terminal of the tenth transistor M10 is coupled to the third voltage VDD. The second terminal of the tenth transistor M10 is coupled to the second terminal of the eighth transistor M8, and the control terminal of the tenth transistor M10 receives the first input signal EN. In this embodiment, the seventh transistor M7 is a P-type field-effect transistor, and the tenth transistor M10 is an N-type field-effect transistor. The back gate of the seventh transistor M7 is coupled to the second terminal of the seventh transistor M7, and the back gate of the eighth transistor M8 is coupled to the first terminal of the eighth transistor M8. The eighth transistor M8 and the ninth transistor M9 are high-voltage metal-oxide-semiconductor field-effect transistors.

[0024] The circuit structure of the second boost circuit block 124 is symmetrical to that of the first boost circuit block 122. The boost and charging component 200 of the second boost circuit block 124 may include an eleventh transistor M11 and a second capacitor C2. The transmission control component 210 may include a twelfth transistor M12. The logic component 240 may include a second inverter IV2. The pull-down component 230 may include a thirteenth transistor M13. The voltage maintaining component 220 may include a fourteenth transistor M14. The eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 each include a first terminal, a second terminal, and a control terminal. The second capacitor C2 includes a first terminal and a second terminal. The second inverter IV2 includes an input terminal and an output terminal. The first terminal of the eleventh transistor M11 is coupled to the third voltage VDD. The control terminal of the eleventh transistor M11 receives the second input signal ENb. The first terminal of the second capacitor C2 is coupled to the second terminal of the eleventh transistor M11. The second terminal of the second capacitor C2 receives the second input signal ENb. A first terminal of the twelfth transistor M12 is coupled to the second terminal of the eleventh transistor M11 and the first terminal of the second capacitor C2. A second terminal of the twelfth transistor M12 is coupled to the second boost input terminal BIN2 of the voltage level shift circuit 110 and can output a second boosted voltage VB2 to the voltage level shift circuit 110. An input terminal of the second inverter IV2 receives the second input signal ENb. An output terminal of the second inverter IV2 is coupled to the control terminal of the twelfth transistor M12. A first terminal of the thirteenth transistor M13 is coupled to the second terminal of the twelfth transistor M12. A second terminal of the thirteenth transistor M13 is coupled to the second voltage VSS. The control terminal of the thirteenth transistor M13 is coupled to the output terminal of the second inverter IV2. A first terminal of the fourteenth transistor M14 is coupled to the third voltage VDD. A second terminal of the fourteenth transistor M14 is coupled to the second terminal of the twelfth transistor M12, and a control terminal of the fourteenth transistor M14 receives the second input signal ENb. In this embodiment, the eleventh transistor M11 is a P-type field-effect transistor, and the fourteenth transistor M14 is an N-type field-effect transistor. The back gate of the eleventh transistor M11 is coupled to the second terminal of the eleventh transistor M11, and the back gate of the twelfth transistor M12 is coupled to the first terminal of the twelfth transistor M12. The twelfth transistor M12 and the thirteenth transistor M13 are high-voltage metal-oxide-semiconductor field-effect transistors.

[0025] In operation, during a transition period of the input signal SEN (i.e., when the first input signal EN or the second input signal ENb transitions from a low voltage level to a high voltage level), the boost circuit 120 can boost the voltage of one of the first boosted voltage VB1 and the second boosted voltage VB2 to a voltage greater than the third voltage VDD based on the third voltage VDD. Specifically, taking the first boost circuit block 122 as an example, when the first input signal EN is at a low voltage level (i.e., equal to the second voltage VSS), the seventh transistor M7 is controlled by the first input signal EN to turn on, charging the first capacitor C1 to the third voltage VDD. The eighth transistor M8 is controlled by the high voltage level provided by the output terminal of the first inverter IV1 to turn off, and the ninth transistor M9 is controlled by the high voltage level provided by the output terminal of the first inverter IV1 to turn on, isolating the first boosted input terminal BIN1 of the voltage level shifting circuit 110 from the first capacitor C1, thereby pulling the first boosted voltage VB1 at the first boosted input terminal BIN1 down to the second voltage VSS. At the same time, the tenth transistor M10 is controlled by the first input signal EN and is turned off.

[0026] When the first input signal EN transitions from a low voltage level to a high voltage level (i.e., from the second voltage VSS to the third voltage VDD), the seventh transistor M7 is controlled by the first input signal EN to be turned off. The eighth transistor M8 is controlled by the low voltage level provided by the output terminal of the first inverter IV1 to be turned on, and the ninth transistor M9 is controlled by the low voltage level provided by the output terminal of the first inverter IV1 to be turned off. This allows the first boosted voltage VB1 to be raised to a level greater than the third voltage VDD (e.g., approximately twice the third voltage VDD) by adding the voltage of the first capacitor C1 (approximately equal to the third voltage VDD) to the high voltage level of the first input signal EN.

[0027] In this way, even if the high voltage level of the first input signal EN is relatively low, the voltage level shifter circuit 110 can be driven by the first boosted voltage VB1, which is approximately twice the voltage of the first input signal EN. This not only improves the transition speed of the voltage level shifter 100 but also reduces the generation of transition current, thereby reducing power consumption. Furthermore, the reduced power consumption further reduces the load on the charge pump circuit used to generate the first voltage VPPY. Incidentally, the transition current in this embodiment is the sum of the current transmitted from the first terminal of the first transistor M1 in the voltage level shifter circuit 110 through the first transistor M1, the third transistor M3, and the fifth transistor M5 to the second terminal of the fifth transistor M5, and the current transmitted from the first terminal of the second transistor M2 through the second transistor M2, the fourth transistor M4, and the sixth transistor M6 to the second terminal of the sixth transistor M6 during the transition period of the input signal SEN.

[0028] Furthermore, during a period when the first input signal EN is at a high voltage level, when the first boosted voltage VB1 is greater than the third voltage VDD, the voltage at the second terminal of the tenth transistor M10 is greater than the voltage at the control terminal, and therefore the tenth transistor M10 remains off until the first boosted voltage VB1 gradually decreases to equal the third voltage VDD due to factors such as leakage current. When the first boosted voltage VB1 decreases to equal the third voltage VDD, the tenth transistor M10 turns on, maintaining the first boosted voltage VB1 at the third voltage VDD and preventing it from further decreasing, thereby preventing the first boosted input terminal BIN1 of the voltage level shift circuit 110 from entering a floating state.

[0029] In this embodiment, the operation of the second boost circuit block 124 can be referenced to the operation of the first boost circuit block 122. Because the first input signal EN and the second input signal ENb are in opposite phases, the first boosted voltage VB1 and the second boosted voltage VB2 are also in opposite phases. The operation of the second boost circuit block 124 will not be further described here.

[0030] exist Figure 3 In the embodiment, the buffer circuit 130 includes a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, and an eighteenth transistor M18. The fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 each include a first terminal, a second terminal, and a control terminal. The first terminal of the fifteenth transistor M15 is coupled to the first voltage VPPY. The control terminal of the fifteenth transistor M15 is coupled to the shift output terminal SOUT. The first terminal of the sixteenth transistor M16 is coupled to the second terminal of the fifteenth transistor M15. The second terminal of the sixteenth transistor M16 is coupled to the second voltage VSS, and the control terminal of the sixteenth transistor M16 is coupled to the shift output terminal SOUT. The first terminal of the seventeenth transistor M17 is coupled to the first voltage VPPY. The control terminal of the seventeenth transistor M17 is coupled to the second terminal of the fifteenth transistor M15 and the first terminal of the sixteenth transistor M16. The first terminal of the eighteenth transistor M18 is coupled to the second terminal of the seventeenth transistor M17 and can output the output signal YSB. A second terminal of the eighteenth transistor M18 is coupled to the second voltage VSS. A control terminal of the eighteenth transistor M18 is coupled to the second terminal of the fifteenth transistor M15 and the first terminal of the sixteenth transistor M16. In this embodiment, the fifteenth transistor M15 to the eighteenth transistor M18 are high-voltage metal-oxide-semiconductor field-effect transistors. Based on the above structure, the first input signal EN and the output signal YSB are in phase.

[0031] In summary, the voltage level shifter of the present invention can operate normally when receiving input signals with relatively low voltage values, thus avoiding errors. For example, in energy-saving electronic products, a low supply voltage is typically used during the power-on read phase. The voltage level shifter of the present invention can avoid errors in the power-on read operation, allowing the power-on readback of internal chip information to operate normally. Furthermore, the voltage level shifter of the present invention can not only increase the transition speed but also reduce the generation of transition current, thereby reducing power consumption. Therefore, the present invention is conducive to the application of energy-saving products and represents a green semiconductor technology.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A voltage level shifter, characterized in that: include: A voltage level shift circuit comprising a first boost input terminal, a second boost input terminal, and a shift output terminal, and operating between a first voltage and a second voltage, wherein the first boost input terminal is configured to receive a first boosted voltage, the second boost input terminal is configured to receive a second boosted voltage, and the shift output terminal is configured to output a shifted voltage; as well as a boost circuit coupled to the voltage level shift circuit, operating between a third voltage and the second voltage, configured to receive an input signal via an input terminal and provide the first boosted voltage and the second boosted voltage to the voltage level shift circuit via an output terminal; The boost circuit responds to the input signal and boosts one of the first boost voltage and the second boost voltage according to the third voltage.

2. The voltage level shifter according to claim 1, wherein: The third voltage is a power supply voltage, and the power supply voltage is less than or equal to 1.2 volts.

3. The voltage level shifter according to claim 1, wherein: The boost circuit includes a plurality of boost circuit blocks, each of which includes: a logic component configured to generate a control signal to the first node according to the input signal; a boost and charge component, coupled between the input terminal and a second node, configured to charge the second node according to the input signal and boost the second node according to the third voltage; and The transmission control component is configured to be coupled to the logic component via the first node and to be coupled to the boost and charge component via the second node, and to determine whether to provide the voltage from the second node to the output end according to the control signal.

4. The voltage level shifter according to claim 3, wherein: Each of the boost circuit blocks further includes: a voltage maintaining element, coupled between the input terminal and the output terminal, and configured to determine whether to provide the third voltage to the output terminal according to the input signal; and The pull-down component is coupled between the first node and the output terminal, and is configured to determine whether to pull the output terminal down to the second voltage according to the control signal.

5. The voltage level shifter according to claim 1, wherein: During a transition period of the input signal, the boost circuit boosts a voltage value of one of the first boosted voltage and the second boosted voltage to a voltage value greater than the third voltage according to the third voltage.

6. The voltage level shifter according to claim 1, wherein: The voltage level shift circuit comprises: A first transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the first voltage; a second transistor comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the first voltage; a third transistor, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third transistor is coupled to the second terminal of the first transistor, the second terminal of the third transistor is coupled to the control terminal of the second transistor and the shift output terminal, and the control terminal of the third transistor is coupled to the second boost input terminal; a fourth transistor, comprising a first terminal, a second terminal, and a control terminal, the first terminal of the fourth transistor being coupled to the second terminal of the second transistor, the second terminal of the fourth transistor being coupled to the control terminal of the first transistor, and the control terminal of the fourth transistor being coupled to the first boost input terminal; a fifth transistor, comprising a first terminal, a second terminal, and a control terminal, the first terminal of the fifth transistor being coupled to the control terminal of the second transistor, the second terminal of the third transistor, and the shift output terminal, the second terminal of the fifth transistor being coupled to the second voltage, and the control terminal of the fifth transistor being coupled to the second boost input terminal; and The sixth transistor includes a first end, a second end, and a control end, the first end of the sixth transistor is coupled to the control end of the first transistor and the second end of the fourth transistor, the second end of the sixth transistor is coupled to the second voltage, and the control end of the sixth transistor is coupled to the first boost input end.

7. The voltage level shifter according to claim 6, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are high-voltage metal oxide semiconductor field effect transistors.

8. The voltage level shifter according to claim 1, wherein: The input signal includes a first input signal and a second input signal, the first input signal and the second input signal are in opposite phases, and the boost circuit includes: a first boost circuit block, coupled to the first boost input terminal, configured to receive the first input signal and provide the first boost voltage according to the first input signal; and The second boost circuit block is coupled to the second boost input terminal, and is configured to receive the second input signal and provide the second boost voltage according to the second input signal.

9. The voltage level shifter according to claim 4, wherein: The plurality of boost circuit blocks include a first boost circuit block, and the boost and charging components of the first boost circuit block include: a seventh transistor comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is coupled to the third voltage, and the control terminal of the seventh transistor receives a first input signal of the input signal; and The first capacitor includes a first end and a second end. The first end of the first capacitor is coupled to the second end of the seventh transistor. The second end of the first capacitor receives the first input signal.

10. The voltage level shifter according to claim 9, wherein: In the first boost circuit block The transmission control component includes an eighth transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the eighth transistor being coupled to the second terminal of the seventh transistor and the first terminal of the first capacitor, the second terminal of the eighth transistor being coupled to the first boost input terminal and outputting the first boost voltage; The logic component includes a first inverter including an input terminal and an output terminal, the input terminal of the first inverter receiving the first input signal, and the output terminal of the first inverter coupled to the control terminal of the eighth transistor; The pull-down component includes a ninth transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the ninth transistor being coupled to the second terminal of the eighth transistor, the second terminal of the ninth transistor being coupled to the second voltage, and the control terminal of the ninth transistor being coupled to the output terminal of the first inverter; as well as The voltage maintaining component includes a tenth transistor, including a first end, a second end and a control end, the first end of the tenth transistor is coupled to the third voltage, the second end of the tenth transistor is coupled to the second end of the eighth transistor, and the control end of the tenth transistor receives the first input signal.

11. The voltage level shifter according to claim 10, wherein: The seventh transistor is a P-type field effect transistor, the tenth transistor is an N-type field effect transistor, the eighth transistor and the ninth transistor are high-voltage metal oxide semiconductor field effect transistors, the back gate of the seventh transistor is coupled to the second end of the seventh transistor, and the back gate of the eighth transistor is coupled to the first end of the eighth transistor.

12. The voltage level shifter according to claim 10, wherein: When the first input signal is at a low voltage level, the seventh transistor is turned on to charge the first capacitor to the third voltage, the eighth transistor is turned off, and the ninth transistor is turned on to pull the first boosted voltage down to the second voltage.

13. The voltage level shifter according to claim 10, wherein: When the first input signal is converted from a low voltage level to a high voltage level, the seventh transistor is turned off, the eighth transistor is turned on, and the ninth transistor is turned off, so as to increase the first boost voltage to be greater than the third voltage through the voltage of the first capacitor.

14. The voltage level shifter according to claim 13, wherein: During the period when the first input signal is at the high voltage level, when the first boosted voltage is greater than the third voltage, the tenth transistor remains off until the first boosted voltage gradually decreases to be equal to the third voltage, so that the first boosted voltage is maintained at the third voltage.

15. The voltage level shifter according to claim 10, wherein: The plurality of boost circuit blocks include a second boost circuit block, and in the second boost circuit block The boost and charging components include: an eleventh transistor comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the eleventh transistor is coupled to the third voltage, and the control terminal of the eleventh transistor receives a second input signal of the input signal, wherein the second input signal is inversely proportional to the first input signal; and a second capacitor comprising a first end and a second end, wherein the first end of the second capacitor is coupled to the second end of the eleventh transistor, and the second end of the second capacitor receives the second input signal; The transmission control component includes a twelfth transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the twelfth transistor being coupled to the second terminal of the eleventh transistor and the first terminal of the second capacitor, the second terminal of the twelfth transistor being coupled to the second boost input terminal and outputting the second boost voltage; The logic component includes a second inverter including an input terminal and an output terminal, the input terminal of the second inverter receiving the second input signal, and the output terminal of the second inverter coupled to the control terminal of the twelfth transistor; the pull-down component includes a thirteenth transistor including a first terminal, a second terminal, and a control terminal, the first terminal of the thirteenth transistor being coupled to the second terminal of the twelfth transistor, the second terminal of the thirteenth transistor being coupled to the second voltage, and the control terminal of the thirteenth transistor being coupled to the output terminal of the second inverter; and The voltage maintaining component includes a fourteenth transistor, including a first end, a second end and a control end, the first end of the fourteenth transistor is coupled to the third voltage, the second end of the fourteenth transistor is coupled to the second end of the twelfth transistor, and the control end of the fourteenth transistor receives the second input signal.

16. The voltage level shifter according to claim 15, wherein: The eleventh transistor is a P-type field effect transistor, the fourteenth transistor is an N-type field effect transistor, the twelfth transistor and the thirteenth transistor are high-voltage metal oxide semiconductor field effect transistors, the back gate of the eleventh transistor is coupled to the second end of the eleventh transistor, and the back gate of the twelfth transistor is coupled to the first end of the twelfth transistor.

17. The voltage level shifter according to claim 1, wherein: Also includes: The buffer circuit is coupled to the voltage level shift circuit, operates between the first voltage and the second voltage, and is configured to receive the shifted voltage to provide an output signal.

18. The voltage level shifter according to claim 17, wherein: The buffer circuit comprises: a fifteenth transistor comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifteenth transistor is coupled to the first voltage, and the control terminal of the fifteenth transistor is coupled to the shift output terminal; a sixteenth transistor, comprising a first terminal, a second terminal, and a control terminal, the first terminal of the sixteenth transistor being coupled to the second terminal of the fifteenth transistor, the second terminal of the sixteenth transistor being coupled to the second voltage, and the control terminal of the sixteenth transistor being coupled to the shift output terminal; a seventeenth transistor comprising a first terminal, a second terminal, and a control terminal, the first terminal of the seventeenth transistor being coupled to the first voltage, the control terminal of the seventeenth transistor being coupled to the second terminal of the fifteenth transistor and the first terminal of the sixteenth transistor; and The eighteenth transistor includes a first end, a second end, and a control end. The first end of the eighteenth transistor is coupled to the second end of the seventeenth transistor and outputs the output signal. The second end of the eighteenth transistor is coupled to the second voltage. The control end of the eighteenth transistor is coupled to the second end of the fifteenth transistor and the first end of the sixteenth transistor.

19. The voltage level shifter according to claim 18, wherein: The fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are high-voltage metal oxide semiconductor field effect transistors.

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