A correlated double sampling successive approximation analog-to-digital converter and a conversion method thereof

Abstract

The application discloses a correlated double sampling successive approximation analog-to-digital converter and a conversion method thereof. The analog-to-digital converter comprises a shift register, a comparator, a positive-phase conversion capacitor array and a negative-phase conversion capacitor array; the positive-phase conversion capacitor array and the negative-phase conversion capacitor array receive a reference voltage, an input voltage and a reset voltage through a reference voltage interface, a signal voltage interface and a reset voltage interface respectively for signal processing, and output a voltage signal to the comparator; a positive-phase input end of the comparator is connected with the positive-phase conversion capacitor array, a negative-phase input end is connected with the negative-phase conversion capacitor array, and an output is connected with the shift register; voltage signals of the positive-phase conversion capacitor array and the negative-phase conversion capacitor array are received by the positive-phase input end and the negative-phase input end respectively for comparison, and valid bit data is output and stored to the shift register. By adopting a single-end signal input and a maximum capacitor bridging structure, the overall area and power consumption of an image sensor readout circuit can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital converter, in particular to a correlated double sampling successive approximation analog-to-digital converter and a conversion method thereof. BACKGROUND

[0002] CMOS image sensor (CIS) is a typical solid image sensor, and its core function is to convert optical signals into electrical signals by using a photoelectric detector, and then amplify, digitize and transmit the signals through a readout integrated circuit (ROIC), so that the optical information is finally presented in the form of an image.

[0003] The readout circuit of the CMOS image sensor is composed of four modules: a correlated double sampling circuit, a signal amplification circuit, an analog-to-digital conversion circuit and a transmission interface circuit. Due to the influence of process manufacturing and actual application, the output of the image sensor readout circuit will deviate under the same input (under the same light condition) or without light, and this deviation is defined as fixed pattern noise. This noise is the largest contributor to the noise in the readout circuit, and has a great influence on the overall performance of the circuit, reducing the clarity and quality of the image.

[0004] In order to eliminate this noise, a noise compensation circuit is often introduced in the design of CMOS chip, which increases the chip layout area and power consumption, and has obvious use limitations in small size pixel array. SUMMARY

[0005] Therefore, the present application provides a correlated double sampling successive approximation analog-to-digital converter and a conversion method thereof.

[0006] The first aspect of the present application provides a correlated double sampling successive approximation analog-to-digital converter, comprising a shift register, a comparator, a positive conversion capacitor array and a negative conversion capacitor array.

[0007] The positive conversion capacitor array and the negative conversion capacitor array are respectively connected to a reference voltage interface, a signal ground, an input voltage interface and a reset voltage interface; the reference voltage, the input voltage and the reset voltage are respectively received through the reference voltage interface, the signal voltage interface and the reset voltage interface for signal processing, and the voltage signal is output to the comparator;

[0008] The positive input end of the comparator is connected to the positive conversion capacitor array, the negative input end is connected to the negative conversion capacitor array, and the output is connected to the shift register; the voltage signals of the positive conversion capacitor array and the negative conversion capacitor array are respectively received through the positive input end and the negative input end for comparison, and the valid bit data is stored to the shift register.

[0009] Further, the positive conversion capacitor array and the negative conversion capacitor array are composed of a plurality of capacitors arranged in binary weighting;

[0010] The top plate of the largest capacitor at one end of the array is connected to a reference voltage interface through a sampling switch, the top plate of the smallest capacitor at the other end of the array is connected to the positive input terminal or the negative input terminal of the comparator, and the top plate of the capacitor in the middle of the array is connected to the adjacent capacitor through a bridge switch;

[0011] The bottom plate of each capacitor is connected to a signal ground or a reference voltage interface through a sampling switch;

[0012] In the positive conversion capacitor array, the bottom plate of the largest capacitor is also connected to an input voltage interface through a sampling switch, and the top plate of the smallest capacitor is also connected to a reset voltage interface through a sampling switch;

[0013] In the negative conversion capacitor array, the bottom plate of the largest capacitor is also connected to a reset voltage interface through a sampling switch, and the top plate of the smallest capacitor is also connected to an input voltage interface through a sampling switch.

[0014] Further, the top plate of the smallest capacitor is also connected to a signal ground.

[0015] Further, in the positive conversion capacitor array and the negative conversion capacitor array, the capacitance difference between adjacent capacitors is 2 times.

[0016] The second aspect of the present application discloses a correlated double sampling analog-to-digital conversion method, applied to the correlated double sampling successive approximation analog-to-digital converter of the first aspect, and characterized by comprising the following steps:

[0017] In the first time period, the input voltage is sampled through the positive conversion capacitor array and the negative conversion capacitor array;

[0018] In the second time period, the reset voltage is sampled through the positive conversion capacitor array and the negative conversion capacitor array;

[0019] The signal is preprocessed in the positive conversion capacitor array and the negative conversion capacitor array;

[0020] The output potentials of the positive conversion capacitor array and the negative conversion capacitor array are compared through the comparator, and the valid bit data is stored to the shift register;

[0021] According to the output valid bit data, the sampling switch of the positive phase conversion capacitor array or the negative phase conversion capacitor array is switched, the step of comparing the output potentials of the positive phase conversion capacitor array and the negative phase conversion capacitor array through the comparator is returned, the comparison of the output potentials of the positive phase conversion capacitor array and the negative phase conversion capacitor array through the comparator is re-computed, new valid bit data is obtained, and the new valid bit data is stored in the shift register until the number of valid bit data reaches the number of bits of the analog-to-digital converter.

[0022] Further, the sampling of the input voltage through the positive phase conversion capacitor array and the negative phase conversion capacitor array in the first time period to obtain an input signal specifically includes the following steps:

[0023] In the positive phase conversion capacitor array, the bridge switch between the top plate of the largest capacitor and the adjacent capacitor is disconnected, the sampling switch between the top plate of the largest capacitor and the reference voltage interface is closed, the sampling switches of the bottom plates of the capacitors other than the largest capacitor are connected to the signal ground, the sampling switch of the bottom plate of the largest capacitor is connected to the input voltage interface, and the top plate of the largest capacitor has the reference voltage potential and the bottom plate has the input voltage potential.

[0024] In the negative phase conversion capacitor array, the bridge switch between the top plate of the largest capacitor and the adjacent capacitor is disconnected, the sampling switch between the top plate of the largest capacitor and the reference voltage interface is closed, the sampling switches of the bottom plates of the capacitors other than the largest capacitor are connected to the signal ground, the sampling switch of the top plate of the smallest capacitor is connected to the input voltage interface, and the top plate of the largest capacitor has the reference voltage potential and the top plate of the smallest capacitor has the input voltage potential.

[0025] Further, the sampling of the reset voltage through the positive phase conversion capacitor array and the negative phase conversion capacitor array in the second time period to obtain a reset signal specifically includes the following steps:

[0026] In the positive phase conversion capacitor array, the sampling switch between the bottom plate of the largest capacitor and the input voltage interface is disconnected, the sampling switch between the top plate of the smallest capacitor and the reset voltage interface is closed, and the top plate of the smallest capacitor has the reset voltage potential.

[0027] In the negative phase conversion capacitor array, the sampling switch between the top plate of the smallest capacitor and the input voltage interface is disconnected, the sampling switch of the bottom plate of the largest capacitor is connected to the reset voltage interface, and the bottom plate of the largest capacitor has the reset voltage potential.

[0028] Further, the signal preprocessing in the positive phase conversion capacitor array and the negative phase conversion capacitor array specifically includes the following steps:

[0029] In the positive phase conversion capacitor array, the sampling switch between the top plate of the largest capacitor and the reference voltage interface is opened, and the sampling switch connected to the signal ground of the control largest capacitor bottom plate, so that the potential of the largest capacitor top plate is the potential difference between the reference voltage and the input voltage;

[0030] In the negative phase conversion capacitor array, the sampling switch between the top plate of the largest capacitor and the reference voltage interface is opened, and the sampling switch connected to the signal ground of the control largest capacitor bottom plate, so that the potential of the largest capacitor top plate is the potential difference between the reference voltage and the reset voltage.

[0031] Further, the output signal of the positive phase conversion capacitor array and the negative phase conversion capacitor array is compared by the comparator, specifically including the following steps:

[0032] In the positive phase conversion capacitor array, the bridge switch between the largest capacitor and the adjacent capacitor is closed, so that the largest capacitor top plate has the following potential and is input to the positive input end of the comparator:

[0033] ;

[0034] Wherein, V ref The reference voltage potential is represented by Vref, V rst The reset voltage potential is represented by Vreset, V sign The input voltage potential is represented by Vin;

[0035] In the negative phase conversion capacitor array, the bridge switch between the largest capacitor and the adjacent capacitor is closed, so that the largest capacitor top plate has the following potential and is input to the negative input end of the comparator:

[0036] ;

[0037] The size of the positive input end potential and the negative input end potential is compared in the comparator;

[0038] When the positive input end potential is greater than the negative input end potential, the valid bit data is set to 1;

[0039] When the negative input end potential is greater than the positive input end potential, the valid bit data is set to 0.

[0040] Further, according to the output valid bit data, the sampling switch of the positive phase conversion capacitor array or the negative phase conversion capacitor array is switched, specifically including the following steps:

[0041] When the effective bit data of the ith comparison is 1, the capacitor bottom plate sampling switch of the ith bit in the inverting conversion capacitor array is connected to the reference potential, so that the top plate of the inverting capacitor array has the following potential and is input to the inverting input end of the comparator:

[0042] ;

[0043] When the effective bit data of the ith comparison is 0, the capacitor bottom plate sampling switch of the ith bit in the non-inverting conversion capacitor array is connected to the reference potential, so that the top plate of the non-inverting capacitor array has the following potential and is input to the non-inverting input end of the comparator:

[0044] .

[0045] The embodiment of the present application has the following beneficial effects: the correlated double sampling successive approximation type analog-to-digital converter and the conversion method thereof directly implement the correlated double sampling technology without additional circuits, so that the area and power consumption of the image sensor readout circuit are reduced.

[0046] Additional aspects and advantages of the present application will be described in the following description section, some of which will become apparent from the following description, or will be understood through practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0048] Figure 1 is a structure schematic diagram of a correlated double sampling successive approximation type analog-to-digital converter of the present application.

[0049] Figure 2 is a step flow schematic diagram of a correlated double sampling analog-to-digital conversion method of the present application.

[0050] Figure 3 is a schematic diagram of the implementation effect of a 3-bit analog-to-digital converter embodiment. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0052] The main principle of the correlated double sampling technology is to subtract the same input signal at different time periods (the output voltage after circuit integration and the output voltage at the reset time) to reduce the noise. It utilizes the continuity of the noise in the time domain. At the same node, the difference after two samplings can greatly eliminate the noise of this type.

[0053] The first embodiment of the present application integrates the correlated double sampling process and the analog-to-digital conversion process to form a correlated double sampling successive approximation analog-to-digital converter. By adopting a single-ended signal input and a maximum capacitor bridging structure, the overall area and power consumption of the image sensor readout circuit are reduced.

[0054] As shown in Figure 1 , the present embodiment provides a correlated double sampling successive approximation analog-to-digital converter, which comprises a shift register, a comparator, a positive conversion capacitor array and a negative conversion capacitor array;

[0055] The positive conversion capacitor array and the negative conversion capacitor array are respectively connected to a reference voltage interface, a signal ground, an input voltage interface and a reset voltage interface; the reference voltage, the input voltage and the reset voltage are respectively received through the reference voltage interface, the signal voltage interface and the reset voltage interface for signal processing, and the output voltage signal is output to the comparator;

[0056] The positive input end of the comparator is connected to the positive conversion capacitor array, the negative input end is connected to the negative conversion capacitor array, and the output is connected to the shift register; the voltage signals of the positive conversion capacitor array and the negative conversion capacitor array are respectively received through the positive input end and the negative input end for comparison, and the valid bit data is stored to the shift register.

[0057] Specifically, the positive conversion capacitor array and the negative conversion capacitor array are composed of a plurality of capacitors arranged in binary weighting, and the last capacitor is used as a filter capacitor. As shown in Figure 1 , the capacitors are 2 N-2 C, 2 N-3 C, …, 2C, C, C; N represents the bit number of the digital-to-analog converter; C represents a unit capacitor. In the present embodiment, the top plate of the maximum capacitor 2 N-2 C at one end of the array is connected to the reference voltage interface through a sampling switch V ref , and the top plate of the minimum capacitor C at the other end of the array is connected to the positive input end or the negative input end of the comparator. Among the capacitors, the maximum capacitor 2 N-2The top plate of C and the capacitor in the middle (2) N- 3 The top plate of (C, ..., 2C) is connected by a bridge switch, which is connected to the maximum capacitor 2. N-2 C's top plate and intermediate capacitor (2) N-3 Between the top plates of C, ..., 2C);

[0058] The base plate of each capacitor is connected to signal ground (gnd) or a reference voltage interface via a sampling switch. V ref ;

[0059] In the inverting capacitor array, the base plate of the largest capacitor is also connected to the input voltage interface via a sampling switch. V sign The top plate of the smallest capacitor is also connected to the reset voltage interface via a sampling switch. V rst ;

[0060] In the inverting capacitor array, the base plate of the largest capacitor is also connected to the reset voltage interface via a sampling switch. V rst The top plate of the smallest capacitor is also connected to the input voltage interface via a sampling switch. V sign .

[0061] In this embodiment of the invention, the base plate of the smallest capacitor is connected to signal ground gnd.

[0062] In this embodiment of the invention, the capacitance difference between adjacent capacitors in the forward-conversion capacitor array and the reverse-conversion capacitor array is 2 times.

[0063] like Figure 2 As shown, the second embodiment of the present invention discloses a correlated double-sampling analog-to-digital converter method, applied to a correlated double-sampling successive approximation analog-to-digital converter of the first embodiment, including the following steps:

[0064] S1. During the first time period, the input voltage is sampled using the positive-phase switching capacitor array and the negative-phase switching capacitor array.

[0065] In step S1, during the first time period, the input voltage is sampled using the inverting and non-inverting capacitor arrays to obtain the input signal. This specifically includes the following steps:

[0066] In the positive phase conversion capacitor array, the bridge switch between the top plate of the maximum capacitor and the adjacent capacitor is opened, the sampling switch between the top plate of the maximum capacitor and the reference voltage interface is closed, the sampling switch of the bottom plate of the capacitor other than the maximum capacitor is connected to the signal ground; the sampling switch of the bottom plate of the maximum capacitor is connected to the input voltage interface; so that the top plate of the maximum capacitor has a reference voltage potential V ref , the bottom plate has an input voltage potential V sign ;

[0067] In the negative phase conversion capacitor array, the bridge switch between the top plate of the maximum capacitor and the adjacent capacitor is opened, the sampling switch between the top plate of the maximum capacitor and the reference voltage interface is closed, the sampling switch of the bottom plate of the capacitor other than the maximum capacitor is connected to the signal ground; the sampling switch of the top plate of the minimum capacitor is connected to the input voltage interface; so that the top plate of the maximum capacitor has a reference voltage potential V ref , the top plate of the minimum capacitor has an input voltage potential V sign .

[0068] S2. In the second time period, the reset voltage is sampled by the positive phase conversion capacitor array and the negative phase conversion capacitor array.

[0069] In step S2, in the second time period, the reset voltage is sampled by the positive phase conversion capacitor array and the negative phase conversion capacitor array to obtain a reset signal, specifically including the following steps:

[0070] In the positive phase conversion capacitor array, the sampling switch between the bottom plate of the maximum capacitor and the input voltage interface is opened; the sampling switch between the top plate of the minimum capacitor and the reset voltage interface is closed; so that the top plate of the minimum capacitor has a reset voltage potential V rst ;

[0071] In the negative phase conversion capacitor array, the sampling switch between the top plate of the minimum capacitor and the input voltage interface is opened; the sampling switch of the bottom plate of the maximum capacitor is connected to the reset voltage interface; so that the bottom plate of the maximum capacitor has a reset voltage potential V rst .

[0072] S3. Signal preprocessing is performed in the positive phase conversion capacitor array and the negative phase conversion capacitor array.

[0073] In step S3, signal preprocessing is performed in the positive phase conversion capacitor array and the negative phase conversion capacitor array, specifically including the following steps:

[0074] In the positive phase conversion capacitor array, the sampling switch between the top plate of the largest capacitor and the reference voltage interface is opened, the sampling switch of the bottom plate of the largest capacitor is connected to the signal ground, so that the potential of the top plate of the largest capacitor is the potential difference between the reference voltage and the input voltage V ref - V sign ;

[0075] In the negative phase conversion capacitor array, the sampling switch between the top plate of the largest capacitor and the reference voltage interface is opened, the sampling switch of the bottom plate of the largest capacitor is connected to the signal ground, so that the potential of the top plate of the largest capacitor is the potential difference between the reference voltage and the reset voltage V ref - V rst .

[0076] S4. Comparing the output potentials of the positive phase conversion capacitor array and the negative phase conversion capacitor array by the comparator, and storing the valid bit data to the shift register.

[0077] In step S4, the output signals of the positive phase conversion capacitor array and the negative phase conversion capacitor array are compared by the comparator, which specifically includes the following steps:

[0078] In the positive phase conversion capacitor array, the bridge switch between the largest capacitor and the adjacent capacitor is closed, so that the top plate of the largest capacitor has the following potential and is input to the positive input end of the comparator:

[0079] ;

[0080] Wherein, V ref Vref represents the reference voltage potential, V rst Vreset represents the reset voltage potential, V sign Vin represents the input voltage potential;

[0081] In the negative phase conversion capacitor array, the bridge switch between the largest capacitor and the adjacent capacitor is closed, so that the top plate of the largest capacitor has the following potential and is input to the negative input end of the comparator:

[0082] ;

[0083] The positive input end potential and the negative input end potential are compared in the comparator;

[0084] When the positive input end potential is greater than the negative input end potential, the valid bit data D1 is set to 1;

[0085] When the inverted input potential is greater than the non-inverted input potential, the valid bit data D1 is set to 0.

[0086] S5. According to the output valid bit data, switch the sampling switch of the non-inverted conversion capacitor array or the inverted conversion capacitor array, return to the step of comparing the output potentials of the non-inverted conversion capacitor array and the inverted conversion capacitor array by the comparator, and compare the output potentials of the non-inverted conversion capacitor array and the inverted conversion capacitor array by the comparator again to obtain new valid bit data, and store the new valid bit data to the shift register until the number of valid bit data reaches the number of bits of the analog-to-digital converter.

[0087] In step S5, according to the output valid bit data, switch the sampling switch of the non-inverted conversion capacitor array or the inverted conversion capacitor array, specifically including the following steps:

[0088] When the valid bit data D i of the i-th comparison is 1, the capacitor bottom plate sampling switch of the i-th bit in the inverted conversion capacitor array is connected to the reference potential, so that the top plate of the inverted capacitor array has the following potential and is input to the inverted input end of the comparator:

[0089] ;

[0090] When the valid bit data D i of the i-th comparison is 0, the capacitor bottom plate sampling switch of the i-th bit in the non-inverted conversion capacitor array is connected to the reference potential, so that the top plate of the non-inverted capacitor array has the following potential and is input to the non-inverted input end of the comparator:

[0091] .

[0092] As Figure 3 shown is an implementation effect diagram of a 3-bit analog-to-digital converter, and the working process is divided into the following five stages:

[0093] The first stage: the bridge switch between the largest capacitor and the remaining capacitors is disconnected, the top plate of the largest capacitor is connected to V ref , and the bottom plate of the remaining capacitors is connected to gnd. Close the sampling switch of the bottom plate of the largest capacitor of the non-inverted conversion capacitor array and the top plate of the remaining capacitors of the inverted conversion capacitor array to sample the input signal for the first time period, and collect the input voltage.

[0094] The second stage: after the first time period, the sampling switch of the bottom plate of the largest capacitor of the non-inverted conversion capacitor array and the top plate of the remaining capacitors of the inverted conversion capacitor array is disconnected. Close the sampling switch of the bottom plate of the largest capacitor of the inverted conversion capacitor array and the top plate of the remaining capacitors of the non-inverted conversion capacitor array to sample the reset signal for the second time period, and collect the reset voltage.

[0095] The third stage: after the second time period, the sampling switch of the bottom plate of the maximum capacitor of the positive conversion capacitor array and the top plate of the rest of the capacitors of the negative conversion capacitor array is disconnected, and the sampling stage is completed. Then, the connection of the top plate of the maximum capacitor and V ref is disconnected, and the bottom plate of the maximum capacitor is connected to gnd, and finally the bridge switch between the maximum capacitor and the rest of the capacitors is closed. At this time, the pre-processing stage is completed, and the comparison stage is entered, and the comparator directly performs the first comparison and outputs the valid bit data D1 of the first comparison.

[0096] The fourth stage: according to the result of the first comparison, if D1=1, the reference voltage connected to the bottom plate of the first bit capacitor (maximum capacitor) of the negative conversion capacitor array is switched from gnd to V ref , and the positive conversion capacitor array remains unchanged; on the contrary, if D1=0, the reference voltage connected to the bottom plate of the first bit capacitor (maximum capacitor) of the positive conversion capacitor array is switched from gnd to V ref The voltage on the low voltage side is raised V ref / 2, and then the comparator performs the second comparison, and outputs the valid bit data D2 of the second comparison.

[0097] The fifth stage: according to the result of the last comparison, if D2=1, the reference voltage connected to the bottom plate of the corresponding capacitor of the negative conversion capacitor array is switched from gnd to V ref , and the other side remains unchanged; on the contrary, if D2=0, the reference voltage connected to the bottom plate of the corresponding capacitor of the positive conversion capacitor array is switched from gnd to V ref The voltage on the low voltage side is raised V ref / 4, and then the comparator performs the third comparison, and outputs the valid bit data D3 of the third comparison. Finally, the arrangement of D1D2D3 is obtained. 3-bit digital signal output.

[0098] The present application realizes the related double sampling technology directly by the analog-to-digital converter without additional circuit through the separate sampling of the maximum capacitor and the rest of the capacitors of the positive conversion capacitor array and the negative conversion capacitor array in two time periods, and through the pre-processing steps of the reference voltage switching and the bridge switch, so that the area and power consumption of the image sensor readout circuit are reduced.

[0099] Those skilled in the art can understand that the modules in the device in the embodiments of the present application can be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments of the present application can be combined into one module or unit or component, and furthermore can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, all combinations of all features disclosed in the present specification (including the corresponding claims, abstract and drawings) and all processes or units of any methods or apparatuses so disclosed can be adopted. Unless explicitly stated otherwise, each feature disclosed in the present specification (including the corresponding claims, abstract and drawings) can be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0100] Through the description of the above embodiments, those skilled in the art can understand that, for the convenience and brevity of description, only the division of the above functional modules is exemplified, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0101] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0102] In addition, the terms "first", "second", and the like used in the embodiments of the present application are only for the purpose of description, and can not be understood as indicating or implying relative importance, or implicitly indicating the number of technical features indicated in the embodiments. Therefore, the features defined with "first", "second" and the like in the embodiments of the present application can explicitly or implicitly indicate that the embodiments include at least one of the features. In the description of the present application, the meaning of the word "plurality" is at least two or two or more, for example, two, three, four, and the like, unless otherwise explicitly specified in the embodiments.

[0103] In the embodiments of the present application, the terms "comprising" and "including" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not only include those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element, and furthermore, components, features, elements with the same name in different embodiments of the present application can have the same meaning or different meanings, and the specific meaning thereof should be determined in the light of its explanation in the specific embodiment or further in combination with the context in the specific embodiment.

[0104] Although the embodiments of the present application have been shown and described above, it is to be understood that the above-described embodiments are exemplary only, and are not to be taken in a limiting sense, but in their conception and true scope thereof, it is understood that changes in the above-described embodiments come within the scope of the present application. It will be readily apparent to those skilled in the art that certain modifications can be made to the above-described embodiments without departing from the scope of the present application. Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the present application. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice in the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the application being indicated by the following claims.

Claims

1. A correlation-dual-sampling successive approximation analog-to-digital converter, characterized in that, It includes a shift register, a comparator, a positive phase conversion capacitor array, and an inverting phase conversion capacitor array; The positive phase conversion capacitor array and the negative phase conversion capacitor array are respectively connected to the reference voltage interface, signal ground, input voltage interface and reset voltage interface; The comparator receives the reference voltage, input voltage, and reset voltage through the reference voltage interface, signal voltage interface, and reset voltage interface, respectively, processes the signals, and outputs the voltage signal to the comparator. The comparator's non-inverting input is connected to a non-inverting capacitor array, its inverting input is connected to an inverting capacitor array, and its output is connected to a shift register. The comparator receives voltage signals from the non-inverting and inverting capacitor arrays respectively through its non-inverting and inverting inputs, compares them, and stores the valid bits of data in the shift register. Both the forward-conversion capacitor array and the reverse-conversion capacitor array include a maximum capacitor, an intermediate capacitor array, and a minimum capacitor. The capacitors in both the forward-conversion capacitor array and the reverse-conversion capacitor array are arranged in groups of 2. N-2 C,2 N-3 The order of C, ..., 2C, C, C is: C; N represents the number of bits in the digital-to-analog converter. C represents a unit capacitance; In the positive phase conversion capacitor array, the base plate of the largest capacitor is connected to the input voltage interface, signal ground and reference voltage interface through its corresponding base plate sampling switch. The base plates of the intermediate capacitor array and the smallest capacitor are each connected to the signal ground and reference voltage interface through their respective corresponding base plate sampling switches. In the positive phase conversion capacitor array, the top plate of the largest capacitor is connected to one end of the positive phase reference voltage sampling switch and one end of the positive phase bridge switch. The other end of the positive phase reference voltage sampling switch is connected to the reference voltage interface. The top plates of the intermediate capacitor array and the smallest capacitor are both connected to the other end of the positive phase bridge switch, the positive phase input terminal of the comparator, and one end of the reset voltage sampling switch. The other end of the reset voltage sampling switch is connected to the reset voltage interface. In the inverting capacitor array, the base plate of the largest capacitor is connected to the reset voltage interface, signal ground and reference voltage interface through its corresponding base plate sampling switch. The base plates of the intermediate capacitor array and the smallest capacitor are each connected to the signal ground and reference voltage interface through their respective corresponding base plate sampling switches. In the inverting capacitor array, the top plate of the largest capacitor is connected to one end of the inverting reference voltage sampling switch and one end of the inverting bridge switch. The other end of the inverting reference voltage sampling switch is connected to the reference voltage interface. The top plates of the intermediate capacitor array and the smallest capacitor are both connected to the other end of the inverting bridge switch, the inverting input terminal of the comparator, and one end of the input voltage sampling switch. The other end of the input voltage sampling switch is connected to the input voltage interface.

2. The correlated double-sampling successive approximation analog-to-digital converter according to claim 1, characterized in that, The other smallest capacitor in the positive-phase conversion capacitor array and the negative-phase conversion capacitor array serves as a filter capacitor. The bottom plate of the other smallest capacitor in the positive-phase conversion capacitor array is connected to signal ground, and the top plate is connected to the positive input terminal of the comparator. The bottom plate of the other smallest capacitor in the negative-phase conversion capacitor array is connected to signal ground, and the top plate is connected to the negative input terminal of the comparator.

3. A correlated double-sampling analog-to-digital converter method, applied to a correlated double-sampling successive approximation analog-to-digital converter as described in any one of claims 1-2, characterized in that, Includes the following steps: During the first time period, the input voltage is sampled through the positive-phase switching capacitor array and the negative-phase switching capacitor array; During the second time period, the reset voltage is sampled using the positive-phase switching capacitor array and the negative-phase switching capacitor array; Signal preprocessing is performed in the positive-phase switching capacitor array and the negative-phase switching capacitor array; The output potentials of the positive-phase switching capacitor array and the negative-phase switching capacitor array are compared by a comparator, and the valid bit data is stored in a shift register. Based on the output valid bit data, switch the sampling switch of the positive-phase conversion capacitor array or the negative-phase conversion capacitor array, return to the step of comparing the output potentials of the positive-phase conversion capacitor array and the negative-phase conversion capacitor array by the comparator, and re-compare the output potentials of the positive-phase conversion capacitor array and the negative-phase conversion capacitor array by the comparator to obtain new valid bit data stored in the shift register until the number of valid bit data reaches the number of bits of the analog-to-digital converter.

4. The correlated double-sampling analog-to-digital conversion method according to claim 3, characterized in that, During the first time period, the input voltage is sampled through the positive-phase conversion capacitor array and the negative-phase conversion capacitor array to obtain the input signal, specifically including the following steps: In the positive phase conversion capacitor array, the positive phase bridge switch between the top plate of the largest capacitor and the adjacent capacitor is disconnected, the positive phase reference voltage sampling switch between the top plate of the largest capacitor and the reference voltage interface is closed, and the sampling switches of the bottom plates of other capacitors except the largest capacitor are controlled to be connected to the signal ground; the sampling switch of the bottom plate of the largest capacitor is controlled to be connected to the input voltage interface; so that the top plate of the largest capacitor has a reference voltage potential and the bottom plate has an input voltage potential. In the inverting capacitor array, the inverting bridge switch between the top plate of the largest capacitor and the adjacent capacitor is disconnected, the inverting reference voltage sampling switch between the top plate of the largest capacitor and the reference voltage interface is closed, and the sampling switches of the bottom plates of other capacitors besides the largest capacitor are connected to the signal ground; the input voltage sampling switch of the top plate of the smallest capacitor is connected to the input voltage interface; so that the top plate of the largest capacitor has a reference voltage potential and the top plate of the smallest capacitor has an input voltage potential.

5. The correlated double-sampling analog-to-digital conversion method according to claim 3, characterized in that, During the second time period, the reset voltage is sampled using the positive-phase switching capacitor array and the negative-phase switching capacitor array to obtain the reset signal, specifically including the following steps: In the positive phase conversion capacitor array, the sampling switch between the bottom plate of the largest capacitor and the input voltage interface is disconnected; the reset voltage sampling switch between the top plate of the smallest capacitor and the reset voltage interface is closed; so that the top plate of the smallest capacitor has a reset voltage potential. In the inverting capacitor array, the input voltage sampling switch between the top plate of the smallest capacitor and the input voltage interface is disconnected; the sampling switch of the bottom plate of the largest capacitor is connected to the reset voltage interface; so that the bottom plate of the largest capacitor has a reset voltage potential.

6. The correlated double-sampling analog-to-digital conversion method according to claim 3, characterized in that, The signal preprocessing performed in the positive-phase conversion capacitor array and the negative-phase conversion capacitor array specifically includes the following steps: In the positive phase conversion capacitor array, the positive phase reference voltage sampling switch between the top plate of the maximum capacitor and the reference voltage interface is disconnected, and the sampling switch of the bottom plate of the maximum capacitor is connected to the signal ground, so that the potential of the top plate of the maximum capacitor is the potential difference between the reference voltage and the input voltage. In the inverting capacitor array, the inverting reference voltage sampling switch between the top plate of the maximum capacitor and the reference voltage interface is disconnected, and the sampling switch of the bottom plate of the maximum capacitor is connected to the signal ground, so that the potential of the top plate of the maximum capacitor is the potential difference between the reference voltage and the reset voltage.

7. The correlated double-sampling analog-to-digital conversion method according to claim 3, characterized in that, The step of comparing the output potentials of the positive-phase conversion capacitor array and the negative-phase conversion capacitor array using a comparator specifically includes the following steps: In the positive-inverting capacitor array, closing the positive-inverting bridge switch between the largest capacitor and its adjacent capacitors causes the top plate of the largest capacitor to have the following potential, which is then input to the positive-inverting input of the comparator: ; in, V ref Indicates the reference voltage potential. V rst Indicates the reset voltage potential. V sign Indicates the input voltage potential; In the inverting capacitor array, closing the inverting bridge switch between the largest capacitor and its adjacent capacitors causes the top plate of the largest capacitor to have the following potential, which is then input to the inverting input of the comparator: ; The comparator compares the magnitudes of the potentials at the non-inverting and inverting input terminals. When the potential at the non-inverting input terminal is greater than the potential at the inverting input terminal, the valid bit data is set to 1; When the potential at the inverting input terminal is greater than the potential at the non-inverting input terminal, the valid bit data is set to 0.

8. The correlated double-sampling analog-to-digital conversion method according to claim 3, characterized in that, The step of switching the sampling switch of the positive-phase conversion capacitor array or the negative-phase conversion capacitor array according to the output valid bit data specifically includes the following steps: When the valid bit data of the i-th comparison is 1, the sampling switch of the bottom plate of the i-th capacitor in the inverting capacitor array is connected to the reference potential, so that the top plate of the inverting capacitor array has the following potential and is input to the inverting input terminal of the comparator: ; When the valid bit data of the i-th comparison is 0, the sampling switch of the bottom plate of the i-th capacitor in the positive-inverting capacitor array is connected to the reference potential, so that the top plate of the positive capacitor array has the following potential and is input to the positive input terminal of the comparator: .

Images