Signal loss detection circuit and control method

Abstract

The invention provides a signal loss detection circuit and a control method. The circuit comprises a waveform generator, a reference peak detector, a data peak detector, a comparator, a signal loss indicator, a digital-to-analog converter and a clock source. The waveform generator is connected with the digital-to-analog converter through a vref pin, the waveform generator is connected with the clock source through a clk pin, the waveform generator is connected with the signal loss indicator through a hys pin, and the waveform generator is connected with the reference peak detector through a vop pin and a von pin; the reference peak detector is connected with a normal phase input end of the comparator, the data peak detector is connected with an inverted phase input end of the comparator, and an output end of the comparator is connected with the signal loss indicator. According to the invention, the waveform generator is adopted to generate the reference waveform with the same four-level pulse amplitude modulation code pattern as the input data waveform, so that the problem of mismatching of conversion efficiency in the prior art is solved, and high-precision signal loss detection is realized.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a signal loss detection circuit and control method. Background Art

[0002] With the rapid development of high-speed communication systems, various modulation technologies, such as PAM4 (four-level pulse amplitude modulation), are being widely used to increase data transmission rates. Signal integrity is crucial in high-speed communication links, and loss of signal (LOS) detection circuits are key modules for ensuring system reliability. Traditional LOS detection circuits monitor the peak-to-peak amplitude of the input signal to determine the signal status. When the signal amplitude falls below a preset threshold, an alarm is triggered to prevent data transmission errors caused by signal attenuation.

[0003] In practical applications, LOS detection circuits typically use a peak detector (PKD) to extract the envelope information of the input signal and compare it with a fixed DC reference voltage. However, this detection method based on a fixed DC threshold has inherent flaws. The conversion efficiency of the peak detector circuit varies depending on the input signal type. Because traditional LOS detection does not consider the impact of signal modulation on the detection results, the use of a uniform DC threshold introduces systematic errors, making the fixed-threshold LOS judgment mechanism inaccurately reflect the actual signal state. When the system processes PAM4 signals, this detection error can lead to false alarms or missed detections, thereby affecting the reliability of the communication system. Summary of the Invention

[0004] In light of this, the present application aims to provide a signal loss detection circuit and control method. This circuit utilizes a waveform generator to generate a reference waveform with the same four-level pulse amplitude modulation pattern as the input data waveform, replacing the DC signal used in the prior art. After passing through a peak detector, the reference waveform and the input data waveform have the same conversion efficiency, resolving the conversion efficiency mismatch issue found in the prior art and enabling high-precision signal loss detection.

[0005] In a first aspect, an embodiment of the present application provides a signal loss detection circuit, the signal loss detection circuit comprising: a waveform generator, a reference peak detector, a data peak detector, a comparator, a signal loss indicator, a digital-to-analog converter, and a clock source; The waveform generator is connected to the digital-to-analog converter via a vref pin, the waveform generator is connected to the clock source via a clk pin, the waveform generator is connected to the signal loss indicator via a hys pin, and the waveform generator is connected to the reference peak detector via a vop pin and a von pin; The reference peak detector is connected to a non-inverting input terminal of the comparator, the data peak detector is connected to an inverting input terminal of the comparator, and an output terminal of the comparator is connected to the signal loss indicator.

[0006] Furthermore, the waveform generator includes a pseudo-random binary sequence generator, a selector, a trigger, a driver and an adder; The output end of the pseudo-random binary sequence generator is connected to the input end of the selector, the output end of the selector is connected to the input end of the trigger, the output end of the trigger is connected to the input end of the driver, and the output end of the driver is connected to the input end of the adder.

[0007] Furthermore, the adder further includes a first error amplifier, a second error amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first NPN transistor, a second NPN transistor, a third NPN transistor, and a fourth NPN transistor; wherein, The first error amplifier and the second error amplifier control the bias currents of the first NMOS transistor and the second NMOS transistor respectively through a feedback loop.

[0008] Furthermore, the source of the first NMOS transistor is connected to the positive end of the first resistor, and the negative end of the first resistor is grounded; The source of the second NMOS transistor is connected to the positive end of the second resistor, and the negative end of the second resistor is grounded; The drain of the first NMOS transistor is connected to the emitter of the first NPN transistor and the emitter of the second NPN transistor, and the drain of the second NMOS transistor is connected to the emitter of the third NPN transistor and the emitter of the fourth NPN transistor.

[0009] Furthermore, the base of the first NPN transistor is connected to the most significant bit positive input signal msbp, and the collector of the first NPN transistor is connected to the negative end of the fifth resistor as the negative output end of the adder; The base of the second NPN transistor is connected to the most significant bit negative input signal MSBN, and the collector of the second NPN transistor is connected to the negative end of the sixth resistor as the positive output end of the adder; The base of the third NPN transistor is connected to the least significant bit positive input signal lsbp, and the collector of the third NPN transistor is connected to the negative end of the fifth resistor as the negative output end of the adder; The base of the fourth NPN transistor is connected to the least significant bit negative input signal lsbn, and the collector of the fourth NPN transistor is connected to the negative end of the sixth resistor as the positive output end of the adder.

[0010] Furthermore, the source of the third NMOS transistor is connected to the positive end of the third resistor, the source of the fourth NMOS transistor is connected to the positive end of the fourth resistor, and the negative end of the third resistor and the negative end of the fourth resistor are grounded; The drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, the drain of the fifth NMOS transistor is connected to the emitter of the first NPN transistor and the emitter of the second NPN transistor, and the drain of the sixth NMOS transistor is connected to the emitter of the third NPN transistor and the emitter of the fourth NPN transistor; The gate of the third NMOS tube is connected to the output end of the first error amplifier, the gate of the fourth NMOS tube is connected to the output end of the second error amplifier, and the gates of the fifth NMOS tube and the sixth NMOS tube are connected to the hys pin.

[0011] Furthermore, the signal loss detection circuit further includes a variable capacitor array, and the variable capacitor array is arranged at the output end of the waveform generator.

[0012] In a second aspect, an embodiment of the present application further provides a control method for a signal loss detection circuit, the control method being applied to the signal loss detection circuit, the control method comprising: When the digital-to-analog converter receives the digital control signal, the digital-to-analog converter is controlled to convert the digital control signal into a DC voltage and transmit the DC voltage as a reference signal to the waveform generator; controlling the waveform generator to generate a reference waveform based on the reference signal, and transmitting the reference waveform to a reference peak detector, so that the reference peak detector inputs a reference peak signal generated based on the reference waveform into a comparator; When the data peak detector receives an input data waveform, the data peak detector is controlled to generate a peak signal based on the input data waveform and input the peak signal to the comparator; wherein the reference waveform and the input data waveform are both four-level pulse amplitude modulation patterns; The comparator is controlled to output a signal loss detection signal based on a comparison result between the peak signal and the reference peak signal.

[0013] Furthermore, the waveform generator includes a pseudo-random binary sequence generator, a selector, a trigger, a driver, and an adder, and the control method further includes: When the pseudo-random binary sequence generator receives a clock signal, controlling the pseudo-random binary sequence generator to generate a pseudo-random binary sequence and transmitting the pseudo-random binary sequence to the selector; When the selector receives a control signal, the selector is controlled to determine a first input signal of the driver from the clock signal and the pseudo-random binary sequence; Using the first input signal as a clock signal of the trigger to control the trigger to generate a second input signal of the driver; The driver is controlled to transmit the first input signal and the second input signal to the adder, so that the adder generates the reference waveform.

[0014] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate through the bus, and when the machine-readable instructions are executed by the processor, the steps of the control method of the signal loss detection circuit as described above are performed.

[0015] Embodiments of the present application provide a signal loss detection circuit and control method. The signal loss detection circuit includes a waveform generator, a reference peak detector, a data peak detector, a comparator, a signal loss indicator, a digital-to-analog converter, and a clock source. The waveform generator is connected to the digital-to-analog converter via a vref pin, the waveform generator is connected to the clock source via a clk pin, the waveform generator is connected to the signal loss indicator via a hys pin, and the waveform generator is connected to the reference peak detector via a vop pin and a von pin. The reference peak detector is connected to the non-inverting input of the comparator, the data peak detector is connected to the inverting input of the comparator, and the output of the comparator is connected to the signal loss indicator.

[0016] This application uses a waveform generator to generate a reference waveform, Wave_ref, with the same four-level pulse amplitude modulation (PAM4) pattern as the input data waveform, Data_in, replacing the DC signal Vth used in the prior art. This allows the reference waveform, Wave_ref, and the input data waveform, Data_in, to achieve the same conversion efficiency after passing through the peak detector, resolving the conversion efficiency mismatch issue found in the prior art and enabling high-precision signal loss detection, particularly for PAM4 signals. Furthermore, a feedback loop is used to control the peak-to-peak value of the output signal to be equal to the reference voltage, while simultaneously implementing four-level pulse amplitude modulation encoding of the output signal, precisely controlling the peak-to-peak value of the output signal and realizing a hysteresis function.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 This is one of the structural diagrams of a signal loss detection circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a waveform generator provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of an adder provided in an embodiment of the present application; Figure 4 This is a second structural diagram of a signal loss detection circuit provided in an embodiment of the present application; Figure 5 A flow chart of a control method for a signal loss detection circuit provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application for which protection is claimed, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, each other embodiment obtained by those skilled in the art without making creative work falls within the scope of protection of the present application.

[0021] First, the application scenarios to which this application is applicable are introduced. This application can be applied in the field of communication technology.

[0022] With the rapid development of high-speed communication systems, various modulation technologies, such as PAM4 (four-level pulse amplitude modulation), are being widely used to increase data transmission rates. Signal integrity is crucial in high-speed communication links, and loss of signal (LOS) detection circuits are key modules for ensuring system reliability. Traditional LOS detection circuits monitor the peak-to-peak amplitude of the input signal to determine the signal status. When the signal amplitude falls below a preset threshold, an alarm is triggered to prevent data transmission errors caused by signal attenuation.

[0023] Research has found that in practical applications, LOS detection circuits typically use a peak detector (PKD) to extract the input signal's envelope information and compare it with a fixed DC reference voltage. However, this detection method based on a fixed DC threshold has inherent flaws: the peak detection circuit's conversion efficiency varies depending on the input signal type. Because traditional LOS detection fails to consider the impact of signal modulation on the detection results, the use of a uniform DC threshold introduces systematic errors, making it difficult for the fixed-threshold LOS determination mechanism to accurately reflect the actual signal state. When the system processes PAM4 signals, this detection error can lead to false alarms or missed detections, compromising the reliability of the communication system.

[0024] Based on this, an embodiment of the present application provides a signal loss detection circuit and control method, which uses a waveform generator to generate a reference waveform with the same four-level pulse amplitude modulation code as the input data waveform. After passing through the peak detector, the reference waveform and the input data waveform have the same conversion efficiency, solving the conversion efficiency mismatch problem existing in the prior art, thereby achieving high-precision signal loss detection.

[0025] See also Figure 1 , Figure 1 This is one of the structural diagrams of a signal loss detection circuit provided in an embodiment of the present application. Figure 1 As shown in , the signal loss detection circuit 100 provided in the embodiment of the present application includes: a waveform generator 110, a reference peak detector 120, a data peak detector 130, a comparator 140, a signal loss indicator 150, a digital-to-analog converter 160 and a clock source 170.

[0026] Here, the waveform generator (WaveGenerator, WG) 110 generates a reference waveform, Wave_ref, which is a four-level pulse amplitude modulation (PAM4) pattern signal with a peak-to-peak value equal to the reference voltage vref. The reference peak detector (PKD_R) 120 performs envelope detection on the reference waveform Wave_ref generated by waveform generator 110 and extracts its DC voltage signal Vpkd_th. The data peak detector (PKD_D) 130 performs envelope detection on the input data waveform Data_in and extracts its DC voltage signal Vpkd_data. The comparator (Comparator) 140 compares the DC voltage signal Vpkd_th output by the reference peak detector 120 with the DC voltage signal Vpkd_data output by the data peak detector 130 to determine whether loss of signal (LOS) has occurred.

[0027] Specifically, the waveform generator 110 is connected to the digital-to-analog converter 160 via the vref pin, the waveform generator 110 is connected to the clock source 170 via the clk pin, the waveform generator 110 is connected to the signal loss indicator 150 via the hys pin, and the waveform generator 110 is connected to the reference peak detector 120 via the vop pin and the von pin.

[0028] The reference peak detector 120 is connected to a non-inverting input of the comparator 140 , the data peak detector 130 is connected to an inverting input of the comparator 140 , and an output of the comparator 140 is connected to the signal loss indicator 150 .

[0029] Thus, the loss-of-signal detection circuit 100 provided in the embodiment of the present application uses a waveform generator 110 to generate a reference waveform Wave_ref, replacing the DC signal Vth used in the prior art, as the input signal for the reference peak detector 120. The vref pin of waveform generator 110 receives the DC voltage Vdac generated by the digital-to-analog converter 160 as a reference signal. The clk pin of waveform generator 110 receives the high-speed clock signal generated by the clock source 170 as an output drive clock. The hys pin of waveform generator 110 receives the LOS signal output by the comparator 140 as a hysteresis control signal. Waveform generator 110 generates a PAM4-coded high-speed AC signal with a symbol period equal to (or proportional to) the period of the input clock clk and a peak-to-peak value equal to vref. Waveform generator 110 also generates a hysteresis signal. When the input signal hys is a logic 0, the output signal amplitude is equal to vref. When the input signal hys is a logic 1, the output signal amplitude is equal to (1+K)·vref, where K is greater than 0 and the hysteresis range is equal to K·vref.

[0030] See also Figure 2 , Figure 2 This is a schematic diagram of the structure of a waveform generator provided in an embodiment of the present application. Figure 2 As shown, waveform generator 110 includes a pseudo-random binary sequence generator (PRBS GEN) 111, a selector (MUX) 112, a flip-flop (DFF) 113, a driver (Buffer) 114, and an adder 115 (ADDER) with controllable output amplitude. Adder 115 is designed to implement four-level pulse amplitude modulation encoding of the output signal and precisely control the peak-to-peak value of the output signal. It also implements signal hysteresis.

[0031] The output end of the pseudo-random binary sequence generator 111 is connected to the input end of the selector 112, the output end of the selector 112 is connected to the input end of the trigger 113, the output end of the trigger 113 is connected to the input end of the driver 114, and the output end of the driver 114 is connected to the input end of the adder 115.

[0032] Specifically, pseudo-random binary sequence generator 111 uses the clk signal as a driving clock to generate a pseudo-random binary sequence. Under the control of the sel signal, selector 112 selects the clk signal or the output signal of pseudo-random binary sequence generator 111 as the input signal Data_lsb for the least significant bit (LSB) driver. Data_lsb also serves as the clock signal for flip-flop 113. Flip-flop 113's data input pin D is connected to its inverting output pin Q_bar, while its positive output pin Q generates the input signal Data_msb for the most significant bit (MSB) driver 114. After passing through driver 114, Data_msb and Data_lsb are input to adder 115, which generates an amplitude-controllable PAM4 signal under the control of the vref and hys signals.

[0033] See also Figure 3 , Figure 3 This is a schematic diagram of the structure of an adder provided in an embodiment of the present application. Figure 3 As shown, the adder 115 further includes a first error amplifier AMP1, a second error amplifier AMP2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a first NPN transistor Q1, a second NPN transistor Q2, a third NPN transistor Q3, and a fourth NPN transistor Q4. Here, the NMOS transistors are N-type metal-oxide semiconductor field-effect transistors.

[0034] Specifically, the positive input terminals of the first error amplifier AMP1 and the second error amplifier AMP2 are connected to the reference voltage vref, and the negative input terminals are connected to the first resistor R1, the second resistor R2, the first NMOS transistor M1 and the second NMOS transistor M2 respectively.

[0035] The first error amplifier AMP1 and the second error amplifier AMP2 respectively control the bias currents of the first NMOS transistor M1 and the second NMOS transistor M2 through a feedback loop.

[0036] The source of the first NMOS transistor M1 is connected to the positive end of the first resistor R1, and the negative end of the first resistor R1 is grounded. The source of the second NMOS transistor M2 is connected to the positive end of the second resistor R2, and the negative end of the second resistor R2 is grounded. The drain of the first NMOS transistor M1 is connected to the emitter of the first NPN transistor Q1 and the emitter of the second NPN transistor Q2 to provide bias current for the first NPN transistor Q1 and the second NPN transistor Q2. The drain of the second NMOS transistor M2 is connected to the emitter of the third NPN transistor Q3 and the emitter of the fourth NPN transistor Q4 to provide bias current for the third NPN transistor Q3 and the fourth NPN transistor Q4.

[0037] Here, because the error amplifier has a very high gain, the positive terminal voltage vr1 of the first resistor R1 and the positive terminal voltage vr2 of the second resistor R2 are equal to the reference voltage vref. The bias current Ids1 of the first NMOS transistor M1 and the bias current Ids2 of the second NMOS transistor M2 are equal to vref / R1 and vref / R2, respectively. The most significant bit bias current Ids1 is equal to twice the least significant bit bias current Ids2, meaning the resistance of the second resistor R2 is twice that of the first resistor R1. The sum of Ids1 and Ids2 is the total tail current Isum, where Isum = 3·Ids2.

[0038] The base of the first NPN transistor Q1 is connected to the most significant bit positive input signal msbp, and the collector of the first NPN transistor Q2 is connected to the negative end of the fifth resistor R5 as the negative output terminal von of the adder 115; the base of the second NPN transistor Q2 is connected to the most significant bit negative input signal msbn, and the collector of the second NPN transistor Q2 is connected to the negative end of the sixth resistor R6 as the positive output terminal vop of the adder; the base of the third NPN transistor Q3 is connected to the least significant bit positive input signal lsbp, and the collector of the third NPN transistor Q3 is connected to the negative end of the fifth resistor R5 as the negative output terminal von of the adder 115; the base of the fourth NPN transistor Q4 is connected to the least significant bit negative input signal lsbn, and the collector of the fourth NPN transistor Q4 is connected to the negative end of the sixth resistor R6 as the positive output terminal vop of the adder 115.

[0039] Here, the positive terminals of the fifth resistor R5 and the sixth resistor R6 are connected to the power supply voltage and have equal resistances, assuming their resistances are R. The maximum single-ended output amplitudes of vop and von are the product of their resistances and the total tail current Isum, i.e., Vout_single_end = R·Isum. The differential output signal amplitude Vamp = 2·R·Isum = 6·R·Ids2. The adder's differential output amplitude Vamp is equal to the reference voltage vref, so vref = 6·R·Ids2 = R2·Ids2, resulting in R2 = 6·R and R1 = 3·R.

[0040] The source of the third NMOS transistor M3 is connected to the positive terminal of the third resistor R3, the source of the fourth NMOS transistor M4 is connected to the positive terminal of the fourth resistor R4, and the negative terminals of the third resistor R3 and the fourth resistor R4 are grounded. Here, the third resistor R3, the fourth resistor R4, and the third through sixth NMOS transistors M3 through M6 form a hysteresis current branch.

[0041] The drain of the third NMOS transistor M3 is connected to the source of the fifth NMOS transistor M5, the drain of the fourth NMOS transistor M4 is connected to the source of the sixth NMOS transistor M6, the drain of the fifth NMOS transistor M5 is connected to the emitter of the first NPN transistor Q1 and the emitter of the second NPN transistor Q2, and the drain of the sixth NMOS transistor M6 is connected to the emitter of the third NPN transistor Q3 and the emitter of the fourth NPN transistor Q4.

[0042] The gate of the third NMOS transistor M3 is connected to the output end of the first error amplifier AMP1, the gate of the fourth NMOS transistor M4 is connected to the output end of the second error amplifier AMP2, and the gates of the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are connected to the hys pin.

[0043] Specifically, when hys is logic 0, M5 and M6 are turned off, and the hysteresis bias current is 0; when hys is logic 1, M5 and M6 are turned on, the bias current of M3 is Ids3, the bias current of M4 is Ids4, and the sum of Ids3 and Ids4 is the total hysteresis current Ihys; the channel lengths of M1 and M3 are equal, and the channel widths are proportional, and the proportional relationship is W1 / W3=1 / K; the channel lengths of M2 and M4 are equal, and the channel widths are proportional, and the proportional relationship is W2 / W4=1 / K; the resistance values ​​of R1 and R3 are proportional, and the proportional relationship is R1 / R3=K / 1; the resistance values ​​of R2 and R4 are proportional, and the proportional relationship is R2 / R4=K / 1; it can be obtained that: Ids3=K·Ids1, Ids4=K·Ids2, Ihys= K·Isum. Therefore, when hys is a logic 0, the adder's output amplitude, Amp_A, equals 2·R·Isum=vref. When hys is a logic 1, the adder's output amplitude, Amp_D, equals 2·R·(Isum+Ihys)=(1+K)·vref. When the input signal amplitude is greater than Amp_D, LOS is a logic 0. When the input signal amplitude is less than Amp_A, LOS is a logic 1. The difference between Amp_D and Amp_A is the hysteresis interval of the LOS signal.

[0044] See also Figure 4 , Figure 4 This is a second structural diagram of a signal loss detection circuit provided in an embodiment of the present application. Figure 4 As shown, the signal loss detection circuit 100 further includes a variable capacitor array 180, which is disposed at the output of the waveform generator 110. As an optional embodiment, a register-controllable variable capacitor array 180 can be added to the output of the waveform generator 110, i.e., the Wave_ref signal line. The function of the variable capacitor array 180 is to precisely adjust the output bandwidth of the waveform generator 110 and change the rise and fall times of the Wave_ref signal. The purpose is to achieve a more accurate imitation of the Data_in signal by the Wave_ref signal, further improving the accuracy of signal loss detection.

[0045] An embodiment of the present application provides a signal loss detection circuit, including a waveform generator, a reference peak detector, a data peak detector, a comparator, a signal loss indicator, a digital-to-analog converter, and a clock source. The waveform generator is connected to the digital-to-analog converter via a vref pin, the waveform generator is connected to the clock source via a clk pin, the waveform generator is connected to the signal loss indicator via a hys pin, and the waveform generator is connected to the reference peak detector via a vop pin and a von pin. The reference peak detector is connected to a non-inverting input of the comparator, the data peak detector is connected to an inverting input of the comparator, and the output of the comparator is connected to the signal loss indicator.

[0046] This application uses a waveform generator to generate a reference waveform, Wave_ref, with the same four-level pulse amplitude modulation (PAM4) pattern as the input data waveform, Data_in, replacing the DC signal Vth used in the prior art. This allows the reference waveform, Wave_ref, and the input data waveform, Data_in, to achieve the same conversion efficiency after passing through the peak detector, resolving the conversion efficiency mismatch issue found in the prior art and enabling high-precision signal loss detection, particularly for PAM4 signals. Furthermore, a feedback loop is used to control the peak-to-peak value of the output signal to be equal to the reference voltage, while simultaneously implementing four-level pulse amplitude modulation encoding of the output signal, precisely controlling the peak-to-peak value of the output signal and realizing a hysteresis function.

[0047] See also Figure 5 , Figure 5 This is a flow chart of a control method for a signal loss detection circuit provided in an embodiment of the present application. The control method is applied to the signal loss detection circuit provided in the above embodiment, such as Figure 5 As shown in , the control method provided by the embodiment of the present application includes: S501 , when a digital-to-analog converter receives a digital control signal, controls the digital-to-analog converter to convert the digital control signal into a DC voltage and transmits the DC voltage as a reference signal to a waveform generator.

[0048] Regarding the above step S501, in a specific implementation, when the digital-to-analog converter receives the digital control signal, the digital-to-analog converter converts the digital control signal to obtain a DC voltage, and transmits the DC voltage as a reference signal to the waveform generator.

[0049] S502 , controlling the waveform generator to generate a reference waveform based on the reference signal, and transmitting the reference waveform to a reference peak detector, so that the reference peak detector inputs a reference peak signal generated based on the reference waveform into a comparator.

[0050] Regarding the above step S502, in a specific implementation, the waveform generator generates a reference waveform based on the reference signal and transmits the reference waveform to the reference peak detector, so that the reference peak detector generates a reference peak signal based on the reference waveform and inputs the reference peak signal to the comparator.

[0051] S503, when the data peak detector receives the input data waveform, controls the data peak detector to generate a peak signal based on the input data waveform, and inputs the peak signal to the comparator; wherein the reference waveform and the input data waveform are both four-level pulse amplitude modulation code types.

[0052] Regarding step S503 above, in a specific implementation, when the data peak detector receives the input data waveform, the data peak detector generates a peak signal based on the input data waveform and inputs the peak signal to the comparator. Here, both the reference waveform and the input data waveform are four-level pulse amplitude modulation patterns.

[0053] S504 , controlling the comparator to output a signal loss detection signal based on a comparison result between the peak signal and the reference peak signal.

[0054] Regarding the above step S504 , in a specific implementation, the comparator outputs a signal loss detection signal based on a comparison result between the received peak signal and the reference peak signal.

[0055] Furthermore, the waveform generator includes a pseudo-random binary sequence generator, a selector, a trigger, a driver, and an adder. The control method provided in the embodiment of the present application also includes: A: When the pseudo-random binary sequence generator receives a clock signal, the pseudo-random binary sequence generator is controlled to generate a pseudo-random binary sequence, and the pseudo-random binary sequence is transmitted to the selector.

[0056] Regarding the above step A, in a specific implementation, when the pseudo-random binary sequence generator receives a clock signal, the pseudo-random binary sequence generator generates a pseudo-random binary sequence and transmits the pseudo-random binary sequence to the selector.

[0057] B: When the selector receives a control signal, the selector is controlled to determine the first input signal of the driver from the clock signal and the pseudo-random binary sequence.

[0058] C: Using the first input signal as the clock signal of the trigger to control the trigger to generate the second input signal of the driver.

[0059] Regarding steps B-C above, in a specific implementation, when the selector receives the control signal, it controls the selector to determine the first input signal of the driver from the clock signal and the pseudo-random binary sequence. The first input signal is used as the clock signal of the trigger, and the trigger generates the second input signal of the driver.

[0060] D: Controlling the driver to transmit the first input signal and the second input signal to the adder, so that the adder generates the reference waveform.

[0061] Regarding the above step D, in a specific implementation, the driver transmits the first input signal and the second input signal to the adder, so that the adder generates a reference waveform.

[0062] A control method for a signal loss detection circuit provided in an embodiment of the present application is applied to the signal loss detection circuit. When a digital-to-analog converter receives a digital control signal, the method controls the digital-to-analog converter to convert the digital control signal to obtain a DC voltage and transmits the DC voltage as a reference signal to a waveform generator. The method controls the waveform generator to generate a reference waveform based on the reference signal and transmits the reference waveform to a reference peak detector, so that the reference peak detector inputs a reference peak signal generated based on the reference waveform into a comparator. When a data peak detector receives an input data waveform, the method controls the data peak detector to generate a peak signal based on the input data waveform and inputs the peak signal into the comparator. The reference waveform and the input data waveform both employ four-level pulse amplitude modulation patterns. The method controls the comparator to output a signal loss detection signal based on a comparison result between the peak signal and the reference peak signal.

[0063] This application uses a waveform generator to generate a reference waveform, Wave_ref, with the same four-level pulse amplitude modulation (PAM4) pattern as the input data waveform, Data_in, replacing the DC signal Vth used in the prior art. This allows the reference waveform, Wave_ref, and the input data waveform, Data_in, to achieve the same conversion efficiency after passing through the peak detector, resolving the conversion efficiency mismatch issue found in the prior art and enabling high-precision signal loss detection, particularly for PAM4 signals. Furthermore, a feedback loop is used to control the peak-to-peak value of the output signal to be equal to the reference voltage, while simultaneously implementing four-level pulse amplitude modulation encoding of the output signal, precisely controlling the peak-to-peak value of the output signal and realizing a hysteresis function.

[0064] See also Figure 6 , Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 6 As shown in FIG, the electronic device 600 includes a processor 610 , a memory 620 and a bus 630 .

[0065] The memory 620 stores machine-readable instructions executable by the processor 610. When the electronic device 600 is running, the processor 610 communicates with the memory 620 via the bus 630. When the machine-readable instructions are executed by the processor 610, the above-mentioned Figure 5 The specific implementation of the steps of the control method of the signal loss detection circuit in the method embodiment shown can be found in the method embodiment, and will not be repeated here.

[0066] The embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the computer program can execute the above-mentioned Figure 5 The specific implementation of the steps of the control method of the signal loss detection circuit in the method embodiment shown can be found in the method embodiment, and will not be repeated here.

[0067] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0068] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. There may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, indirect coupling or communication connection of devices or units, which may be electrical, mechanical or other forms.

[0069] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0070] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0071] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0072] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The scope of protection of the present application is not limited thereto. Although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-mentioned embodiments within the technical scope disclosed in the present application, or perform equivalent replacements for some of the technical features thereof. These modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A signal loss detection circuit, characterized in that: The signal loss detection circuit includes: a waveform generator, a reference peak detector, a data peak detector, a comparator, a signal loss indicator, a digital-to-analog converter, and a clock source; The waveform generator is connected to the digital-to-analog converter via a vref pin, the waveform generator is connected to the clock source via a clk pin, the waveform generator is connected to the signal loss indicator via a hys pin, and the waveform generator is connected to the reference peak detector via a vop pin and a von pin; The reference peak detector is connected to a non-inverting input terminal of the comparator, the data peak detector is connected to an inverting input terminal of the comparator, and an output terminal of the comparator is connected to the signal loss indicator.

2. The signal loss detection circuit according to claim 1, wherein: The waveform generator includes a pseudo-random binary sequence generator, a selector, a trigger, a driver and an adder; The output end of the pseudo-random binary sequence generator is connected to the input end of the selector, the output end of the selector is connected to the input end of the trigger, the output end of the trigger is connected to the input end of the driver, and the output end of the driver is connected to the input end of the adder.

3. The signal loss detection circuit according to claim 2, characterized in that The adder further includes a first error amplifier, a second error amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a first NPN transistor, a second NPN transistor, a third NPN transistor and a fourth NPN transistor; wherein, The first error amplifier and the second error amplifier control the bias currents of the first NMOS transistor and the second NMOS transistor respectively through a feedback loop.

4. The signal loss detection circuit according to claim 3, characterized in that: The source of the first NMOS transistor is connected to the positive end of the first resistor, and the negative end of the first resistor is grounded; The source of the second NMOS transistor is connected to the positive end of the second resistor, and the negative end of the second resistor is grounded; The drain of the first NMOS transistor is connected to the emitter of the first NPN transistor and the emitter of the second NPN transistor, and the drain of the second NMOS transistor is connected to the emitter of the third NPN transistor and the emitter of the fourth NPN transistor.

5. The signal loss detection circuit according to claim 3, wherein: The base of the first NPN transistor is connected to the most significant bit positive input signal msbp, and the collector of the first NPN transistor is connected to the negative end of the fifth resistor as the negative output end of the adder; The base of the second NPN transistor is connected to the most significant bit negative input signal MSBN, and the collector of the second NPN transistor is connected to the negative end of the sixth resistor as the positive output end of the adder; The base of the third NPN transistor is connected to the least significant bit positive input signal lsbp, and the collector of the third NPN transistor is connected to the negative end of the fifth resistor as the negative output end of the adder; The base of the fourth NPN transistor is connected to the least significant bit negative input signal lsbn, and the collector of the fourth NPN transistor is connected to the negative end of the sixth resistor as the positive output end of the adder.

6. The signal loss detection circuit according to claim 3, characterized in that The source of the third NMOS transistor is connected to the positive end of the third resistor, the source of the fourth NMOS transistor is connected to the positive end of the fourth resistor, and the negative end of the third resistor and the negative end of the fourth resistor are grounded; The drain of the third NMOS transistor is connected to the source of the fifth NMOS transistor, the drain of the fourth NMOS transistor is connected to the source of the sixth NMOS transistor, the drain of the fifth NMOS transistor is connected to the emitter of the first NPN transistor and the emitter of the second NPN transistor, and the drain of the sixth NMOS transistor is connected to the emitter of the third NPN transistor and the emitter of the fourth NPN transistor; The gate of the third NMOS tube is connected to the output end of the first error amplifier, the gate of the fourth NMOS tube is connected to the output end of the second error amplifier, and the gates of the fifth NMOS tube and the sixth NMOS tube are connected to the hys pin.

7. The signal loss detection circuit according to claim 1, wherein: The signal loss detection circuit further includes a variable capacitor array, which is arranged at the output end of the waveform generator.

8. A control method for a signal loss detection circuit, the control method being applied to the signal loss detection circuit according to any one of claims 1 to 7, characterized in that: The control method includes: When the digital-to-analog converter receives the digital control signal, the digital-to-analog converter is controlled to convert the digital control signal into a DC voltage and transmit the DC voltage as a reference signal to the waveform generator; controlling the waveform generator to generate a reference waveform based on the reference signal, and transmitting the reference waveform to a reference peak detector, so that the reference peak detector inputs a reference peak signal generated based on the reference waveform into a comparator; When the data peak detector receives an input data waveform, the data peak detector is controlled to generate a peak signal based on the input data waveform and input the peak signal to the comparator; wherein the reference waveform and the input data waveform are both four-level pulse amplitude modulation patterns; The comparator is controlled to output a signal loss detection signal based on a comparison result between the peak signal and the reference peak signal.

9. The control method according to claim 8, characterized in that: The waveform generator includes a pseudo-random binary sequence generator, a selector, a trigger, a driver, and an adder, and the control method further includes: When the pseudo-random binary sequence generator receives a clock signal, controlling the pseudo-random binary sequence generator to generate a pseudo-random binary sequence and transmitting the pseudo-random binary sequence to the selector; When the selector receives a control signal, the selector is controlled to determine a first input signal of the driver from the clock signal and the pseudo-random binary sequence; Using the first input signal as a clock signal of the trigger to control the trigger to generate a second input signal of the driver; The driver is controlled to transmit the first input signal and the second input signal to the adder, so that the adder generates the reference waveform.

10. An electronic device, characterized in that: include: A processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor and the memory communicate via the bus. When the processor runs the machine-readable instructions, the steps of the control method of the signal loss detection circuit according to any one of claims 8 to 9 are executed.

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