A method and system for converting flexbus interface to PCIe interface based on FPGA

Abstract

The application provides a method and system for converting a FlexBus interface into a PCIe interface based on FPGA. The method comprises: a FlexBus interface DRAM controller receiving 16-bit data, converting the 16-bit data into 32-bit data through dynamic bit width switching and time-sharing output logic, and storing the 32-bit data into DRAM; an AXI protocol conversion module encapsulating the 32-bit data into AXI burst transmission and writing the 32-bit data into a specified address of DDR; a PCIe BAR space mapping module mapping the DDR address to a PCIe BAR space; and a PCIe device initiating a read-write request through the BAR space, converting the read-write request into AXI signals and interacting with DDR to achieve efficient data transmission. The application significantly improves data transmission efficiency and system stability by means of cross-clock domain synchronization, bit width switching and burst transmission optimization, and meets the efficient data interaction requirements in the field of embedded systems and data acquisition.

Description

Technical Field

[0001] This invention relates to the technical field of embedded system interface protocol conversion, specifically to a method and system for converting an FPGA-based Flexbus interface to a PCIe interface. Background Technology

[0002] In existing technologies, the FlexBus interface used in some embedded systems and data acquisition devices limits data transmission rates due to its fixed data bit width (e.g., 16 bits) and lack of support for higher data bit widths. Furthermore, direct connections between the FlexBus interface and modern high-speed interfaces (such as PCIe) suffer from clock domain conflicts and data synchronization issues, leading to data loss or address misalignment. Traditional solutions typically rely on dedicated interface chips or complex hardware designs, which are not only costly but also inflexible and difficult to adapt to different application scenarios. Therefore, an efficient, flexible, and cost-effective interface conversion method is needed to address these problems in existing technologies. Summary of the Invention

[0003] The purpose of this invention is to provide a method and system for converting a Flexbus interface to a PCIe interface based on an FPGA, so as to solve the technical problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for converting an FPGA-based FlexBus interface to a PCIe interface, comprising the following steps:

[0005] Step 1: The FlexBus interface DRAM controller receives 16-bit data from the FlexBus interface and converts the data into a 32-bit width and stores it in DRAM through dynamic data bit width switching and time-division output logic;

[0006] Step 2: The AXI protocol conversion module receives 32-bit data from the DRAM controller, encapsulates it into an AXI burst transmission, and writes it to the specified address area of ​​the DDR storage medium;

[0007] Step 3: The PCIe BAR space mapping module maps the DDR physical address segment to the PCIe BAR space through the AXItoPCIe bridging logic;

[0008] Step 4: PCIe devices initiate read / write requests through the BAR space, convert them into AXI signals to interact with the DDR storage medium, and achieve efficient data transmission.

[0009] Preferably, step 1 further includes a sub-step for implementing dynamic data bit width switching and time-division output logic:

[0010] Sub-step 11: The FlexBus signal processing module detects the FlexBus clock edge and the falling edge of the chip select signal, captures the rising and falling edges of the clock through a two-stage delay register chain, and calculates the corresponding edge flags;

[0011] Sub-step 12: Simultaneously synchronize the chip select signal with two-level registers to ensure stability across clock domains;

[0012] Sub-step 13: The bidirectional data bus control module dynamically switches the data direction according to the control signal: it receives 16-bit data in write mode and outputs 32-bit DRAM data in two stages in read mode.

[0013] Preferably, an asynchronous FIFO is inserted in the DRAM read path to isolate the FlexBus from the DRAM clock domain.

[0014] Preferably, the AXI protocol conversion module performs protocol conversion based on signal mapping rules, which are as follows: FlexBus data is converted into 32-bit AXI data by concatenating 16 high and low bits in a time-division multiplexing manner; FlexBus addresses are mapped to AXI write addresses and read addresses after address alignment and burst length configuration; and the FlexBus clock is synchronized with the AXI clock through a cross-clock domain asynchronous FIFO buffer.

[0015] Preferably, the address mapping mechanism on which the DDR physical address segment is mapped to the PCIe BAR space in step 3 is as follows: the DDR physical address segment (such as 0x80000000~0x8FFFFFFF) is mapped to the PCIe device BAR0 space, and direct addressing at the PCIe end is supported. TLP packets are generated through the AXItoPCIe bridging logic to realize DDR access.

[0016] Preferably, in step 2, when the AXI protocol conversion module encapsulates 32-bit data into AXI burst transmission, it preloads the data into the PCIe transmission queue according to the AXI burst length to reduce link latency; and it splits large blocks of AXI data into the maximum effective payload of PCIe (e.g., 256B) to adapt to the link layer efficiency and improve data transmission efficiency.

[0017] Preferably, in step 3, the clock domain conversion logic built into the PCIe IP core (such as Xilinx XDMA) is used to achieve seamless conversion between the AXI clock domain and the PCIe clock domain without additional design, ensuring stable data transmission between different clock domains.

[0018] This invention also provides a system for converting a FlexBus interface to a PCIe interface based on an FPGA, the system comprising:

[0019] The FlexBus-DRAM controller is used to achieve cross-clock domain synchronization and dynamic data bit width switching;

[0020] The AXI protocol conversion engine is used to map FlexBus timings to AXI channel signals (AR / AW / W / R).

[0021] The PCIe BAR space mapping module is used to configure DDR physical addresses to PCIe BAR space and supports end-to-end access.

[0022] The DRAM controller includes the following functional modules:

[0023] The clock and reset module is used to generate the DRAM high-frequency clock (ram_clk) and the global reset signal;

[0024] The FlexBus signal processing module is used to detect the FlexBus clock edge (FLEXBUS_clk_p / n) and the falling edge of the chip select signal (FLEXBUS_cs_n).

[0025] A bidirectional data bus control module is used to dynamically switch the data direction (write mode receives data, read mode outputs high and low 16 bits in a time-division multiplexing manner).

[0026] The DRAM read / write control module is used to generate write enable (wr_en), address (wr_addr / rd_addr), and data path (wr_data / rd_data).

[0027] Compared with the prior art, the beneficial effects of the present invention are:

[0028] This invention expands the data transmission capability of a 16-bit physical bus to an equivalent 32-bit by dynamically switching the data bit width, thereby significantly improving the data transmission rate. Simultaneously, thanks to a cross-clock domain synchronization mechanism, the system can operate stably under different clock frequencies, effectively suppressing metastability propagation and enhancing timing robustness. Furthermore, in burst transmission mode, automatic address increment reduces bus switching overhead, thereby lowering transmission latency and further improving the efficiency of data interaction. Attached Figure Description

[0029] Figure 1 : A flowchart of a method for converting a FlexBus interface to a PCIe interface based on FPGA provided by the present invention;

[0030] Figure 2 The following is a structural block diagram of a system based on FPGA for converting a flexbus interface to a PCIe interface, which is provided by the present invention. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] Please see Figure 1-2 This invention provides a technical solution: a system based on FPGA to convert a FlexBus interface to a PCIe interface, the system comprising...

[0033] The FlexBus-DRAM controller is used to implement cross-clock domain synchronization and dynamic data bit width switching. The AXI protocol conversion engine is used to map FlexBus timings to AXI channel signals (AR / AW / W / R).

[0034] The PCIe BAR space mapping module is used to configure DDR physical addresses to the PCIe BAR space, supporting end-to-end access.

[0035] The DRAM controller includes the following functional modules:

[0036] The clock and reset module is used to generate the DRAM high-frequency clock (ram_clk) and the global reset signal.

[0037] The FlexBus signal processing module is used to detect the FlexBus clock edge (FLEXBUS_clk_p / n) and the falling edge of the chip select signal (FLEXBUS_cs_n).

[0038] A bidirectional data bus control module is used to dynamically switch the data direction (write mode receives data, read mode outputs high and low 16 bits in a time-division multiplexing manner).

[0039] The DRAM read / write control module is used to generate write enable (wr_en), address (wr_addr / rd_addr), and data path (wr_data / rd_data).

[0040] Based on the above-described FPGA-based FlexBus interface to PCIe interface system, this invention provides an FPGA-based FlexBus interface to PCIe interface conversion method, which includes the following steps:

[0041] 1. The clock and reset module in the system generates a high-frequency DRAM clock (ram_clk) and a global reset signal. This provides a stable clock and reset basis for subsequent operations, ensuring system initialization and synchronization.

[0042] 2. FlexBus Signal Processing Module: The FlexBus signal processing module in the system receives the clock signal (FLEXBUS_clk_p / n) and chip select signal (FLEXBUS_cs_n) from the FlexBus interface and performs the following operations:

[0043] Detect the FlexBus clock edge (FLEXBUS_clk_p / n) and the falling edge of the chip select signal (FLEXBUS_cs_n).

[0044] The rising edge (FLEXBUS_clk_p) and falling edge (FLEXBUS_clk_n) of FLEXBUS_clk are captured by a two-level delay register chain.

[0045] Calculate the rising edge flag: ~FLEXBUS_clk_delay[1]∧FLEXBUS_clk_delay[0].

[0046] Calculate the falling edge flag: FLEXBUS_clk_delay[1] ∧ ~FLEXBUS_clk_delay[0].

[0047] By synchronizing the FLEXBUS_cs signal through a two-stage register chain, a falling edge flag FLEXBUS_cs_n is generated, ensuring stability across clock domains. This effectively suppresses metastability propagation.

[0048] Bidirectional data bus control module: The bidirectional data bus control module in the system dynamically switches the data direction according to the control signal.

[0049] When the control signal control=0, the data bus is set to a high impedance state (16'bzzzzzzzzzzzzzzzz) to receive 16-bit data sent by the MCU.

[0050] When control=1, 32-bit DRAM data is output in two stages:

[0051] The lower 16-bit stage: control_rd_addr = 0, output rd_data[15:0].

[0052] High 16-bit stage: control_rd_addr = 1 or a falling edge of the FlexBus clock is detected (FLEXBUS_clk_n = 1), output rd_data[31:16].

[0053] By using time-division multiplexing and high-low 16-bit concatenation, FlexBus data is converted into 32-bit AXI data to meet the timing requirements of FlexBus and ensure correct data transmission.

[0054] DRAM Read / Write Control Module: After the bidirectional data bus control module completes the data direction switching, the DRAM read / write control module in the system performs the following operations based on the control signal:

[0055] Write operation:

[0056] When FLEXBUS_clk_p is active and chip select is inactive (FLEXBUS_cs = 0), a single-cycle write enable pulse (wr_en) is generated.

[0057] The write address counter (wr_addr) increments automatically on the rising edge of ram_clk, supporting burst writes.

[0058] The input data (FLEXBUS_data) is latched into the wr_data register on the rising edge of FLEXBUS_clk_p.

[0059] Read operation:

[0060] In read mode (control=1), the read address (rd_addr) is incremented on the falling edge of FLEXBUS_clk.

[0061] The high and low 16-bit data are switched by the control_rd_addr state machine to adapt to the timing requirements of FlexBus and ensure the flexibility and efficiency of read operations.

[0062] 5. The AXI protocol conversion module receives 32-bit data from the DRAM controller, encapsulates it into an AXI burst transfer (Burst Length = 2), and writes it to the designated address region of the DDR storage medium. During this process, an AXI write channel signal (AW) and a data channel signal (W) are generated to send the data to the DDR storage medium, and the data write is confirmed via the AXI write response channel (B). Simultaneously, data is preloaded into the PCIe transmission queue according to the AXI burst length, reducing link latency and significantly improving data transmission efficiency.

[0063] 6. FlexBus data (FLEXBUS_data) is converted into 32-bit AXI data (WDATA / RDATA) by concatenating 16 high and low bits in a time-division multiplexing manner. The FlexBus address (FlexBUS_addr) is mapped to the AXI write address (AWADDR) and read address (ARADDR) after address alignment and burst length configuration (ARLEN / AWLEN). The FlexBus clock (FlexBUS_clk) is synchronized with the AXI clock (ACLK) through an asynchronous FIFO buffer across clock domains to ensure data integrity and stability.

[0064] 7. DDR storage media receives AXI burst data and writes it to the specified address area. When a PCIe device initiates a read request, the PCIe BAR space mapping module converts the read request into an AXI read request signal (AR). The DDR storage media reads data from the specified address and returns it, supporting efficient read and write operations.

[0065] 8. The PCIe BAR space mapping module maps DDR physical address segments to the BAR0 space of the PCIe device, supporting direct addressing. When the PCIe device initiates a read / write request, the mapping module converts the request address (e.g., 0x80000000~0x8FFFFFFF) into a DDR physical address, generates a TLP packet through the AXItoPCIe bridging logic, and splits large blocks of AXI data into the maximum PCIe payload (e.g., 256B) to achieve DDR access and adapt to link layer efficiency. After adaptation, the signal is sent to the DDR storage medium, and the returned data is converted into a PCIe signal and sent to the PCIe device, ensuring efficient PCIe interaction.

[0066] 9. PCIe devices initiate read and write requests through the BAR space: During a read operation, the mapping module converts the read request into an AXI read request, the DDR storage medium returns data, and the mapping module converts this data into a PCIe signal and sends it to the PCIe device. During a write operation, the mapping module converts the write request into an AXI write request, the DDR storage medium writes data and returns a write response signal, supporting efficient PCIe read and write operations.

[0067] Through the above steps, an efficient conversion from the FPGA-based FlexBus interface to the PCIe interface was achieved, ensuring smooth data transmission and processing between different interfaces, while optimizing data transmission efficiency and system stability.

[0068] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for converting a FlexBus interface to a PCIe interface based on an FPGA, characterized in that, Includes the following steps: Step 1: The FlexBus interface DRAM controller receives 16-bit data from the FlexBus interface and converts the data into a 32-bit width and stores it in DRAM through dynamic data bit width switching and time-division output logic; Step 2: The AXI protocol conversion module receives 32-bit data from the DRAM controller, encapsulates it into an AXI burst transmission, and writes it to the specified address area of ​​the DDR storage medium. Step 3: The PCIe BAR space mapping module maps the DDR physical address segment to the PCIe BAR space through the AXItoPCIe bridging logic; Step 4: PCIe devices initiate read / write requests through the BAR space, convert them into AXI signals to interact with the DDR storage medium, and achieve efficient data transmission.

2. The method for converting an FPGA-based FlexBus interface to a PCIe interface according to claim 1, characterized in that, Step 1 also includes sub-steps for implementing dynamic data bit width switching and time-division output logic: Sub-step 11: The FlexBus signal processing module detects the FlexBus clock edge and the falling edge of the chip select signal, captures the rising and falling edges of the clock through a two-stage delay register chain, and calculates the corresponding edge flags; Sub-step 12: Simultaneously synchronize the chip select signal with two-level registers to ensure stability across clock domains; Sub-step 13: The bidirectional data bus control module dynamically switches the data direction according to the control signal: it receives 16-bit data in write mode and outputs 32-bit DRAM data in two stages in read mode.

3. The method for converting an FPGA-based FlexBus interface to a PCIe interface according to claim 2, characterized in that, An asynchronous FIFO is inserted into the DRAM read path to isolate the FlexBus from the DRAM clock domain.

4. The method for converting an FPGA-based FlexBus interface to a PCIe interface according to claim 1, characterized in that, The AXI protocol conversion module performs protocol conversion based on signal mapping rules, which are as follows: FlexBus data is converted into 32-bit AXI data by concatenating 16 high and low bits in a time-division multiplexing manner; FlexBus addresses are mapped to AXI write addresses and read addresses after address alignment and burst length configuration; and the FlexBus clock is synchronized with the AXI clock through a cross-clock domain asynchronous FIFO buffer.

5. The method for converting an FPGA-based FlexBus interface to a PCIe interface according to claim 1, characterized in that, The address mapping mechanism for mapping the DDR physical address segment to the PCIe BAR space in step 3 is as follows: the DDR physical address segment is mapped to the PCIe device BAR0 space, and direct addressing at the PCIe end is supported. TLP packets are generated through the AXItoPCIe bridging logic to realize DDR access.

6. The method for converting an FPGA-based FlexBus interface to a PCIe interface according to claim 1, characterized in that, In step 2, when the AXI protocol conversion module encapsulates 32-bit data into AXI burst transmission, it preloads the data into the PCIe transmission queue according to the AXI burst length to reduce link latency; and it splits large blocks of AXI data into the maximum effective payload of PCIe (such as 256B) to adapt to the link layer efficiency and improve data transmission efficiency.

7. The method for converting an FPGA-based FlexBus interface to a PCIe interface according to claim 1, characterized in that, In step 3, the built-in clock domain conversion logic of the PCIe IP core is used to achieve seamless conversion between the AXI clock domain and the PCIe clock domain without the need for additional design, ensuring stable data transmission between different clock domains.

8. A system for converting a FlexBus interface to a PCIe interface based on an FPGA, the system comprising: The FlexBus-DRAM controller is used to achieve cross-clock domain synchronization and dynamic data bit width switching; The AXI protocol conversion engine is used to map FlexBus timings to AXI channel signals; The PCIe BAR space mapping module is used to configure DDR physical addresses to PCIe BAR space and supports end-to-end access. The DRAM controller includes the following functional modules: Clock and reset module, used to generate DRAM high-frequency clock and global reset signal; The FlexBus signal processing module is used to detect the FlexBus clock edge and the falling edge of the chip select signal; The bidirectional data bus control module is used to dynamically switch the data direction, where the write mode receives data and the read mode outputs 16 high and low bits in a time-division multiplexing manner. The DRAM read / write control module is used to generate write enable, address, and data path.

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