A bus interface with polarity correction function and a polarity correction method

Abstract

A bus interface with polarity correction function and a polarity correction method are disclosed. The bus interface includes: a DCR measurement circuit, used in standby power mode to apply voltages to unknown line networks X1 and X2 based on a backup power supply, a first resistor, and a second resistor, measuring the DCR parameters of unknown line networks X1 and X2, and obtaining a first DCR measurement result and a second DCR measurement result respectively; a comparison circuit, used to compare the values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal; a state latching circuit, used to latch the polarity detection result signal when the main power network is activated; and a line sequence switching circuit, used in normal power mode to switch the conduction and disconnection of unknown line networks X1 and X2 with the preceding A-line network and B-line network based on the polarity detection result signal. This achieves polarity detection and correction for the two introduced unknown line networks.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a bus interface with polarity correction function, a polarity correction method, and a communication node device. Background Technology

[0002] EIA-485 (also known as RS-485) is a standard for multi-point communication using two-wire, half-duplex, balanced transmission lines, belonging to the physical layer of the OSI model. Digital communication networks implementing this standard can perform long-distance, efficient communication in environments with electronic noise, making them extremely suitable for use in industrial automation environments.

[0003] EIA-485 uses the differential voltage value between two transmission cables: line A (positive differential terminal) and line B (negative differential terminal). ( ) represents bus logic, when the differential voltage between lines A and B... greater than When, it indicates bus logic 1, when the differential voltage between lines A and B is 1. Less than When the bus logic is 0, the differential voltage between lines A and B is 0. When the value is near zero, it indicates that the bus logic is uncertain. Because EIA-485 uses differential signaling to transmit data, it possesses extremely strong common-mode interference suppression capabilities. Furthermore, since the common-mode level range on the EIA-485 bus is only -7.0V to +12.0V (RS-232 is -15.0V to +15.0V), EIA-485 also boasts strong electrical safety, making its interface circuits less susceptible to damage. Due to these advantages, the EIA-485 communication standard is often used in industrial environments with harsh electromagnetic conditions to meet the communication needs of field data transmission and process control.

[0004] However, the EIA-485 standard only specifies electrical characteristics and signal functions, without constraining the order or name of the connector's A and B pins. When interconnecting devices from different manufacturers that conform to the EIA-485 standard, A-wires must be connected to A-wires and B-wires to B-wires; otherwise, normal communication is impossible. Device manufacturers typically design EIA-485 physical interfaces according to their corporate standards or internal design conventions. For example, some devices define the interface names as A / B, while others define them as + / -. This makes it easy for incorrect pinouts to cause bus malfunctions during interconnection, leading to difficulties in manual error correction.

[0005] Therefore, how to provide a circuit for automatically detecting and correcting the line sequence correspondence between lines A and B is a key research topic for those skilled in the art. Summary of the Invention

[0006] In a first aspect, this application provides a bus interface with polarity correction function. The bus interface includes: a power management circuit, a DC impedance (DCR) measurement circuit, a comparator circuit, a status latch circuit, and a line sequence switching circuit. The power management circuit is used to supply power to the DCR measurement circuit, the comparator circuit, and the status latch circuit using a backup power network when the bus interface is in a standby power state, and to supply power to the status latch circuit and the line sequence switching circuit using a main power network when the bus interface is in a constant power state. The DCR measurement circuit, the comparator circuit, the status latch circuit, and the line sequence switching circuit are cascaded. The DCR measurement circuit includes docking components for interfacing with an X1 unknown line network and an X2 unknown line network, and the line sequence switching circuit includes docking components for communicating with the A line network and the B line network of the preceding stage of the bus interface, respectively. The backup power network is connected to one end of a first resistor, and the other end of the first resistor is connected to the X1 unknown line network. The backup power network is connected to one end of a second resistor, and the other end of the second resistor is connected to the X1 unknown line network. The X2 unknown line network is connected; the DCR measurement circuit is used, in the standby power state, to apply voltage to the X1 unknown line network and the X2 unknown line network based on the backup power supply, the first resistor, and the second resistor, and to measure the DCR parameters of the X1 unknown line network and the X2 unknown line network, respectively obtaining a first DCR measurement result and a second DCR measurement result; the comparison circuit is used to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal, the polarity detection result signal being used to indicate The unknown line corresponding to the larger DCR measurement result is connected to the A-line network of the preceding stage, and the unknown line corresponding to the smaller DCR measurement result is connected to the B-line network of the preceding stage. The state latching circuit is used to latch the polarity detection result signal when the main power network is activated, and continuously output the polarity detection result signal to the line sequence switching circuit. The line sequence switching circuit is used to switch the connection and disconnection of the X1 unknown line network and the X2 unknown line network with the A-line network and the B-line network of the preceding stage based on the polarity detection result signal under the constant power state.

[0007] It should be noted that, according to the requirements for fault protection circuits in the EIA-485 bus standard, the bus should be equipped with fault protection circuits. Specifically, pull-up bias resistors (connected between the A-line network and the positive power supply) and pull-down bias resistors (connected between the B-line network and ground) should be installed on both the A and B lines of the bus to mitigate the differential voltage during idle states. Forced to be placed within a defined voltage difference range (above 200mV).

[0008] The bus interface provided in this application, based on the characteristic that the A line of the external bus network connected through the X1 and X2 docking components of the bus interface is equipped with a bias resistor pull-up and the B line is equipped with a bias resistor pull-down, measures the DCR parameters of the X1 unknown line network and the X2 unknown line network using a DCR measurement circuit in standby power mode. In the unknown line network belonging to line B, a loop is formed between the backup power supply, the additional resistor, the pull-down bias resistor, and the GND network. Under the voltage division effect of the additional resistor and the pull-down bias resistor, a stable and relatively low voltage value is obtained at the unknown line network belonging to line B (for example, assuming the backup power supply is 3.0V, this voltage value is generally between 0.1V and 0.3V). In the unknown line network belonging to line A, since line A does not have a pull-down bias resistor (i.e., it is not grounded), it cannot form a loop. Therefore, the unknown line network belonging to line A obtains a stable voltage value that is higher than that of the unknown line network belonging to line B (for example, assuming the backup power supply is 3.0V, this voltage value is generally around 3.0V). This distinguishes whether the unknown line network X1 and the unknown line network X2 connected to the bus interface belong to line A or line B.

[0009] It should be noted that in the actual deployment of EIA-485 standard bus networks, the bias circuit (with bias pull-up and bias pull-down resistors respectively set on the A and B lines of the bus) is usually configured by the system integrator at the end of the bus segment. It should be specifically noted that the external bias circuit is not within the scope of the bus interface provided in this application. The bus interface provided in this application is the minimum implementable product independent of the external bias circuit, which is in line with the deployment method of bias resistor circuits in EIA-485 standard bus networks.

[0010] The embodiment of this application provides a bus interface with polarity correction function. In standby mode, based on the DCR measurement circuit and comparison circuit, the polarity of the two unknown line networks is detected by utilizing the difference in DCR parameters between the A-line network and the B-line network. After power-on (normal power mode), based on the state latch circuit and line sequence switching circuit, the polarity connection relationship between the two unknown line networks and the internal A-line and B-line is automatically corrected.

[0011] Therefore, on the one hand, it solves the problem of interconnection errors caused by inconsistent order or name of A-line pins and B-line pins of EIA-485 standard equipment from different manufacturers, and supports communication devices configured with the bus interface provided in this application to be blindly connected to the bus network with arbitrary pin order.

[0012] On the other hand, using a backup power supply to perform polarity detection before powering on the device can eliminate the detection time after power-on, thus shortening the polarity correction time after power-on. Furthermore, when the main power supply is activated, the polarity detection result is latched by a state latch circuit, which continuously outputs the polarity detection result signal to drive the line sequence switching circuit. This avoids the backup power supply from being insufficient due to the state latch circuit prematurely latching and continuously outputting the drive signal. Additionally, after the main power network is powered on, the line sequence switching circuit performs the correction action based on the main power supply and maintains the corrected state, avoiding premature correction and maintaining the corrected state from causing the backup power supply to continuously consume power.

[0013] In some possible implementations, the power management circuit is further configured to use the main power network to power the DCR measurement circuit and the comparator circuit under the constant power condition; the DCR measurement circuit is further configured to disable the measurement function of the DCR measurement circuit under the constant power condition; and the comparator circuit is further configured to disable the comparison function of the comparator circuit under the constant power condition.

[0014] Using this method, after the main power supply is turned on and the polarity detection result is latched, the measurement function of the DCR measurement circuit and the comparison function of the comparison circuit are disabled, reducing unnecessary power consumption.

[0015] In some possible implementations, the state latch circuit includes a capacitor for delaying the input signal of the state latch circuit, so that the state latch circuit can stably receive the polarity detection result signal when the comparison circuit switches from a standby power state to a constant power state.

[0016] This approach, through a combination of capacitor delay and edge triggering, perfectly solves the signal synchronization problem and avoids the use of expensive non-volatile memory.

[0017] In some possible implementations, the power management circuit is further configured to charge the backup power network using the main power network after the main power network is activated.

[0018] In some possible implementations, the power management circuit includes: a resistor R101, a diode D101, and a battery BT101; wherein one end of the resistor R101 is connected to the main power network, the other end is connected to the anode of the diode D101, the cathode of the diode D101 is connected to the backup power network and the positive terminal of the battery BT101, and the negative terminal of the battery BT101 is connected to the GND network.

[0019] In some possible implementations, the DCR measurement circuit includes: resistors R201, R202, R203, R204, R205, transistor Q201, and transistor Q202; one end of resistor R201 is connected to the main power network, and the other end is connected to one end of resistors R202 and R203 respectively; the other end of resistor R203 is connected to the GND network; the other end of resistor R202 is connected to the base of transistor Q201 and the base of transistor Q202 respectively; the emitters of transistor Q201 and Q202 are both connected to the backup power network; and the collectors of transistor Q201 and Q202 are connected to the X1 unknown line network and the X2 unknown line network respectively through resistors R204 and R205.

[0020] In some possible implementations, the comparator circuit includes analog switch chip U301, analog switch chip U303, voltage comparator chip U302, resistor R301, resistor R302, and resistor R303. The first DCR measurement result and the second DCR measurement result are respectively represented as voltage signals in the X1 unknown line network and the X2 unknown line network under the standby power state. The comparator circuit is connected to the X2 unknown line network through the common terminal (pin 5) of the analog switch chip U301 to obtain the second DCR measurement result, and the comparator circuit is connected to the X1 unknown line network through the common terminal (pin 5) of the analog switch chip U303 to obtain the first DCR measurement result. The input pins (pin 1) of both the analog switch chip U301 and the analog switch chip U303 are connected to the main power network, and the power supply pins (pin 2) of both the analog switch chip U301 and the analog switch chip U303 are connected to the standby power network. The power supply network is configured such that pin 3 of the GND terminal of analog switch chip U301 and pin 3 of the GND terminal of analog switch chip U303 are both connected to the GND network. Pin 4 of the normally closed terminal of analog switch chip U301 and pin 4 of analog switch chip U303 are respectively connected to one end of resistor R302 and one end of resistor R303. The other ends of resistor R302 and the other ends of resistor R303 are respectively connected to the non-inverting input of voltage comparator chip U302. The voltage comparator chip U302 has its first pin connected to the inverting input pin 3, its second pin connected to the GND network, its fifth pin connected to the backup power network, its sixth pin connected to the backup power network, its seventh pin connected to the backup power network, its eighth pin connected to the backup power network, its ninth pin connected to the backup power network, its ellipse resistor R301 connected between the voltage comparator chip U302's fifth pin and its sixth pin connected to the first signal output network.

[0021] In some possible implementations, the state latch circuit includes a Class D flip-flop chip U401, a resistor R401, and a capacitor C401. The data pin 1 of the Class D flip-flop chip U401 is connected to the first signal output network of the comparator circuit and simultaneously connected to the GND network through the capacitor C401. The clock pin 2 of the Class D flip-flop chip U401 is connected to the main power network. The GND pin 3 of the Class D flip-flop chip U401 is connected to the GND network. The output pin 4 of the Class D flip-flop chip U401 is connected to the second signal output network through the resistor R401. The power pin 5 of the Class D flip-flop chip U401 is connected to the backup power network.

[0022] In some possible implementations, the line sequence switching circuit includes: a miniature signal electromagnetic relay U501, a transistor Q501, a resistor R501, and a resistor R502. One end of resistor R501 is connected to the second signal output network of the state latching circuit. The other end of resistor R501 is connected to one end of resistor R502 and the base of transistor Q501. The other end of resistor R502 is connected to the GND network. The emitter of transistor Q501 is connected to the GND network. The collector of transistor Q501 is connected to pin 1 of the control terminal a of the miniature signal electromagnetic relay U501. The control terminal (pin 8) of the electromagnetic relay U501 is connected to the main power supply network. Pin 2 of the normally closed terminal of channel 1 and pin 5 of the normally open terminal of channel 2 of the ultra-small signal electromagnetic relay U501 are both connected to the X1 unknown line network. Pin 4 of the normally open terminal of channel 1 and pin 7 of the normally closed terminal of channel 2 of the ultra-small signal electromagnetic relay U501 are both connected to the X2 unknown line network. Pin 3 of the common terminal of channel 1 of the ultra-small signal electromagnetic relay U501 is connected to the A line network. Pin 6 of the common terminal of channel 2 of the ultra-small signal electromagnetic relay U501 is connected to the B line network.

[0023] Secondly, this application also provides a polarity correction method, which is applied to a bus interface with polarity correction function as described in any one of the first aspects. The method includes: in a standby power state, measuring the DCR parameters of the X1 unknown line network and the X2 unknown line network based on a DCR measurement circuit to obtain a first DCR measurement result and a second DCR measurement result; in the standby power state, comparing the values ​​of the first DCR measurement result and the second DCR measurement result based on a comparison circuit to obtain a polarity detection result signal, wherein the polarity detection result signal is used to indicate that the unknown line corresponding to the larger DCR measurement result is connected to the A line of the front stage of the bus interface, and the unknown line corresponding to the smaller DCR measurement result is connected to the B line of the front stage; when the main power network is activated, latching the polarity detection result signal based on a state latching circuit and continuously outputting the polarity detection result signal to a line sequence switching circuit; in a normal power state, the polarity detection result signal drives the line sequence switching circuit to switch the connection and disconnection of the X1 unknown line network and the X2 unknown line network with the A line and B line of the front stage.

[0024] Thirdly, this application provides a bus interface with polarity correction function, the bus interface comprising:

[0025] Power management circuit, DCR measurement circuit, comparator circuit, and line sequence switching circuit;

[0026] The power management circuit is used to supply power to the bus interface using a backup power network when the bus interface is in standby power mode.

[0027] The DCR measurement circuit, the comparator circuit, and the line sequence switching circuit are cascaded. The DCR measurement circuit includes docking components for interfacing with an external bus network and an X1 unknown line network and an X2 unknown line network. The line sequence switching circuit includes docking components for communicating with the A line network and the B line network of the preceding stage of the bus interface, respectively. The DCR measurement circuit also includes a first resistor and a second resistor. The backup power network is connected to one end of the first resistor, and the other end of the first resistor is connected to the X1 unknown line network. The backup power network is connected to one end of the second resistor, and the other end of the second resistor is connected to the X2 unknown line network.

[0028] The DCR measurement circuit is used to apply voltage to the X1 unknown line network and the X2 unknown line network based on the backup power supply, the first resistor, and the second resistor in the backup power state, and measure the DCR parameters of the X1 unknown line network and the X2 unknown line network to obtain the first DCR measurement result and the second DCR measurement result respectively.

[0029] The comparison circuit is used to compare the values ​​of the first DCR measurement result and the second DCR measurement result in the standby power state to obtain a polarity detection result signal. The polarity detection result signal is used to indicate that the unknown line corresponding to the larger DCR measurement result is connected to the A-line network of the previous stage, and the unknown line corresponding to the smaller DCR measurement result is connected to the B-line network of the previous stage.

[0030] The line sequence switching circuit is used, under the standby power state, to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the preceding A line network and B line network based on the polarity detection result signal.

[0031] This method allows the bus interface to detect the polarity of two unknown line networks before and during device power-on and standby power-on, based on the DCR measurement and comparison circuits and utilizing the difference in DCR parameters between the A-line and B-line networks. Furthermore, based on the line sequence switching circuit, it automatically corrects the polarity connection relationship between the two unknown bus line networks and the internal A-line and B-line, respectively. This solves the problem of interconnection errors caused by inconsistent pin order or names of A-line and B-line pins in EIA-485 standard devices from different manufacturers.

[0032] In some possible implementations, the power management circuitry in the bus interface provided by the third aspect also includes a main power network, which is further used to charge the backup power network using the main power network after the main power network is activated.

[0033] Fourthly, this application also provides a communication node device, the communication node device including a core controller, an EIA-485 bus transceiver circuit, and a bus interface (the bus interface is the bus interface of any embodiment of the first aspect or the third aspect), the core controller and the EIA-485 bus transceiver circuit are connected through a transmit data line TX and a receive data line RX, and the EIA-485 bus transceiver circuit and the bus interface are connected through lines A and B.

[0034] It is understood that the polarity correction method and communication node device with polarity correction function provided above are all implemented based on the bus interface of any of the first or third aspects provided in the embodiments of this application. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding bus interface, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a hardware circuit topology diagram of a bus interface with polarity correction function provided in an embodiment of this application;

[0036] Figure 2 This is a circuit schematic diagram of a power management circuit provided in an embodiment of this application;

[0037] Figure 3 This is a circuit schematic diagram of a DCR measurement circuit provided in an embodiment of this application;

[0038] Figure 4 This is a circuit schematic diagram of a comparison circuit provided in an embodiment of this application;

[0039] Figure 5 This is a circuit schematic diagram of a state latch circuit provided in an embodiment of this application;

[0040] Figure 6 This is a circuit schematic diagram of a line sequence switching circuit provided in an embodiment of this application;

[0041] Figure 7 This is a hardware circuit topology diagram provided in this application embodiment, which applies the bus interface with polarity correction function provided in this application to an EIA-485 communication node device.

[0042] Figure 8 This is a schematic diagram of a typical EIA-485 communication bus network topology provided in an embodiment of this application;

[0043] Figure 9 This is a circuit schematic diagram of an EIA-485 bus configuration device provided in an embodiment of this application. Detailed Implementation

[0044] To make the inventive purpose, technical features, and beneficial effects of this application clearer and easier to understand, the specific embodiments and examples of this application will be clearly and completely described below with reference to some accompanying drawings. Obviously, the specific embodiments and examples described below are only some concrete representations of this application, and not all of the content of this application. Based on this part, all other concrete representations obtained by those skilled in the art without creative effort are within the protection scope of the claims of this application.

[0045] The present application will now be described in further detail with reference to the accompanying drawings.

[0046] Please see Figure 1 , Figure 1 This is a flowchart illustrating a bus interface with polarity correction functionality, provided as an embodiment of this application. Figure 1 As shown, the bus interface includes:

[0047] Power management circuit, DCR measurement circuit, comparator circuit, status latch circuit, and line sequence switching circuit;

[0048] The power management circuit is used to power the DCR measurement circuit, comparison circuit, and status latch circuit using a backup power network (shown as Backup_Power in the figure) when the bus interface is in standby power mode, and to power the status latch circuit and line sequence switching circuit using a main power network (shown as Main_Power in the figure) when the bus interface is in constant power mode.

[0049] The DCR measurement circuit, comparator circuit, state latch circuit, and line sequence switching circuit are cascaded. The DCR measurement circuit includes a docking component for connecting the X1 unknown line network and the X2 unknown line network to an external bus network (in... Figure 1 (Shown as X1 and X2 docking components) The line sequence switching circuit includes docking components for connecting to the positive differential terminal A line network and the negative differential terminal B line network of the front stage of the bus interface, respectively; The DCR measurement circuit also includes a first resistor and a second resistor. The backup power network is directly or indirectly connected to one end of the first resistor, and the other end of the first resistor is connected to the X1 unknown line network. The backup power network is directly or indirectly connected to one end of the second resistor, and the other end of the second resistor is connected to the X2 unknown line network.

[0050] The DCR measurement circuit is used to apply voltage to the X1 unknown line network and the X2 unknown line network based on the backup power supply, the first resistor, and the second resistor in the standby power state, and measure the DCR parameters of the X1 unknown line network and the X2 unknown line network to obtain the first DCR measurement result and the second DCR measurement result respectively.

[0051] The comparison circuit is used to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal. The polarity detection result signal is used to indicate that the unknown line corresponding to the larger DCR measurement result is connected to the A-line network of the previous stage, and the unknown line corresponding to the smaller DCR measurement result is connected to the B-line network of the previous stage.

[0052] The state latch circuit is used to latch the polarity detection result signal when the main power network is activated, and continuously output the polarity detection result signal to the line sequence switching circuit.

[0053] The line sequence switching circuit is used to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the A line network and the B line network of the preceding stage based on the polarity detection result signal under normal power conditions.

[0054] In the embodiments of this application, the DCR measurement circuit, the comparison circuit, the state latch circuit, and the line sequence switching circuit are connected in series according to the signal flow direction.

[0055] In this embodiment, the X1 unknown line network and the X2 unknown line network are divided into two channels after being introduced into the bus interface. The first channel is connected to the DCR measurement circuit, and the second channel is connected to the line sequence switching circuit. The first channel of the X1 and X2 unknown line networks is connected to the DCR measurement circuit to measure the DCR parameters of the X1 and X2 unknown line networks respectively. The measurement results are transmitted to a comparison circuit for comparison, and the comparison result signal is transmitted to a state latching circuit. Finally, the line sequence switching circuit, based on the drive signal output by the state latching circuit, completes the line sequence switching operation between the second channel X1 and X2 unknown line networks and the preceding A and B line networks.

[0056] In this embodiment, under standby power conditions, the DCR measurement circuit applies voltage to the X1 unknown line network based on the backup power supply and the first resistor, and applies voltage to the X2 unknown line network based on the backup power supply and the second resistor, to measure the DCR parameters at the two unknown line networks. It is understood that the additional resistors (the first resistor and the second resistor) are used to prevent the unknown line networks from being directly connected to the backup power supply, which would cause the voltage at the unknown line networks to always be the backup power supply voltage, making it impossible to accurately measure the DCR parameters of the unknown line networks.

[0057] In this embodiment, the connection between the backup power network and one end of the first resistor means that there is a direct or indirect connection between the backup power supply and the first resistor. As an example, if the backup power supply and the first resistor are directly connected, the DCR measurement circuit can continuously operate based on the backup power supply providing a voltage signal to the X1 unknown line network in both standby and normal power states. As another example, the backup power supply and the first resistor are indirectly connected via a transistor (or other suitable switching device) to activate the DCR measurement circuit's function in standby state (i.e., providing a voltage signal to the X1 unknown line network based on the backup power supply and the first resistor), while disabling the DCR measurement circuit's function in normal power state (i.e., disconnecting the connection between the backup power supply and the first resistor). The connection between the backup power supply and the second resistor is similar and will not be detailed further.

[0058] Understandably, the measurement of direct current resistance (DCR) is essentially achieved indirectly through voltage drop. The DCR parameter obtained by the DCR measurement circuit provided in this application can be either a voltage signal parameter or an impedance signal parameter, wherein the voltage signal parameter is proportional to the impedance signal parameter. For ease of understanding and description, the following example uses the voltage signal parameter as the DCR parameter.

[0059] The embodiment of this application provides a bus interface with polarity correction function. In standby mode, based on the DCR measurement circuit and comparison circuit, the polarity of the two unknown line networks is detected by utilizing the difference in DCR parameters between the A-line network and the B-line network. After power-on (normal power mode), based on the state latch circuit and line sequence switching circuit, the polarity connection relationship between the two unknown line networks and the internal A-line and B-line is automatically corrected.

[0060] The bus interface provided in this application is applicable to any two-wire bus network conforming to the EIA-485 standard. This bus network must comply with the EIA-485 standard and be configured with fault protection circuitry, specifically: pull-up and pull-down resistors are used on lines A and B of the bus respectively to reduce the differential voltage of the bus in the idle state. The voltage must be forced to be above 200mV. Furthermore, the pull-up and pull-down bias resistor parameters should be calculated and configured according to the EIA-485 standard. For example, the pull-up and pull-down bias resistor parameters are generally consistent, ranging from 680Ω to 1000Ω. Preferably, this application applies to any two-wire bus network conforming to the EIA-485 standard, but each node connected to the bus network must comply with the EIA-485 standard to limit the common-mode voltage and ground potential difference; that is, the reference ground potential of each node on the bus must be kept consistent.

[0061] In some possible implementations, the backup power network is indirectly connected to the first resistor and the second resistor, respectively. The power management circuit is also used to power the DCR measurement circuit and the comparator circuit using the main power network under normal power conditions. The DCR measurement circuit is also used to disable the measurement function of the DCR measurement circuit under normal power conditions. The comparator circuit is also used to disable the comparison function of the comparator circuit under normal power conditions.

[0062] Using this method, after the main power supply is turned on and the polarity detection result is latched, the measurement function of the DCR measurement circuit and the comparison function of the comparison circuit are disabled, reducing unnecessary power consumption.

[0063] In some possible implementations, the state latch circuit includes a capacitor for delaying the input signal to the state latch circuit, so that the state latch circuit can stably receive the polarity detection result signal when the comparator circuit switches from a standby power state to a constant power state.

[0064] This method uses a capacitor to delay the input signal of the state latch circuit, ensuring that the circuit can reliably receive valid input signals. It avoids the problem that the state latch circuit cannot receive valid input signals due to the instantaneous change in output level caused by the comparison circuit switching from standby power to constant power.

[0065] In some possible implementations, the power management circuitry is also used to charge the backup power network using the main power network after the main power network is activated.

[0066] The following examples illustrate the construction of each circuit in the bus interface.

[0067] In some possible implementations, the circuit schematic of the power management circuit provided in this application is as follows: Figure 2 As shown, it includes resistor R101, diode D101, and battery BT101.

[0068] In this circuit, one end of resistor R101 is connected to the main power supply network, and the other end is connected to the anode of diode D101. The cathode of diode D101 is connected to the backup power supply network and the positive terminal of battery BT101, and the negative terminal of battery BT101 is connected to the GND network.

[0069] In standby mode, when the main power network loses power, diode D101 is in the off state, and battery BT101 starts to supply power to the backup power network.

[0070] Under normal power conditions, the main power network is powered on. The main power network charges the battery BT101 through the current limiting effect of resistor R101 and the unidirectional conduction effect of diode D101, while simultaneously supplying power to the backup power network.

[0071] As an example, the resistance of resistor R101 is 10kΩ, but it can also be any other suitable value; this article does not limit this to any particular value.

[0072] Preferably, to ensure the compatibility of subsequent circuits with the voltages of the main power network and the backup power network, and the safety of the main power supply charging battery BT101, the voltage of battery BT101 is equal to or slightly greater than the voltage of the main power network. As an example, if the standard voltage of battery BT101 is 3.0V, then the main power network should preferably use a DC 3.3V standard to ensure the compatibility of subsequent circuits with the voltages of the main power network and the backup power network, and the safety of the main power supply charging battery BT101.

[0073] Preferably, the main power supply network should be connected to the preceding low-voltage DC power supply. For example, if this application is used as a submodule in a device, the main power supply should be connected to the low-voltage DC power supply inside the device.

[0074] It should be noted that the power management circuit can also be other suitable circuit structures, and this article does not limit it. For example, the diode D101 in the power management circuit can also be replaced by logic gates, analog switch chips, or other alternative designs, and this article does not limit it.

[0075] In some possible implementations, the circuit schematic of the DCR measurement circuit provided in this application is as follows: Figure 3 As shown, it includes: resistors R201, R202, R203, R204 (also known as the first resistor), R205 (also known as the second resistor), transistor Q201, and transistor Q202.

[0076] One end of resistor R201 is connected to the main power supply network, and the other end is connected to one end of resistors R202 and R203 respectively. The other end of resistor R203 is connected to the GND network. The other end of resistor R202 is connected to the base (pin 1) of transistor Q201 and the base (pin 1) of transistor Q202 respectively. The emitter (pin 2) of transistor Q201 and the emitter (pin 2) of transistor Q202 are both connected to the backup power supply network. The collector (pin 3) of transistor Q201 and the collector (pin 3) of transistor Q202 are connected to the X1 unknown line network and the X2 unknown line network respectively through resistors R204 and R205.

[0077] Under normal power conditions, when the main power network is powered on, the voltage divider formed by resistors R201 and R203 makes the base voltage and emitter voltage of transistors Q201 and Q202 equal. Neither transistor Q201 nor Q202 will be turned on, and the DCR measurement function is disabled.

[0078] In standby mode, when the main power network loses power, a closed loop is formed from the backup power network through the emitters of transistors Q201 and Q202, resistors R202 and R203, and finally to the GND network. The closed loop contains a positive DC current, which causes transistors Q201 and Q202 to turn on and operate in the saturation region, thus activating the DCR measurement function.

[0079] When the DCR measurement circuit is activated, the voltages at the collectors of transistors Q201 and Q202, along with resistors R204 and R205, are connected to the unknown X1 network and the unknown X2 network, respectively, to perform DCR measurement on the GND network, and the first DCR measurement result and the second DCR measurement result are obtained respectively.

[0080] In this scenario, assuming the X1 unknown line network is line B in the external EIA-485 bus network and the X2 unknown line network is line A in the bus network, under the voltage excitation of the emitter of transistor Q201, the voltage division effect of resistor R204, and the voltage division effect of the pull-up bias resistor of line B in the bus network, the X1 unknown line network obtains a stable and relatively low voltage value, typically between 0.1V and 0.3V, since the X1 unknown line is only a single wire with very low internal resistance. Meanwhile, the emitter of transistor Q202, resistor R205, the pull-up bias resistor of line A in the bus network, and the X2 unknown line network do not form a loop to ground, resulting in no voltage drop. Therefore, the X2 unknown line network obtains a stable and relatively high voltage value, typically around 3.0V. Similarly, assuming that the X1 unknown line network is line A in the external EIA-485 bus network and the X2 unknown line network is line B in the bus network, then the X1 unknown line network obtains a stable and higher voltage value, and the X2 unknown line network obtains a stable and lower voltage value.

[0081] As an example, the resistance values ​​of resistors R201, R203, R204, and R205 are 1kΩ, 10kΩ, 10kΩ, 10kΩ, and 10kΩ respectively, or other suitable values ​​may be used, which are not limited in this article.

[0082] The DCR measurement circuit is used so that the DCR measurement function is activated in standby mode. After the main power is turned on and the polarity detection result is latched, the DCR measurement function is deactivated to reduce unnecessary power consumption.

[0083] It should be noted that the DCR measurement circuit can also be other suitable circuit structures, which are not limited in this article. For example, transistors Q201 and Q202 in the DCR measurement circuit can also be replaced by logic gates, analog switch chips, or other alternative designs, which are not limited in this article.

[0084] In some possible implementations, the first and second DCR measurement results can be represented as voltage signals (or impedance signals) in the X1 and X2 unknown line networks, respectively, under standby power conditions. The comparator circuit, connected to the same X1 and X2 unknown line networks as the DCR measurement circuit, obtains the first and second DCR measurement results. This approach eliminates the need to quantize the specific values ​​of the DCR measurement results. The comparator circuit obtains the DCR measurement results from the two unknown line networks by connecting to them, using analog voltage signals instead of quantized values. This eliminates intermediate links in the signal chain, reduces costs, and improves reliability.

[0085] It should be noted that in some other possible implementations, the reading of the DCR measurement result can also be quantized (e.g., quantized into a voltage reading, or converted from a voltage reading into an impedance value) and then fed into a comparison circuit for comparison. This article does not limit this approach.

[0086] In some possible implementations, the circuit schematic of the comparator circuit provided in this application is as follows: Figure 4 As shown, it includes: analog switch chip U301, analog switch chip U303, voltage comparator chip U302, resistor R301, resistor R302, and resistor R303.

[0087] The first DCR measurement result and the second DCR measurement result are respectively represented by the voltage signals in the X1 unknown line network and the X2 unknown line network in the standby power state. The comparison circuit is connected to the X2 unknown line network through the common terminal (pin 5) of the analog switch chip U301 to obtain the above-mentioned second DCR measurement result corresponding to the X2 unknown line network. The comparison circuit is connected to the X1 unknown line network through the common terminal (pin 5) of the analog switch chip U303 to obtain the above-mentioned first DCR measurement result corresponding to the X1 unknown line network.

[0088] The input terminals (pin 1) of analog switch chip U301 and U303 are both connected to the main power supply network. The power supply terminals (pin 2) of both analog switch chip U301 and U303 are connected to the backup power supply network. The GND terminals (pin 3) of both analog switch chip U301 and U303 are connected to the GND network. The normally open terminals (pin 6) of both analog switch chip U301 and U303 are not connected. The normally closed terminals (pin 4) of both analog switch chip U301 and U303 are connected to resistor R302. One end of resistor R303 and the other end of resistor R302 are connected to the non-inverting input (pin 1) and the inverting input (pin 3) of voltage comparator chip U302, respectively. The GND terminal (pin 2) of voltage comparator chip U302 is connected to the GND network. The power supply terminal (pin 5) of voltage comparator chip U302 is connected to the backup power network. Resistor R301 is connected across the power supply terminal (pin 5) and the output terminal (pin 4) of voltage comparator chip U302. The output terminal (pin 4) of voltage comparator chip U302 is connected to the COMP_1 network (also known as the first signal output network).

[0089] Under normal power conditions, driven by the DC voltage of the main power network, the common terminal (pin 5) and normally closed terminal (pin 4) of analog switch chip U301 are disconnected, and the common terminal (pin 5) and normally closed terminal (pin 4) of analog switch chip U303 are disconnected. The first DCR measurement result and the second DCR measurement result will not affect the comparison circuit, thus disabling the comparison function of the comparison circuit.

[0090] In standby mode, there is no DC voltage in the main power network. The common terminal (pin 5) and normally closed terminal (pin 4) of analog switch chip U301 are closed, and the common terminal (pin 5) and normally closed terminal (pin 4) of analog switch chip U303 are closed. The DC signal on the unknown X2 line network (second DCR measurement result) and the DC signal on the unknown X1 line network (first DCR measurement result) are transmitted to the voltage comparator chip U302 for comparison through analog switch chip U301 and analog switch chip U303, and through resistors R302 and R303, respectively.

[0091] During the comparison, if the DC voltage on the X2 unknown line network (the second DCR measurement result) is significantly lower than the DC voltage on the X1 unknown line network (the first DCR measurement result), the output terminal (pin 4) of the voltage comparator chip outputs a low level (e.g., 0V) (also known as the first polarity detection result) to the COMP_1 network (also known as the first signal output network), indicating that the externally connected X1 unknown line network belongs to line A and the X2 unknown line network belongs to line B. This connects the X1 unknown line network to the A line of the front stage of the bus interface and connects the X2 unknown line network to the B line of the front stage.

[0092] If the DC voltage on the X2 unknown line network is significantly higher than that on the X1 unknown line network, since the voltage comparator chip U302 uses an open collector (OC) output, under the pull-up bias of resistor R301, the output terminal (pin 4) of the voltage comparator chip outputs a high level to the COMP_1 network (specifically equal to the backup power supply voltage; for example, if the backup power supply voltage is 3V, this high level is 3V) (also known as the second polarity detection result). This indicates that the X2 unknown line network is connected to the A line of the front stage of the bus interface, and the X1 unknown line network is connected to the B line of the front stage.

[0093] As an example, the resistance values ​​of resistors R302, R303, and R301 are 1kΩ, 1kΩ, and 10kΩ respectively, or other suitable values ​​may be used, which are not limited in this article.

[0094] This comparator circuit achieves two advantages: First, by directly connecting to the unknown line network, it obtains the DCR measurement results of the two unknown line networks. This means using analog voltage signals instead of quantized values, eliminating intermediate links in the signal chain, reducing costs, and improving reliability. Second, the comparator function is activated in standby mode, and deactivated after the main power is supplied and the polarity detection result is latched, thus reducing unnecessary power consumption.

[0095] It should be noted that the comparator circuit can also be other suitable circuit constructions, which are not limited in this article. For example, the voltage comparator chip in the comparator circuit can also be a device based on other voltage comparison principles that meet the requirements, and the analog switch chip can also be a device based on other switching design principles that meet the requirements.

[0096] In some possible implementations, the circuit schematic of the state latch circuit provided in this application is as follows: Figure 5 As shown, it includes: a Class D flip-flop chip U401, a resistor R401, and a capacitor C401.

[0097] The data terminal (pin 1) of the Class D flip-flop chip U401 is connected to the COMP_1 network of the comparator circuit and simultaneously connected to the GND network through capacitor C401. The clock terminal (pin 2) of the Class D flip-flop chip U401 is connected to the main power supply network. The GND terminal (pin 3) of the Class D flip-flop chip U401 is connected to the GND network. The output terminal (pin 4) of the Class D flip-flop chip U401 is connected to the RELAY_CTRL network (also known as the second signal output network) through resistor R401. The power supply terminal (pin 5) of the Class D flip-flop chip U401 is connected to the backup power supply network.

[0098] For example, the resistance of resistor R401 is 10R, or it may be other suitable values, which are not limited in this article.

[0099] In both normal and backup power states, the clock input (pin 2) of the Class D flip-flop chip U401 is a stable voltage signal. Since the Class D flip-flop chip U401 is a rising edge triggered chip, its output remains unchanged. Only when the bus interface switches from backup power to normal power state, the clock input (pin 2) of the Class D flip-flop chip U401 receives a rising edge voltage due to the power-on operation of the main power network. At this time, the polarity detection result signal (TTL level) of the COMP_1 network is transmitted to the output (pin 4) of the Class D flip-flop and maintained in this state. In the normal power state, the polarity detection result signal is continuously output to the line sequence switching circuit using the backup power network and the RELAY_CTRL network.

[0100] However, when the pre-amplifier circuit switches from standby power to constant power, analog switch chips U301 and U303 switch the connection between the X1 unknown line network and the X2 unknown line network and the voltage comparator chip U302, causing a momentary change in the output level, which makes it difficult for this circuit to receive a valid input signal. Therefore, capacitor C401 is used to delay the input signal of this circuit to ensure that this circuit can stably and reliably receive a valid input signal.

[0101] For example, the capacitor C401 should preferably be 100nF. Taking the commonly used YAGEO MLCC (multilayer ceramic capacitor) model CC0603KRX7R9BB104 as an example, according to its datasheet specifications, when a 3.0V voltage is applied across its terminals and it is fully charged, it takes approximately 2.3ms for the voltage across its terminals to drop from 3.0V to 0.6V (80% drop) after the applied 3.0V voltage is disconnected. This delay is sufficient for the state latching circuit to effectively recognize the input signal and respond.

[0102] This state latch circuit serves two purposes. First, after the main power supply is powered on, the state latch circuit latches the polarity detection result, continuously outputting a polarity detection signal to drive the line sequence switching circuit. This avoids the problem of insufficient backup power supply caused by the state latch circuit prematurely latching and continuously outputting a drive signal. Second, using a capacitor to delay the input signal of the state latch circuit ensures that the circuit can stably and reliably receive valid input signals. This avoids the problem of the state latch circuit being unable to receive valid input signals due to the instantaneous change in output level caused by the comparison circuit switching from backup power to constant power.

[0103] It should be noted that the state latch circuit provided in this application can also have other constructions, and this document does not limit it. For example, the latching function of the state latch circuit can also be implemented based on non-volatile memory, and this document does not limit it.

[0104] In some possible implementations, the circuit schematic of the line sequence switching circuit provided in this application is as follows: Figure 6 As shown, it includes: a miniature signal electromagnetic relay U501, a transistor Q501, a resistor R501, and a resistor R502.

[0105] In this circuit, one end of resistor R501 is connected to the RELAY_CTRL network of the state latch circuit, and the other end of resistor R501 is connected to one end of resistor R502 and the base (pin 1) of transistor Q501. The other end of resistor R502 is connected to the GND network. The emitter (pin 2) of transistor Q501 is connected to the GND network. The collector (pin 3) of transistor Q501 is connected to the control terminal a (pin 1) of the miniature signal electromagnetic relay U501. The control terminal b (pin 8) of the miniature signal electromagnetic relay U501 is connected to the main power supply network. The normally closed terminal (pin 2) of channel 1 and the normally open terminal (pin 5) of channel 2 of the ultra-miniature signal electromagnetic relay U501 are both connected to the X1 unknown line network. The normally open terminal (pin 4) of channel 1 and the normally closed terminal (pin 7) of channel 2 of the ultra-miniature signal electromagnetic relay U501 are both connected to the X2 unknown line network. The common terminal (pin 3) of channel 1 of the ultra-miniature signal electromagnetic relay U501 is connected to the A line network, and the common terminal (pin 6) of channel 2 of the ultra-miniature signal electromagnetic relay U501 is connected to the B line network.

[0106] In standby mode, there is no power supply voltage in the main power network. Therefore, regardless of the signal input to RELAY_CTRL, the miniature signal electromagnetic relay U501 does not operate. The common terminal (pin 3) of channel 1 and the normally closed terminal (pin 2) of channel 1 of the miniature signal electromagnetic relay U501 remain closed, as do the common terminal (pin 6) of channel 2 and the normally closed terminal (pin 7) of channel 2. That is, in the default state, the A-line network of the preceding stage (shown as EIA-485_A in the diagram) is connected to the unknown line network X1, and the B-line network of the preceding stage (shown as EIA-485_B in the diagram) is connected to the unknown line network X2.

[0107] Under normal power conditions, the main power supply network has a DC power supply voltage, such as 3.3V. When the RELAY_CTRL network inputs a low-level (0V) signal, there is no forward conduction current between the base and emitter of transistor Q501, so transistor Q501 is not turned on. Therefore, there is no conduction current between the collector and emitter of transistor Q501, and the coil of the miniature signal electromagnetic relay U501 also has no conduction current. The miniature signal electromagnetic relay U501 does not operate. The common terminal (pin 3) of channel 1 and the normally closed terminal (pin 2) of channel 1 of the miniature signal electromagnetic relay U501 remain closed, and the common terminal (pin 6) and normally closed terminal (pin 7) of channel 2 of the miniature signal electromagnetic relay U501 remain closed. That is, the A-line network of the preceding stage is connected to the unknown line network X1, and the B-line network of the preceding stage is connected to the unknown line network X2.

[0108] When a 3.0V signal is input to the RELAY_CTRL network, a forward current exists between the base and emitter of transistor Q501. Transistor Q501 is turned on and operates in the saturation region. Affected by the DC 3.3V power supply voltage in the main power network, a forward current exists between the self-power network, the control b terminal (pin 8) of the miniature signal electromagnetic relay U501, the control a terminal (pin 1) of the miniature signal electromagnetic relay U501, the collector of transistor Q501, the emitter of transistor Q501, and finally to the GND network. The miniature signal electromagnetic relay U501 is activated. The common terminal (pin 3) of channel 1 and the normally open terminal (pin 4) of channel 1 of the miniature signal electromagnetic relay U501 remain closed, and the common terminal (pin 6) of channel 2 and the normally open terminal (pin 5) of channel 2 of the miniature signal electromagnetic relay U501 remain closed. That is, connect the previous A-line network to the unknown line network X2, and connect the previous B-line network to the unknown line network X1.

[0109] For example, the resistance values ​​of resistors R501 and R502 are both 10kΩ, or other suitable values ​​may be used, which are not limited in this article.

[0110] In a typical embodiment, the bus interface provided in this application is deployed as a downstream circuit of the EIA-485 bus transceiver circuit in an EIA-485 communication node device. For example... Figure 7 The diagram shows the hardware circuit topology of the EIA-485 communication node device, which includes a core controller, an EIA-485 bus transceiver circuit, a bus interface provided in this application (hereinafter referred to as the bus interface), and other circuits.

[0111] The core controller is used to perform data acquisition, command issuance, calculation, and logic driving for other circuits. The core controller drives the EIA-485 bus transceiver circuit through a TTL-level standard UART communication interface. The TX line is used to send data to the EIA-485 bus transceiver circuit, and the RX line is used to receive data returned by the EIA-485 bus transceiver circuit. The EIA-485 bus transceiver circuit converts the TTL-level standard data sent by the core controller via the TX line into EIA-485 standard data, and simultaneously converts the EIA-485 standard data returned by the bus interface into TTL standard data.

[0112] The bus interface is connected to the EIA-485 bus transceiver circuit, with lines A and B strictly corresponding. As the final stage circuit of the EIA-485 communication power-saving device, the bus interface exposes the X1 unknown line network interface and the X2 unknown line network interface to the outside of the device, which can be used to connect to the EIA-485 two-wire bus with any line sequence.

[0113] It should be noted that the front-end of the bus interface can be a bus transceiver circuit, or it can be any other EIA-485 circuit that includes A-line and B-line ports. This article does not limit this.

[0114] In this embodiment of the application, the DCR measurement circuit includes docking components for the X1 unknown line network and X2 unknown line network for interfacing with an external bus network (i.e., docking components exposed by the bus interface for interfacing with the X1 unknown line network and X2 unknown line network), and the line sequence switching circuit includes docking components for communicating with the A line network and B line network of the bus interface respectively (i.e., docking components exposed by the bus interface for communicating with the A line network and B line network of the bus interface). Both can be active terminals (plugs) or interface terminals, and this document does not limit them.

[0115] In a typical embodiment, an EIA-485 communication node device including the bus interface provided in this application can form a typical EIA-485 communication bus network, as shown in the topology diagram of the communication bus network. Figure 8 As shown.

[0116] Figure 8 In this communication bus structure, EIA-485 communication node device 1 acts as the master station device, while EIA-485 communication node devices 2, 3, 4, 5, 6, and 7 act as slave stations. The number of slave stations can vary depending on other requirements; this document does not impose a limit on this.

[0117] In addition, an EIA-485 bus configuration device is deployed at the end of the bus network. The circuit schematic of the EIA-485 bus configuration device is shown below. Figure 9 As shown. This EIA-485 bus configuration device includes potentiometers RP601 and RP602.

[0118] In this configuration, potentiometer RP601 has pin 1 connected to a 3.3V DC power supply network, pin 2 floating, and pin 2 connected to the X1 unknown line network. Potentiometer RP602 has pin 2 connected to the X2 unknown line network, pin 1 connected to the GND network, and pin 3 floating.

[0119] It is evident that a typical EIA-485 communication bus network, consisting of several EIA-485 communication node devices employing the bus interface of this application and a single EIA-485 bus configuration device, possesses significant technical advantages compared to traditional device networking: any device in the bus network can be connected to the bus in any wiring order, and stable and reliable communication between all devices can be guaranteed without any abnormalities. The specific working mechanism is as follows.

[0120] According to the EIA-485 standard, "The EIA-485 two-wire communication bus should be equipped with a fault protection circuit, that is, by using bias resistors to pull up and pull down the A and B lines of the bus respectively, to reduce the differential voltage of the bus in the idle state." "Forced to be above 200mV". Figure 8 The circuit diagram of the bus configuration device shown is as follows: Figure 9 As shown, then Figure 8In the communication bus network, the lower line shown in the diagram where the terminal EIA-485 bus configuration device is connected is the EIA-485_A line, and the upper line shown in the diagram where the EIA-485 bus configuration device is connected is the EIA-485_B line.

[0121] For EIA-485 communication node devices, since their internal design includes the bus interface of this application, regardless of the wiring sequence used by the EIA-485 communication node device to access the bus network, its polarity correction function can always ensure that the bus network works normally. The following uses 'EIA-485 communication node device 1' as an example for specific explanation.

[0122] like Figure 8 As shown, port X1 of EIA-485 communication node device 1 is connected to the upper line (EIA-485_B line), and port X2 of EIA-485 communication node device 1 is connected to the lower line (EIA-485_A line). When the bus network is de-energized, the bus interface inside EIA-485 communication node device 1 operates in standby mode. Therefore, the bus interface first measures the voltage to the GND network on the unknown X1 and unknown X2 lines. Based on the working principle of the DCR measurement circuit, line X2 belongs to line A and has a higher DCR parameter, while line X1 belongs to line B and has a lower DCR parameter. This measurement result is transmitted to the comparator circuit. Based on the working principle of the comparator circuit, the comparator circuit outputs a high-level signal to the state latch circuit. Based on the working principle of the state latch circuit, the output signal of the state latch circuit remains unchanged. When the bus network switches from a power-off state to a power-on state, the bus interface inside the EIA-485 communication node device 1 also switches from a standby power state to a constant power state. Based on the working principle of the state latch circuit, the state latch circuit outputs a high-level signal and maintains it. Based on the working principle of the line sequence switching circuit, the high-level signal causes the line sequence switching circuit to connect the EIA-485_A line and the X2 line, and at the same time connect the EIA-485_B line and the X1 line, thereby realizing the polarity correction function.

[0123] Generally, RS-232 deployments typically follow the electrical characteristics, mechanical interfaces, signal functions, connector pin order, and connector mechanical dimensions specifications defined in TIA / EIA-232-F, ITU-T V.24, and ISO 2110. However, the EIA-485 standard only specifies electrical characteristics and signal functions, without constraining connector pin order or mechanical dimensions. In actual manufacturing, equipment manufacturers usually design EIA-485 physical interfaces (connectors) according to company standards or internal design practices. During subsequent equipment integration and electrical deployment, issues often arise regarding incorrect A-line and B-line connections when interconnecting EIA-485 physical interfaces (connectors). This is particularly problematic in large-scale system-level EIA-485 bus network deployments. If several devices in the bus network have incorrect pin order, manual error correction during post-deployment debugging becomes extremely complex and difficult.

[0124] To address these issues and overcome the difficulties in manual error correction arising from bus malfunctions caused by incorrect wiring sequences in actual EIA-485 standard bus deployments, some domestic and international industrial automation equipment manufacturers have offered solutions. For example, utility model patent CN 214125285 U discloses an RS485 non-polarity communication circuit, consisting of interface line-A, interface line-B, interface line-first identification line, interface line-second identification line, first controlled switch, second controlled switch, third controlled switch, fourth controlled switch, and a comparison module. Compared to traditional technologies, this disclosure achieves communication regardless of whether the interface lines are connected in either direction at an extremely low cost. However, it also increases the bus wiring from 2 wires to 4 wires, significantly increasing the bus complexity and drastically reducing operational stability, thus lacking sufficient practicality.

[0125] However, the bus interface with polarity correction function provided in the embodiments of this application, in the standby power state, based on the DCR measurement circuit and the comparison circuit, utilizes the difference in DCR parameters of the A-line network and the B-line network to realize the polarity detection of the two unknown line networks. After power-on (normal power state), based on the state latch circuit and the line sequence switching circuit, the polarity connection relationship between the two unknown line networks and the internal A-line and B-line is automatically corrected, without the need to increase the number of buses, which is practical.

[0126] It should be noted that "at least one" in this application refers to one or more items. "More than one" means two or more items. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, it should be understood that although the terms "first," "second," etc., may be used in this application to describe various objects, these objects should not be limited to these terms. These terms are only used to distinguish the objects from each other. The terms "comprising" and "having," and any variations thereof, mentioned above, are intended to cover non-exclusive inclusion.

Claims

1. A bus interface with polarity correction function, characterized in that, The bus interface includes: Power management circuit, DC impedance DCR measurement circuit, comparator circuit, status latch circuit, and line sequence switching circuit; The power management circuit is used to supply power to the DCR measurement circuit, the comparison circuit, and the status latch circuit using a backup power network when the bus interface is in a standby power state, and to supply power to the status latch circuit and the line sequence switching circuit using a main power network when the bus interface is in a constant power state. The DCR measurement circuit, the comparison circuit, the state latching circuit, and the line sequence switching circuit are cascaded. The DCR measurement circuit includes docking components for interfacing with an external bus network and an X1 unknown line network and an X2 unknown line network. The line sequence switching circuit includes docking components for communicating with the A line network and the B line network of the preceding stage of the bus interface, respectively. The DCR measurement circuit also includes a first resistor and a second resistor. The backup power network is connected to one end of the first resistor, and the other end of the first resistor is connected to the X1 unknown line network. The backup power network is connected to one end of the second resistor, and the other end of the second resistor is connected to the X2 unknown line network. The DCR measurement circuit is used to apply voltages to the X1 unknown line network and the X2 unknown line network respectively based on the backup power supply, the first resistor, and the second resistor in the backup power state, measure the DCR parameters of the X1 unknown line network and the X2 unknown line network respectively, and obtain the first DCR measurement result and the second DCR measurement result respectively. The comparison circuit is used to compare the numerical values ​​of the first DCR measurement result and the second DCR measurement result to obtain a polarity detection result signal. The polarity detection result signal is used to indicate that the unknown line corresponding to the larger DCR measurement result is connected to the A-line network of the previous stage, and the unknown line corresponding to the smaller DCR measurement result is connected to the B-line network of the previous stage. The state latching circuit is used to latch the polarity detection result signal when the main power network is activated, and to continuously output the polarity detection result signal to the line sequence switching circuit. The line sequence switching circuit is used to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the preceding A line network and B line network based on the polarity detection result signal under the constant power state.

2. The bus interface as described in claim 1, characterized in that, The power management circuit is also used to power the DCR measurement circuit and the comparison circuit using the main power network under the constant power condition; The DCR measurement circuit is also used to disable the measurement function of the DCR measurement circuit under the constant power state. The comparison circuit is also used to disable the comparison function of the comparison circuit under the constant power state.

3. The bus interface as described in claim 1 or 2, characterized in that, The state latching circuit includes a capacitor. The capacitor is used to delay the input signal of the state latch circuit so that the state latch circuit can stably receive the polarity detection result signal when the comparison circuit switches from the standby power state to the constant power state.

4. The bus interface as described in claim 3, characterized in that, The power management circuit is also used to charge the backup power network using the main power network after the main power network is activated.

5. The bus interface as described in claim 4, characterized in that, The power management circuit includes: resistor R101, diode D101, and battery BT101; In this circuit, one end of resistor R101 is connected to the main power network, and the other end is connected to the anode of diode D101. The cathode of diode D101 is connected to the backup power network and the positive terminal of battery BT101. The negative terminal of battery BT101 is connected to the GND network.

6. The bus interface as described in claim 5, characterized in that, The DCR measurement circuit includes: resistors R201, R202, R203, R204, R205, transistor Q201, and transistor Q202. One end of resistor R201 is connected to the main power network, and the other end is connected to one end of resistors R202 and R203 respectively. The other end of resistor R203 is connected to the GND network. The other end of resistor R202 is connected to the base of transistor Q201 and the base of transistor Q202 respectively. The emitters of transistors Q201 and Q202 are both connected to the backup power network. The collectors of transistors Q201 and Q202 are connected to the X1 unknown line network and the X2 unknown line network respectively through resistors R204 and R205.

7. The bus interface as described in claim 6, characterized in that, The comparator circuit includes analog switch chip U301, analog switch chip U303, voltage comparator chip U302, resistor R301, resistor R302, and resistor R303. The first DCR measurement result and the second DCR measurement result are respectively represented by the voltage signals in the X1 unknown line network and the X2 unknown line network under the standby power state. The comparison circuit is connected to the X2 unknown line network through the common terminal 5 of the analog switch chip U301 to obtain the second DCR measurement result. The comparison circuit is connected to the X1 unknown line network through the common terminal 5 of the analog switch chip U303 to obtain the first DCR measurement result. The input pin 1 of both analog switch chip U301 and analog switch chip U303 is connected to the main power network. The power supply pins 2 and 2 of both analog switch chip U301 and U303 are connected to the backup power network. The GND pins 3 and 3 of both analog switch chip U301 and U303 are connected to the GND network. The normally closed pins 4 and 4 of both analog switch chip U301 and U303 are connected to one end of resistor R302 and one end of resistor R303, respectively. The other ends of resistor R302 and resistor R303 are respectively connected to pin 1 of the non-inverting input terminal and pin 3 of the inverting input terminal of voltage comparator chip U302. Pin 2 of the GND terminal of voltage comparator chip U302 is connected to the GND network. Pin 5 of the power supply terminal of voltage comparator chip U302 is connected to the backup power supply network. Resistor R301 is connected between pin 5 of the power supply terminal and pin 4 of the output terminal of voltage comparator chip U302. Pin 4 of the output terminal of voltage comparator chip U302 is connected to the first signal output network.

8. The bus interface as described in claim 7, characterized in that, The state latching circuit includes a Class D flip-flop chip U401, a resistor R401, and a capacitor C401. Specifically, the data pin 1 of the Class D flip-flop chip U401 is connected to the first signal output network of the comparator circuit and simultaneously connected to the GND network through the capacitor C401; the clock pin 2 of the Class D flip-flop chip U401 is connected to the main power supply network; the GND pin 3 of the Class D flip-flop chip U401 is connected to the GND network; the output pin 4 of the Class D flip-flop chip U401 is connected to the second signal output network through the resistor R401; and the power pin 5 of the Class D flip-flop chip U401 is connected to the backup power supply network.

9. The bus interface as described in claim 8, characterized in that, The line sequence switching circuit includes: a miniature signal electromagnetic relay U501, a transistor Q501, a resistor R501, and a resistor R502. In this circuit, one end of resistor R501 is connected to the second signal output network of the state latch circuit; the other end of resistor R501 is connected to one end of resistor R502 and the base of transistor Q501; the other end of resistor R502 is connected to the GND network; the emitter of transistor Q501 is connected to the GND network; the collector of transistor Q501 is connected to pin 1 of control terminal a of the ultra-miniature signal electromagnetic relay U501; and pin 8 of control terminal b of the ultra-miniature signal electromagnetic relay U501 is connected to the main power supply network. Pin 2 of the normally closed terminal of channel 1 of the miniature signal electromagnetic relay U501 and pin 5 of the normally open terminal of channel 2 of the ultra-miniature signal electromagnetic relay U501 are both connected to the X1 unknown line network. Pin 4 of the normally open terminal of channel 1 of the ultra-miniature signal electromagnetic relay U501 and pin 7 of the normally closed terminal of channel 2 of the ultra-miniature signal electromagnetic relay U501 are both connected to the X2 unknown line network. Pin 3 of the common terminal of channel 1 of the ultra-miniature signal electromagnetic relay U501 is connected to the A line network. Pin 6 of the common terminal of channel 2 of the ultra-miniature signal electromagnetic relay U501 is connected to the B line network.

10. A polarity correction method, characterized in that, The method is applied to a bus interface with polarity correction function as described in any one of claims 1 to 9, and the method includes: In standby mode, based on the DCR measurement circuit, the DCR parameters of the unknown X1 line network and the unknown X2 line network are measured to obtain the first DCR measurement result and the second DCR measurement result. In the standby power state, based on the comparison circuit, the values ​​of the first DCR measurement result and the second DCR measurement result are compared to obtain a polarity detection result signal. The polarity detection result signal is used to indicate that the unknown line corresponding to the larger DCR measurement result is connected to the A line of the front stage of the bus interface, and the unknown line corresponding to the smaller DCR measurement result is connected to the B line of the front stage. When the main power network is activated, the polarity detection result signal is latched based on the state latching circuit, and the polarity detection result signal is continuously output to the line sequence switching circuit. Under normal power conditions, the polarity detection result signal drives the line sequence switching circuit to switch the conduction and disconnection of the X1 unknown line network and the X2 unknown line network with the A line and B line of the preceding stage.

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