Circuit board manufacturing method, impedance compensation method and circuit board

Abstract

The invention relates to the technical field of circuit board manufacturing, and discloses a circuit board manufacturing method, an impedance compensation method and a circuit board, and the circuit board manufacturing method comprises the steps: obtaining an inner-layer circuit design drawing of the circuit board; dividing the inner-layer circuit design drawing into a preset number of areas; calculating the residual copper rate of each region; and according to a deviation value between the residual copper rate of each region and a preset standard residual copper rate, adjusting the line width of the line in the corresponding region of the inner-layer line design drawing so as to prepare the inner-layer line of the circuit board by using the adjusted inner-layer line design drawing. The problem of inconsistent impedance caused by dielectric thickness change is solved, and high-speed signal transmission of the circuit board is more stable and reliable.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board manufacturing, and in particular to a circuit board manufacturing method, an impedance compensation method, and a circuit board. Background Art

[0002] During high-speed signal transmission, if there is an impedance mismatch in the transmission path, some signal energy will be reflected at the impedance discontinuity, while the remaining energy will continue to propagate along the transmission line. This impedance discontinuity can induce multiple reflections, leading to waveform distortion at the receiving end. This manifests as a decrease in signal integrity and the appearance of typical signal integrity defects such as overshoot, undershoot, and ringing, significantly impacting signal transmission quality. Summary of the Invention

[0003] In view of this, the embodiments of the present application provide a method for manufacturing a circuit board, an impedance compensation method, and a circuit board, which can effectively solve the problem of impedance mismatch in the prior art that affects the quality of signal transmission.

[0004] In a first aspect, an embodiment of the present application provides a method for manufacturing a circuit board, comprising: Obtain the inner layer circuit design drawing of the circuit board; Dividing the inner layer circuit design into a preset number of areas; Calculate the residual copper rate of each of the areas; According to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, the line width of the corresponding area of ​​the inner layer circuit design drawing is adjusted, so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design drawing.

[0005] In some embodiments, adjusting the line width of the corresponding area of ​​the inner layer circuit design drawing according to the deviation value between the residual copper rate of each area and the preset standard residual copper rate includes: If the residual copper rate in the current area is higher than the standard residual copper rate, widening the line width of the circuit in the current area; If the residual copper rate in the current area is lower than the standard residual copper rate, line width reduction processing is performed on the lines in the current area.

[0006] In some embodiments, if the residual copper rate in the current area is higher than the standard residual copper rate, performing line width widening processing on the line in the current area includes: When the residual copper rate of the current area increases by a first preset ratio each time relative to the standard residual copper rate, the line width of the line in the current area is positively increased according to a second preset ratio; In some embodiments, if the residual copper rate in the current area is lower than the standard residual copper rate, performing line width reduction processing on the line in the current area includes: When the variation of the residual copper rate in the current area relative to the standard residual copper rate decreases by a first preset ratio each time, the line width of the line in the current area is negatively reduced according to a second preset ratio.

[0007] In some embodiments, before adjusting the line width of the corresponding area of ​​the inner layer circuit design drawing according to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, the impedance compensation method further includes: Determining independent circuits and dense circuits in the inner layer circuit design diagram; The line width of each independent circuit in the inner layer circuit design drawing is preliminarily adjusted.

[0008] In some embodiments, dividing the inner layer circuit design into a preset number of regions includes: The number of regions into which the inner layer circuit design drawing is divided is determined based on the impedance tolerance of the circuit board, and the number of regions increases as the impedance tolerance decreases.

[0009] In some embodiments, determining the number of regions into which the inner layer circuit design drawing is divided based on the impedance tolerance of the circuit board includes: When the impedance tolerance of the circuit board is a first preset tolerance, dividing the inner layer circuit design drawing into a first number of grid areas; When the impedance tolerance of the circuit board is a second preset tolerance, the inner layer circuit design drawing is divided into areas with a second number of grids, wherein the first preset tolerance is greater than the second preset tolerance, and the first number of grids is less than the second number of grids. In some embodiments, calculating the residual copper rate of each of the regions includes: The residual copper rate of each of the regions is calculated using image recognition technology; wherein the residual copper rate is the ratio of the copper foil area of ​​the current region to the total area of ​​the current region.

[0010] In a second aspect, an embodiment of the present application provides a circuit board, wherein the inner layer circuit of the circuit board is manufactured using at least one of the methods described in the first aspect.

[0011] In a third aspect, an embodiment of the present application provides an impedance compensation method for a circuit board, comprising: Divide the inner layer circuit design of the circuit board into a preset number of areas; Calculate the residual copper rate of each of the areas; According to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, the line width of the corresponding area of ​​the inner layer circuit design drawing is adjusted.

[0012] The embodiments of the present application have the following beneficial effects: The method for manufacturing a circuit board of the present application includes: obtaining an inner layer circuit design drawing of the circuit board; dividing the inner layer circuit design drawing into a preset number of regions; calculating the residual copper rate of each of the regions; adjusting the line width of the circuit in the corresponding region of the inner layer circuit design drawing according to the deviation value between the residual copper rate of each region and the preset standard residual copper rate, so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design drawing. The present application divides the inner layer circuit design drawing of the circuit board into regions and adjusts the line width of the circuit in the corresponding region according to the residual copper rate in each region, thereby compensating for the impedance difference caused by the change in dielectric thickness, solving the impedance inconsistency problem caused by the change in dielectric thickness, meeting stricter impedance tolerance requirements, improving impedance control accuracy, and making high-speed signal transmission more stable and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A first flow chart of a method for manufacturing a circuit board according to an embodiment of the present application is shown; Figure 2 A schematic diagram of the partitioning of the inner layer circuit design diagram of an embodiment of the present application is shown; Figure 3 A second flow chart of the method for manufacturing a circuit board according to an embodiment of the present application is shown; Figure 4 A flow chart of an impedance compensation method for a circuit board according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0016] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0017] Hereinafter, the terms "including", "having" and their cognates used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the aforementioned items, and should not be understood as excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the aforementioned items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the aforementioned items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and should not be understood as indicating or implying relative importance.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0019] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0020] Taking into account the problem of impedance mismatch in the prior art, which affects the quality of signal transmission, among the many factors that affect the characteristic impedance of the transmission line, the dielectric thickness is a key parameter. The change in the thickness of the transmission line dielectric layer will directly affect the changing trend of its characteristic impedance value. When the actual impedance value deviates from the design target value, an impedance mismatch state will be formed, which will then cause the aforementioned signal integrity problem. The present application provides a method for manufacturing a circuit board, an impedance compensation method and a circuit board. The present application divides the inner layer circuit design drawing of the circuit board into areas, and adjusts the line width of the lines in the corresponding areas according to the residual copper rate in each area, thereby compensating for the impedance difference caused by the change in dielectric thickness, solving the impedance inconsistency problem caused by the change in dielectric thickness, and responding to more stringent impedance tolerance requirements, improving the impedance control accuracy, and making high-speed signal transmission more stable and reliable.

[0021] The following describes the method for manufacturing the circuit board in conjunction with some specific embodiments.

[0022] Figure 1 A schematic flow chart of a method for manufacturing a circuit board according to an embodiment of the present application is shown. Exemplarily, the method includes steps S101-S104: S101: Obtain an inner layer circuit design drawing of a circuit board.

[0023] Exemplarily, the inner layer circuit design drawing can be in any format, and the inner layer circuit design drawing can be a Gerber file, or a bitmap, etc. It can be understood that the inner layer of the circuit board can be one or more of a ground layer, a signal layer, a power layer, etc. The inner layer circuit design drawing of the circuit board can be made according to the actual application situation. S102: Divide the inner layer circuit design drawing into a preset number of areas.

[0024] The number of regions within the inner-layer circuit design can be determined based on actual application requirements. For example, the number of regions can be determined based on the impedance tolerance of the circuit board. Generally, the number of regions increases as the impedance tolerance of the circuit board decreases. Impedance is a critical parameter in high-speed signal transmission. The smaller the impedance tolerance of the circuit board, the higher the requirement for circuit uniformity. To achieve higher-precision control, more detailed analysis and compensation of the inner-layer circuits are required.

[0025] The multi-layer board pressing of the circuit board is to cut the resin layer PP into sheets, place them between the inner core board and the core board or between the core board and the copper foil, and then melt the resin on the PP through high temperature and high pressure in a press, and fill the copper-free area on the core board. After cooling, the resin solidifies, and the core board and the copper foil are bonded together. The PP sheet flows in liquid form under high temperature and high pressure, filling the gaps between the boards. When the inner layer copper is small, PP sheets of the same thickness are evenly distributed in the gaps between the layers. More resin filling causes the overall thickness of the PP sheet to be thinner after cooling and solidification. The greater the difference in residual copper rate between different areas, the more obvious the change in dielectric thickness, which leads to impedance differences between different areas.

[0026] Since the dielectric thickness is uncontrollable, it is necessary to adjust the line width to offset the impact of uneven dielectric thickness on impedance. The design drawing is divided into several areas, and the residual copper rate is calculated independently in each area and the line width compensation is performed. The more areas are divided, the more subtle changes in the residual copper rate can be captured, thereby adjusting the line width more finely and achieving a more uniform impedance distribution to meet the impedance standards required by the circuit board.

[0027] Exemplarily, when the impedance tolerance of the circuit board is a first preset tolerance, the inner layer circuit design drawing of the circuit board is divided into a first number of grid areas; when the impedance tolerance of the circuit board is a second preset tolerance, the inner layer circuit design drawing of the circuit board is divided into a second number of grid areas. It is understood that the first preset tolerance is greater than the second preset tolerance, and the first number of grids is less than the second number of grids. For example, when the impedance tolerance of the circuit board is ±7%, the inner layer circuit design drawing of the circuit board is divided into 3×3 grid areas; when the impedance tolerance of the circuit board is ±5%, the inner layer circuit design drawing of the circuit board is divided into 4×4 grid areas. It is understood that the number and method of dividing the inner layer circuit design drawing into areas are not limited. It can be divided only along the width direction of the design drawing, or along the length direction of the design drawing, or along the width and length directions of the design drawing, such as Figure 2 As shown, the design diagram can be divided into 3×4 grid areas.

[0028] S103: Calculate the residual copper rate of each area.

[0029] It can be understood that the residual copper rate of a region is the ratio of the actual copper foil area in that region to the total area of ​​that region. Exemplarily, image recognition technology can be used to calculate the residual copper rate of each region. Specifically, an image of the inner layer circuit design drawing is obtained, and the obtained image is processed by denoising and grayscaling to improve recognition accuracy. Then, based on the impedance tolerance of the circuit board, the entire image is divided into various regions. The number of pixels representing copper foil and the total number of pixels in each region are counted, and the ratio of the number of copper foil pixels to the total number of pixels in the region is calculated to obtain the residual copper rate of the region.

[0030] As can be seen, the use of image recognition technology greatly improves the efficiency and accuracy of residual copper rate calculations. More accurate residual copper rate calculations lead to more reasonable line width compensation, thereby improving overall impedance consistency. Furthermore, this method is adaptable to design drawings of varying resolutions and formats, supporting a variety of area division methods.

[0031] S104: adjusting the line width of the circuit in the corresponding area of ​​the inner layer circuit design drawing according to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, so as to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design drawing.

[0032] The standard residual copper rate can be set based on actual application conditions, for example, the standard residual copper rate is 50%. Exemplarily, the residual copper rate of each region is compared with the standard residual copper rate. If the residual copper rate of the current region is equal to the preset standard residual copper rate, the original line width of the line in the current region is maintained; if the residual copper rate of the current region is higher than the standard residual copper rate, the line width of the line in the current region is widened; if the residual copper rate of the current region is lower than the standard residual copper rate, the line width of the line in the current region is reduced.

[0033] Regarding the degree of line width increase or reduction, in one embodiment, when the residual copper ratio exceeds the standard residual copper ratio, the line width can be increased to a preset ratio of the original line width, for example, increasing the line width to 100.5% of the original line width. Alternatively, when the residual copper ratio exceeds the standard residual copper ratio, the line width can be increased by a preset value, for example, increasing the line width by 5μm. Similarly, the degree of line width reduction can also be expressed as a preset ratio or preset value.

[0034] In another embodiment, for situations where an increase is required, the line width can be adjusted in steps according to the difference between the residual copper rate in the region and the standard residual copper rate. For example, when the residual copper rate in the current region increases by a first preset ratio relative to the standard residual copper rate, the line width of the lines in the current region is increased in a positive direction according to a second preset ratio. For example, when the residual copper rate in the current region is compared with the standard residual copper rate of 50%, the line width increases by 0.8% for every 5% increase. Similarly, for situations where a decrease is required, for example, when the residual copper rate in the current region decreases by a first preset ratio relative to the standard residual copper rate, the line width of the lines in the current region is decreased in a negative direction according to a second preset ratio. For example, when the residual copper rate in the current region decreases by a 5% ratio relative to the standard residual copper rate, the line width of the lines in the current region is decreased in a negative direction according to a second preset ratio. For example, when the residual copper rate in the current region decreases by a 5% ratio relative to the standard residual copper rate, the line width of the lines in the current region is decreased in a negative direction according to a second preset ratio. For example, when the residual copper rate in the current region decreases by a 5% ratio, the line width decreases by 0.8%. The above numerical values ​​are only a feasible example and are not intended to be the only limitation.

[0035] It can be understood that by setting a segmented compensation coefficient based on the degree of deviation between the residual copper rate and the standard value, the line width compensation can be more refined and can more accurately match the actual impedance requirements, thereby improving the impedance consistency of the overall line.

[0036] This embodiment utilizes regional division combined with residual copper ratio calculation and linewidth compensation strategies to achieve both local and global optimization. The introduction of the key parameter, residual copper ratio, makes compensation more targeted. This linewidth compensation mechanism effectively offsets impedance variations caused by dielectric thickness fluctuations, aligning impedance across different regions and meeting high-precision impedance control requirements. This improved impedance consistency reduces signal reflections and ringing during transmission, improving signal integrity and transmission quality.

[0037] In one embodiment, Figure 3 Another flow chart of the method for manufacturing a circuit board according to an embodiment of the present application is shown. Based on the above embodiment, before step S104, the compensation method further includes: S201: Determine independent circuits and dense circuits in an inner layer circuit design diagram.

[0038] It is understandable that independent lines are those with relatively ample space and no other closely spaced lines around them. These lines experience more severe copper foil undercuts during etching, resulting in significant line width loss. Examples include isolated traces in power planes and single signal lines far from other lines. Dense lines are those with very close spacing between them and arranged in a high density. These lines have lower etching rates and minimal line width loss.

[0039] The line spacing threshold can be set based on actual application needs. For example, it can be used to determine whether other lines exist within 5 mm of a line. If so, it is considered a dense line; if not, it is an independent line. Graphics software can be used to perform image recognition and analysis on the inner layer line design to classify the inner layer lines into independent lines and dense lines.

[0040] S202: Preliminary adjustment is made to the line width of each independent line in the inner layer line design drawing.

[0041] During circuit board manufacturing, independent lines, lacking surrounding support structures, are susceptible to excessive etching during etching, resulting in narrowed line widths. However, densely packed lines, due to the dense distribution of copper foil, restrict the diffusion of the etching solution, resulting in slower etching speeds and better line width preservation. Inconsistent line widths directly lead to impedance fluctuations, so the line widths of individual lines on inner-layer circuit designs must be compensated to offset etching losses.

[0042] The compensation value may be set according to actual application conditions, may be set according to etching process parameters, or may be compensated for the line width of the corresponding independent circuit in the inner layer circuit design drawing according to the copper thickness of each independent circuit.

[0043] In this embodiment, not only the residual copper rate is taken into account, but also the difference between independent lines and dense lines. Preliminary line width compensation is performed on independent lines, unifying the line width benchmarks for different line types, making subsequent compensation based on the residual copper rate more consistent. The step-by-step compensation mechanism can more effectively address the impact of multiple variables on impedance, ultimately making the characteristic impedance of different areas tend to be consistent, thereby meeting higher standards of impedance control.

[0044] In one embodiment, based on the above embodiment, after the inner layer circuits of the circuit board are prepared using the adjusted inner layer circuit design drawing, the impedance value of the circuit board with the prepared inner layer circuits can be measured using an impedance measurement device to verify the impedance consistency. Furthermore, the line width can also be adjusted based on the measured impedance value. Exemplarily, after the inner layer circuits of the circuit board are prepared using the adjusted inner layer circuit design drawing, the compensation method further includes: Connect the circuit board with the prepared inner-layer circuits to the test fixture of the impedance measurement device. Using time-domain reflectometry, send a step signal, measure the time difference and amplitude of the reflected wave, and calculate the impedance value. This impedance value is compared with the target impedance value to determine whether it meets the tolerance requirements. If not, adjust the line width of the inner-layer circuits on the circuit board based on the impedance value.

[0045] In this embodiment, by actually measuring the impedance of a completed circuit board, the effectiveness of line width compensation based on residual copper ratio calculations can be evaluated. Adjusting the line width on the circuit board based on the impedance value meets the need for higher-precision impedance control. The test results can also serve as a basis for parameter adjustments during the design and manufacturing of subsequent batches of products, forming a closed-loop control system.

[0046] An embodiment of the present application further provides a circuit board. Exemplarily, the inner layer circuit of the circuit board is manufactured using the above method.

[0047] The embodiment of the present application also provides an impedance compensation method for a circuit board. Figure 4 A schematic flow chart of an impedance compensation method for a circuit board according to an embodiment of the present application is shown. Exemplarily, the impedance compensation method includes: S301: Divide the inner layer circuit design of the circuit board into a preset number of areas; S302: Calculate the residual copper rate of each area; S303: adjusting the line width of the corresponding area of ​​the inner layer circuit design drawing according to the deviation value between the residual copper rate of each area and the preset standard residual copper rate.

[0048] It can be understood that the various steps of this embodiment have been explained in detail in the above embodiments and will not be repeated here.

[0049] Exemplarily, the above-mentioned preparation process includes: providing a core board, copper-cladding the core board, applying a photosensitive dry film to the copper surface of the copper-clad core board, and heat-pressing to ensure that there are no bubbles. Using ultraviolet light, the circuit pattern is transferred to the dry film through a photo-painted negative generated by adjusting the inner layer circuit design, dissolving the unexposed areas. An alkaline solution is used to remove the dry film from the unexposed areas, exposing the copper surface to be etched. An acidic etchant is used to dissolve the exposed copper to form the circuit pattern. The remaining dry film is removed to form a circuit board with prepared inner layer circuits. The outer layer circuits can then be prepared on this circuit board based on the actual application.

[0050] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0051] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0052] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a smart phone, personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0053] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A method for manufacturing a circuit board, characterized in that: include: Obtain the inner layer circuit design drawing of the circuit board; Dividing the inner layer circuit design into a preset number of areas; Calculate the residual copper rate of each of the areas; According to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, the line width of the corresponding area of ​​the inner layer circuit design drawing is adjusted to prepare the inner layer circuit of the circuit board using the adjusted inner layer circuit design drawing.

2. The method for manufacturing a circuit board according to claim 1, wherein: The adjusting the line width of the corresponding area of ​​the inner layer circuit design drawing according to the deviation value between the residual copper rate of each area and the preset standard residual copper rate includes: If the residual copper rate in the current area is higher than the standard residual copper rate, widening the line width of the circuit in the current area; If the residual copper rate in the current area is lower than the standard residual copper rate, line width reduction processing is performed on the lines in the current area.

3. The method for manufacturing a circuit board according to claim 2, wherein: If the residual copper rate in the current area is higher than the standard residual copper rate, performing line width widening processing on the line in the current area includes: When the variation of the residual copper rate in the current area relative to the standard residual copper rate increases by a first preset ratio each time, the line width of the line in the current area is positively increased according to a second preset ratio.

4. The method for manufacturing a circuit board according to claim 2, wherein: If the residual copper rate in the current area is lower than the standard residual copper rate, performing line width reduction processing on the line in the current area includes: When the variation of the residual copper rate in the current area relative to the standard residual copper rate decreases by a first preset ratio, the line width of the line in the current area is negatively reduced according to a second preset ratio.

5. The method for manufacturing a circuit board according to claim 1, wherein: Before adjusting the line width of the corresponding area of ​​the inner layer circuit design drawing according to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, the method further includes: Determining independent circuits and dense circuits in the inner layer circuit design diagram; The line width of each independent circuit in the inner layer circuit design drawing is preliminarily adjusted.

6. The method for manufacturing a circuit board according to claim 1, wherein: The dividing the inner layer circuit design diagram into a preset number of areas includes: The number of regions into which the inner layer circuit design drawing is divided is determined based on the impedance tolerance of the circuit board, and the number of regions increases as the impedance tolerance decreases.

7. The method for manufacturing a circuit board according to claim 6, wherein: Determining the number of regions divided into which the inner layer circuit design drawing is divided based on the impedance tolerance of the circuit board includes: When the impedance tolerance of the circuit board is a first preset tolerance, dividing the inner layer circuit design drawing into a first number of grid areas; When the impedance tolerance of the circuit board is a second preset tolerance, the inner layer circuit design drawing is divided into areas with a second number of grids, wherein the first preset tolerance is greater than the second preset tolerance, and the first number of grids is less than the second number of grids.

8. The method for manufacturing a circuit board according to claim 1, wherein: Calculating the residual copper rate of each of the regions includes: The residual copper rate of each of the regions is calculated using image recognition technology; wherein the residual copper rate is the ratio of the copper foil area of ​​the current region to the total area of ​​the current region.

9. A circuit board, characterized in that: The circuit board is manufactured using the method according to any one of claims 1 to 8 to obtain the inner layer circuit of the circuit board.

10. A circuit board impedance compensation method, characterized in that: include: Divide the inner layer circuit design of the circuit board into a preset number of areas; Calculate the residual copper rate of each of the areas; According to the deviation value between the residual copper rate of each area and the preset standard residual copper rate, the line width of the corresponding area of ​​the inner layer circuit design drawing is adjusted.

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