Semiconductor memory device and method for manufacturing semiconductor memory device

Abstract

Embodiments provide a semiconductor memory device and a method of manufacturing the semiconductor memory device capable of suppressing poor formation of a step portion. According to one embodiment, a semiconductor memory device includes: a stacked body in which a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked layer by layer; and a stepped portion provided in a portion of the laminated body, the plurality of first conductive layers and the plurality of first insulating layers being processed in a stepped shape, the stepped portion having a plurality of plateau surfaces formed by the plurality of first conductive layers and a plurality of stepped surfaces connecting the plurality of plateau surfaces to each other in the lamination direction of the laminated body, the plurality of first conductive layers extend in a first direction intersecting the lamination direction, and the layer thickness of at least a portion of the portion of each of the plurality of first conductive layers that forms the plateau surface is thicker than the layer thickness of the other portion of the corresponding conductive layer. The first insulating layer at the lowermost layer of each of the plurality of stepped surfaces has a tapered portion extending toward a landing surface connected to the corresponding stepped surface on the lower side, and the width of the lower surface of the tapered portion in the first direction is greater than the layer thickness of the first insulating layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device. Background Art

[0002] For example, a three-dimensional nonvolatile memory includes a laminated body formed by alternating multiple conductive layers and multiple insulating layers. At the ends of the laminated body, stepped portions are formed to allow each conductive layer to be led out to upper-layer wiring.

[0003] As the thickness of stacked layers decreases and the number of stacked layers increases, the processing of step portions tends to become more difficult. In some cases, poor step formation may lead to a decrease in the electrical characteristics of a semiconductor memory device. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device that can suppress defective formation of a step portion.

[0005] The semiconductor storage device of the embodiment comprises: a stacked body formed by alternately stacking multiple first conductive layers and multiple first insulating layers layer by layer; and a stepped portion provided on a portion of the stacked body, the multiple first conductive layers and the multiple first insulating layers being processed into a stepped shape, the stepped portion having multiple platform surfaces formed by the multiple first conductive layers and multiple step surfaces connecting the multiple platform surfaces to each other in the stacking direction of the stacked body, and extending in a first direction intersecting the stacking direction, the layer thickness of at least a portion of the portions of the multiple first conductive layers respectively forming the platform surfaces is formed to be thicker than the layer thickness of other portions of the corresponding conductive layer, and among the multiple first insulating layers, the lowest first insulating layer of each of the multiple step surfaces has a tapered portion extending toward the platform surface connected to the corresponding step surface on the lower side, and the width of the lower surface of the tapered portion in the first direction is greater than the layer thickness of the first insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a diagram showing a schematic configuration example of a semiconductor memory device according to the first embodiment.

[0007] Figure 2 This is a diagram showing a detailed configuration example of the semiconductor memory device according to the first embodiment.

[0008] Figure 3 These are diagrams sequentially illustrating a part of the procedure of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0009] Figure 4These are diagrams sequentially illustrating a part of the procedure of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0010] Figure 5 These are diagrams sequentially illustrating a part of the procedure of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0011] Figure 6 These are diagrams sequentially illustrating a part of the procedure of the method for manufacturing the semiconductor memory device according to the first embodiment.

[0012] Figure 7 This is a diagram illustrating a part of the procedure of a method for manufacturing a semiconductor memory device according to a comparative example.

[0013] Figure 8 This is a diagram showing a detailed configuration example of a semiconductor memory device according to the second embodiment.

[0014] Figure 9 These are diagrams sequentially illustrating a portion of the procedure of a method for manufacturing a semiconductor memory device according to the second embodiment. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0016] Furthermore, the constituent elements in the following embodiments include elements that can be easily conceived by those skilled in the art or elements that are substantially the same.

[0017] [Implementation Method 1]

[0018] (Configuration Example of Semiconductor Memory Device)

[0019] Figure 1 This is a diagram showing a schematic configuration example of a semiconductor memory device 1 according to the first embodiment. Figure 1 (a) is a cross-sectional view of the semiconductor memory device 1 along the X direction. Figure 1 (b) is a schematic top view showing the layout of the semiconductor memory device 1. Figure 1 In (a), hatching is omitted for the sake of easy viewing of the accompanying drawings. Figure 1 In (a), a portion of the selection gate line and upper layer wiring is omitted.

[0020] In this specification, both the X and Y directions are directions along the plane of a word line WL, described later, and the X and Y directions are orthogonal to each other. Furthermore, the electrical extraction direction of the word line WL, described later, is sometimes referred to as a first direction, which is along the X direction. Furthermore, a direction intersecting the first direction is sometimes referred to as a second direction, which is along the Y direction. However, the semiconductor memory device 1 may include manufacturing variations, so the first and second directions are not necessarily orthogonal.

[0021] like Figure 1 As shown, the semiconductor memory device 1 includes a peripheral circuit CUA, a memory region MR, a through-contact region TP, and a step region SR on a substrate SB.

[0022] The substrate SB is a semiconductor substrate such as a silicon substrate. A peripheral circuit CUA including transistors TS and wiring is arranged on the substrate SB. The peripheral circuit CUA contributes to the operation of the memory cell described later.

[0023] The peripheral circuit CUA is covered by an insulating layer 50. A source line SL is arranged on the insulating layer 50. A plurality of word lines WL are stacked on the source line SL. The plurality of word lines WL are covered by an insulating layer 49. The insulating layer 49 also extends around the plurality of word lines WL.

[0024] The word lines WL are provided with a plurality of plate contacts LI that penetrate the word lines WL in the stacking direction and extend along the X direction.

[0025] Between the plate-shaped contacts LI, the memory regions MR, the step region SR, and the through-contact region TP are arranged side by side in the X direction. The memory regions MR are spaced apart from each other in the X direction with the step region SR and the through-contact region TP interposed therebetween.

[0026] In the memory region MR, a plurality of pillars PL are arranged, penetrating word lines WL in the stacking direction. Memory cells are formed at the intersections of the pillars PL and the word lines WL. Thus, the semiconductor memory device 1 is configured as a three-dimensional nonvolatile memory in which memory cells are three-dimensionally arranged in the memory region MR.

[0027] The step region SR includes a plurality of step portions SP formed by mortar-shaped hollowing of a plurality of word lines WL in the stacking direction. In one step region SR, for example, two step portions SP arranged in the Y direction are arranged with one plate-shaped contact LI interposed therebetween.

[0028] The step portion SP forms one side of a mortar-shaped shape that steps down from both sides in the X direction and one side in the Y direction toward the bottom surface. However, the other side in the Y direction of the step portion SP is open toward the side surface of the plate-shaped contact LI.

[0029] Each segment of the step portion SP is composed of word lines WL of each level. Each word line WL maintains electrical continuity across the step region SR in the X direction via the stepped portion on one side of the step portion SP in the Y direction. Contacts CC are located on the terrace surface of each segment of the step portion SP, connecting each word line WL to the upper-layer wiring MX.

[0030] From these contacts CC, write voltages and read voltages are applied to memory cells in the memory region MR on both sides in the X direction via the word lines WL at the same height as the memory cells.

[0031] A through-contact region TP is disposed on one side of the step region SR in the X direction. A through-contact C4 is disposed in the through-contact region TP, penetrating multiple word lines WL. The through-contact C4 connects the peripheral circuit CUA disposed on the underlying substrate SB to the upper-layer wiring MX connected to the contact CC of the step portion SP. Various voltages applied to the memory cell from the contact CC are controlled by the peripheral circuit CUA via the through-contact C4 and the upper-layer wiring MX.

[0032] Figure 2 This is a diagram showing a detailed configuration example of the semiconductor memory device 1 according to the first embodiment. Figure 2 (a) is a cross-sectional view of the step region SR along the X direction. Figure 2 (b) is a partially enlarged view showing a cross section of the step portion SP arranged in the step region SR. Figure 2 In (a), the structure below the insulating layer 50 including the substrate SB and the peripheral circuit CUA is omitted.

[0033] like Figure 2 As shown in (a), in the stepped region SR, a source line SL is arranged on an insulating layer 50, and a laminated body LM is arranged on the source line SL. The laminated body LM has a structure in which multiple word lines WL and multiple insulating layers OL are alternately laminated. The multiple word lines WL are each composed of, for example, a tungsten layer or a molybdenum layer. These word lines WL are an example of a first conductive layer. The multiple insulating layers OL are each composed of, for example, a silicon oxide layer.

[0034] A stepped portion SP extending in the X direction is provided in the laminate LM. In the stepped portion SP, a plurality of word lines WL and a plurality of insulating layers OL are processed into a stepped shape. The entire stepped region SR including the stepped portion SP is covered by an insulating layer 51 such as a silicon oxide layer. Insulating layers 52 to 54 are formed on the upper surface of the insulating layer 51. The insulating layers 52 to 54, together with the insulating layer 51, respectively constitute Figure 1 A portion of the insulating layer 49.

[0035] Each segment of the step portion SP is formed by one or more word lines WL and an insulating layer OL. In each segment, the uppermost layer is the word line WL, and the lowermost layer is the insulating layer OL. Figure 2 In the example of FIG, each segment of the step portion SP is formed by a set of word lines WL and an insulating layer OL.

[0036] The top surface of each word line WL that forms the step portion SP is referred to as a terrace surface TR. Furthermore, the X-direction end surfaces of each word line WL and insulating layer OL that form the step portion SP are referred to as step surfaces SS. Specifically, the step portion SP includes multiple terrace surfaces TR and multiple step surfaces SS.

[0037] The plurality of step surfaces SS connect the terrace surfaces TR in the stacking direction. Specifically, the plurality of step surfaces SS connect to the terrace surface TR in the upper section above and to the terrace surface TR in the lower section below. The end surface of the insulating layer OL, which forms the lower layer of the step surfaces SS, has a tapered portion TPa that expands toward the terrace surface TR.

[0038] The layer thickness of the portion forming the terrace surface TR of the word line WL is formed to be thicker than the layer thickness of the other portion of the corresponding word line WL.

[0039] In addition, in this specification, the direction in which the terrace surface TR of each stage of the step portion SP faces is defined as an upward direction.

[0040] Each contact CC penetrates insulating layers 52 and 51, reaching the word line WL of each step of terrace SP. Contact CC includes insulating layer 56 covering the sidewalls of contact CC and conductive layer 22 filling the inner surface of insulating layer 56. The lower end of conductive layer 22 is connected to terrace surface TR of the corresponding word line WL. The upper end of conductive layer 22 is connected to upper-layer wiring MX arranged in insulating layer 54 via plug V0 extending through insulating layer 53.

[0041] As described above, the semiconductor memory device 1 includes the peripheral circuit CUA (see Figure 1), and the upper-layer wiring MX is electrically connected to the peripheral circuit CUA. The peripheral circuit CUA includes multiple transistors TS that facilitate the electrical operation of the memory cell. Data is read and written to the memory cell by applying a voltage to the memory cell via the peripheral circuit CUA, the through-contact C4, the upper-layer wiring MX, the contact CC, and the word line WL.

[0042] use Figure 2 (b) of the drawings will now describe the specific positional relationship among the terrace surface TR, the step surface SS, and the tapered portion TPa.

[0043] exist Figure 2 (b) shows, for example, a case where, starting from the bottom, an insulating layer OLm, a word line WLm, an insulating layer OLn, and a word line WLn are sequentially stacked. The thickness To of the insulating layers OLm and OLn is determined based on the distance between the stacked word lines WL to prevent mutual interference from causing problems with device operation. Specifically, if the distance between the word lines WL is greater than the thickness To, the word lines WL will not cause problems with device operation due to mutual interference.

[0044] A terrace surface TRm is formed on word line WLm, and a terrace surface TRn is formed on word line WLn. Furthermore, a step surface SSn is connected to terrace surface TRn above and to terrace surface TRm below. The insulating layer OLn below step surface SSn has a tapered portion TPan that expands toward terrace surface TRm.

[0045] The terrace surface TRm is a portion protruding in the X direction from a position SF on the upper surface of the word line WLm that vertically overlaps with the X-direction end SEn of the stepped word line WLn. The terrace surface TRm includes a first portion Pam where the word line WLm is formed thicker, and a second portion Pbm where the word line WLm is thinner than the first portion Pam.

[0046] The first portion Pam is the region of the terrace surface TRm on the X-direction end side. The layer thickness Twa of the word line WLm in the first portion Pam is thicker than the layer thickness Twb of the second portion Pbm. The first portion Pam is connected to a contact CC. Meanwhile, the second portion Pbm is the region of the terrace surface TRm opposite the X-direction end side. The second portion Pbm extends from position SG to position SF, overlapping with the end surface SNm on the step surface SSn side of the first portion Pam, as viewed from above. Therefore, the X-direction width Wa of the second portion Pbm corresponds to the distance between position SF and the end surface SNm of the word line WLm.

[0047] The tapered portion TPan extends along the second portion Pbm, with the end portion TPas of the tapered portion TPan on the terrace surface TRm side reaching the first portion Pam. In other words, the first portion Pam covers the end portion TPas of the tapered portion TPan on the terrace surface TRm side. Therefore, the second portion Pbm is covered by the tapered portion TPan. At this point, the width Wb of the lower surface of the tapered portion TPan in the X direction is slightly larger than the width Wa of the second portion Pbm in the X direction.

[0048] Furthermore, the width Wb in the X direction of the lower surface of the tapered portion TPan is set to be greater than the thickness To of the insulating layer OLn. Specifically, the distance between the end SEn of the word line WLn and the end surface SNm of the word line WLm is ensured to be greater than the thickness To. As a result, the word lines WLn and WLm are sufficiently separated in the X direction, preventing problems with device operation caused by mutual interference.

[0049] (Method for Manufacturing Semiconductor Memory Device)

[0050] Next, use Figures 3 to 7 , a method for manufacturing the semiconductor memory device 1 according to the first embodiment will be described. Figures 3 to 7 FIG is a diagram sequentially illustrating a part of the process of manufacturing the semiconductor memory device 1 according to the first embodiment. Figures 3 to 7 Before the illustrated process, the peripheral circuit CUA is formed on the substrate SB, and the insulating layer 50 covering the peripheral circuit CUA has been formed.

[0051] Figures 3 to 6 It mainly shows a case where a step portion SP is formed in a region which will later become the step region SR. Figures 3 to 6 It is a cross-sectional view taken along the X direction of a region which will later become the step region SR.

[0052] like Figure 3 As shown in (a), a source line SL is formed on an insulating layer 50. A laminated body LMs is formed on the source line SL by alternately laminating a plurality of insulating layers NL and a plurality of insulating layers OL. The lowermost layer of the laminated body LMs is the insulating layer OL, and the uppermost layer is the insulating layer NL.

[0053] The multiple insulating layers NL are, for example, silicon nitride layers. The multiple insulating layers NL function as sacrificial layers that are later replaced with word lines WL. These insulating layers NL are examples of first insulating layers. Furthermore, the multiple insulating layers OL are, for example, silicon oxide layers. These insulating layers OL are examples of second insulating layers.

[0054] A mask pattern 72 is formed on the laminate body LMs, covering a portion of the laminate body LMs. The mask pattern 72 is, for example, a carbon-containing layer. Using the mask pattern 72, the exposed portions of the insulating layer NL and the insulating layer OL are removed layer by layer by etching. Next, the ends of the mask pattern 72 are retreated by treatment using oxygen plasma or the like, exposing the upper surface of the laminate body LMs. The insulating layer NL and the insulating layer OL are further removed layer by layer by etching.

[0055] The thinning of the mask pattern 72 and the etching of the insulating layer NL and the insulating layer OL of the laminated body LMs are repeated several times. Figure 3 The step portion SPa shown in (b) is the first step portion.

[0056] The stepped portion SPa extends in the X direction and has a stepped shape formed by processing multiple insulating layers NL and multiple insulating layers OL. The stepped portion SPa includes terrace surfaces TRa formed by the multiple insulating layers NL and multiple step surfaces SSa. The multiple step surfaces SSa connect the terrace surfaces TRa in the stacking direction of the stacked body LMs.

[0057] The terrace surface TRa is the top surface of the insulating layer NL that constitutes each section of the step portion SPa. Furthermore, the step surface SSa is the X-direction end surface of the insulating layer NL and the insulating layer OL that constitute each section of the step portion SPa. The upper side of the step surface SSa is the insulating layer NL, and the lower side is the insulating layer OL. The step surface SSa is connected to the terrace surface TRa above the insulating layer NL and below the insulating layer OL. The terrace surface TRa is an example of a first terrace surface. Furthermore, the step surface SSa is an example of a first step surface.

[0058] Furthermore, when forming the step portion SPa, the insulating layer OL below the step surface SSa is processed so that it includes a tapered portion TPa that extends downward toward the terrace surface TRa connected to the step surface SSa. As a result, the vicinity of the step surface SSa in the terrace surface TRa is covered by the tapered portion TPa. Furthermore, when processing the tapered portion TPa, the width Wb of the lower surface of the tapered portion TPa in the X direction is greater than the thickness To of the insulating layer OL.

[0059] After the step portion SPa is formed, the mask pattern 72 is removed by ashing using oxygen plasma or the like.

[0060] like Figure 4 As shown in FIG. 5 ( a ), the insulating layer NLa is formed to cover the entire step portion SPa along the shape of the step portion SPa. Thus, the terrace surface TRb is formed above the terrace surface TRa.

[0061] The insulating layer NLa has the same main component as the insulating layer NL. Specifically, the insulating layer NLa is, for example, a silicon nitride layer. The insulating layer NLa is an example of a third insulating layer.

[0062] like Figure 4 As shown in (b), the insulating layer NLa covering the step portion SPa is etched back. At this time, by using anisotropic etching such as RIE (Reactive Ion Etching), the insulating layer NLa covering the step surface SSa can be removed while the insulating layer NLa constituting the terrace surface TRb remains.

[0063] Furthermore, at this time, the tapered portion TPa formed below the step surface SSa functions as an etch stop when removing the insulating layer NLa covering the step surface SSa. That is, the downward etching process for removing the insulating layer NLa ends when it reaches the tapered portion TPa. This is because the tapered portion TPa, which is a silicon oxide layer or the like, has a certain etching selectivity relative to the insulating layer NLa, which is a silicon nitride layer or the like. Thus, by having the tapered portion TPa function as an etch stop, etching of the terrace surface TRa, which is connected to the bottom of the step surface SSa, can be suppressed.

[0064] Thereby, a step portion SPc which will later become the step portion SP is formed.

[0065] The terrace portion SPc includes a plurality of terrace surfaces TRb and a plurality of stepped surfaces SSc. The plurality of stepped surfaces SSc are end surfaces of the insulating layer OL, the insulating layer NL, and the insulating layer NLa in the X direction.

[0066] like Figure 5 As shown in (a), an insulating layer 51 is deposited to cover the step portion SPc and reach the height position of the upper surface of the unprocessed laminated body LMs. In addition, an insulating layer 52 is formed to cover the upper surface of the unprocessed laminated body LMs and the insulating layer 51.

[0067] Although not shown, pillars PL are formed in the laminated body LMs by a predetermined method. The pillars PL may be formed before the step region SR is formed.

[0068] The insulating layer NL and the insulating layer NLa of the laminate LMs are removed by etching solution, and the removed portion is filled with a metal such as a tungsten layer. Figure 5 This process of replacing the insulating layer with the word line WL is sometimes called a replacement process.

[0069] Through the above process, a laminated body LM is formed in which a plurality of word lines WL and a plurality of insulating layers OL are alternately laminated layer by layer. Furthermore, a step portion SP having a terrace surface TR and a step surface SS is formed in the laminated body LM.

[0070] In the step portion SP, the layer thickness of the portion forming the terrace surface TR of the word line WL is formed thicker than the layer thickness of the other portion of the corresponding word line WL. This is because after the insulating layer NLa is deposited on the terrace surface TRa of the insulating layer NL, the insulating layer NL and the insulating layer NLa are replaced with the word line WL.

[0071] then, Figure 6 This shows the situation where contact CC is formed. Figure 6 and Figures 3-5 Similarly, a cross section along the X direction of a region including the step portion SP is shown.

[0072] like Figure 6 As shown in (a), a plurality of contact holes HLC are formed, which penetrate the insulating layers 52 and 51 and reach the terrace surfaces TR. The contact holes HLC later become contacts CC connected to the word lines WL.

[0073] Each of these contact holes HLC reaches a different depth. As the contact holes HLC reach the word lines WL in the upper layer of the laminate LM, the word lines WL are subjected to greater overetching. However, because the layer thickness of the portion forming the terrace TR of the word lines WL is formed thicker, even under etching conditions that allow the deepest contact holes HLC to be processed, the lower ends of the multiple contact holes HLC can be prevented from penetrating the terrace TR.

[0074] like Figure 6 As shown in (b), an insulating layer 56 is formed to cover the sidewalls of the contact hole HLC. Furthermore, a conductive layer 22 such as a tungsten layer is filled in the gap of the contact hole HLC remaining inside the insulating layer 56. Thus, the contact CC is formed.

[0075] In addition, although not shown, after forming the contact CC, insulating layers 53 and 54 are formed on the insulating layer 52 to form a plug V0 connected to the conductive layer 22 of the contact CC and extending in the insulating layer 53, and an upper wiring MX connected to the plug V0 and arranged in the insulating layer 54.

[0076] Furthermore, although not shown, after forming contact CC or before forming contact CC, through-contact C4 is formed in through-contact region TP. Furthermore, plate contact LI is formed before or at the same time as through-contact C4 is formed. Furthermore, through-contact C4, plate contact LI, and contact CC are connected to upper-layer wiring MX, and pillar PL is connected to a bit line (not shown).

[0077] As described above, the semiconductor memory device 1 according to the first embodiment is manufactured.

[0078] (Comparative Example)

[0079] Next, use Figure 7 , a method for manufacturing a semiconductor storage device according to a comparative example is described. Figure 7 This is a diagram illustrating a part of the procedure of a method for manufacturing a semiconductor memory device according to a comparative example.

[0080] Figure 7 (a) is a cross-sectional view showing a step portion SPbx where the insulating layer NLb is formed in a method for manufacturing a semiconductor memory device according to a comparative example. Figure 7 (b) is a cross-sectional view showing an example of a state in which the insulating layer NLb in the step surface SSbx is removed. Figure 7 (c) is a cross-sectional view showing another example of a state where the insulating layer NLb in the step surface SSbx is removed. Figure 7 (a) is the same as that of embodiment 1 Figure 4 The corresponding figure of (a) is, Figure 7 (b) and (c) are the same as those in Implementation 1. Figure 4 (b) corresponds to the figure.

[0081] like Figure 7 As shown in (a), in the manufacturing method of the semiconductor memory device of the comparative example, no tapered portion is formed on the step portion SPbx. After the insulating layer NLb is formed on the step portion SPbx, the insulating layer NLb on the step surface SSbx is removed mainly by a process such as RIE.

[0082] So, if Figure 7 As shown in (b), a recessed portion TC may be formed in a portion of the terrace surface TRax. This is because both the insulating layer NLb to be removed and the insulating layer NL forming the terrace surface TRax are made of silicon nitride layers, etc. Therefore, even after removing the insulating layer NLb, the etching in the downward direction does not end, and the etching may spread to the terrace surface TRax.

[0083] If such a recess TC is formed in the terrace surface TRax, word line WL formation may be defective during subsequent replacement processing, thereby hindering voltage application to the memory cell via the word line WL and degrading the electrical characteristics of the semiconductor memory device.

[0084] On the other hand, in order to avoid the formation of the concave portion TC, it is conceivable to shorten the processing time such as RIE. Figure 7 As shown in (c), there is a possibility that a residue Rd of the insulating layer NLb is generated on the step surface SSax.

[0085] If such residue Rd exists on step surface SSax, the residue Rd is replaced by a tungsten layer during subsequent replacement processing. Such a tungsten layer spanning multiple word lines may become a leakage path, causing a short circuit between multiple word lines.

[0086] (Summary)

[0087] According to the semiconductor storage device 1 of embodiment 1, in a stepped portion SP provided in a portion of a laminated body LM in which a plurality of word lines WL and a plurality of insulating layers OL are alternately stacked layer by layer, the layer thickness of the portions of the plurality of word lines WL that respectively form the platform surfaces TR is formed to be thicker than the layer thickness of other portions of the corresponding word lines WL.

[0088] Thus, when forming the contact CC, it is possible to suppress the contact CC from penetrating the terrace surface TR, thereby suppressing deterioration in the electrical characteristics of the semiconductor memory device 1 .

[0089] Furthermore, the insulating layer OL of the lowest layer of the plurality of step surfaces SSa of the stepped portion SP has a tapered portion TPa that expands toward a terrace surface TRa connected to the corresponding step surface SSa on the lower side.

[0090] Thus, the tapered portion TPa protects the terrace surface TRa, thereby suppressing the formation of a recess TC in the terrace surface TRa when the insulating layer NLa covering the step surface SSa is etched away. As a result, during the subsequent replacement process, formation defects of the word line WL can be suppressed, thereby suppressing degradation of the electrical characteristics of the semiconductor memory device 1.

[0091] In addition, the multiple platform surfaces TR respectively include: a first part Pa, in which the layer thickness of the word line WL is formed to be thicker; and a second part Pb, in which the layer thickness is thinner than the layer thickness of the first part Pa near the boundary with the corresponding step surface SS, and the first part Pa covers the end part of the platform surface TR side of the conical part TPa.

[0092] Thus, the entire second portion Pb is covered by the tapered portion Tpa, thereby more reliably preventing the recess TC from being formed in the terrace surface TRa. As a result, deterioration of the electrical characteristics of the semiconductor memory device 1 can be more reliably suppressed.

[0093] In addition, the width Wb of the lower surface of the tapered portion TPa in the X direction is larger than the thickness To of the insulating layer OL.

[0094] Thus, the distance between the first portions Pa of the terrace surfaces TR can be set to a distance greater than or equal to a distance at which the step surface SS of the upper word line WL and the thickened portion of the lower word line WL do not electrically affect each other. As a result, degradation of the electrical characteristics of the semiconductor memory device 1 can be suppressed.

[0095] [Implementation Method 2]

[0096] (Configuration Example of Semiconductor Memory Device)

[0097] use Figure 8 , a semiconductor memory device 2 according to a second embodiment will be described. In the semiconductor memory device 2 according to the second embodiment, the shape of the tapered portion of the insulating layer OL is different from that of the first embodiment. Hereinafter, the same reference numerals are assigned to the same components as those of the first embodiment, and their description may be omitted.

[0098] Figure 8 This is a diagram showing a detailed configuration example of a semiconductor memory device 2 according to the second embodiment. Figure 8 Same as implementation 1 Figure 2 (b) corresponds to the figure.

[0099] exist Figure 8 In the figure, the stacked body of the second embodiment shows a case where, for example, the insulating layer OLp, the word line WLp, the insulating layer OLq, and the word line WLq are stacked in this order from the bottom.

[0100] A terrace surface TRp is formed on word line WLp, and a terrace surface TRq is formed on word line WLq. In addition, a step surface SSq is connected to terrace surface TRq at the top and to terrace surface TRp at the bottom.

[0101] The insulating layer OLq below the stepped surface SSq has a tapered portion TPb extending toward the terrace surface TRp. The tapered portion TPb extends to a position corresponding to the word line WLq above the stepped surface SSq.

[0102] (Method for Manufacturing Semiconductor Memory Device)

[0103] Next, use Figure 9 , a method for manufacturing the semiconductor storage device 2 according to the second embodiment is described. Figure 9 The figures sequentially illustrate a part of the process of the method for manufacturing the semiconductor memory device 2 according to Embodiment 2. In the following, the same components as those in the above-mentioned embodiment are denoted by the same reference numerals, and their description may be omitted.

[0104] exist Figure 9 Before the illustrated process, the peripheral circuit CUA is formed on the substrate SB, and the insulating layer 50 covering the peripheral circuit CUA has been formed.

[0105] exist Figure 9 Before the process (a), a step portion SPd is formed in the same manner as in the first embodiment. The step portion SPd is a step-like shape in which the plurality of insulating layers NL and OL extend in the X direction. Each step of the step portion SPd is formed by a set of insulating layers NL and OL.

[0106] The step portion SPd includes terraces TRd formed by the plurality of insulating layers OL and a plurality of step surfaces SSd. The plurality of step surfaces SSd connect the plurality of terraces TRd in the stacking direction of the stacked body LMt. The step portion SPd is an example of a second step portion.

[0107] The terrace surface TRd is the top surface of the insulating layer OL in each section of the step portion SPd. Furthermore, the step surface SSd is the X-direction end surface of the insulating layer NL and the insulating layer OL in each section of the step portion SPd. The upper side of the step surface SSd is the insulating layer OL, and the lower side is the insulating layer NL. The terrace surface TRd is an example of a second terrace surface. The step surface SSd is an example of a second step surface.

[0108] like Figure 9 As shown in FIG. 1a , an insulating layer OLa is formed as a fourth insulating layer, covering the entire step portion SPd, along the shape of the step portion SPd. The insulating layer OLa has the same main component as the insulating layer OL. Specifically, the insulating layer OLa is, for example, a silicon oxide layer. The insulating layer OLa is an example of a fourth insulating layer.

[0109] like Figure 9 As shown in (b), the portion of the insulating layer OLa formed on the terraces TRd and the portion of the insulating layers OL forming the terraces TRd are etched. This exposes the terraces TRe formed by the insulating layers NL. This forms a step portion SPe, which serves as a first step.

[0110] The terrace portion SPe includes a plurality of terrace surfaces TRe and a plurality of step surfaces SSe formed by a plurality of insulating layers NL. The plurality of terrace surfaces TRe corresponds to the plurality of terrace surfaces TRa in the first embodiment.

[0111] The terrace surface TRe is the top surface of the insulating layer NL that constitutes each section of the step portion SPe. Furthermore, the step surface SSe is the X-direction end surface of the insulating layer NL and the insulating layer OL that constitute each section of the step portion SPe. The upper side of the step surface SSe is the insulating layer NL, and the lower side is the insulating layer OL. The step surface SSe is connected to the terrace surface TRe above the insulating layer NL and below the insulating layer OL, respectively. The terrace surface TRe is an example of a first terrace surface. Furthermore, the step surface SSe is an example of a first step surface.

[0112] When forming the step portion SPe, the lower insulating layer OL is processed so that it has a tapered portion TPb extending toward the terrace surface TRe connected to the lower side of the step surface SSe. As a result, the vicinity of the step surface SSe in the terrace surface TRe is covered by the tapered portion TPb.

[0113] Furthermore, when processing the tapered portion TPb, the insulating layer OLa covering the step surface SSd is processed to have an inclined surface that is continuous with the tapered portion TPb and to have a tapered portion TPc that extends from a position on the step surface SSe corresponding to the upper insulating layer NL toward the terrace surface TRe. Since the tapered portion TPc is composed of the insulating layer OLa, its main component is the same as that of the insulating layer OL.

[0114] By depositing the tapered portion TPc, whose main component is the same as the insulating layer OL, above the tapered portion TPb formed of the insulating layer OL, the overall height of the tapered portion is increased. This enhances the tapered portion's function as an etching stopper when the insulating layer NLa is subsequently removed. Furthermore, by increasing the overall height of the tapered portion, the gradient of the tapered shape can be made gentler. This allows the terrace surface TRe to be covered over a wider area.

[0115] Although not shown, an insulating layer NLa is deposited on the terrace surface TRe of the terrace portion Spe formed as described above. Subsequently, similar to the first embodiment, insulating layers 51 and 52 are formed, and a replacement process is performed to replace the insulating layers with word lines WL. Furthermore, by forming contacts CC, plugs V0, upper-layer wiring MX, and through-contacts C4, the semiconductor memory device of the second embodiment is manufactured.

[0116] Furthermore, in the method for manufacturing a semiconductor memory device according to the second embodiment, the tapered portion TPb is described as extending to a position corresponding to the upper word line WL. However, the present invention is not limited thereto. As long as the tapered portion TPb can independently function as an etch stop layer for the terrace surface TRe, it does not necessarily need to extend to a position corresponding to the upper word line WL.

[0117] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention, and are also intended to be included in the invention set forth in the claims and their equivalents.

[0118] Description of Reference Numerals

[0119] 1, 2: semiconductor memory device, CC: contact, LM, LMs, LMt: laminate, NL, NLa, OL, OLa: insulating layer, SP, SPa, SPc, SPd, SPe: stepped portion, SR: stepped region, SS, SSa, SSc, SSd, SSe: step surface, TPa, TPb, TPc: tapered portion, TR, TRa, TRb, TRd, TRe: terrace surface, WL: word line.

Claims

1. A semiconductor memory device comprising: a laminate formed by alternately laminating a plurality of first conductive layers and a plurality of first insulating layers; and A stepped portion is provided on a portion of the laminate, wherein the plurality of first conductive layers and the plurality of first insulating layers are processed into a stepped shape, the stepped portion having a plurality of terraces formed by the plurality of first conductive layers and a plurality of step surfaces connecting the plurality of terraces to each other in the lamination direction of the laminate, and extending in a first direction intersecting the lamination direction, The thickness of at least a portion of the portions of the plurality of first conductive layers that form terraces is formed to be thicker than the thickness of other portions of the corresponding conductive layers. In the plurality of first insulating layers, the lowermost first insulating layer of each of the plurality of step surfaces has a tapered portion that expands toward a terrace surface connected to the corresponding step surface on the lower side. A width of the lower surface of the tapered portion in the first direction is greater than a thickness of the first insulating layer.

2. The semiconductor memory device according to claim 1, The plurality of platform surfaces respectively have: In the first portion, the first conductive layer is formed to be thicker; and The second portion has a layer thickness that is thinner than that of the first portion near the boundary with the corresponding step surface. The first portion covers an end portion of the tapered portion extending toward the platform surface.

3. A method for manufacturing a semiconductor memory device, comprising: forming a laminated body in which a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated layer by layer; and The plurality of first insulating layers and the plurality of second insulating layers are processed into a stepped shape in a portion of the laminate to form a first stepped portion, the first stepped portion having a plurality of first terraces formed by the plurality of first insulating layers and a plurality of first step surfaces connecting the plurality of first terraces in a lamination direction of the laminate, and extending in a first direction intersecting the lamination direction; When forming the first step portion, The lowermost second insulating layer of each of the plurality of first step surfaces in the plurality of second insulating layers is processed so that the second insulating layer has a tapered portion extending toward a first terrace surface connected to the corresponding first step surface on the lower side, and the width of the lower surface of the tapered portion in the first direction is greater than the thickness of the first insulating layer. The entire first step portion is covered by a third insulating layer having the same main component as the first insulating layer. A portion of the third insulating layer covering the plurality of first step surfaces is removed.

4. The method for manufacturing a semiconductor memory device according to claim 3, When forming the first step portion, In a portion of the laminate, the plurality of first insulating layers and the plurality of second insulating layers are processed into a stepped shape to form a second stepped portion, wherein the second stepped portion has a plurality of second terraces formed by the plurality of second insulating layers and a plurality of second step surfaces connecting the plurality of second terraces to each other in the lamination direction of the laminate, and extends in the first direction. The entire second step portion is covered by a fourth insulating layer having the same main component as the second insulating layer. The portion of the fourth insulating layer formed on the multiple second platform surfaces and the portion of the multiple second insulating layers forming the multiple second platform surfaces are etched until the multiple first platform surfaces are exposed, and are processed into the second insulating layer including the bottommost layer of each of the multiple first step surfaces in the multiple second insulating layers and the tapered portion of the fourth insulating layer.

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