Longitudinal multi-time programmable memory device and preparation method thereof
By forming drain, buffer and source regions on semiconductor silicon and combining the vertical structure of oxide layer and floating gate region, the problem of oxide layer damage of MTP memory cell under high voltage is solved, and low voltage carrier tunneling and area reduction are achieved.
Patent Information
- Application Number
- CN202510779585.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-12
- Publication Date
- 2025-09-19
AI Technical Summary
Existing MTP memory cells require high voltage during programming and erasing, which causes oxide layer traps to damage the oxide layer under the action of a high electric field, leading to device failure. At the same time, the lateral structure occupies a large area.
A vertical multi-time programmable memory device structure is adopted. By forming a drain region, a buffer region and a source region on semiconductor silicon, and forming an oxide layer and a floating gate region on the surface of the source region, a small voltage is used to achieve carrier tunneling, reduce damage to the oxide layer, and adopt a vertical structure to reduce the area.
It realizes carrier tunneling at a low voltage, avoids damage to the oxide layer, and reduces the area of the storage unit.
Smart Images
Figure CN120676635A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a vertical multi-time programmable memory device and a preparation method thereof. Background Art
[0002] MTP (Multi-Time Programmable Memory) is a commonly used technology in integrated circuits. This technology allows for precision adjustment or customization of chips after they leave the factory, and can be used as a storage memory module for chips. Its basic principle is to adjust device parameters such as the threshold voltage by capturing or releasing charges in the storage medium, thereby affecting the output current value.
[0003] In the prior art, a conventional MTP memory cell structure stores data by using a floating gate FG. During programming and erasing, a large voltage difference needs to be applied to the source (S) and drain (D) electrodes in order to allow carriers in the channel to enter the floating gate FG. Typically, a voltage difference of about 4V is required. A voltage of at least 8V is applied to the control gate CG to allow carriers to enter or move out of the floating gate layer. However, this method places very high demands on the quality of the oxide layer under the control gate CG, requiring very few traps and sufficient thickness. However, as the number of device programming and erasing cycles gradually increases, the oxide layer under the control gate CG will develop more and more traps under the action of a higher electric field, eventually leading to a short circuit between the control gate CG and the active area channel, resulting in device failure. At the same time, since the device unit is actually composed of two tubes arranged horizontally, the memory cell still has a relatively large area.
[0004] Currently, no effective solutions have been proposed for the problems in related technologies. Summary of the Invention
[0005] In view of the problems in the related art, the present invention proposes a vertical multi-time programmable memory device and a manufacturing method thereof to overcome the above technical problems existing in the existing related art.
[0006] To this end, the specific technical solutions adopted in the present invention are as follows:
[0007] According to one aspect of the present invention, a method for preparing a vertical multi-time programmable memory device is provided, the method comprising:
[0008] Performing first conductivity type ion implantation on intrinsic semiconductor silicon to form a drain region, a buffer region, and a source region, and repairing crystal damage caused by the ion implantation process through a high-temperature annealing process;
[0009] Based on the mask, an etching stop area is set through a photolithography step, and etching is performed based on the etching stop area to obtain a first groove and a second groove;
[0010] Performing wet oxidation on the surface of the source region to form an oxide layer, and depositing and filling polysilicon in the second groove on the front surface of the device to form a floating gate region, washing away the oxide layer on the surface of the wafer, and depositing a barrier layer metal in the first groove;
[0011] An insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer to form a control gate. The barrier layer metal is etched through a mask and electroplated to form a source electrode. A drain electrode is formed on the back of the device through a post-processing process.
[0012] Furthermore, implanting first conductive type ions into the intrinsic semiconductor silicon to form a drain region, a buffer region, and a source region, and repairing crystal damage caused by the ion implantation process through a high-temperature annealing process includes:
[0013] Performing ion implantation of the first conductivity type on the back surface of the intrinsic semiconductor silicon to form a drain region, and after the drain region implantation is completed, performing an annealing process to repair crystal damage caused by the ion implantation process;
[0014] On the front surface of the intrinsic semiconductor silicon, a thin film of the first conductivity type is pre-deposited and pushed into the interior of the intrinsic semiconductor silicon to form a buffer zone;
[0015] Based on the buffer zone, ions of the first conductivity type are implanted into the intrinsic semiconductor silicon to form a source region. After the implantation is completed, a high-temperature annealing process is performed to repair the crystal damage caused during the ion implantation process.
[0016] Furthermore, the implantation depth of the drain region is less than the doping depth of the intrinsic semiconductor silicon; and the implantation depth of the source region is less than the doping depth of the buffer region.
[0017] Furthermore, based on the mask, an etching stop region is set through a photolithography step, and etching is performed based on the etching stop region to obtain the first groove and the second groove, including:
[0018] On the front surface of the source region, based on a mask, a mask pattern is transferred to a photosensitive photoresist material through a photolithography step, and a position without a photoresist opening is etched downward to obtain a first groove, and the photoresist is removed;
[0019] Based on the mask on the positive surface of the source area, the mask pattern is transferred to the photosensitive photoresist material through a photolithography step, and the position without the photoresist opening is etched downward to obtain a second groove, and the photoresist is removed.
[0020] Furthermore, the depth of the first groove reaches the bottom of the buffer region; the depth of the second groove reaches the bottom of the source region.
[0021] Further, wet oxidation is performed on the surface of the source region to form an oxide layer, and polysilicon is deposited and filled in the second groove on the front surface of the device to form a floating gate region, the oxide layer on the surface of the wafer is washed away, and a barrier layer metal is deposited in the first groove to form the barrier layer metal.
[0022] Performing wet oxidation on the surface of the source region to form an oxide layer, and depositing and filling polysilicon in the second groove on the front surface of the device based on a mask to form a floating gate region;
[0023] The oxide layer on the surface of the wafer is washed away, and based on the mask, a material is deposited in the first groove and reacts with the semiconductor silicon to form a barrier layer metal.
[0024] Furthermore, an insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer to form a control gate. The barrier layer metal is etched through a mask and metal is electroplated to form a source electrode. A drain electrode is formed on the back of the device through a post-processing process, including:
[0025] An insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer;
[0026] Based on the mask, the mask pattern is transferred to the photosensitive photoresist material through the photolithography step, the excess part of the deposited metal polysilicon is etched away at the position without the photoresist opening, and the surface photoresist is removed to form the control gate;
[0027] The insulating layer on the barrier metal is etched away through a mask, and metal is electroplated on the exposed barrier metal surface to form a source electrode. A drain electrode is formed on the back of the device through a post-processing process.
[0028] According to another aspect of the present invention, a vertical multi-time programmable memory device is provided, which includes intrinsic semiconductor silicon, a drain region is provided at the bottom of the intrinsic semiconductor silicon, and a drain electrode is provided at the bottom of the drain region; a buffer region is provided at the top of the intrinsic semiconductor silicon, and a source region is provided at the top of the buffer region; first grooves are symmetrically opened at the top of the source region, a second groove is provided between two groups of first grooves, a barrier layer metal is provided inside the first groove, a source electrode is provided at the top of the first groove, an oxide layer is provided inside the second groove, and a floating gate region is provided inside the oxide layer; an insulating layer is provided at the top of the source region and the top of the second groove, and a control gate is provided in the middle of the top of the insulating layer.
[0029] The beneficial effects of the present invention are:
[0030] The present invention surrounds the channel of the device by controlling the gate. Compared with traditional multi-time programmable memory devices, only very small gate voltage and source voltage need to be applied to achieve carrier tunneling into the floating gate region, avoiding the increasing number of traps in the oxide layer under the control gate under high voltage, which eventually leads to a short circuit between the control gate and the channel and device failure. Only a very small gate voltage needs to be applied to achieve channel conduction and a large conduction current. At the same time, the present invention adopts a vertical memory cell structure, which reduces the area of the memory cell compared to the existing memory cell structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0032] Figure 1 1 is a flow chart of a method for preparing a vertical multi-time programmable memory device according to an embodiment of the present invention;
[0033] Figure 2 This is a schematic diagram of the structure of a traditional multi-time programmable device;
[0034] Figure 3 2 is a schematic structural diagram of an intrinsic semiconductor silicon and a drain region in a vertical multi-time programmable memory device according to an embodiment of the present invention;
[0035] Figure 4 yes Figure 3 A cross-sectional view cut downward along the dotted line ab;
[0036] Figure 5 1 is a schematic structural diagram of an intrinsic semiconductor silicon, a drain region, a buffer region and a source region in a vertical multi-time programmable memory device according to an embodiment of the present invention;
[0037] Figure 6 yes Figure 5 A cross-sectional view cut downward along the dotted line ab;
[0038] Figure 7 1 is a cross-sectional view taken downward along dotted line ab of an intrinsic semiconductor silicon, a drain region, a buffer region, a source region, a first groove, and a second groove in a vertical multi-time programmable memory device according to an embodiment of the present invention;
[0039] Figure 8 yes Figure 7 Example image viewed from the top;
[0040] Figure 92 is a schematic structural diagram of an oxide layer formed by wet oxidation in a vertical multi-time programmable memory device according to an embodiment of the present invention;
[0041] Figure 10 yes Figure 9 Example image viewed from the top;
[0042] Figure 11 is one of the cross-sectional views of a local structure of a vertical multi-time programmable memory device according to an embodiment of the present invention, cut downward along the dotted line ab;
[0043] Figure 12 yes Figure 11 Example image viewed from the top;
[0044] Figure 13 FIG2 is a second cross-sectional view of a partial structure of a vertical multi-time programmable memory device according to an embodiment of the present invention, cut downward along the dotted line ab;
[0045] Figure 14 yes Figure 13 Example image viewed from the top;
[0046] Figure 15 FIG3 is a third cross-sectional view of a partial structure of a vertical multi-time programmable memory device cut downward along dotted line ab according to an embodiment of the present invention;
[0047] Figure 16 yes Figure 15 Example image viewed from the top.
[0048] In the picture:
[0049] 100. Intrinsic semiconductor silicon; 101. Drain region; 102. Buffer region; 103. Source region; 104. First groove; 105. Second groove; 106. Oxide layer; 107. Floating gate region; 108. Barrier metal layer; 109. Insulation layer; 110. Control gate; 111. Source; 112. Drain; 201. Conventional oxide layer; 202. Epitaxial layer; 203. Substrate. DETAILED DESCRIPTION
[0050] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention. They are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. By referring to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0051] According to an embodiment of the present invention, a vertical multi-time programmable memory device and a method for manufacturing the same are provided.
[0052] The present invention will now be further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to an embodiment of the present invention, a method for preparing a vertical multi-time programmable memory device includes:
[0053] S1. Performing first conductivity type ion implantation on intrinsic semiconductor silicon to form a drain region, a buffer region, and a source region, and repairing crystal damage caused during the ion implantation process through a high-temperature annealing process.
[0054] Specifically, performing first conductivity type ion implantation on intrinsic semiconductor silicon to form a drain region, a buffer region, and a source region, and repairing crystal damage caused by the ion implantation process through a high-temperature annealing process includes:
[0055] Performing ion implantation of the first conductivity type on the back surface of the intrinsic semiconductor silicon to form a drain region, and after the drain region implantation is completed, performing an annealing process to repair crystal damage caused by the ion implantation process;
[0056] On the front surface of the intrinsic semiconductor silicon, a thin film of the first conductivity type is pre-deposited and pushed into the interior of the intrinsic semiconductor silicon to form a buffer zone;
[0057] Based on the buffer zone, ions of the first conductivity type are implanted into the intrinsic semiconductor silicon to form a source region. After the implantation is completed, a high-temperature annealing process is performed to repair the crystal damage caused during the ion implantation process.
[0058] Specifically, the implantation depth of the drain region is less than the doping depth of the intrinsic semiconductor silicon; and the implantation depth of the source region is less than the doping depth of the buffer region.
[0059] S2. Based on the mask, an etching stop area is set through a photolithography step, and etching is performed based on the etching stop area to obtain a first groove and a second groove.
[0060] Specifically, based on a mask, an etching stop region is set through a photolithography step, and etching is performed based on the etching stop region to obtain the first groove and the second groove, which includes:
[0061] On the front surface of the source region, based on a mask, a mask pattern is transferred to a photosensitive photoresist material through a photolithography step, and a position without a photoresist opening is etched downward to obtain a first groove, and the photoresist is removed;
[0062] Based on the mask on the positive surface of the source area, the mask pattern is transferred to the photosensitive photoresist material through a photolithography step, and the position without the photoresist opening is etched downward to obtain a second groove, and the photoresist is removed.
[0063] Specifically, the depth of the first groove reaches the bottom of the buffer region; the depth of the second groove reaches the bottom of the source region.
[0064] Specifically, removing the photoresist means removing unnecessary photoresist.
[0065] S3. Perform wet oxidation on the surface of the source region to form an oxide layer, and deposit and fill polysilicon in the second groove on the front surface of the device to form a floating gate region. Wash away the oxide layer on the surface of the wafer, and deposit a barrier layer metal in the first groove.
[0066] Specifically, wet oxidation is performed on the surface of the source region to form an oxide layer, and polysilicon is deposited and filled in the second groove on the front surface of the device to form a floating gate region, the oxide layer on the surface of the wafer is washed away, and a barrier layer metal is deposited in the first groove to form the barrier layer metal.
[0067] Performing wet oxidation on the surface of the source region to form an oxide layer, and depositing and filling polysilicon in the second groove on the front surface of the device based on a mask to form a floating gate region;
[0068] The oxide layer on the surface of the wafer is washed away, and based on the mask, a material is deposited in the first groove and reacts with the semiconductor silicon to form a barrier layer metal.
[0069] Specifically, the oxide layer is wet oxidized on the surface of the source region to form an oxide film; since this oxide layer is formed by wet oxidation, quality defects will be generated inside the oxide layer, creating favorable conditions for subsequent hole electrons to tunnel into the floating gate region to store charges.
[0070] Specifically, a substance is deposited in the first groove and reacts with semiconductor silicon to form a barrier metal layer. That is, a substance is deposited in the first groove and can react with semiconductor silicon to generate metal silicide to form a barrier metal layer.
[0071] S4. Deposit an insulating material film on the surface of the device to form an insulating layer, and deposit metal polysilicon on the surface of the insulating layer to form a control gate. Etch the barrier layer metal through a mask and electroplate the metal to form a source. Form a drain on the back of the device through a post-processing process.
[0072] Specifically, an insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer to form a control gate. The barrier layer metal is etched through a mask and metal is electroplated to form a source electrode. The drain electrode is formed on the back of the device through a post-processing process, including:
[0073] An insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer;
[0074] Based on the mask, the mask pattern is transferred to the photosensitive photoresist material through the photolithography step, the excess part of the deposited metal polysilicon is etched away at the position without the photoresist opening, and the surface photoresist is removed to form the control gate;
[0075] The insulating layer on the barrier metal is etched away through a mask, and metal is electroplated on the exposed barrier metal surface to form a source electrode. A drain electrode is formed on the back of the device through a post-processing process.
[0076] like Figure 3-Figure 16 As shown, according to another embodiment of the present invention, a vertical multi-time programmable memory device is provided, which includes an intrinsic semiconductor silicon 100, wherein a drain region 101 is provided at the bottom of the intrinsic semiconductor silicon 100, and a drain electrode 113 is provided at the bottom of the drain region 101; a buffer region 102 is provided at the top of the intrinsic semiconductor silicon 100, and a source region 103 is provided at the top of the buffer region 102; first grooves 104 are symmetrically opened at the top of the source region 103, a second groove 105 is provided between two groups of first grooves 104, a barrier layer metal 108 is provided inside the first groove 104, a source electrode 111 is provided at the top of the first groove 104, an oxide layer 106 is provided inside the second groove 105, and a floating gate region 107 is provided inside the oxide layer 106; an insulating layer 109 is provided at the top of the source region 103 and the top of the second groove 105, and a control gate 110 is provided in the middle of the top of the insulating layer 109.
[0077] In the prior art, such as Figure 2 The figure shows the conventional MTP storage unit structure. Figure 2 In the conventional oxide layer 201, epitaxial layer 202, substrate 203, floating gate FG stores data. When programming ( Figure 2 Path ①) Erase ( Figure 2 In path ②), in order to make the carriers in the channel enter the floating gate FG, a large voltage difference needs to be applied to the source (S) and drain (D). Usually, a voltage difference of about 4V is required. The control gate CG is applied with a voltage of at least 8V to make the carriers enter ( Figure 2 Path ①) or move out ( Figure 2 Path ②) Floating gate layer. However, this approach places high demands on the quality of the oxide layer beneath the control gate CG, requiring minimal traps and sufficient thickness. However, as the number of device programming and erasure cycles increases, the traditional oxide layer 201 beneath the control gate CG, under the influence of high electric fields, will develop more and more traps, eventually leading to a short circuit between the control gate CG and the active channel, resulting in device failure. Furthermore, because the device unit is actually composed of two transverse transistors, the memory cell still has a relatively large area.
[0078] When the first conductivity type is P-type ions, the programming state of the longitudinal multi-time programmable memory device is when a negative voltage (approximately 1V to 2V) is applied to the control gate 110 and a positive voltage (approximately 2V to 3V) is applied to the source 103M (i.e., the source 111). Due to the action of the electric fields of the two, the holes in the source region 103 will be attracted and tunneled into the floating gate region 107, and the holes in the intrinsic semiconductor silicon 100 will drift and diffuse toward the drain region 101, thereby causing the voltage of the drain 101M (i.e., the drain 112) to rise when reading; the erased state of the longitudinal multi-time programmable memory device is when a positive voltage (approximately 1V to 2V) is applied to the control gate 110 and a negative voltage (approximately 2V to 3V) is applied to the source 103M. Under the action of the electric fields of the two, the holes in the floating gate region 107 will tunnel back to the source region 103.
[0079] When the first conductivity type is N-type ions, the programming state of the longitudinal multi-time programmable memory device is when a positive voltage (about 1V~2V) is applied to the control gate 110 and a negative voltage (about 2V~3V) is applied to the source 103M. Under the action of the electric fields of the two, the electrons in the source region 103 will be attracted and tunneled into the floating gate region 107, and the electrons in the intrinsic semiconductor silicon 100 will drift and diffuse toward the drain region 101, thereby causing the voltage of the drain 101M to drop when reading; the erase state of the longitudinal multi-time programmable memory device is when a negative voltage (about 1V~2V) is applied to the control gate 110 and a positive voltage (about 2V~3V) is applied to the source 103M. Under the action of the electric fields of the two, the electrons in the floating gate region 107 will tunnel back to the source region 103.
[0080] To sum up, with the help of the above-mentioned technical solution of the present invention, the present invention surrounds the channel of the device by the control gate. Compared with the traditional multi-time programmable memory device, only a very small gate voltage and source voltage need to be applied to achieve carrier tunneling into the floating gate region, avoiding the increasing number of traps in the oxide layer under the control gate under high voltage, which eventually leads to a short circuit between the control gate and the channel and device failure. It only needs to apply a very small gate voltage to achieve channel conduction and a larger conduction current. At the same time, the present invention adopts a vertical memory cell structure, which reduces the area of the memory cell compared to the existing memory cell structure.
[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A method for preparing a vertical multi-time programmable memory device, characterized in that: The method includes: Performing first conductivity type ion implantation on intrinsic semiconductor silicon to form a drain region, a buffer region, and a source region, and repairing crystal damage caused by the ion implantation process through a high-temperature annealing process; Based on the mask, an etching stop area is set through a photolithography step, and etching is performed based on the etching stop area to obtain a first groove and a second groove; Performing wet oxidation on the surface of the source region to form an oxide layer, and depositing and filling polysilicon in the second groove on the front surface of the device to form a floating gate region, washing away the oxide layer on the surface of the wafer, and depositing a barrier layer metal in the first groove; An insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer to form a control gate. The barrier layer metal is etched through a mask and electroplated to form a source electrode. A drain electrode is formed on the back of the device through a post-processing process.
2. The method for preparing a vertical multi-time programmable memory device according to claim 1, wherein: The step of implanting first conductive type ions into the intrinsic semiconductor silicon to form a drain region, a buffer region, and a source region, and repairing crystal damage caused by the ion implantation process through a high-temperature annealing process comprises: Performing ion implantation of the first conductivity type on the back surface of the intrinsic semiconductor silicon to form a drain region, and after the drain region implantation is completed, performing an annealing process to repair crystal damage caused by the ion implantation process; On the front surface of the intrinsic semiconductor silicon, a thin film of the first conductivity type is pre-deposited and pushed into the interior of the intrinsic semiconductor silicon to form a buffer zone; Based on the buffer zone, ions of the first conductivity type are implanted into the intrinsic semiconductor silicon to form a source region. After the implantation is completed, a high-temperature annealing process is performed to repair the crystal damage caused during the ion implantation process.
3. The method for preparing a vertical multi-time programmable memory device according to claim 2, wherein: The implantation depth of the drain region is less than the doping depth of the intrinsic semiconductor silicon; and the implantation depth of the source region is less than the doping depth of the buffer region.
4. The method for preparing a vertical multi-time programmable memory device according to claim 1, wherein: The method of setting an etching stop area based on a mask through a photolithography step, and etching the first groove and the second groove based on the etching stop area includes: On the front surface of the source region, based on a mask, a mask pattern is transferred to a photosensitive photoresist material through a photolithography step, and a position without a photoresist opening is etched downward to obtain a first groove, and the photoresist is removed; Based on the mask on the positive surface of the source area, the mask pattern is transferred to the photosensitive photoresist material through a photolithography step, and the position without the photoresist opening is etched downward to obtain a second groove, and the photoresist is removed.
5. The method for preparing a vertical multi-time programmable memory device according to claim 4, wherein: The depth of the first groove reaches the bottom of the buffer region; the depth of the second groove reaches the bottom of the source region.
6. The method for preparing a vertical multi-time programmable memory device according to claim 1, wherein: The step of wet-oxidizing the surface of the source region to form an oxide layer, depositing and filling polysilicon in the second groove on the front surface of the device to form a floating gate region, washing off the oxide layer on the surface of the wafer, and depositing a barrier metal in the first groove comprises: Performing wet oxidation on the surface of the source region to form an oxide layer, and depositing and filling polysilicon in the second groove on the front surface of the device based on a mask to form a floating gate region; The oxide layer on the surface of the wafer is washed away, and based on the mask, a material is deposited in the first groove and reacts with the semiconductor silicon to form a barrier layer metal.
7. The method for preparing a vertical multi-time programmable memory device according to claim 1, wherein: The steps of depositing an insulating material film on the surface of the device to form an insulating layer, depositing metal polysilicon on the surface of the insulating layer to form a control gate, etching the barrier layer metal through a mask and electroplating metal to form a source electrode, and forming a drain electrode on the back of the device through a post-processing process include: An insulating material film is deposited on the surface of the device to form an insulating layer, and metal polysilicon is deposited on the surface of the insulating layer; Based on the mask, the mask pattern is transferred to the photosensitive photoresist material through the photolithography step, the excess part of the deposited metal polysilicon is etched away at the position without the photoresist opening, and the surface photoresist is removed to form the control gate; The insulating layer on the barrier metal is etched away through a mask, and metal is electroplated on the exposed barrier metal surface to form a source electrode. A drain electrode is formed on the back of the device through a post-processing process.
8. A vertical multi-time programmable memory device manufactured by the method for manufacturing a vertical multi-time programmable memory device according to any one of claims 1 to 7, characterized in that: The vertical multi-time programmable memory device includes intrinsic semiconductor silicon, a drain region is provided at the bottom of the intrinsic semiconductor silicon, and a drain electrode is provided at the bottom of the drain region; A buffer zone is provided on the top of the intrinsic semiconductor silicon, and an active zone is provided on the top of the buffer zone; A first groove is symmetrically provided at the top of the source region, a second groove is provided between two groups of the first grooves, a barrier metal layer is provided inside the first groove, a source electrode is provided at the top of the first groove, an oxide layer is provided inside the second groove, and a floating gate region is provided inside the oxide layer; An insulating layer is provided at the top of the source region and the top of the second groove, and a control gate is provided at the middle of the top of the insulating layer.