Vertical LED chip and preparation method thereof

Abstract

The invention relates to the technical field of photoelectron manufacturing, and particularly discloses a vertical LED chip and a preparation method thereof. The preparation method of the vertical LED chip comprises the following steps: sequentially forming an N-type semiconductor layer, a multi-quantum well layer, a P-type semiconductor layer, a current blocking layer, a P-type conductive reflecting layer, an insulating layer, an N-type conductive reflecting layer and a metal bonding layer on a patterned substrate, then bonding the patterned substrate with a conductive substrate, and removing the patterned substrate; and thinning the convex part of the N-type semiconductor layer, and performing step etching to form a passivation protection layer and a P electrode. Wherein the height of the lug boss after thinning is less than or equal to 1.5 microns, and the difference between the inclination angle of the side wall of the lug boss after thinning and the inclination angle of the side wall of the lug boss before thinning is less than or equal to 10 degrees. According to the invention, the brightness and reliability of the vertical LED chip can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic manufacturing, and in particular to a vertical LED chip and a preparation method thereof. Background Art

[0002] In recent years, vertical LED chips have become a key development direction in the semiconductor lighting industry due to their excellent heat dissipation performance and efficient light output. Compared to traditional lateral structures, vertical LED chips significantly reduce thermal resistance by distributing electrodes on both sides of the chip, thereby improving current carrying capacity and luminous efficiency, making them suitable for high-power and high-brightness applications.

[0003] In existing vertical LED chips, the N-type electrode is often fabricated directly on the N-type semiconductor layer, with the conductive substrate serving as the P-electrode. However, the high resistivity of the N-type semiconductor layer results in uneven current distribution, significantly reducing luminous brightness. Furthermore, in existing LED chips based on patterned substrates, after peeling, the N-type semiconductor layer in contact with the substrate often forms a pyramid structure. During the step etching process, different areas are etched to varying depths, often damaging other functional layers, reducing chip yield and reliability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a vertical LED chip and a preparation method thereof, which have high brightness and strong reliability.

[0005] In order to solve the above technical problems, the present invention provides a method for preparing a vertical LED chip, which comprises:

[0006] (1) sequentially forming an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on a patterned substrate, and forming a first hole exposing the N-type semiconductor layer to obtain an epitaxial wafer; wherein the N-type semiconductor layer includes a raised portion and a body portion in contact with the patterned substrate;

[0007] (2) forming a current blocking layer on the epitaxial wafer, wherein the current blocking layer covers the P-type semiconductor layer and the wall of the first hole;

[0008] (3) forming a P-type conductive reflective layer on the current blocking layer to obtain a first intermediate; wherein the P-type conductive reflective layer is electrically connected to the P-type semiconductor layer through a second hole provided on the current blocking layer;

[0009] (4) forming an insulating layer, an N-type conductive reflective layer, and a metal bonding layer in sequence on the first intermediate to obtain a second intermediate;

[0010] (5) bonding the second intermediate to a conductive substrate and removing the patterned substrate;

[0011] (6) thinning the protrusion to obtain a third intermediate; wherein the height of the protrusion after thinning is less than or equal to 1.5 μm, and the difference between the inclination angle of the side wall of the protrusion after thinning and the inclination angle of the side wall of the protrusion before thinning is less than or equal to 10°;

[0012] (7) forming a third hole exposing the current blocking layer on the third intermediate to obtain a fourth intermediate;

[0013] (8) A passivation protection layer and a P electrode are formed on the fourth intermediate to obtain a finished vertical LED chip.

[0014] As an improvement to the above technical solution, the patterned substrate is provided with a plurality of raised patterns, and the height of the raised patterns is 1 μm to 2.5 μm; and / or

[0015] The thickness of the N-type semiconductor layer is 2 μm to 5 μm, the height of the protrusion before thinning is 1 μm to 2.5 μm, and the height of the protrusion after thinning is 0.6 μm to 1.2 μm.

[0016] As an improvement of the above technical solution, step (6) includes:

[0017] (6.1) forming a first photoresist layer on one side of the N-type semiconductor layer of the third intermediate body;

[0018] (6.2) etching and thinning the first photoresist layer to expose the top of the protrusion;

[0019] (6.3) using the first gas as a reaction gas, performing dry etching to thin the protrusion and the first photoresist layer;

[0020] (6.4) removing the remaining first photoresist layer;

[0021] The thickness of the first photoresist layer before thinning is 1 μm to 2 μm greater than the height of the protrusion before thinning.

[0022] As an improvement to the above technical solution, in step (6.2), the first photoresist layer is thinned by dry etching using a second gas as a reaction gas; wherein the second gas includes O2; the process parameters of the dry etching include: an upper power of 100W to 300W, a lower power of 50W to 200W, a chamber pressure of 3mtorr to 10mtorr, and a flow rate of the second gas of 40sccm to 80sccm; and / or

[0023] In step (6.3), the first gas is selected from one or more of Cl2, BCl3, Ar, and SF6; the process parameters of dry etching include: upper power of 100W to 500W, lower power of 50W to 200W, chamber pressure of 3mtorr to 10mtorr, and flow rate of the first gas of 40sccm to 80sccm.

[0024] As an improvement of the above technical solution, in step (6.3), the first gas is a mixed gas of Cl2 and BCl3, and the volume ratio of Cl2, BCl3, and SF6 is (3~5):(2~5):(0.1~1), so that the etching rate of the first photoresist layer during dry etching: the etching rate of the protruding portion is 1:(0.8~1.2).

[0025] As an improvement of the above technical solution, in step (6.2), the second gas is a mixed gas of O2 and C4F6, and the volume ratio of O2 to C4F6 is (2-3):1.

[0026] As an improvement of the above technical solution, step (7) includes:

[0027] (7.1) forming a second photoresist layer on one side of the N-type semiconductor layer of the third intermediate body;

[0028] (7.2) etching and removing the N-type semiconductor layer, the multi-quantum well layer, and the P-type semiconductor layer in the first predetermined region to form a third hole exposing the current blocking layer; wherein the current blocking layer at the bottom of the third hole is etched and thinned, and a pyramid-like morphology is formed on the surface; the thinned thickness of the current blocking layer is ≤ 0.3 μm;

[0029] (7.3) Remove the remaining second photoresist layer.

[0030] As an improvement of the above technical solution, step (3) includes:

[0031] (3.1) etching the current blocking layer to form a second hole surrounding the first hole;

[0032] (3.2) forming a P-type conductive reflective layer and patterning the layer to expose the current blocking layer in the second predetermined area;

[0033] (3.3) forming a P-type metal extension layer to obtain a second intermediate; wherein the P-type metal extension layer covers the P-type conductive reflective layer and the current blocking layer in the second predetermined area;

[0034] Step (8) includes:

[0035] (8.1) forming a passivation protective layer on the fourth intermediate;

[0036] (8.2) removing the passivation protection layer and the current blocking layer in a third predetermined region to expose the P-type metal extension layer; the third predetermined region is located within the third hole and is disposed near an edge of the conductive substrate;

[0037] (8.3) A P-electrode is formed, wherein the P-electrode is electrically connected to the P-type metal extension layer.

[0038] As an improvement of the above technical solution, step (4) includes:

[0039] (4.1) forming an insulating layer on the first intermediate body;

[0040] (4.2) forming a fourth hole on the insulating layer on the bottom wall of the first hole to expose the N-type semiconductor layer;

[0041] (4.3) forming and patterning an N-type conductive reflective layer, wherein the N-type conductive reflective layer is electrically connected to the N-type semiconductor layer through the fourth hole; wherein a projection of the N-type conductive reflective layer on the conductive substrate at least partially overlaps with a projection of the P-type conductive reflective layer on the conductive substrate;

[0042] (4.4) A metal bonding layer is formed to obtain a second intermediate.

[0043] Correspondingly, the present invention also discloses a vertical LED chip, which is prepared by the above-mentioned method for preparing the vertical LED chip.

[0044] The implementation of the present invention has the following beneficial effects:

[0045] In one embodiment of the present invention, a method for fabricating a vertical LED chip comprises: first, current extraction from the N-type semiconductor layer is achieved through the N-type conductive reflective layer, metal bonding layer, and conductive substrate within the first hole. These layers all have low resistivity, improving the uniformity of current expansion and enhancing luminous uniformity. Second, after peeling off the patterned substrate to expose the N-type semiconductor layer, the raised portion is thinned so that the height of the raised portion after thinning is less than or equal to 1.5 μm, and the difference between the tilt angle of the sidewall of the raised portion after thinning and the tilt angle of the sidewall of the raised portion before thinning is less than or equal to 10°. This significantly reduces etching damage to the current blocking layer during subsequent step etching, improving reliability; it also maintains the light extraction function of the raised portion, ensuring high brightness of the vertical LED chip. Third, the current introduced by the P-electrode is distributed through the P-type conductive reflective layer and injected into different locations of the P-type semiconductor layer through the second hole, optimizing current distribution and improving luminous uniformity. Fourthly, by preparing an N-type conductive reflective layer and a P-type conductive reflective layer respectively to reflect the light emitted by the multi-quantum well layer, the light reflectivity is effectively improved and the brightness is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 2 is a schematic diagram of the structure of the epitaxial wafer after step S1 in one embodiment of the present invention;

[0047] Figure 2 2 is a schematic diagram of the structure of the epitaxial wafer after step S2 in one embodiment of the present invention;

[0048] Figure 3 This is a schematic structural diagram of the first intermediate obtained in step S3 in one embodiment of the present invention;

[0049] Figure 4 2 is a schematic structural diagram of the first intermediate obtained in step S33 in another embodiment of the present invention;

[0050] Figure 5 This is a schematic structural diagram of the second intermediate obtained in step S4 in one embodiment of the present invention;

[0051] Figure 6 This is a schematic structural diagram of the second intermediate after step S5 in one embodiment of the present invention;

[0052] Figure 7 1 is a schematic diagram of the principle of thinning the N-type semiconductor layer in steps S61 to S64 in one embodiment of the present invention;

[0053] Figure 8 This is a schematic structural diagram of the fourth intermediate obtained in step S7 in one embodiment of the present invention;

[0054] Figure 9 Schematic diagram of the thinning principle of the current blocking layer during the step etching process in S71 to S73 in one embodiment of the present invention;

[0055] Figure 10 3 is a schematic structural diagram of a vertical LED chip obtained in step S8 in one embodiment of the present invention. DETAILED DESCRIPTION

[0056] To make the objectives, technical solutions, and advantages of the present invention more apparent, the present invention will be described in further detail below with reference to the accompanying drawings. It is hereby stated that any directional terms such as "up," "down," "left," "right," "front," "back," "inside," and "outside" that appear or will appear herein are based solely on the accompanying drawings and are not intended to limit the present invention.

[0057] An embodiment of the present invention provides a method for preparing a vertical LED chip, comprising the following steps:

[0058] S1: forming an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer in sequence on a patterned substrate, and forming a first hole exposing the N-type semiconductor layer to obtain an epitaxial wafer;

[0059] The patterned substrate 1 is a patterned sapphire substrate, but is not limited thereto. A plurality of raised patterns are provided on the patterned substrate 1, each having a height of 0.8 μm to 3 μm, preferably 1 μm to 2.5 μm. During the subsequent growth of the N-type semiconductor layer 21, these raised patterns can form raised portions 211 on the N-type semiconductor layer 21. These raised portions 211 can improve light extraction efficiency and enhance the brightness of the vertical LED chip.

[0060] The N-type semiconductor layer 21 may be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto. Preferably, it is an N-type GaN layer. The thickness of the N-type semiconductor layer 21 is 1 μm to 5 μm, preferably 2 μm to 5 μm. When based on the patterned substrate 1, the N-type semiconductor layer 21 includes a raised portion 211 in contact with the patterned substrate 1 and a main portion 212. The height of the raised portion 211 is the same as the height of the raised pattern, which is 0.8 μm to 3 μm, preferably 1 μm to 2.5 μm.

[0061] The multi-quantum well layer 22 is, but is not limited to, an InGaN-GaN MQW layer, an InGaN-AlGaN MQW layer, or an AlGaN-AlGaN MQW layer. The p-type semiconductor layer 23 can be, but is not limited to, a p-type GaN layer, a p-type AlGaN layer, or a p-type GaAs layer. Preferably, the multi-quantum well layer 22 is an InGaN-GaN MQW layer, and the p-type semiconductor layer 23 is a p-type GaN layer.

[0062] Specifically, the N-type semiconductor layer 21, the multi-quantum well layer 22, and the P-type semiconductor layer 23 together constitute an epitaxial layer, and the thickness of the epitaxial layer is 4 μm to 8 μm. It should be noted that in some embodiments, the epitaxial layer may also include one or more of a buffer layer, an intrinsic semiconductor layer, a stress buffer layer, an electron blocking layer, and an ohmic contact layer commonly used in the art, but is not limited thereto.

[0063] Preferably, in some embodiments, after forming the N-type semiconductor layer 21, the multi-quantum well layer 22, and the P-type semiconductor layer 23, a step of forming a transparent conductive layer 25 is also included. The transparent conductive layer 25 may be an ITO layer, an IZO layer, or an AZO layer, but is not limited thereto. Preferably, the transparent conductive layer 25 is an ITO layer. The thickness of the transparent conductive layer 25 is 10 nm to 200 nm. By providing the transparent conductive layer 25, the expansion of the current can be effectively improved, so that the current flowing into the P electrode 43 is evenly distributed through the transparent conductive layer 25 and then enters the multi-quantum well layer 22, thereby improving the luminous brightness of the vertical LED chip.

[0064] Specifically, after forming the N-type semiconductor layer 21, the multi-quantum well layer 22, and the P-type semiconductor layer 23, the first hole 24 is formed by etching. Specifically, the first hole 24 can be formed by dry etching or wet etching, but is not limited thereto. Preferably, in some embodiments, the first hole 24 is formed by dry etching to optimize etching accuracy.

[0065] Specifically, see Figure 1 In some embodiments, the first hole 24 is arranged in the central area of ​​the epitaxial layer so that the subsequently formed P-type conductive reflective layer 41 and the second hole 31 are arranged around the first hole 24, thereby allowing the current injected through the P-type conductive reflective layer 41 to flow through multiple locations to the N-type conductive reflective layer 6 located in the first hole 24, thereby optimizing the current distribution and improving the luminous brightness.

[0066] S2: forming a current blocking layer on the epitaxial wafer;

[0067] Specifically, see Figure 2 The current blocking layer 3 covers the P-type semiconductor layer 23 and the walls (including the sidewalls and bottom wall) of the first hole 24. The introduction of the current blocking layer 3 further optimizes current spreading under high current density and improves the reliability of the vertical LED chip.

[0068] Specifically, the current blocking layer 3 is a SiO2 layer or an Al2O3 layer, but is not limited thereto. Preferably, it is a SiO2 layer. The thickness of the current blocking layer 3 is 0.5 μm to 1.5 μm, ensuring that it maintains an appropriate thickness after subsequent step etching, thereby improving the reliability of the vertical LED chip. However, the thickness should not be too large, as this would result in excessively high operating voltages for the vertical LED chip.

[0069] S3: forming a P-type conductive reflective layer on the current blocking layer to obtain a first intermediate;

[0070] Specifically, the P-type conductive reflective layer 41 can reflect light, so that the light emitted by the multi-quantum well layer 22 is reflected by the P-type conductive reflective layer 41 and the N-type conductive reflective layer 6 and then emitted from the N-type semiconductor layer 21 side. The P-type conductive reflective layer 41 can also play a role in guiding the current of the P electrode 43 into the P-type semiconductor layer 23. Specifically, see Figure 3 By opening the second hole 31 on the current blocking layer 3 , the P-type conductive reflective layer 41 can be electrically connected to the P-type semiconductor layer 23 .

[0071] Specifically, the P-type conductive reflective layer 41 is made of one or more of, but not limited to, Ag, Al, Ti, Ni, and TiW. Preferably, the P-type conductive reflective layer 41 has an Ag / TiW stacked structure. The thickness of the P-type conductive reflective layer 41 is 100 nm to 1000 nm, preferably 150 nm to 800 nm.

[0072] Specifically, in the finished vertical LED chip, the P-type conductive reflective layer 41 may cover the entire region corresponding to the current blocking layer 3, or may only cover the current blocking layer 3 corresponding to the N-type semiconductor layer 21. Of course, the P-type conductive reflective layer 41 in the region of the first hole 24 will be discontinuous to prevent electrical continuity between the P-type conductive reflective layer 41 and the N-type conductive reflective layer 6, thereby preventing a short circuit in the vertical LED chip.

[0073] Preferably, in some embodiments, step S3 includes:

[0074] S31: etching the current blocking layer to form a second hole arranged around the first hole;

[0075] Specifically, the current blocking layer 3 can be etched through a photolithography process to form second holes 31. The number of second holes 31 is one or more, preferably multiple. The multiple second holes 31 arranged around the first hole 24 can distribute the current, improve the current distribution uniformity, and enhance the luminous brightness.

[0076] S32: forming a P-type conductive reflective layer and patterning the layer to expose the current blocking layer in the second predetermined area;

[0077] Specifically, a photoresist layer may be formed on the current blocking layer 3 first, and then exposed and developed to form the P-type conductive reflective layer 41, which is then removed by a photoresist stripping process. Alternatively, the P-type conductive reflective layer 41 may be formed first and then patterned by a photolithography and etching process.

[0078] Specifically, after the P-type conductive reflective layer 41 is patterned, the current blocking layer 3 in the second predetermined area 200 can be exposed. The second predetermined area 200 is disposed on one side of the first hole 24.

[0079] More specifically, in the finished vertical LED chip, the inner boundary of the projection of the second predetermined area 200 onto the conductive substrate 8 corresponds to the outer boundary of the projection of the P-type semiconductor layer 23 onto the conductive substrate 8. This approach reduces metal usage and production costs while also ensuring high light reflectivity. It also reduces the area of ​​the P-electrode 43, increasing the light-emitting area and brightness.

[0080] S33: forming a P-type metal extension layer to obtain a first intermediate;

[0081] Specifically, the P-type metal extension layer 42 is a stacked structure commonly found in the art, comprising Au, Ti, Cr, Pt, Cu, and the like. Preferred structures include, but are not limited to, Ti / Pt / Au / Cr, Cr / Pt / Au / Ti, or Cr / Pt / Au / Cr. The thickness of the P-type metal extension layer 42 is between 300 nm and 2000 nm, preferably between 500 nm and 1500 nm.

[0082] Specifically, see Figure 4 The P-type metal extension layer 42 covers the P-type conductive reflective layer 41 and the current blocking layer 3 of the second preset area 200. It can mainly disperse the current and also protect the P-type metal extension layer 42 to improve the reliability of the vertical LED chip.

[0083] S4: forming an insulating layer, an N-type conductive reflective layer, and a metal bonding layer in sequence on the first intermediate to obtain a second intermediate;

[0084] Specifically, the insulating layer 5 is a SiO2 layer, an Al2O3 layer, a SiN x The insulating layer 5 may be a laminated structure composed of one or at least two of the layers, but is not limited thereto. Preferably, in some embodiments, the insulating layer 5 is a laminated structure formed by a SiO2 layer and an Al2O3 layer. The thickness of the insulating layer 5 is 500nm to 1500nm. The insulating layer 5 can insulate the N-type conductive reflective layer 6 from the P-type conductive reflective layer 41 and the P-type metal extension layer 42. Accordingly, see Figure 5 In order to better achieve the insulation function, the insulation layer 5 covers the P-type conductive reflective layer 41 and the P-type metal extension layer 42.

[0085] Specifically, the N-type conductive reflective layer 6 can reflect light. Since the P-type conductive reflective layer 41 does not completely cover the entire multi-quantum well layer 22, the N-type conductive reflective layer 6 is further introduced. In addition, the N-type conductive reflective layer 6 is electrically connected to the N-type semiconductor layer 21 through the fourth hole 51 provided on the insulating layer 5, thereby achieving electrical connection with the N-type semiconductor layer 21. Specifically, the N-type conductive reflective layer 6 is made of one or more of Ag, Al, Ti, Ni, and TiW, but is not limited thereto. Preferably, the N-type conductive reflective layer 6 is an Ag / TiW stacked structure. The thickness of the N-type conductive reflective layer 6 is 100nm to 1000nm, preferably 150nm to 800nm.

[0086] Specifically, the metal bonding layer 7 is made of one or more of Au, Sn, AuSn alloy, and NiSn alloy. Preferably, the metal bonding layer 7 is a stacked structure of Ti / Au / Sn or Ti / Ni / Sn. The thickness of the metal bonding layer 7 is 1 μm to 4 μm.

[0087] Preferably, in some embodiments, step S4 includes:

[0088] S41: forming an insulating layer on the first intermediate body;

[0089] S42: forming a fourth hole on the insulating layer on the bottom wall of the first hole to expose the N-type semiconductor layer;

[0090] Specifically, the fourth hole 51 penetrates the insulating layer 5 and the current blocking layer 3 to expose the N-type semiconductor layer 21 .

[0091] S43: forming an N-type conductive reflective layer and patterning it;

[0092] Specifically, a photoresist layer may be formed on the insulating layer 5 first, and then exposed and developed to form the N-type conductive reflective layer 6, which is then removed by a stripping process. Alternatively, the N-type conductive reflective layer 6 may be formed first and then patterned by a photolithography and etching process.

[0093] Preferably, after the N-type conductive reflective layer 6 is patterned, in the finished vertical LED chip, the projection of the N-type conductive reflective layer 6 on the conductive substrate at least partially overlaps with the projection of the P-type conductive reflective layer 41 on the conductive substrate. This further improves light reflectivity and enhances the brightness of the vertical LED chip. More preferably, the projection of the N-type conductive reflective layer 6 on the conductive substrate overlaps with the projection of the first hole 24 on the conductive substrate, or the projection of the N-type conductive reflective layer 6 on the conductive substrate is slightly larger than the projection of the first hole 24 on the conductive substrate. Furthermore, the P-type conductive reflective layer 41 at least partially covers the sidewalls of the first hole 24. Based on this embodiment, the brightness of the light can be further improved.

[0094] S44: forming a metal bonding layer to obtain a second intermediate.

[0095] S5: bonding the second intermediate to the conductive substrate and removing the patterned substrate;

[0096] Specifically, after the patterned substrate 1 is removed, the raised portion 211 of the N-type semiconductor layer 21 is exposed.

[0097] S6: thinning the raised portion to obtain a third intermediate;

[0098] Specifically, the raised portion 211 can be thinned by wet etching or dry etching so that the height of the raised portion 211 is ≤1.5μm, which greatly reduces the etching damage to the current blocking layer 3 during the subsequent step etching process and improves reliability. Preferably, the height of the raised portion 211 after thinning is 0.6μm to 1.2μm. At the same time, in order not to reduce the light extraction efficiency, the side wall inclination angle of the raised portion 211 should change by ≤10° before and after thinning, that is, the difference between the side wall inclination angle of the raised portion 211 after thinning and the side wall inclination angle of the raised portion 211 before thinning is ≤10°, more preferably 1° to 5°.

[0099] Preferably, in some embodiments, step S6 includes:

[0100] S61: forming a first photoresist layer on one side of the N-type semiconductor layer of the third intermediate body;

[0101] Specifically, a photoresist may be spin-coated on the N-type semiconductor layer 21 and then baked and cured to form the first photoresist layer 400. The viscosity of the photoresist is less than 100 cP. Figure 7 b. The thickness of the first photoresist layer 400 is 1 μm to 2 μm greater than the height of the protrusion 211 before thinning, so as to ensure etching uniformity and high yield.

[0102] S62: etching and thinning the first photoresist layer to expose the top of the protrusion;

[0103] Specifically, the first photoresist layer 400 can be thinned by wet etching or dry etching, but is not limited thereto. Preferably, in some embodiments, the first photoresist layer 400 is thinned by dry etching using the second gas as the reaction gas; this process ensures that the N-type GaN layer is not damaged while thinning the first photoresist. Specifically, the dry etching process parameters include: an upper power of 100W to 300W, a lower power of 50W to 200W, a chamber pressure of 3mtorr to 10mtorr, and a second gas flow rate of 40sccm to 80sccm.

[0104] Specifically, the second gas includes O2. More specifically, the second gas is a mixed gas of O2 and C4F6, and the volume ratio of O2 to C4F6 is (2-3):1. The surface of the first photoresist layer 400 obtained by the etching gas after thinning is relatively rough. When the protrusion 211 and the first photoresist layer 400 are etched at the same time in the later stage, the side wall of the protrusion 211 can also be etched to varying degrees, thereby increasing the roughening rate and further improving the light extraction efficiency.

[0105] S63: using the first gas as a reaction gas, dry etching to thin the protrusion and simultaneously thin the first photoresist layer;

[0106] Specifically, the process parameters of the dry etching include: upper power of 100W to 500W, lower power of 50W to 200W, chamber pressure of 3mtorr to 10mtorr, and flow rate of the first gas of 40sccm to 80sccm.

[0107] Specifically, see Figure 7 c. During the dry etching process, not only the protruding portion 211 is etched and thinned, but also the first photoresist layer 400 around it is thinned.

[0108] Specifically, the first gas is selected from one or more of Cl2, BCl3, Ar, and SF6, but is not limited thereto. Preferably, in some embodiments, the first gas is a mixture of Cl2 and BCl3, and the volume ratio of Cl2, BCl3, and SF6 is (3-5):(2-5):(0.1-1), so that the etching rate of the first photoresist layer 400 during the dry etching process is 1:(0.8-1.2). This ensures that the protrusion 211 will not be flattened while being thinned, thereby ensuring that the light extraction efficiency is not reduced.

[0109] S64: removing the remaining first photoresist layer;

[0110] S7: forming a third hole exposing the current blocking layer on the third intermediate to obtain a fourth intermediate;

[0111] Specifically, a mask layer (SiO2 layer or photoresist layer) can be first formed on the third intermediate body, and then the third hole 26 can be formed by photolithography and etching, that is, by step etching. Because the protrusion 211 is thinned in this technical solution, the current blocking layer 3 is etched less during the step etching process, and the thinned thickness is ≤0.3μm.

[0112] Preferably, in some embodiments, step S7 includes:

[0113] S71: forming a second photoresist layer on one side of the N-type semiconductor layer of the third intermediate body;

[0114] S72: etching and removing the N-type semiconductor layer, the multi-quantum well layer, and the P-type semiconductor layer in the first predetermined region to form a third hole exposing the current blocking layer;

[0115] Specifically, see Figure 8 The third hole 26 is formed on one side of the first hole 24 and can be used to form the P electrode 43 later.

[0116] Specifically, see Figure 9In the process of forming the third hole 26, the current blocking layer 3 at the bottom will inevitably be etched to form a pyramid-like morphology. This technical solution can control the thinning thickness to less than 0.3μm, effectively improving the reliability of the vertical LED chip.

[0117] More preferably, in some embodiments, the N-type semiconductor layer 21, multi-quantum well layer 22, and P-type semiconductor layer 23 above the first predetermined region 100 are removed to form a third hole 26; the first predetermined region 100 includes the second predetermined region 200. Based on this embodiment, the amount of Ag used in the P-type conductive reflective layer can be reduced, thereby lowering production costs.

[0118] S73: removing the remaining second photoresist layer.

[0119] S8: forming a passivation protection layer and a P electrode on the fourth intermediate.

[0120] The passivation protection layer 9 covers the hole wall (side wall + bottom wall) of the third hole 26, and also covers the N-type semiconductor layer 21 and the side wall of the epitaxial layer formed by step etching. The passivation protection layer 9 can effectively passivate the dangling bonds, reduce leakage, improve the luminous efficiency of the vertical LED chip, and improve reliability. Specifically, the passivation protection layer 9 can be a SiO2 layer, an Al2O3 layer, a SiN x Preferably, in some embodiments, the passivation protection layer 9 is a SiO2 layer with a thickness of 60 nm to 500 nm.

[0121] Specifically, P-electrode 43 is a metal stack structure commonly found in the art, such as a stack structure composed of Au, Ti, Cr, Pt, Cu, etc. Preferably, it can be a Pt layer or an Au layer. P-electrode 43 has a thickness of 500 nm to 1500 nm. P-electrode 43 is electrically connected to the P-type reflective layer. Preferably, P-electrode 43 is electrically connected to P-type metal extension layer 42.

[0122] Preferably, in some embodiments, step S8 includes:

[0123] S81: forming a passivation protective layer on the fourth intermediate;

[0124] S82: removing the passivation protection layer and the current blocking layer in the third preset area to expose the P-type metal extension layer;

[0125] Specifically, the third predetermined area is located in the third hole and is disposed close to the edge of the conductive substrate.

[0126] S83: forming a P electrode.

[0127] In summary, the fabrication method of the vertical LED chip according to the present invention, firstly, utilizes the N-type conductive reflective layer 6, metal bonding layer 7, and conductive substrate 8 within the first hole 24 to jointly extract current from the N-type semiconductor layer 21. These layers all have low resistivity, improving the uniformity of current spreading and thus the uniformity of light emission. Secondly, after peeling off the patterned substrate 1 to expose the N-type semiconductor layer 21, the raised portion 211 is thinned, such that the height of the raised portion 211 after thinning is less than or equal to 1.5 μm, and the difference between the tilt angle of the sidewalls of the raised portion 211 after thinning and the tilt angle of the sidewalls of the raised portion 211 before thinning is less than or equal to 10°. This significantly reduces etching damage to the current blocking layer 3 during subsequent step etching, thereby optimizing reliability. Furthermore, the light extraction function of the raised portion 211 is maintained, ensuring the high brightness of the vertical LED chip. Third, the current introduced by the P-electrode 43 is distributed through the P-type conductive reflective layer 41 and injected into different locations of the P-type semiconductor layer 23 through the second hole 31, optimizing the current distribution and improving the uniformity of light emission. Fourth, by forming the N-type conductive reflective layer 6 and the P-type conductive reflective layer 41 separately to reflect the light emitted by the multi-quantum well layer 22, the light reflectivity is effectively improved, thereby enhancing the brightness.

[0128] Specifically, based on the preparation method of this application, the height of the protrusion 211 and the sidewall inclination angle were controlled to vary, and a vertical LED chip with a size of 1235 μm × 1060 μm was prepared. The chip brightness and operating voltage were tested at 350 mA. The specific experimental results are shown in the following table:

[0129]

[0130] As can be seen from the table, by changing the inclination angle of the sidewall of the protrusion before and after thinning, and controlling the height of the protrusion after thinning, the etching loss of the current blocking layer can be effectively reduced, the brightness can be increased, and the reliability of the vertical LED chip can be improved.

[0131] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a vertical LED chip, characterized in that: include: (1) sequentially forming an N-type semiconductor layer, a multi-quantum well layer, and a P-type semiconductor layer on a patterned substrate, and forming a first hole exposing the N-type semiconductor layer to obtain an epitaxial wafer; wherein the N-type semiconductor layer includes a raised portion and a body portion in contact with the patterned substrate; (2) forming a current blocking layer on the epitaxial wafer, wherein the current blocking layer covers the P-type semiconductor layer and the wall of the first hole; (3) forming a P-type conductive reflective layer on the current blocking layer to obtain a first intermediate; wherein the P-type conductive reflective layer is electrically connected to the P-type semiconductor layer through a second hole provided on the current blocking layer; (4) forming an insulating layer, an N-type conductive reflective layer, and a metal bonding layer in sequence on the first intermediate to obtain a second intermediate; (5) bonding the second intermediate to a conductive substrate and removing the patterned substrate; (6) thinning the protrusion to obtain a third intermediate; wherein the height of the protrusion after thinning is less than or equal to 1.5 μm, and the difference between the inclination angle of the side wall of the protrusion after thinning and the inclination angle of the side wall of the protrusion before thinning is less than or equal to 10°; (7) forming a third hole exposing the current blocking layer on the third intermediate to obtain a fourth intermediate; (8) A passivation protection layer and a P electrode are formed on the fourth intermediate to obtain a finished vertical LED chip.

2. The method for preparing a vertical LED chip according to claim 1, wherein: The patterned substrate is provided with a plurality of protruding patterns, and the height of the protruding patterns is 1 μm to 2.5 μm; and / or The thickness of the N-type semiconductor layer is 2 μm to 5 μm, the height of the protrusion before thinning is 1 μm to 2.5 μm, and the height of the protrusion after thinning is 0.6 μm to 1.2 μm.

3. The method for preparing a vertical LED chip according to claim 1, wherein: Step (6) includes: (6.1) forming a first photoresist layer on one side of the N-type semiconductor layer of the third intermediate body; (6.2) etching and thinning the first photoresist layer to expose the top of the protrusion; (6.3) using the first gas as a reaction gas, performing dry etching to thin the protrusion and the first photoresist layer; (6.4) removing the remaining first photoresist layer; The thickness of the first photoresist layer before thinning is 1 μm to 2 μm greater than the height of the protrusion before thinning.

4. The method for preparing a vertical LED chip according to claim 3, wherein: In step (6.2), the first photoresist layer is thinned by dry etching using a second gas as a reaction gas; wherein the second gas includes O2; the process parameters of the dry etching include: an upper power of 100W to 300W, a lower power of 50W to 200W, a chamber pressure of 3mtorr to 10mtorr, and a flow rate of the second gas of 40sccm to 80sccm; and / or In step (6.3), the first gas is selected from one or more of Cl2, BCl3, Ar, and SF6; the process parameters of dry etching include: upper power of 100W to 500W, lower power of 50W to 200W, chamber pressure of 3mtorr to 10mtorr, and flow rate of the first gas of 40sccm to 80sccm.

5. The method for preparing a vertical LED chip according to claim 3, wherein: In step (6.3), the first gas is a mixed gas of Cl2 and BCl3, and the volume ratio of Cl2, BCl3, and SF6 is (3~5):(2~5):(0.1~1), so that the etching rate of the first photoresist layer during dry etching: the etching rate of the protruding portion is 1:(0.8~1.2).

6. The method for preparing a vertical LED chip according to claim 4, wherein: In step (6.2), the second gas is a mixed gas of O2 and C4F6, and the volume ratio of O2 to C4F6 is (2-3):

1.

7. The method for preparing a vertical LED chip according to claim 1, wherein: Step (7) includes: (7.1) forming a second photoresist layer on one side of the N-type semiconductor layer of the third intermediate body; (7.2) etching and removing the N-type semiconductor layer, the multi-quantum well layer, and the P-type semiconductor layer in the first predetermined region to form a third hole exposing the current blocking layer; wherein the current blocking layer at the bottom of the third hole is etched and thinned, and a pyramid-like morphology is formed on the surface; the thinned thickness of the current blocking layer is ≤ 0.3 μm; (7.3) Remove the remaining second photoresist layer.

8. The method for preparing a vertical LED chip according to claim 1, wherein: Step (3) includes: (3.1) etching the current blocking layer to form a second hole surrounding the first hole; (3.2) forming a P-type conductive reflective layer and patterning the layer to expose the current blocking layer in the second predetermined area; (3.3) forming a P-type metal extension layer to obtain a second intermediate; wherein the P-type metal extension layer covers the P-type conductive reflective layer and the current blocking layer in the second predetermined area; Step (8) includes: (8.1) forming a passivation protective layer on the fourth intermediate; (8.2) removing the passivation protection layer and the current blocking layer in a third predetermined region to expose the P-type metal extension layer; the third predetermined region is located within the third hole and is disposed near an edge of the conductive substrate; (8.3) A P-electrode is formed, wherein the P-electrode is electrically connected to the P-type metal extension layer.

9. The method for preparing a vertical LED chip according to claim 1, wherein: Step (4) includes: (4.1) forming an insulating layer on the first intermediate body; (4.2) forming a fourth hole on the insulating layer on the bottom wall of the first hole to expose the N-type semiconductor layer; (4.3) forming and patterning an N-type conductive reflective layer, wherein the N-type conductive reflective layer is electrically connected to the N-type semiconductor layer through the fourth hole; wherein a projection of the N-type conductive reflective layer on the conductive substrate at least partially overlaps with a projection of the P-type conductive reflective layer on the conductive substrate; (4.4) A metal bonding layer is formed to obtain a second intermediate.

10. A vertical LED chip, characterized in that: The vertical LED chip is prepared by the preparation method of any one of claims 1 to 9.

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