Method for manufacturing printed circuit board

Abstract

The present invention provides a method for manufacturing a printed wiring board which can more effectively suppress pattern defects and has excellent high-frequency characteristics. The manufacturing method of the printed circuit board comprises the following steps: preparing an insulating base material with a rough surface; the method comprises the following steps of: performing chemical plating on the rough surface of the insulating base material to form a chemical plating layer which has a surface with a peak top density (Sds) of 0.90 [mu] m <-2 > to 1.30 [mu] m <-2 > and a peak top curvature (Ssc) of 1.00 [mu] m <-1 > to 4.00 [mu] m <-1 >, and the thickness of the chemical plating layer is 1.0 [mu] m or less; laminating a photoresist on the surface of the electroless plating layer; exposing and developing the photoresist to form a photoresist pattern; electroplating the electroless plating layer by means of a resist pattern; stripping the resist pattern; and removing, by etching, a useless portion of the electroless plating layer exposed due to the peeling of the resist pattern to form a wiring pattern.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a printed circuit board. Background Art

[0002] In recent years, with the demand for miniaturization and high density of printed circuit boards, the miniaturization (fine pitch) of circuits has been sought. As a method for manufacturing printed circuit boards suitable for miniaturization of circuits, the semi-additive process (SAP process) is widely used. The SAP process is a method suitable for forming extremely fine circuits. As an example, the SAP process is performed using a roughened copper foil with a carrier. For example, Figure 8 and Figure 9 As shown, the roughened copper foil 110 is stamped using a prepreg 112 and a primer layer 113 so that it is tightly adhered to an insulating resin substrate 111 having a lower circuit 111b on a bottom substrate 111a (process (a)). After peeling off the carrier (not shown), a via 114 is formed by laser perforation as needed (process (b)). Next, the roughened copper foil 110 is removed by etching to expose the primer layer 113 with a roughened surface profile (process (c)). After applying chemical copper plating 115 to the roughened surface (process (d)), it is masked in a predetermined pattern by exposure and development using a dry film 116 (process (e)), and electroplated copper 117 is applied (process (f)). After the dry film 116 is removed to form the wiring portion 117a (step (g)), the unnecessary chemically plated copper 115 between adjacent wiring portions 117a and the wiring portions 117a is removed by etching (step (h)), thereby obtaining wiring 118 formed in a predetermined pattern.

[0003] In the SAP method using a roughened copper foil like this, the roughened copper foil itself is removed by etching after laser perforation (process (c)). In addition, the surface of the laminate from which the roughened copper foil has been removed is transferred with the concave-convex shape of the roughened surface of the roughened copper foil, so that the adhesion between the insulating layer (for example, the primer layer 113, or the prepreg 112 in the absence of the primer layer 113) and the electroplated circuit (for example, wiring 118) can be ensured in subsequent processes. However, the surface profile suitable for improving the adhesion with the electroplated circuit basically has a tendency to become rough concave-convex, and therefore, the etching property relative to chemical copper plating is easily reduced in process (h). That is, in order to eliminate residual copper, it is necessary to etch more for the rough concave-convex part of the chemical copper plating.

[0004] Therefore, a method has been proposed in which the roughened particles are reduced in size and have a necked shape, thereby achieving good etching properties while ensuring the required adhesion of the plated circuit when used in the SAP method. For example, in Patent Document 1 (International Publication No. 2016 / 158775), a roughened copper foil is disclosed: having a roughened surface on at least one side, the roughened surface having a plurality of roughly spherical protrusions composed of copper particles, and the average height of the roughly spherical protrusions is 2.60 μm or less. In addition, in Patent Document 2 (International Publication No. 2018 / 211951), a roughened copper foil is disclosed: having a roughened surface on at least one side, the roughened surface having primary roughened particles with a necked portion and secondary roughened particles on the surface of the primary roughened particles, and the ten-point average roughness Rz of the roughened surface is low roughness of less than 1.7 μm.

[0005] In addition, in order to make the circuit more miniaturized, in the SAP method, it is possible to consider using a copper foil with a smooth surface and very small roughening particles, and to perform chemical plating relatively thinly to form the circuit. However, in the circuit formed in this way, problems such as short circuits and poor patterns such as convex portions will occur. A method for manufacturing a printed circuit board to address this problem is proposed. For example, in patent document 3 (International Publication No. 2020 / 196105), a method for manufacturing a printed circuit board including such a process is disclosed: chemical plating is performed on an insulating substrate having a rough surface to form a chemical plating layer having a thickness of less than 1.0 μm, the chemical plating layer having an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less and a surface with a kurtosis Sku of 2.0 or more and 3.5 or less. In addition, Patent Document 4 (International Publication No. 2020 / 196106) discloses that an electroless plating layer is formed, wherein the electroless plating layer has an arithmetic mean waviness Wa of 0.10 μm or more and 0.25 μm or less and a valley void volume Vvv of 0.010 μm. 3 / μm 2 Above and 0.028μm 3 / μm 2 According to the methods disclosed in Patent Documents 3 and 4, it is possible to manufacture a printed wiring board that effectively suppresses pattern defects and has excellent fine circuit formability.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: International Publication No. 2016 / 158775

[0009] Patent Document 2: International Publication No. 2018 / 211951

[0010] Patent Document 3: International Publication No. 2020 / 196105

[0011] Patent Document 4: International Publication No. 2020 / 196106 Summary of the Invention

[0012] When manufacturing printed circuit boards using the methods disclosed in Patent Documents 3 and 4, the problem of pattern defects can be solved to a certain extent. However, it is desirable to further suppress pattern defects. In addition, with the recent advancement in the performance of portable electronic devices and the like, the development of higher-frequency signals is underway to process large amounts of information at high speeds, and there is a need for printed circuit boards suitable for high-frequency applications such as 5G, millimeter waves, and base station antennas. However, achieving both suppression of pattern defects and good high-frequency characteristics is not easy.

[0013] The inventors of the present invention have discovered that by performing electroless plating on an insulating substrate having a rough surface, forming an electroless plating layer having a surface in which the peak density Sds and peak curvature Ssc are controlled within predetermined ranges, it is possible to manufacture a printed wiring board that more effectively suppresses pattern defects and exhibits excellent high-frequency characteristics.

[0014] Therefore, an object of the present invention is to provide a method for manufacturing a printed wiring board that can more effectively suppress pattern defects and has excellent high-frequency characteristics.

[0015] According to the present invention, the following technical solutions are provided.

[0016] [Technical Solution 1]

[0017] A method for manufacturing a printed circuit board, wherein:

[0018] The manufacturing method includes the following steps:

[0019] (a) Preparing an insulating substrate having a rough surface;

[0020] (b) performing chemical plating on the rough surface of the insulating substrate to form a chemical plating layer, wherein the chemical plating layer has a peak density Sds of 0.90 μm measured in accordance with EUR15178N －2 Above and 1.30μm －2 The peak curvature Ssc measured in accordance with EUR15178N is 1.00 μm. －1 Above and 4.00μm －1 The thickness of the chemical plating layer is less than 1.0 μm;

[0021] (c) laminating a photoresist on the surface of the chemically plated layer;

[0022] (d) exposing and developing the photoresist to form a resist pattern;

[0023] (e) electroplating the chemical plating layer with the aid of the resist pattern;

[0024] (f) stripping the resist pattern; and

[0025] (g) The unnecessary portion of the electroless plating layer exposed by the peeling of the resist pattern is removed by etching to form a wiring pattern.

[0026] [Technical Solution 2]

[0027] According to the method for manufacturing a printed circuit board according to technical solution 1,

[0028] The surface of the electroless plating layer has an interface developed area ratio Sdr measured in accordance with EUR15178N of 5.00% or more and 10.00% or less.

[0029] [Technical Solution 3]

[0030] The method for manufacturing a printed circuit board according to technical solution 1 or 2, wherein:

[0031] The peak curvature Ssc of the surface of the chemical plating layer is 2.30 μm －1 Above and 3.50μm －1 the following.

[0032] [Technical Solution 4]

[0033] The method for manufacturing a printed circuit board according to any one of technical solutions 1 to 3, wherein:

[0034] The process (a) comprises the following steps:

[0035] (a-1) A surface-treated copper foil having a peak top density Sds of 1.00 μm measured in accordance with EUR15178N was prepared. －2 Above and 1.50μm －2 The following peak curvature Ssc measured in accordance with EUR15178N is 4.00 μm －1 Above and 6.00μm －1 The treated surface has an interface development area ratio Sdr of 20.00% or more and 40.00% or less measured in accordance with EUR15178N,

[0036] (a-2) after laminating an insulating base material on the treated surface of the surface-treated copper foil and transferring the surface shape of the treated surface to the surface of the insulating base material,

[0037] (a-3) The surface-treated copper foil is removed by etching to obtain an insulating base material having the rough surface.

[0038] [Technical Solution 5]

[0039] The method for manufacturing a printed circuit board according to any one of technical solutions 1 to 4, wherein:

[0040] The thickness of the chemical plating layer is greater than or equal to 0.3 μm and less than or equal to 1.0 μm.

[0041] [Technical Solution 6]

[0042] The method for manufacturing a printed circuit board according to any one of technical solutions 1 to 5, wherein:

[0043] The photoresist includes a dry film resist.

[0044] [Technical Solution 7]

[0045] According to the method for manufacturing a printed circuit board according to technical solution 6,

[0046] The dry film resist has a thickness of 2 μm or more and 35 μm or less.

[0047] [Technical Solution 8]

[0048] The method for manufacturing a printed circuit board according to any one of technical solutions 1 to 7, wherein:

[0049] The wiring pattern has a thickness of 2 μm or more and 30 μm or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 This is a process flow chart showing the first half of the steps (steps (a) to (c)) in one example of the production method of the present invention.

[0051] Figure 2 This is a process flow chart showing the latter half of the steps (steps (d) to (g)) in one example of the production method of the present invention.

[0052] Figure 3 This is a process flow chart showing an example of steps for preparing an insulating substrate having a rough surface.

[0053] Figure 4 These are diagrams for explaining the influence of surface foreign matter during exposure and development when the surface after electroless plating does not have a sufficient concavo-convex shape.

[0054] Figure 5 These are diagrams for explaining the influence of surface foreign matter during exposure and development when the surface after electroless plating has sufficient unevenness.

[0055] Figure 6 This is a diagram for explaining the procedure of evaluating the number of dust detections in the embodiment.

[0056] Figure 7A This is a diagram for explaining the peak density Sds measured in accordance with EUR15178N, showing Sds = 5 μm －2 FIG. 1 is a diagram showing an example of the surface and peak of a case.

[0057] Figure 7B This is a diagram for explaining the peak density Sds measured in accordance with EUR15178N, and shows Sds = 1 μm －2 FIG. 1 is a diagram showing an example of the surface and peak of a case.

[0058] Figure 8 This is a process flow chart for explaining the SAP method, and is a diagram showing the first half of the processes (process (a) to process (d)).

[0059] Figure 9 This is a process flow chart for explaining the SAP method, and is a diagram showing the latter half of the process (process (e) to process (h)). DETAILED DESCRIPTION

[0060] definition

[0061] Definitions of parameters used to define the present invention are shown below.

[0062] In this specification, "peak top density Sds" or "Sds" refers to a parameter indicating the number of peak tops per unit area measured in accordance with EUR15178N. Figure 7A and 7B As shown in the calculation of Sds, the point higher than the 8 adjacent points N is regarded as the peak S. The larger the value, the denser the protrusions are (refer to Figure 7A On the other hand, the smaller the value, the more sparse the protrusions are (see Figure 7B ).

[0063] In this specification, "peak curvature Ssc" or "Ssc" refers to a parameter that represents the average of the principal curvatures of the peak apex of a surface, measured in accordance with EUR15178N. The smaller the value, the more rounded the point of contact with another object. On the other hand, the larger the value, the sharper the point of contact with another object. In addition, while the parameters specified in ISO25178 only consider the significant peaks remaining after identification by segmentation, the parameters specified in EUR15178N detect local peaks and significant peaks without distinction. Therefore, when the surface shape is the same, the Ssc specified in EUR15178N becomes a value larger than the Spc specified in ISO25178 (Spc < Ssc).

[0064] In this specification, "interface developed area ratio Sdr" or "Sdr" refers to a parameter that indicates how much the developed area (surface area) of a defined region has increased relative to the area of ​​the defined region, as measured in accordance with EUR15178N. In this specification, the interface developed area ratio Sdr is expressed as the increase in surface area (%). The smaller the value, the closer the surface shape is to being flat, with the Sdr of a completely flat surface being 0%. On the other hand, the larger the value, the more uneven the surface shape is. For example, if the Sdr of a surface is 10%, it means that the surface area of ​​the surface has increased by 10% compared to a completely flat surface.

[0065] Sds, Ssc, and Sdr can each be calculated by measuring the surface profile of a predetermined measurement area (e.g., a two-dimensional area of ​​64.397 μm x 64.463 μm) on the roughened surface using a commercially available laser microscope. In this specification, Sds, Ssc, and Sdr are measured without using the S and L filters for cutoff. Preferred measurement and analysis conditions for the surface profile using a laser microscope are described in the Examples below.

[0066] Method for manufacturing printed circuit board

[0067] The present invention relates to a method for manufacturing a printed circuit board. The method comprises the steps of (a) preparing an insulating substrate, (b) forming an electroless plating layer, (c) laminating a photoresist, (d) forming a resist pattern, (e) forming an electroplating layer, (f) stripping the resist pattern, and (g) forming a wiring pattern.

[0068] Below, refer to Figures 1 to 5 Steps (a) to (g) will be described separately.

[0069] (a) Preparation of insulating substrate

[0070] like Figure 1As shown in (a), an insulating substrate 20 having a rough surface 20a is prepared. The insulating substrate 20 may have rough surfaces 20a on both sides or only on one side. The insulating substrate 20 preferably contains an insulating resin. In addition, the insulating substrate 20 is preferably a prepreg and / or a resin sheet. Prepreg is a general term for composite materials formed by impregnating synthetic resins into substrates such as synthetic resin plates, glass plates, glass fabrics, glass non-woven fabrics, and paper. Preferred examples of insulating resins impregnated in prepregs include epoxy resins, cyanate resins, bismaleimide triazine resins (BT resins), polyphenylene ether resins, and phenolic resins. In addition, examples of insulating resins constituting resin sheets include insulating resins such as epoxy resins, polyimide resins, and polyester resins. From the viewpoint of improving insulation properties, the insulating substrate 20 may also contain filler particles composed of various inorganic particles such as silica and alumina. The thickness of the insulating base material 20 is not particularly limited, but is preferably 1 μm to 1000 μm, more preferably 2 μm to 400 μm, and even more preferably 3 μm to 200 μm. The insulating base material 20 may be composed of multiple layers.

[0071] The rough surface 20a of the insulating substrate 20 can be formed by various methods. Typically, it is formed by transferring the uneven shape of the treated surface of the surface-treated copper foil to the surface of the insulating substrate 20. According to a preferred embodiment of the present invention, the rough surface 20a is formed using the surface-treated copper foil by the following method: (a-1) preparing a surface-treated copper foil having a predetermined treated surface; (a-2) laminating the insulating substrate on the treated surface of the surface-treated copper foil, transferring the surface shape of the treated surface to the surface of the insulating substrate; and (a-3) removing the surface-treated copper foil by etching to obtain the insulating substrate having a rough surface. The specific steps of each process are as follows.

[0072] (a-1) Preparation of surface-treated copper foil

[0073] like Figure 3As shown in (a-1), a surface-treated copper foil 10 having a treated surface 10a on at least one side is prepared. The treated surface 10a is a surface that has been subjected to some surface treatment, typically a roughened surface. Typically, the treated surface 10a is formed by having a plurality of protrusions (e.g., roughened particles). In either case, the surface-treated copper foil 10 may have the treated surface 10a on both sides or may have the treated surface 10a only on one side. In the case of having the treated surface 10a on both sides, when used for the SAP method, since the surface on the laser irradiation side (the surface on the side opposite to the surface in contact with the insulating substrate) is also surface-treated, the laser absorption is improved, and as a result, the laser perforation performance can also be improved. In addition, the surface-treated copper foil 10 may also be in the form of a copper foil with a carrier. In this case, typically, the copper foil with a carrier includes a carrier, a peeling layer provided on the carrier, and a surface-treated copper foil 10 provided on the peeling layer in a manner such that the treated surface 10a is on the outside. However, the copper foil with a carrier may adopt a known layer structure other than the surface-treated copper foil 10 .

[0074] The peak top density Sds of the treated surface 10a of the surface treated copper foil 10 is preferably 1.00 μm. －2 Above and 1.50μm －2 less than 1.00 μm, more preferably 1.00 μm －2 Above and 1.40μm －2 Below, more preferably 1.10 μm －2 Above and 1.40μm －2 Below, particularly preferably 1.20 μm －2 Above and 1.40μm －2 Furthermore, the peak curvature Ssc of the treated surface 10a of the surface-treated copper foil 10 is preferably 4.00 μm. －1 Above and 6.00μm －1 Below, more preferably 4.50 μm －1 Above and 6.00μm －1 Below, more preferably 4.50 μm －1 Above and 5.00μm －1Below. Furthermore, the expanded area ratio Sdr of the interface of the treated surface 10a of the surface-treated copper foil 10 is preferably 20.00% or more and 40.00% or less, and more preferably 20.00% or more and 25.00% or less. By using the surface-treated copper foil 10 having the treated surface 10a with Sds, Ssc and Sdr within the above-mentioned ranges, the insulating substrate 20 is given a concave-convex shape, thereby making it easy to form a chemical plating layer 22 having the specific surface parameters described later on the rough surface 20a of the insulating substrate 20. The treated surface 10a having the above-mentioned surface parameters can be formed by subjecting the copper foil surface to a surface treatment (typically a roughening treatment) under known or desired conditions. In addition, commercially available copper foil having a treated surface 10a that satisfies the above-mentioned various conditions can also be selectively obtained.

[0075] (a-2) Transfer of Concavo-convex Shape to Insulating Base Material

[0076] like Figure 3 As shown in (a-2), an insulating substrate 20' (i.e., an insulating substrate 20 without a rough surface 20a) is laminated on the treated surface 10a of the surface-treated copper foil 10 to form a copper-clad laminate 12. By doing so, the surface shape of the treated surface 10a can be transferred to the surface of the insulating substrate 20'. The lamination of the insulating substrate 20' is preferably accompanied by hot stamping or hot lamination, and the processing temperature and processing time of the hot stamping or hot lamination can be appropriately determined based on the type of the laminated insulating substrate 20' and based on known conditions. The preferred type of the insulating substrate 20' is as described above with respect to the insulating substrate 20. In addition, the insulating substrate 20' can also be laminated on the surface-treated copper foil 10 via a primer layer (not shown) pre-applied to the treated surface 10a of the surface-treated copper foil 10. In this case, the primer layer is regarded as a part of the insulating substrate. The primer layer is preferably composed of a resin, and the resin preferably contains an insulating resin. If desired, via holes (not shown) may be formed in the copper-clad laminate 12 by laser drilling before removing the surface-treated copper foil 10 as the next step.

[0077] (a-3) Removal of surface-treated copper foil

[0078] like Figure 3 As shown in (a-3), the surface-treated copper foil 10 of the copper-clad laminate 12 is removed by etching to obtain an insulating substrate 20 having a rough surface 20a. The etching of the surface-treated copper foil 10 can be performed using, for example, a sulfuric acid-hydrogen peroxide-based etching solution and in accordance with etching methods and conditions commonly used in the manufacture of printed circuit boards, and is not particularly limited.

[0079] (b) Formation of chemical plating layer

[0080] like Figure 1As shown in (b), the rough surface 20a of the insulating substrate 20 is electrolessly plated (e.g., electroless copper plating) to form an electroless plating layer 22 having a thickness of 1.0 μm or less. The electroless plating is performed using a commercially available electroless plating solution and in accordance with the methods and conditions commonly used in the manufacture of printed circuit boards, and is not particularly limited. The peak density Sds on the surface of the electroless plating layer 22 is 0.90 μm. －2 Above and 1.30μm －2 Below, and the peak curvature Ssc is 1.00μm －1 Above and 4.00μm －1 By performing electroless plating on the insulating substrate 20 having the rough surface 20a, an electroless plating layer 22 is formed having a surface in which the peak density Sds and the peak curvature Ssc are controlled within predetermined ranges. This allows for the manufacture of a printed wiring board that more effectively suppresses pattern defects and has excellent high-frequency characteristics.

[0081] As mentioned above, with the further miniaturization of circuits required by the SAP method in recent years, in order to achieve excellent etching properties, it is considered to use a copper foil with a smooth surface and smaller roughening particles to give a roughened surface profile to the insulating substrate. In addition, as long as the surface of the insulating substrate to which the roughened surface profile is given can be electrolessly plated thinly (for example, less than 1.0 μm), the etching amount can be reduced and the circuit can be further miniaturized, which is very convenient. However, in the SAP method, there is a problem of poor patterning: when a circuit is attempted to be formed using a copper foil with a smooth surface and smaller roughening particles and electrolessly plated thinly, a short circuit and a convex portion will occur in the formed circuit. The mechanism for the occurrence of this poor patterning is not necessarily certain, but it is speculated as follows.

[0082] That is, when a surface-treated copper foil is used to transfer the surface shape to an insulating substrate, the rough surface of the insulating substrate roughly reflects the surface profile of the surface-treated copper foil. Moreover, when chemical plating is applied to the rough surface of the insulating substrate with a thickness of 1.0 μm or less, the surface shape of the chemically plated layer roughly reflects the surface shape of the rough surface of the insulating substrate. Therefore, when a copper foil with a smooth surface and very small roughening particles (in other words, a copper foil with a finer concave-convex shape) is used as the copper foil for transferring the surface profile to the insulating substrate, it can be said that it is difficult to give the surface of the chemically plated layer a sufficient concave-convex shape. In addition, in the usual manufacturing process of printed circuit boards, in order to form a circuit in a predetermined pattern, such operations are performed: Figure 4 (i)~ Figure 4 As shown in (iv), a photoresist 24 (for example, comprising a dry film resist 24a and a support film 24b) is further laminated on the surface of the chemical plating layer 22 laminated on the insulating substrate 20, and exposure and development are performed to form a resist pattern 26. Figure 4As shown in (i), when the photoresist 24 is stacked or exposed, foreign matter F (such as dust or scratches on the photoresist surface, air drawn in when the photoresist is stacked, etc.) may adhere to or be mixed into the surface of the photoresist 24. For example, in a factory manufacturing printed circuit boards, the cleanliness of the clean room is operated at a level of about 100 to 1000, and it is difficult to completely eliminate foreign matter in the environment. In addition, it is also difficult to detect tiny scratches on the surface of the photoresist 24. In this regard, when exposing the photoresist 24 that is stacked on the chemical plating layer 22 and has not been given a sufficient concave-convex shape, as shown in FIG. Figure 4 As shown in (ii), the exposure incident light I incident from a direction perpendicular to the main surface of the laminate is directly reflected by the electroless plating layer 22 and emitted as exposure reflected light R in a direction 180° opposite to the exposure incident light I. Therefore, the portion of the photoresist 24 (for example, the dry film resist 24a) directly below the foreign matter F that should have been exposed remains unexposed (see FIG. Figure 4 (iii)) will form a hole H after development (refer to Figure 4 As a result, it is conceivable that electroplating is performed on a portion where a circuit should not be formed, and the unnecessary electroplated portion causes a short circuit or a convex portion of the circuit, resulting in a problem of pattern defect.

[0083] Furthermore, polyethylene terephthalate (PET) film is typically used as the support film 24b constituting the photoresist 24. In this case, a lubricant is added to the PET film to improve fluidity and mold release properties during heat forming. Typically, the particle size of the lubricant varies, with a certain proportion of large-sized particles (e.g., with a diameter of 10 μm or more). Therefore, the large-sized foreign matter inevitably present in such a PET film can cause areas that should have been exposed to remain unexposed, as described above, potentially resulting in pattern defects. Furthermore, while it is conceivable to perform exposure after peeling off the PET film to expose the dry film, such exposure can cause deformation of the dry film due to oxygen. In other words, the aforementioned pattern defects caused by the lubricant and the like contained in the PET film are unavoidable. In this regard, the conventional methods for manufacturing printed circuit boards disclosed in Patent Document 3 (International Publication No. 2020 / 196105) and Patent Document 4 (International Publication No. 2020 / 196106) have room for improvement in eliminating pattern defects caused by large-sized foreign matter. On the other hand, it is conceivable that the roughness of the chemical plating surface is excessively large due to the use of a surface-treated copper foil with a larger surface roughness to transfer the surface shape to the insulating substrate. However, when such a method is adopted, it will lead to a deterioration of the high-frequency characteristics. In this way, it is not easy to take into account both the suppression of pattern defects and good high-frequency characteristics.

[0084] In this regard, the method of the present invention can achieve both further suppression of pattern defects and good high-frequency characteristics. The mechanism is not necessarily certain, but it is believed to be as follows. That is, by setting the peak top density Sds on the surface of the electroless plating layer 22 to 0.90 μm －2 Above and 1.30μm －2 Below and the peak curvature Ssc is set to 1.00 μm －1 Above and 4.00μm －1 The surface of the electroless plating layer 22 has a moderate concavoconvex shape (see Figure 5 Therefore, during exposure, the exposure incident light I incident from a direction perpendicular to the main surface of the laminate is diffusely reflected on the concave and convex parts of the surface of the chemical plating layer 22 when it reaches the surface of the chemical plating layer 22 (refer to Figure 5 As a result, the exposure reflected light R can expose the portion of the photoresist 24 (eg, dry film resist 24a) directly below the foreign matter F (see Figure 5 (iii)). Here, typically, the light of the wavelength used for exposing the photoresist 24 is absorbed by about 60% to 70% in the chemical plating layer 22 composed of copper or the like. Therefore, for example, when the angle between the exposure incident light I and the exposure reflected light R is too large, the exposure reflected light R is absorbed by the chemical plating layer 22 (for example, the concave and convex portion near the reflection portion), resulting in a situation where the pattern defect caused by the foreign matter F is not eliminated. In this regard, by combining the peak density Sds and the peak curvature Ssc within the above-mentioned range to control the surface shape of the chemical plating layer 22, it is easy to control the angle between the exposure incident light I and the exposure reflected light R within the desired range. As a result, the portion of the photoresist 24 (for example, the dry film resist 24a) directly below the foreign matter F can be exposed very effectively. In other words, even if the foreign matter F present on the surface and / or inside the photoresist 24 is of a huge size, its influence can be eliminated. In this way, the formation of unexposed portions of the photoresist 24 caused by foreign matter F can be effectively prevented, and the formation of unnecessary holes H caused by development can be suppressed (see FIG. Figure 5 (iv)). This makes it possible to avoid problems such as short circuits and pattern defects such as protrusions. Even so, it is possible to achieve excellent high-frequency characteristics because the surface of the electroless plating layer 22 having a peak density Sds and a peak curvature Ssc within the above-mentioned ranges has a relatively low roughness, which is effective in reducing the skin effect.

[0085] From the above viewpoint, the peak top density Sds of the surface of the electroless plating layer 22 is 0.90 μm －2 Above and 1.30μm －2 Below, preferably 0.90 μm －2 Above and 1.20μm－2 Below, more preferably 1.10 μm －2 Above and 1.20μm －2 the following.

[0086] Furthermore, the peak curvature Ssc of the surface of the electroless plating layer 22 is 1.00 μm. －1 Above and 4.00μm －1 Below, preferably 2.30 μm －1 Above and 3.50μm －1 Below, more preferably 2.30 μm －1 Above and 3.00μm －1 the following.

[0087] The surface area ratio Sdr of the interface of the electroless plating layer 22 is preferably 5.00% to 10.00%, more preferably 5.00% to 6.00%. Within the above range, while achieving excellent high-frequency characteristics, pattern defects caused by larger foreign matter F can be further suppressed.

[0088] The electroless plating layer 22 having the above-described unique surface parameters can be formed by electroless plating on the rough surface 20a of the insulating substrate 20 at a thickness of 1.0 μm or less. As described above, it can be said that the surface shape of the electroless plating layer 22 substantially reflects the surface shape of the rough surface 20a of the insulating substrate 20. Furthermore, the rough surface 20a can preferably be formed by transferring the surface shape of the surface-treated copper foil 10 having the surface parameters described in (a) above to the insulating substrate 20.

[0089] The thickness of the electroless plating layer 22 is 1.0 μm or less, preferably 0.3 μm or more and 1.0 μm or less. Such a thickness can reduce the amount of etching during wiring pattern formation, and is extremely suitable for forming fine circuits.

[0090] (c) Photoresist stacking

[0091] like Figure 1 As shown in (c), a photoresist 24 is laminated on the surface of the chemical plating layer 22. The lamination speed when laminating the photoresist 24 is not particularly limited, and is typically 1.0 m / min or more and 2.0 m / min or less. The photoresist 24 can use a known material commonly used in the manufacture of printed circuit boards. The photoresist 24 can be either a negative type or a positive type, and can also be either a film type or a liquid type. Preferably, the photoresist 24 includes a dry film resist 24a. In addition, the photoresist 24 is preferably a photosensitive film, for example, a photosensitive dry film. As Figure 1As shown in (c), the photoresist 24 may also be formed by further laminating a supporting film 24b such as a polyethylene terephthalate (PET) film on a dry film resist 24a as a photosensitive layer. From the perspective of improving fluidity and mold release during thermoforming, the supporting film 24b such as a PET film typically contains a lubricant. In this regard, according to the present invention, as described above, pattern defects caused by lubricants and the like can be effectively suppressed. The thickness of the photoresist 24 or dry film resist 24a is preferably not less than 2 μm and not more than 35 μm, and more preferably not less than 5 μm and not more than 24 μm.

[0092] (d) Formation of resist pattern

[0093] like Figure 2 As shown in (d), a resist pattern 26 is formed by exposing and developing the photoresist 24. Exposure and development can be carried out in accordance with the known methods and conditions commonly used in the manufacture of printed circuit boards and are not particularly limited. For example, as an exposure method, in addition to a mask exposure method using a negative mask pattern or a positive mask pattern, a direct drawing exposure method such as a Laser Direct Imaging (LDI) exposure method or a Digital Light Processing (DLP) exposure method can also be used. The exposure dose during exposure is preferably 5 mJ / cm 2 Above and 150mJ / cm 2 The following is a description of the method of development. Alternatively, the development method may be either wet development or dry development. In the case of wet development, the developer used may be sodium carbonate, sodium hydroxide, an amine aqueous solution, or the like. Furthermore, if the photoresist 24 includes a support film 24b, development is preferably performed after removing the support film 24b.

[0094] (e) Formation of electroplating layer

[0095] Electroplating (e.g. copper plating) is performed on the chemical plating layer 22 by means of the resist pattern 26. By doing so, Figure 2 As shown in (e), the electroplating layer 28 can be formed between the resist patterns 26. The electroplating can be performed according to various pattern plating methods and conditions commonly used in the manufacture of printed circuit boards, such as copper sulfate plating solutions and copper pyrophosphate plating solutions, and is not particularly limited.

[0096] (f) Stripping of resist pattern

[0097] In this process, the resist pattern 26 is peeled off. As a result, Figure 2As shown in (f), the electroplated layer 28 remains in the form of a wiring pattern, and the useless portion of the chemically plated layer 22 that does not form a wiring pattern is exposed. The resist pattern 26 can be stripped using a sodium hydroxide aqueous solution, an amine solution, or an aqueous solution thereof, in accordance with various stripping methods and conditions commonly used for printed circuit boards, and is not particularly limited.

[0098] (g) Formation of wiring pattern

[0099] The unnecessary portions of the electroless plating layer 22 (i.e., portions where no wiring pattern is formed) exposed by the removal of the resist pattern 26 are removed by etching, forming the wiring pattern 30. Etching of the unnecessary portions of the electroless plating layer 22 can be performed using, for example, a sulfuric acid-hydrogen peroxide-based etchant, according to etching methods and conditions commonly used in printed circuit board manufacturing, and is not particularly limited. The thickness of the wiring pattern 30 (i.e., circuit height) is preferably between 2 μm and 30 μm. The wiring pitch of the wiring pattern 30 is preferably within a range of 10 μm (e.g., line width / space = 5 μm / 5 μm) to 20 μm (e.g., line width / space = 10 μm / 10 μm). By forming the circuit on an electroless plating layer 22 having a thickness of 1.0 μm or less and the predetermined surface parameters described above, such a highly miniaturized wiring pattern can be formed. While wiring patterns with wiring pitches within the aforementioned range are prone to pattern defects such as short circuits and protrusions, as described above, the method of the present invention can effectively address these issues.

[0100] Alternatively, as needed, an insulating layer and an nth wiring pattern (n is an integer greater than 2) may be alternately formed on the wiring pattern 30 to make a multilayer circuit board. For each wiring pattern constituting the multilayer circuit board, the wiring pattern 30 may be used as the first wiring pattern, and may be referred to as the second wiring pattern, the third wiring pattern, ..., the nth wiring pattern in sequence. The continuous stacked structure consisting of the first wiring pattern, the nth wiring pattern and the insulating layer is generally referred to as a build-up layer or a build-up wiring layer. There is no particular limitation on the method used for forming the build-up layer after the second wiring pattern. In addition to the above-mentioned SAP method, an improved semi-additive method (MSAP method), a full additive method, a subtractive method, etc. may also be used. In addition, as needed, bumps for mounting such as solder resist and columns may be formed on the wiring pattern on the outermost surface of the build-up layer. In either case, the known methods commonly used in printed circuit boards may be appropriately added without particular limitation.

[0101] [Example]

[0102] The present invention will be described in more detail with reference to the following examples.

[0103] Example 1~Example 15

[0104] Fifteen types of surface-treated copper foil were prepared and used to transfer the surface profile to an insulating substrate. The roughened surface of the resulting insulating substrate was electrolessly plated to create a laminate for evaluation, and various evaluations were performed as follows.

[0105] (1) Preparation of surface treated copper foil

[0106] Fifteen types of surface-treated copper foils 10 were prepared, each having a treated surface 10a having the parameters shown in Table 2 on at least one surface. Some of these surface-treated copper foils 10 were commercially available, while the others were separately produced using known methods. The various parameters of the treated surface 10a of the prepared surface-treated copper foils 10 were measured or calculated as follows.

[0107] The surface roughness of the treated surface 10 a of the surface-treated copper foil 10 was measured using a laser microscope in accordance with EUR 15178 N. Specific measurement conditions are shown in Table 1.

[0108]

Table 1

[0109] Table 1

[0110]

[0111] The measurement data obtained by the above-mentioned laser microscope was read using analysis software ("OLS5100 LEXT (Version 2.1.2.215)" manufactured by Olympus Corporation), directly converted into a LEXT file format as unprocessed data, and output. The LEXT file was read using other analysis software ("MountainsMap (Version 9.0.9878)" manufactured by Digital Surf Corporation) and analyzed (analysis area: 64.397μm×64.463μm). Specifically, from the analysis object label, select "Parameter table" and "Default settings" in sequence to display the parameter analysis screen. In the parameter analysis screen, select "EUR15178N" as the specification, select "First order surface" as the wavelength processing, select "Least squares plane" as the F operation (F operation) for shape removal, and select "Sds", "Ssc" and "Sdr" as the parameters. On the other hand, in this screen, the S filter and the L filter are not selected (that is, cutoff by the S filter and the L filter is not performed). Then, select "Export Analysis Results" to save the analysis results. From these analysis results, the peak density Sds, peak curvature Ssc, and interface expansion area ratio Sdr are read. For each example, these parameters are calculated in five different fields of view. The average value across the entire field of view is used as the Sds, Ssc, and Sdr of the treated surface 10a of the surface-treated copper foil 10. The results are shown in Table 2.

[0112] (2) Preparation of evaluation laminate

[0113] After laminating two sheets of prepreg (manufactured by Mitsubishi Gas Chemical Co., Ltd., GHPL-830NSF, thickness 100 μm), Figure 3 As shown in FIG. 1 , the surface treated copper foil 10 prepared in the above (1) is laminated on the insulating substrate 20 ' in such a manner that the treated surface 10a contacts the insulating substrate 20 ', and the pressing temperature is 220°C, the pressing time is 90 minutes, and the pressing pressure is 40 kgf / cm 2 The copper-clad laminate 12 was obtained by stamping under the conditions of . The surface-treated copper foil 10 of the copper-clad laminate 12 was completely removed using a sulfuric acid-hydrogen peroxide-based etching solution to obtain an insulating substrate 20 having a rough surface 20a to which the surface shape of the treated surface 10a was transferred. The insulating substrate 20 was electrolessly plated with copper using an electroless copper plating solution (manufactured by Atotech, Atotech MV+) to form an electroless plating layer 22 on the rough surface 20a side. The thickness of the electroless plating layer 22 is shown in Table 2. In this way, a laminate before laminating the photoresist in the SAP method (hereinafter referred to as an evaluation laminate) was obtained.

[0114] (3) Surface profile measurement of evaluation laminate

[0115] The peak top density Sds, peak top curvature Ssc, and interface development area ratio Sdr of the electroless plating layer 22 side surface of the evaluation laminate obtained above were measured using a laser microscope for surface roughness analysis in accordance with EUR15178N. The measurement and analysis conditions for each parameter were the same as those for the surface-treated copper foil in (1) above. The results are shown in Table 2.

[0116] (4) Various evaluations

[0117] The obtained evaluation laminate or circuit board was evaluated for various properties as follows.

[0118] <Dust detection number>

[0119] The dust detection number was evaluated as follows. First, a negative photoresist 24 (RY-5319, manufactured by Hitachi Chemical Co., Ltd.) having a thickness of 19 μm was laminated on the surface of the electroless plating layer 22 side of the evaluation laminate obtained above at a lamination speed of 1.5 m / min. Figure 6As shown in (i), a glass mask 25 is laminated on the surface of the photoresist 24. In addition, a circular shading portion B (diameter 8μm to 15μm (each 1μm is 1 level, a total of 8 levels), 25 each × 12 fields of view) is provided in the center of each area divided by 100μm×100μm in the glass mask 25, which is assumed to be a foreign matter such as dust. Therefore, the portion of the glass mask 25 where the shading portion B is not provided allows light to pass through, while on the other hand, the portion of the glass mask 25 where the shading portion B is provided does not allow light to pass through. The evaluation laminate after the glass mask 25 is laminated is exposed (70mJ / cm 2 ) and developed to form a resist pattern 26. The surface of the evaluation laminated body on the resist pattern 26 side after development was observed under a magnification of 700 times using a digital microscope (VHX-7000 manufactured by KEYENCE Co., Ltd.). Figure 6 As shown in (ii), the number of holes H formed in the resist pattern 26 is counted. Then, the number of hole detections in each field of view is classified according to the size of the light-shielding portion B and averaged (that is, a maximum of 25 for each size) as the number of dust detections. In addition, it can be said that the more dust detections there are (that is, the better the resolution), the higher the possibility of useless electroplating on parts where circuits should not be formed, and the easier it is to produce pattern defects. Therefore, in each sample, the diameter of the largest light-shielding portion B with a dust detection number of less than 13 is regarded as the maximum size of dust that can eliminate pattern defects. The results are shown in Table 2.

[0120] <Evaluation of high-frequency characteristics>

[0121] A high-frequency substrate (Matsushita Corporation, MEGTRON 7, 68 μm thick x 2 sheets) was prepared as an insulating resin substrate. A copper foil with a carrier having the surface-treated copper foil 10 prepared in (1) above was laminated on both sides of the insulating resin substrate in such a manner that the treated surface 10a of the surface-treated copper foil 10 abutted against the insulating resin substrate. After being pressed using a vacuum press at a press pressure of 3 MPa, a temperature of 190°C, and a press time of 90 minutes, the carrier and the peeling layer were peeled off and removed. The surface-treated copper foil 10 was completely removed using a sulfuric acid-hydrogen peroxide etching solution, resulting in an insulating substrate 20 having a rough surface 20a that had the surface shape of the treated surface 10a transferred. Subsequently, the insulating substrate 20 was electrolessly plated with copper using an electroless copper plating solution (Atotech MV+, Atotech Co., Ltd.), forming an electroless plating layer 22 with a thickness of 0.5 μm on the rough surface side. Afterwards, copper plating was performed until the copper layer reached a thickness of 18 μm to produce a copper-clad laminate. A subtractive circuit was formed on the copper-clad laminate using a cupric chloride etchant (circuit height: 18 μm, circuit width: 320 μm, circuit length: 300 mm). This yielded a substrate for measuring transmission loss, on which a microstrip line was formed with a characteristic impedance of 50 Ω ± 2 Ω. The resulting substrate for measuring transmission loss was measured using a network analyzer (Keysight Technologies, N5225B) under the following conditions, and the transmission loss (dB) at 50 GHz was measured.

[0122] (Setting conditions)

[0123] -IF Bandwidth: 100Hz

[0124] -Frequency: 10MHz~50GHz

[0125] -Data points: 501 points

[0126] -Average: Off

[0127] -Calibration method: SOLT (e-cal)

[0128] The transmission loss (absolute value) obtained at 50 GHz was evaluated by ranking based on the following criteria. The results are shown in Table 2.

[0129] <High-Frequency Characteristics Evaluation Criteria>

[0130] - Rating A (Best): Transmission loss (absolute value) less than 13.5dB

[0131] - Rating B (good): Transmission loss (absolute value) is 13.5 dB or more and less than 15.0 dB

[0132] - Rating C (poor): Transmission loss (absolute value) is 15.0 or more

[0133]

Table 2

[0134]

Claims

1. A method for manufacturing a printed circuit board, wherein: The manufacturing method includes the following steps: (a) Preparing an insulating substrate having a rough surface; (b) performing chemical plating on the rough surface of the insulating substrate to form a chemical plating layer, wherein the chemical plating layer has a peak density Sds of 0.90 μm measured in accordance with EUR15178N －2 Above and 1.30μm －2 The peak curvature Ssc measured in accordance with EUR15178N is 1.00 μm. －1 Above and 4.00μm －1 The thickness of the chemical plating layer is less than 1.0 μm; (c) laminating a photoresist on the surface of the chemically plated layer; (d) exposing and developing the photoresist to form a resist pattern; (e) electroplating the chemical plating layer with the aid of the resist pattern; (f) stripping the resist pattern; as well as (g) The unnecessary portion of the electroless plating layer exposed by the peeling of the resist pattern is removed by etching to form a wiring pattern.

2. The method for manufacturing a printed circuit board according to claim 1, wherein: The surface of the electroless plating layer has an interface developed area ratio Sdr measured in accordance with EUR15178N of 5.00% or more and 10.00% or less.

3. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein: The peak curvature Ssc of the surface of the chemical plating layer is 2.30 μm －1 Above and 3.50μm －1 the following.

4. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein: The process (a) comprises the following steps: (a-1) A surface-treated copper foil having a peak top density Sds of 1.00 μm measured in accordance with EUR15178N was prepared. －2 Above and 1.50μm －2 The following peak curvature Ssc measured in accordance with EUR15178N is 4.00 μm －1 Above and 6.00μm －1 The treated surface has an interface development area ratio Sdr of 20.00% or more and 40.00% or less measured in accordance with EUR15178N, (a-2) after laminating an insulating base material on the treated surface of the surface-treated copper foil and transferring the surface shape of the treated surface to the surface of the insulating base material, (a-3) The surface-treated copper foil is removed by etching to obtain an insulating base material having the rough surface.

5. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein: The thickness of the chemical plating layer is greater than or equal to 0.3 μm and less than or equal to 1.0 μm.

6. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein: The photoresist includes a dry film resist.

7. The method for manufacturing a printed circuit board according to claim 6, wherein: The dry film resist has a thickness of 2 μm or more and 35 μm or less.

8. The method for manufacturing a printed circuit board according to claim 1 or 2, wherein: The wiring pattern has a thickness of 2 μm or more and 30 μm or less.

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