Capacitance scale, capacitive displacement sensor and preparation method of capacitance scale

Abstract

The invention provides a capacitance scale, a capacitive displacement sensor and a preparation method of the capacitance scale. The capacitance scale comprises at least one capacitor bank. The at least one capacitor bank is arranged along a preset direction; each capacitor bank comprises a plurality of capacitor units which are continuously arranged along a preset direction; wherein in each capacitor bank, the capacitance values of all the capacitor units sequentially form a monotonic sequence, and in the monotonic sequence, any two adjacent capacitance values are not equal. The capacitor bank is arranged in the capacitor scale, the capacitance values of all the capacitor units in the capacitor bank sequentially form the monotonic sequence, the monotonic characteristic enables the capacitance change gradient on the capacitor scale to have directivity, dynamic calibration in the stepping direction can be assisted, and misoperation is avoided.

Description

Technical Field

[0001] The present application relates to the field of displacement measurement, and in particular to a capacitance scale, a capacitive displacement sensor, and a method for preparing the capacitance scale. Background Art

[0002] In the field of precision machining, precision displacement (angle) sensors are an indispensable and important component, and are compared to the ruler of intelligent manufacturing. Their accuracy directly determines the leading level of the machining and manufacturing links.

[0003] A grating measuring device is a precision sensor that can accurately measure displacement (or rotation angle) and is widely used in the precision manufacturing industry.

[0004] However, the current gate-type capacitance scale does not have the capability of step-wise calibration and fool-proofing. Summary of the Invention

[0005] The main technical problem solved by the present application is to provide a capacitance scale, a capacitive displacement sensor and a method for preparing the capacitance scale, so as to solve the problem of how to calibrate the stepping direction of the gate-type capacitance scale in the prior art.

[0006] In order to solve the above technical problems, the first technical solution provided by this application is to provide a capacitance scale, which includes: At least one capacitor group is arranged along a preset direction; each capacitor group includes a plurality of capacitor units arranged continuously along the preset direction; In each capacitor group, the capacitance values ​​of the capacitor units sequentially form a monotonic sequence, and in the monotonic sequence, any two adjacent capacitance values ​​are not equal.

[0007] Each capacitor unit includes a first electrode, a dielectric layer, and a second electrode stacked in sequence; in the capacitor unit, the second electrode at least partially overlaps with the first electrode; The capacitance scale has a plurality of intervals which are continuously arranged along a preset direction and have equal widths; the capacitance units are arranged in the intervals and correspond to the intervals one by one.

[0008] The area of ​​the overlapping region between the first electrode and the corresponding second electrode is defined as the overlapping area; in each capacitor group, the overlapping areas of each capacitor unit sequentially constitute a first arithmetic progression, and the first arithmetic progression is proportional to the corresponding monotonic progression.

[0009] The spacing between the first electrode and the corresponding second electrode is defined as the inter-plate distance; in each capacitor group, the inter-plate distances of each capacitor unit sequentially form a second arithmetic progression, and the second arithmetic progression is set proportionally to the corresponding monotonic progression.

[0010] In each capacitor group, the dielectric constants of the dielectric layers of the capacitor units sequentially form a third arithmetic progression, and the third arithmetic progression is arranged in proportion to the corresponding monotonic progression.

[0011] There is one capacitor group; and the monotonic sequence in the capacitor group is an increasing arithmetic sequence or a decreasing arithmetic sequence.

[0012] There are multiple capacitor groups; the multiple capacitor groups are arranged along a preset direction, and in the preset direction, the monotonic sequence in each capacitor group is an arithmetic sequence with consistent monotonicity.

[0013] The capacitance scale further includes a capacitance unit located between any adjacent capacitance groups; the capacitance unit located between adjacent capacitance groups is defined as a reference unit; the reference unit is located in the interval; the capacitance value of the reference unit is greater than the capacitance value of any capacitance unit in each capacitance group, or the capacitance value of the reference unit is less than the capacitance value of any capacitance unit in each capacitance group.

[0014] In order to solve the above technical problems, the second technical solution provided by this application is to provide a capacitive displacement sensor, which includes: Capacitance scale, which is the capacitance scale mentioned above; The counter is displaced relative to the capacitance scale and is used to detect the capacitance change on the capacitance scale and output displacement data.

[0015] In order to solve the above technical problems, the third technical solution provided by the present application is to provide a method for preparing a capacitance scale, which includes: At least one capacitor group is prepared on a substrate; at least one capacitor group is arranged along a preset direction; Wherein, preparing at least one capacitor group on the substrate includes: A plurality of capacitor units are prepared on a substrate; each capacitor group includes a plurality of capacitor units arranged continuously along a preset direction; in each capacitor group, the capacitance values ​​of the capacitor units sequentially form a monotonic series, and in the monotonic series, any two adjacent capacitance values ​​are not equal.

[0016] Beneficial effects of the present application: Different from the prior art, the present application provides a capacitance scale, a capacitive displacement sensor, and a method for preparing a capacitance scale, wherein the capacitance scale includes at least one capacitance group. The at least one capacitance group is arranged along a preset direction; each capacitance group includes a plurality of capacitance units arranged continuously along the preset direction; wherein, in each capacitance group, the capacitance values ​​of the capacitance units sequentially form a monotonic series, and in the monotonic series, any two adjacent capacitance values ​​are not equal. By providing a capacitance group in the capacitance scale and making the capacitance values ​​of the capacitance units in the capacitance group sequentially form a monotonic series, the monotonic characteristic makes the capacitance change gradient on the capacitance scale directional, which can assist in dynamic calibration of the step direction and avoid misoperation (i.e., fool-proof design). BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technical workers in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 is a schematic diagram of the three-dimensional structure of a grid-type measurement device provided in an embodiment of the present application; Figure 2 Schematic diagram of the three-dimensional structure of the grid scale provided in an embodiment of the present application; Figure 3 Schematic diagram of the structure of the gate type measurement device provided in an embodiment of the present application; Figure 4 1 is a structural diagram of a first embodiment of a capacitance scale provided in an embodiment of the present application; Figure 5 This is a schematic structural diagram of a first embodiment of a capacitance unit in a capacitance scale provided by an embodiment of the present application, viewed from above; Figure 6 This is a schematic structural diagram of a second embodiment of a capacitance unit in a capacitance scale provided by an embodiment of the present application, viewed from above; Figure 7 This is a schematic structural diagram of a third embodiment of a capacitance unit in a capacitance scale provided by an embodiment of the present application, viewed from above; Figure 8 2 is a schematic structural diagram of a second embodiment of a capacitance scale provided in an embodiment of the present application; Figure 9 1 is a schematic structural diagram of a third embodiment of a capacitance scale provided in an embodiment of the present application; Figure 10 1 is a structural diagram of a fourth embodiment of a capacitance scale provided in an embodiment of the present application; Figure 11 1 is a schematic structural diagram of a fifth embodiment of a capacitance scale provided in an embodiment of the present application; Figure 12 1 is a structural diagram of a sixth embodiment of a capacitance scale provided in an embodiment of the present application; Figure 13 2 is a structural diagram of a seventh embodiment of a capacitance scale provided in an embodiment of the present application; Figure 14 1 is a schematic structural diagram of an eighth embodiment of a capacitance scale provided in an embodiment of the present application; Figure 15 1 is a schematic structural diagram of a ninth embodiment of a capacitance scale provided in an embodiment of the present application; Figure 161 is a schematic structural diagram of an embodiment of a capacitive displacement sensor provided in an embodiment of the present application; Figure 17 A schematic flow chart of an embodiment of a method for preparing a capacitance scale provided in an embodiment of the present application; Figure 18 yes Figure 17 A schematic flow chart of an embodiment of step S10; Figure 19 yes Figure 18 Schematic diagram of the structure corresponding to steps S11 to S14; Figure 20 This is a flow chart of an implementation of step S15 provided in an embodiment of the present application; Figure 21 is a structural diagram corresponding to step S15; Figure 22 This is a flow chart of an implementation of step S16 provided in an embodiment of the present application; Figure 23 It is a structural diagram corresponding to step S16.

[0019] Description of Figure Numbers: 1. Capacitance scale; 10. Interval; 11. Capacitance group; 111. First capacitor group; 112. Second capacitor group; 12. Capacitance unit; 121. First electrode; 1210. First lead; 1220. Second lead; 122. Second electrode; 123. Dielectric layer; 13. First conductive layer; 14. Dielectric material layer; 141. Groove; 15. Second conductive layer; 16. Insulating layer; 17. Substrate; 18. Reference unit; 2. Counter; 3. Capacitive displacement sensor; L, physical quantity; L1 / L2 / x; width; S0 / S1 / S2 / S3 / S4 / S5 / S6, capacitance value; C1 / C2 / C3 / C4 / C5 / C6 / C7 / C8 / C9, capacitance value. DETAILED DESCRIPTION

[0020] The following describes the embodiments of the present application in detail with reference to the accompanying drawings.

[0021] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features identified. Therefore, features identified as "first," "second," or "third" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined. All directional designations in the embodiments of this application (such as up, down, left, right, front, back, etc.) are intended only to illustrate the relative positional relationships and movement of components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional designations will also change accordingly. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to such process, method, product, or apparatus.

[0024] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, that the embodiments described herein may be combined with other embodiments.

[0025] See also Figures 1 to 3 , Figure 1 is a schematic diagram of the three-dimensional structure of the grid type measurement device provided in an embodiment of the present application, Figure 2 is a schematic diagram of the three-dimensional structure of the grid scale provided in an embodiment of the present application, Figure 3 Schematic diagram of the structure of the grid type measurement device provided in an embodiment of the present application.

[0026] Generally speaking, a grid type measuring device consists of two parts: a grid type scale and a counter, such as Figure 1 As shown. A grating scale depicts equal quantities of physical quantity L, i.e., an equally divided scale. For example, a traditional high-precision mechanical scale has an equally spaced contrast substrate. Specifically, a grating scale includes alternating bright and dark substrates, with the bright substrate width being L2 and the dark substrate width being L1, where L = L1 + L2.

[0027] When a grating scale follows a mechanical device's movement or rotation, the number of times N the equal physical quantity L appears is captured by a counter, allowing the displacement X = L * N to be calculated. However, the equal quantity L of current equal-division scale gratings is a fixed value.

[0028] However, the current equally divided grid scale does not have the step direction calibration and anti-foolproofing functions, that is, it cannot determine whether the mechanical device is moving forward or backward, because the number of times N collected by the counter has no directionality, such as Figure 3 It also does not have the ability to "return to zero" calibration, that is, it cannot determine whether the mechanical device has returned to "zero" after being reset.

[0029] See also Figures 4 to 8 , Figure 4 is a structural diagram of the first embodiment of the capacitance scale provided by the embodiment of the present application, Figure 5 1 is a schematic structural diagram of a first embodiment of a capacitance unit in a capacitance scale provided by an embodiment of the present application from a top view. Figure 6 1 is a schematic structural diagram of a second embodiment of a capacitance unit in a capacitance scale provided by an embodiment of the present application from a top view. Figure 7 1 is a schematic structural diagram of a third embodiment of a capacitance unit in a capacitance scale provided by an embodiment of the present application from a top view. Figure 8 1 is a schematic structural diagram of a second embodiment of a capacitive scale provided in an embodiment of the present application.

[0030] To address the above technical issues, the present application provides a capacitance scale 1. The capacitance scale 1 includes at least one capacitor group 11. The at least one capacitor group 11 is arranged along a predetermined direction. Each capacitor group 11 includes a plurality of capacitor units 12 arranged continuously along the predetermined direction. Within each capacitor group 11, the capacitance values ​​of the capacitor units 12 sequentially form a monotonic sequence, and within the monotonic sequence, any two adjacent capacitance values ​​are unequal.

[0031] By providing a capacitor group 11 in the capacitance scale 1 and making the capacitance values ​​of the capacitor units 12 in the capacitor group 11 form a monotonic series in sequence, the monotonic characteristic makes the capacitance change gradient on the capacitance scale 1 directional, which can assist in dynamic calibration of the step direction and avoid erroneous operation (i.e., fool-proof design).

[0032] The monotonic sequence can be an arithmetic sequence or a non-arithmetic sequence. There are no excessive restrictions here and you can choose according to actual needs.

[0033] The following mainly uses the monotonic sequence as an arithmetic sequence as an example for explanation. In each capacitor group 11, the capacitance values ​​of the capacitor units 12 sequentially arranged along a preset direction sequentially form an arithmetic sequence.

[0034] There is no restriction on the specific value of the tolerance of the arithmetic progression here, and it can be selected according to actual needs.

[0035] Each capacitor group 11 includes at least two capacitor units 12 .

[0036] In some embodiments, each capacitor unit 12 includes a first electrode 121, a dielectric layer 123, and a second electrode 122 stacked in sequence; in the capacitor unit 12, the second electrode 122 is at least partially overlapped with the first electrode 121; the capacitance scale 1 has a plurality of intervals 10 of equal width arranged continuously along a preset direction; the capacitor units 12 are arranged in the intervals 10 and correspond one to one with the intervals 10.

[0037] Exemplarily, the first electrodes 121 in each capacitor unit 12 are made of the same material.

[0038] Exemplarily, the second electrodes 122 in each capacitor unit 12 are made of the same material.

[0039] A capacitor unit 12 acts as a parallel plate capacitor.

[0040] In each capacitor unit 12 , the first electrode 121 and the second electrode 122 serve as plates of a parallel plate capacitor, respectively. The overlapping area of ​​the first electrode 121 and the second electrode 122 is the effective area of ​​the plates in the parallel plate capacitor.

[0041] The first electrode 121 is externally connected to a first voltage, and the second electrode 122 is externally connected to a second voltage. By controlling the first voltage and the second voltage, an electric field is established between the plates of the parallel plate capacitor, so that the counter 2 can identify the capacitance value of the capacitor unit 12.

[0042] Exemplarily, in each capacitor group 11 , the voltage difference between the first electrode 121 and the second electrode 122 in the capacitor unit 12 is not zero.

[0043] In the preset direction, the width x of each interval 10 is equal, so that the counter 2 (see Figure 16 ) and the capacitance scale 1 can be kept constant, so that the capacitance change of the capacitance scale 1 is proportional to the relative displacement, thereby regularizing the pulse signal or trigger interval of the counter 2 and reducing the complexity of signal processing (for example, each movement of the width x of an interval 10 triggers a capacitance sampling).

[0044] The shapes of the sections 10 can be different or the same, which is not limited here and can be selected according to actual needs.

[0045] Exemplarily, the shapes and sizes of the sections 10 are the same, and the sections 10 are rectangular.

[0046] In other embodiments, the shapes of the intervals 10 are different, and / or the sizes of the intervals 10 are different. For example, in a direction parallel to the capacitor unit 12, the intervals 10 are rectangular in shape, the widths x of the intervals 10 are equal (i.e., the widths along the predetermined direction are equal), and the lengths of the intervals 10 are different (i.e., the widths along the direction perpendicular to the predetermined direction are different).

[0047] The capacitor units 12 are spaced apart to avoid electric field interference between the plates of adjacent capacitor units 12 , thereby facilitating the counter 2 to collect the capacitance between the capacitor units 12 .

[0048] In some embodiments, the capacitor units 12 are arranged at non-equidistant intervals. For example, in a predetermined direction, the widths of the capacitor units 12 are different, and the positions of the capacitor units 12 in the corresponding intervals 10 are the same (see FIG. Figure 4 and Figure 5 ).

[0049] Exemplarily, the capacitor units 12 are all close to the same side edge of the interval 10 .

[0050] In other embodiments, the capacitor unit 12 may be located in the middle of the interval 10. There is no limitation on the position of the capacitor unit 12 in the interval 10, and the position may be selected according to actual needs.

[0051] In other embodiments, the capacitor units 12 are arranged at equal intervals in the preset direction. For example, in the preset direction, the widths of the capacitor units 12 are the same, and the positions of the capacitor units 12 in the corresponding intervals 10 are the same (see FIG. Figure 6 and Figure 7 ).

[0052] In the direction parallel to the capacitance scale 1, the shape of the capacitor unit 12 can be the same as or different from the shape of the interval 10, and the shape of each capacitor unit 12 in each capacitor group 11 can be the same or different. There are no excessive restrictions here and the selection is made according to actual needs.

[0053] Exemplarily, in a direction parallel to the capacitance scale 1 , the shape of the capacitance unit 12 is the same as the shape of the interval 10 , both being rectangular.

[0054] In some embodiments, the area of ​​the overlapping region between the first electrode 121 and the corresponding second electrode 122 is defined as the overlapping area; in each capacitor group 11, the overlapping areas of each capacitor unit 12 sequentially constitute a first arithmetic sequence, and the first arithmetic sequence is set proportionally to the corresponding monotonic sequence.

[0055] In each capacitor group 11, the overlapping areas of the capacitor units 12 sequentially form a first arithmetic progression, and the first arithmetic progression is proportional to the corresponding monotonic progression. It can be understood that in any capacitor group 11, the overlapping areas of the capacitor units 12 sequentially form a first arithmetic progression, and the capacitance values ​​of the capacitor units 12 sequentially form a first monotonic progression. The first arithmetic progression in the same capacitor group 11 is proportional to the first monotonic progression.

[0056] For example, the first arithmetic progression: denoted as A={a1, a2,…, ak}.

[0057] The first monotonic sequence is denoted as B = {b1, b2, …, bk}, where k is greater than 1.

[0058] The first arithmetic progression and the corresponding first monotonic progression have the same number of terms, both of which are k terms.

[0059] The first arithmetic sequence is the n-fold sequence (also called multiple sequence) of the first monotone sequence, that is, A=n*B, which means that each item satisfies ai=n*bi (for all i=1, 2,…, k).

[0060] That is, the capacitance difference between the capacitor units 12 is related to the overlapping area of ​​the capacitor units 12 , and the overlapping area of ​​the capacitor units 12 determines the tolerance of the first arithmetic progression.

[0061] The distance between the first electrode 121 and the corresponding second electrode 122 is defined as the inter-plate distance.

[0062] In each capacitor group 11 , the distances between the plates of each capacitor unit 12 are equal, and the dielectric constants of the dielectric layers 123 of each capacitor unit 12 are equal, so as to ensure that the capacitance of each capacitor unit 12 is determined by the overlapping area of ​​the capacitor units 12 .

[0063] In some specific embodiments, Figure 4 As shown, in each capacitor group 11, the widths of the capacitor units 12 along a predetermined direction form an arithmetic progression. In each capacitor unit 12, the first electrode 121 and the corresponding second electrode 122 completely overlap, i.e., the planar area of ​​the capacitor unit 12 is the same as the overlapping area. Specifically, in a direction parallel to the capacitance scale 1, each capacitor unit 12 is rectangular in shape. In the predetermined direction, the widths of the rectangles are different, and the lengths of the rectangles are the same.

[0064] In capacitor unit 12, the first electrode 121 and the second electrode 122 are completely overlapped, and a predetermined spacing is maintained between the first electrode 121 and the second electrode 122, ensuring that the capacitance of capacitor unit 12 is determined solely by the plate area (i.e., the area of ​​the first electrode 121 or the second electrode 122). By adjusting the width of each capacitor unit 12 electrode (i.e., the first electrode 121 or the second electrode 122) along a predetermined direction, the capacitance difference is directly controlled. This design simplifies the manufacturing process and helps improve the consistency of the capacitance gradient.

[0065] In other embodiments, in each capacitor group 11, the width of each capacitor unit 12 along the predetermined direction may be a non-arithmetic progression, and in at least some of the capacitor units 12, the first electrode 121 and the corresponding second electrode 122 may overlap.

[0066] Exemplarily, the preset direction is the length direction of the capacitive scale 1 .

[0067] Exemplarily, the capacitance scale 1 further includes a first conductive layer 13, a dielectric material layer 14, and a second conductive layer 15; the dielectric material layer 14 is at least partially located between the first conductive layer 13 and the second conductive layer 15; the first conductive layer 13 is used to form a first electrode 121, and the second conductive layer 15 is used to form a second electrode 122; the dielectric material layer 14 is used to form a dielectric layer 123 of the capacitor unit 12.

[0068] The first conductive layer 13 is patterned to form the first electrode 121 , and the second conductive layer 15 is patterned to form the second electrode 122 , so as to simplify the process of preparing the electrode plates in each capacitor unit 12 .

[0069] Exemplarily, the first conductive layer 13, the dielectric material layer 14 and the second conductive layer 15 are stacked in sequence so that the first conductive layer 13 and the second conductive layer 15 maintain a set distance. It can be understood that the thickness of the dielectric material layer 14 between the first conductive layer 13 and the second conductive layer 15 is the set distance, that is, the plate spacing between each capacitor unit 12 is the same. Specifically, the first conductive layer 13 and the second conductive layer 15 are respectively used to form the pole plates of the capacitor unit 12, so that the set distance is maintained between the first electrode 121 and the second electrode 122 in each capacitor unit 12. In addition, it can also ensure that the dielectric constant between each capacitor unit 12 is the same, so that the capacitance difference between each capacitor unit 12 is mainly determined by the overlapping area of ​​each capacitor unit 12. There is no restriction on the numerical value of the set distance here, and it is selected according to actual needs.

[0070] There is no limitation on the materials and thicknesses of the first conductive layer 13 and the second conductive layer 15 , and they can be selected according to actual needs.

[0071] In some specific embodiments, in a direction parallel to the capacitance scale 1 , the shapes of the capacitor units 12 may be the same or different.

[0072] For example, each capacitor group 11 includes three capacitor units 12. For example, in the direction parallel to the capacitance scale 1, the shape of each capacitor unit 12 is rectangular (see Figure 5 and Figure 6 For another example, in the direction parallel to the capacitance scale 1, the shapes of the capacitor units 12 are different (see Figure 7 ).

[0073] In some specific embodiments, the sizes of the capacitor units 12 may be the same or different.

[0074] For example, in a direction parallel to the capacitance scale 1, the shapes of the capacitor units 12 are the same, and the sizes of the capacitor units 12 are different. The first electrode 121 and the second electrode 122 in each capacitor unit 12 are completely overlapped, and the capacitance difference between the capacitor units 12 is determined according to the difference in the overlapping area between the capacitor units 12 (see Figure 4 ).

[0075] For another example, in a direction parallel to the capacitance scale 1, the shapes of the capacitor units 12 are the same, and the sizes of the capacitor units 12 are the same. The capacitance difference between the capacitor units 12 is determined based on the difference in the overlapping area between the capacitor units 12 (see Figure 8 ).

[0076] There is no restriction on the shape and size of each capacitor unit 12 , and they can be selected according to actual needs.

[0077] See also Figure 4 、 Figure 9 and Figure 10 , Figure 9 is a structural diagram of a third embodiment of a capacitive scale provided in an embodiment of the present application, Figure 10 1 is a schematic structural diagram of a fourth embodiment of a capacitive scale provided in an embodiment of the present application.

[0078] In other embodiments, Figure 9 As shown, the spacing between the first electrode 121 and the corresponding second electrode 122 is defined as the inter-plate distance; in each capacitor group 11, the inter-plate distances of each capacitor unit 12 sequentially constitute a second arithmetic progression, and the second arithmetic progression is set proportionally to the corresponding monotonic progression.

[0079] The second arithmetic sequence is arranged in proportion to the corresponding monotonic sequence, that is, the second arithmetic sequence is a multiple sequence of the corresponding monotonic sequence in the same capacitor unit 12 .

[0080] In each capacitor group 11 , the overlapping areas of the capacitor units 12 are equal, and the dielectric constants of the dielectric layers 123 of the capacitor units 12 are equal, so as to ensure that the capacitance of each capacitor unit 12 is determined by the distance between the plates of the capacitor unit 12 .

[0081] Exemplarily, the first electrode 121 of each capacitor unit 12 is formed by patterning the same conductive layer to simplify the manufacturing process.

[0082] Exemplarily, the dielectric layer 123 of each capacitor unit 12 is made of the same material to ensure that the dielectric constants of the dielectric layer 123 of each capacitor unit 12 are the same.

[0083] Illustratively, in each capacitor unit 12, the first electrode 121 and the second electrode 122 are completely overlapped. In other embodiments, the first electrode 121 and the second electrode 122 may be partially overlapped, as long as the overlapping areas of the capacitor units 12 are the same.

[0084] Exemplarily, each capacitor group 11 includes three capacitor units 12. In a preset direction, the capacitance values ​​of the three capacitor units 12 arranged consecutively are represented as C1, C2, and C3 in sequence, and form a first arithmetic progression.

[0085] In some other embodiments, Figure 10 As shown, in each capacitor group 11 , the dielectric constants of the dielectric layers 123 of the capacitor units 12 sequentially form a third arithmetic progression, and the third arithmetic progression is proportional to the corresponding monotonic progression.

[0086] The third arithmetic sequence is arranged in proportion to the corresponding monotonic sequence, that is, the third arithmetic sequence is a multiple sequence of the corresponding monotonic sequence in the same capacitor unit 12 .

[0087] In each capacitor group 11 , the overlapping areas of the capacitor units 12 are equal, and the inter-plate distances of the capacitor units 12 are equal, so as to ensure that the capacitance value of each capacitor unit 12 is determined by the dielectric constant of the dielectric layer 123 of the capacitor unit 12 .

[0088] Exemplarily, the first electrode 121 of each capacitor unit 12 is formed by patterning the same conductive layer, and the second electrode 122 is formed by patterning the same conductive layer, so as to simplify the manufacturing process.

[0089] Illustratively, in each capacitor group 11 , the dielectric layer 123 of each capacitor unit 12 is made of the same material, and the doping concentration of the dielectric layer 123 of each capacitor unit 12 is different to ensure that the dielectric constant of the dielectric layer 123 of each capacitor unit 12 is the same.

[0090] In other embodiments, in each capacitor group 11 , the dielectric layer 123 of each capacitor unit 12 may be made of different materials.

[0091] In some embodiments, the capacitive scale 1 further includes a substrate 17 and an insulating layer 16; the first conductive layer 13, the dielectric material layer 14, the second conductive layer 15 and the insulating layer 16 are sequentially arranged on the substrate 17, the dielectric material layer 14 covers the first electrodes 121 and fills the gaps between the first electrodes 121; the insulating layer 16 covers the second conductive layer 15 and fills the gaps between the second electrodes 122.

[0092] The dielectric material layer 14 covers the first electrodes 121 and fills the gaps between the first electrodes 121 . In addition to forming the dielectric layer 123 , the dielectric material layer 14 can also insulate the first electrodes 121 of each capacitor unit 12 , thereby simplifying the preparation of the capacitor unit 12 .

[0093] The material and thickness of the insulating layer 16 are not limited here and can be selected according to actual needs.

[0094] The side of the insulating layer 16 away from the substrate 17 is the working surface of the capacitive scale 1 .

[0095] There is at least one capacitor group 11. The following mainly uses the example that the overlapping areas of the capacitor units 12 in each capacitor group 11 sequentially form a first arithmetic progression, and the first arithmetic progression is proportional to the corresponding monotonic progression.

[0096] In some embodiments, as Figure 4 As shown, there is one capacitor group 11; the monotonic sequence in the capacitor group 11 is an increasing arithmetic sequence or a decreasing arithmetic sequence.

[0097] During the measurement process, the capacitance scale 1 and counter 2 undergo relative displacement. In response to the capacitance value sequence received by counter 2 including a continuous subsequence with the same monotonicity as the monotonic sequence, it is determined that counter 2 has displaced relative to capacitance scale 1 in a predetermined direction. In response to the capacitance value sequence received by counter 2 including a continuous subsequence with the opposite monotonicity to the monotonic sequence, it is determined that counter 2 has displaced relative to capacitance scale 1 in the opposite direction of the predetermined direction, thereby achieving direction calibration. In response to the capacitance value sequence received by counter 2 including multiple continuous subsequences with opposite monotonicity; and / or the capacitance value sequence received by counter 2 including a constant subsequence, it is determined that the measurement is abnormal, and an abnormality alarm function can be implemented.

[0098] Monotonicity means that two sequences (or subsequences) have the same changing trend. For example, both subsequences are increasing, or both subsequences are decreasing.

[0099] Monotonicity refers to the opposite trend of change of two sequences (or subsequences). For example, one of the two subsequences increases while the other decreases.

[0100] A constant subsequence is a contiguous subsequence where all elements have the same value.

[0101] Exemplarily, the capacitor bank 11 includes nine capacitor units 12. In a preset direction, the capacitance values of the nine continuously arranged capacitor units 12 are successively represented as C1, C2, C3, C4, C5, C6, C7, C8, C9, and form a monotonic sequence. In the preset direction, the overlapping areas of the nine continuously arranged capacitor units 12 are successively represented as S1, S2, S3, S4, S5, S6, S7, S8, S9, and form a first arithmetic progression.

[0102] Specifically, when the monotonic sequence in the capacitor bank 11 is an increasing arithmetic progression, S1 < S2 < S3 < S4 < S5 < S6 < S7 < S8 < S9, and C1 < C2 < C3 < C4 < C5 < C6 < C7 < C8 < C9. During the measurement process, the capacitance scale 1 and the counter 2 have a relative displacement. In response to the capacitance value sequence received by the counter 2 being an increasing subsequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the preset direction; in response to the capacitance value sequence received by the counter 2 being a decreasing subsequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the opposite direction of the preset direction, thereby achieving direction calibration.

[0103] When the monotonic sequence in the capacitor bank 11 is a decreasing arithmetic progression, S1 > S2 > S3 > S4 > S5 > S6 > S7 > S8 > S9, and C1 > C2 > C3 > C4 > C5 > C6 > C7 > C8 > C9. During the measurement process, the capacitance scale 1 and the counter 2 have a relative displacement. In response to the capacitance value sequence received by the counter 2 being an increasing subsequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the opposite direction of the preset direction; in response to the capacitance value sequence received by the counter 2 being a decreasing subsequence, it is determined that the counter 2 is displaced relative to the capacitance scale 1 in the preset direction, thereby achieving direction calibration.

[0104] In response to the capacitance value sequence received by the counter 2 including both an increasing subsequence and a decreasing subsequence; and / or, when the capacitance value sequence received by the counter 2 includes a constant subsequence, the measurement is abnormal, and an abnormal alarm function can be realized.

[0105] Please refer to Figure 4 and Figure 11 , Figure 11 is a schematic structural diagram of the fifth embodiment of the capacitance scale provided by the embodiment of the present application.

[0106] In some other embodiments, there are multiple capacitor banks 11; the multiple capacitor banks 11 are arranged in a preset direction, and in the preset direction, the monotonic sequences in each capacitor bank 11 are arithmetic progressions with the same monotonicity.

[0107] In the preset direction, the monotonic number series in each capacitor group 11 is an arithmetic series with consistent monotonicity, which means that in the preset direction, the monotonic number series in each capacitor group 11 is an increasing arithmetic series, or the monotonic number series in each capacitor group 11 is a decreasing arithmetic series.

[0108] Exemplarily, the plurality of capacitor groups 11 are arranged continuously along a preset direction.

[0109] In some embodiments, as Figure 11 As shown, the structures of the capacitor groups 11 are identical. Specifically, each capacitor group 11 includes the same number of capacitor units 12, and the monotonic sequence of each capacitor group 11 is identical. Each capacitor group 11 includes at least three capacitor units 12.

[0110] During the measurement process, the capacitance scale 1 and counter 2 undergo relative displacement. In response to the capacitance value sequence received by counter 2 including a continuous subsequence of a monotonic sequence, it is determined that counter 2 has displaced relative to capacitance scale 1 in a predetermined direction. In response to the capacitance value sequence received by counter 2 including a reverse subsequence of a monotonic sequence, it is determined that counter 2 has displaced relative to capacitance scale 1 in the opposite direction of the predetermined direction, thereby achieving directional calibration. In response to the capacitance value sequence received by counter 2 including both a continuous subsequence of a monotonic sequence and a reverse subsequence of a monotonic sequence, the measurement is abnormal, and an abnormality alarm function can be implemented.

[0111] A continuous subsequence is a sequence of consecutive elements selected from the original sequence in the order of the original sequence. The elements in a continuous subsequence maintain the original order and no intermediate elements are skipped.

[0112] A reverse subsequence is a sequence consisting of a continuous segment of elements selected from the original sequence in the reverse order of the original sequence. For example, a reverse subsequence of a monotonic sequence is a sequence consisting of a continuous segment of elements selected from the monotonic sequence in the reverse order of the monotonic sequence.

[0113] In this embodiment, each capacitor group 11 includes the same number of capacitor units 12 , and the monotonic sequence of each capacitor group 11 is the same, which can simplify the manufacturing process and the determination procedure of the counter 2 .

[0114] See also Figure 4 、 Figures 12 to 15 , Figure 12 : is a structural diagram of a sixth embodiment of a capacitance scale provided in an embodiment of the present application, Figure 13 : is a structural diagram of the seventh embodiment of the capacitance scale provided by the embodiments of the present application, Figure 14 is a structural diagram of an eighth embodiment of a capacitance scale provided in an embodiment of the present application, Figure 15 1 is a schematic structural diagram of a ninth embodiment of a capacitance scale provided in an embodiment of the present application.

[0115] In some other embodiments, the capacitor group 11 is divided into a first capacitor group 111 and a second capacitor group 112, and the first capacitor group 111 and the second capacitor group 112 are arranged alternately along a preset direction. The monotonic sequence in the first capacitor group 111 is different from the monotonic sequence in the second capacitor group 112. For example, the number of capacitor units 12 in the first capacitor group 111 and the second capacitor group 112 is the same, and / or the tolerance of the monotonic sequence in the first capacitor group 111 is different from the tolerance of the monotonic sequence in the second capacitor group 112. For another example, the number of capacitor units 12 in the first capacitor group 111 and the second capacitor group 112 is the same, and the tolerance of the monotonic sequence in the first capacitor group 111 is the same as the tolerance of the monotonic sequence in the second capacitor group 112, and the values ​​in the monotonic sequence in the first capacitor group 111 are different from the values ​​in the monotonic sequence in the second capacitor group 112.

[0116] Exemplarily, each capacitor group 11 includes at least two capacitor units 12 .

[0117] The difference in the monotonic sequence in the capacitor group 11 results in a different way of determining the displacement direction of the counter 2 in the counter 2 .

[0118] In some embodiments, as Figure 12 As shown, each capacitor group 11 includes two capacitor units 12 .

[0119] The monotonic sequence in the first capacitor group 111 is defined as the first sequence, and the monotonic sequence in the second capacitor group 112 is defined as the second sequence. The reverse order of the first sequence is the first reverse order, and the reverse order of the second sequence is the second reverse order. For example, Figure 6 As shown, the first sequence is C1, C2. The second sequence is C2, C3. The first inverted sequence is C2, C1. The second inverted sequence is C3, C2.

[0120] Specifically, during the measurement process, the capacitance scale 1 and the counter 2 undergo relative displacement. In response to the capacitance value sequence received by the counter 2 including a continuous first sequence and a second sequence (for example, C1, C2, C2, C3 or C2, C3, C1, C2), it is determined that the counter 2 is displaced along a preset direction relative to the capacitance scale 1; in response to the capacitance value sequence received by the counter 2 including a continuous first inverse sequence and a second inverse sequence (for example, C2, C1, C3, C2 or C3, C2, C2, C1), it is determined that the counter 2 is displaced in the opposite direction of the preset direction relative to the capacitance scale 1; in response to the capacitance value sequence received by the counter 2 including both the second sequence and the first sequence, the measurement is abnormal.

[0121] In other embodiments, Figure 13 and Figure 14As shown, the first capacitor group 111 includes at least two capacitor units 12, and the second capacitor group 112 includes at least three capacitor units 12. The number of capacitor units 12 in the first capacitor group 111 and the number of capacitor units 12 in the second capacitor group 112 can be the same or different.

[0122] In the monotonic sequence defining each capacitor group 11 , any continuous subsequence including three capacitance values ​​is a third sequence, and the reverse order of the third sequence is a fourth sequence.

[0123] Specifically, during the measurement process, the capacitance scale 1 and the counter 2 undergo relative displacement. In response to the capacitance value sequence received by the counter 2 including the third sequence, it is determined that the counter 2 is displaced along a preset direction relative to the capacitance scale 1; in response to the capacitance value sequence received by the counter 2 including the fourth sequence, it is determined that the counter 2 is displaced in the opposite direction of the preset direction relative to the capacitance scale 1; in response to the capacitance value sequence received by the counter 2 including both the third sequence and the fourth sequence, the measurement is abnormal.

[0124] It should be understood that as the number of intervals 10 of the capacitance scale 1 increases, the overlapping area of ​​the capacitance units 12 arranged at the end of the preset direction may become very large, so that the spacing distance between adjacent capacitance units 12 arranged at the end of the preset direction is shorter, causing interference in the electric field between the plates, which is not conducive to the counter 2 collecting capacitance changes; and is not conducive to the equal width design of the intervals 10 in the preset direction.

[0125] By providing multiple capacitor groups 11, the embodiments of the present application can reduce the number of capacitor units 12 within a single capacitor group 11, thereby reducing constraints on the overlapping area of ​​capacitor units 12 and facilitating control of the spacing between capacitor units 12, thereby simplifying the manufacturing process. Furthermore, the provision of multiple capacitor groups 11 is suitable for capacitance scales 1 with a large number of intervals 10, thereby expanding the measurement range of capacitance scale 1.

[0126] In some embodiments, as Figure 15 As shown, the capacitance scale 1 further includes a capacitance unit 12 located between any adjacent capacitance groups 11; the capacitance unit 12 located between the adjacent capacitance groups 11 is defined as a reference unit 18; the reference unit 18 is located in the interval 10; the capacitance value of the reference unit 18 is greater than the capacitance value of any capacitance unit 12 in each capacitance group 11, or the capacitance value of the reference unit 18 is less than the capacitance value of any capacitance unit 12 in each capacitance group 11.

[0127] The reference unit 18 is located outside the capacitor group 11 and does not belong to the capacitor group 11 . The capacitance value of the reference unit 18 is denoted as S0 .

[0128] The interval 10 where the reference unit 18 is located is the zero interval, ie the “zero point” of the capacitance scale 1 .

[0129] When the capacitance value received by the counter 2 is the capacitance of the reference unit 18 , it is determined that the counter 2 returns to the “zero point” of the capacitance scale 1 ; otherwise, it returns to zero.

[0130] There is only one reference unit 18, which ensures the uniqueness of the system "zero point".

[0131] The capacitance value of the reference unit 18 is greater than the capacitance value of any capacitance unit 12 in each capacitance group 11, or the capacitance value of the reference unit 18 is less than the capacitance value of any capacitance unit 12 in each capacitance group 11, so as to ensure the uniqueness of the capacitance value of the reference unit 18 and the uniqueness of the system "zero point".

[0132] Exemplarily, the voltage difference between the first electrode 121 and the second electrode 122 of the reference unit 18 is 0. At this time, the capacitance value of the reference unit 18 can be ignored, that is, the capacitance value of the reference unit 18 received by the counter 2 is 0.

[0133] In response to the counter 2 receiving the capacitance value of the reference unit 18, the counter 2 returns to the "zero point" of the capacitance scale 1. How to determine the displacement direction of the counter 2 is described above and will not be repeated here.

[0134] The “zero point calibration” function can be achieved by setting the reference unit 18 .

[0135] See also Figure 16 , Figure 16 Schematic diagram of the structure of a capacitive displacement sensor according to an embodiment of the present application.

[0136] The present application provides a capacitive displacement sensor 3. Capacitive displacement sensor 3 includes a capacitance scale 1 and a counter 2. Capacitive scale 1 is the capacitance scale 1 described above. Counter 2 is displaced relative to capacitance scale 1 and is used to detect capacitance changes on capacitance scale 1 and output displacement data.

[0137] Counter 2 receives the capacitance value of capacitance unit 12 on capacitance scale 1. The number of times the capacitance value of capacitance unit 12 is received multiplied by the width x of interval 10 is the displacement. That is, X=x*N, where X represents the displacement and N represents the number of times the capacitance value of capacitance unit 12 is received.

[0138] The determination of the displacement direction of the counter 2 is as described above.

[0139] See also Figure 4 、 Figure 11 、 Figures 17 to 19 , Figure 17 A schematic flow chart of an embodiment of a method for preparing a capacitance scale provided in an embodiment of the present application is provided. Figure 18 yes Figure 17A schematic flow chart of an embodiment of step S10, Figure 19 yes Figure 18 Schematic diagram of the structure corresponding to steps S11 to S14.

[0140] The present application provides a method for preparing a capacitance ruler, which is used to prepare the capacitance ruler 1 mentioned above.

[0141] The preparation method of the capacitance ruler includes: S10: preparing at least one capacitor group on a substrate; at least one capacitor group is arranged along a preset direction; wherein, preparing at least one capacitor group on a substrate comprises: preparing a plurality of capacitor units on the substrate; each capacitor group comprises a plurality of capacitor units continuously arranged along a preset direction; in each capacitor group, the capacitance values ​​of the capacitor units sequentially form a monotonic series, and in the monotonic series, any two adjacent capacitance values ​​are not equal.

[0142] In one specific embodiment, step S10 includes: S11: preparing a plurality of first electrodes arranged along a preset direction on a substrate.

[0143] Specifically, a plurality of intervals 10 of equal width are set on the substrate 17 and are arranged continuously along a preset direction. The first electrodes 121 are located in the intervals 10 and are arranged in a one-to-one correspondence with the intervals 10 .

[0144] In the preset direction, the width x of the intervals 10 is the same.

[0145] When the first electrode 121 is prepared, a first lead 1210 is also prepared. The first lead 1210 is connected to the first electrode 121 and is disposed one-to-one with the first electrode 121. The first electrode 121 is connected to an external power source through the first lead 1210.

[0146] S12: preparing a dielectric material layer on a side of the first electrode away from the substrate; the dielectric material layer is used to form a dielectric layer, and the dielectric layer is arranged in a one-to-one correspondence with the first electrode.

[0147] Specifically, the dielectric material layer 14 covers the first electrodes 121 and fills the gaps between the first electrodes 121 .

[0148] The surface of the dielectric material layer 14 away from the first electrode 121 is planarized so that a predetermined distance is maintained between the first electrode 121 and the second electrode 122 by the dielectric material layer 14 .

[0149] S13: preparing a plurality of second electrodes arranged along a preset direction on a side of the dielectric material layer away from the substrate; the second electrodes are arranged in a one-to-one correspondence with the first electrodes; the first electrodes, the corresponding dielectric layers and the corresponding second electrodes constitute a capacitor unit, and the plurality of capacitor units arranged continuously constitute a capacitor group.

[0150] Specifically, the second electrodes 122 are located within the intervals 10 and are disposed in a one-to-one correspondence with the intervals 10. The second electrodes 122 and the corresponding first electrodes 121 are at least partially overlapped in a direction perpendicular to the substrate 17, so that the first electrodes 121, the second electrodes 122, and the dielectric layer 123 can form a parallel plate capacitor.

[0151] When the second electrode 122 is prepared, a second lead 1220 is also prepared. The second lead 1220 is connected to the second electrode 122 and is provided in a one-to-one correspondence with the second electrode 122. The second electrode 122 is connected to an external power source through the second lead 1220.

[0152] The arrangement of the capacitor units 12 is determined according to the arrangement of the capacitor groups 11 .

[0153] S14: preparing an insulating layer on a side of the second electrode away from the substrate.

[0154] Specifically, the insulating layer 16 covers the second electrodes 122 and fills the gaps between the second electrodes 122 .

[0155] See also Figure 4 、 Figures 19 to 23 , Figure 20 This is a flow chart of an implementation of step S15 provided in an embodiment of the present application. Figure 21 is a schematic structural diagram corresponding to step S15, Figure 22 This is a flow chart of an implementation of step S16 provided in an embodiment of the present application. Figure 23 It is a structural diagram corresponding to step S16.

[0156] In other embodiments, Figure 10 、 Figure 20 and Figure 21 As shown, between step S12 and step S13, the following steps are also included: S15: performing ion doping treatment on the dielectric material layer.

[0157] In each capacitor group 11, the ion doping and / or ion doping concentration of the dielectric layer 123 of each capacitor unit 12 is different, so that in each capacitor group 11, the dielectric constants of the dielectric layer 123 of each capacitor unit 12 sequentially constitute a third arithmetic progression, and the third arithmetic progression is arranged in proportion to the corresponding monotonic progression.

[0158] Exemplarily, in each capacitor group 11 , the ion doping concentration of the dielectric layer 123 of each capacitor unit 12 is different.

[0159] In some other embodiments, Figure 9 、 Figure 20 and Figure 21 As shown, between step S12 and step S13, the following steps are also included: S16: forming a plurality of grooves with different depths on the surface of the dielectric material layer, wherein the grooves are arranged in a one-to-one correspondence with the first electrodes.

[0160] The groove 141 communicates with the surface of the dielectric material layer 14 away from the first electrode 121 .

[0161] In the subsequent step, i.e., step S13, the second electrode 122 is at least partially disposed in the groove 141. The second electrode 122 is disposed in a one-to-one correspondence with the groove 141 and covers the bottom wall of the corresponding groove 141, so that the distance between the bottom wall of the groove 141 and the corresponding first electrode 121 is the distance between the second electrode 122 in the groove 141 and the corresponding first electrode 121. In other words, the distance between the bottom wall of the groove 141 and the corresponding first electrode 121 is the inter-plate distance.

[0162] The second electrode 122 may be entirely located in the groove 141 , or may be partially located in the groove 141 and protruded from the surface of the dielectric material layer 14 away from the first electrode 121 .

[0163] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0164] The above is only an implementation method of the present application and does not limit the scope of patent protection of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the scope of patent protection of the present application.

Claims

1. A capacitance scale, characterized in that: include: At least one capacitor group is arranged along a preset direction; each of the capacitor groups includes a plurality of capacitor units arranged continuously along the preset direction; In each of the capacitor groups, the capacitance values ​​of the capacitor units sequentially form a monotonic series, and in the monotonic series, any two adjacent capacitance values ​​are not equal.

2. The capacitance scale according to claim 1, wherein: Each of the capacitor units comprises a first electrode, a dielectric layer, and a second electrode stacked in sequence; in the capacitor unit, the second electrode at least partially overlaps with the first electrode; The capacitance scale has a plurality of intervals that are continuously arranged along the preset direction and have equal widths; the capacitance units are arranged in the intervals and correspond one to one with the intervals.

3. The capacitance scale according to claim 2, wherein: The area of ​​the overlapping region between the first electrode and the corresponding second electrode is defined as the overlapping area; in each of the capacitor groups, the overlapping areas of the capacitor units sequentially constitute a first arithmetic sequence, and the first arithmetic sequence is arranged in proportion to the corresponding monotonic sequence.

4. The capacitance ruler according to claim 2, wherein: The distance between the first electrode and the corresponding second electrode is defined as the inter-plate distance; in each of the capacitor groups, the inter-plate distances of each capacitor unit sequentially constitute a second arithmetic progression, and the second arithmetic progression is arranged in proportion to the corresponding monotonic progression.

5. The capacitance scale according to claim 2, wherein: In each of the capacitor groups, the dielectric constants of the dielectric layers of the capacitor units sequentially form a third arithmetic progression, and the third arithmetic progression is arranged in proportion to the corresponding monotonic progression.

6. The capacitance scale according to any one of claims 1 to 5, characterized in that: There is one capacitor group; the monotonic sequence in the capacitor group is an increasing arithmetic sequence or a decreasing arithmetic sequence.

7. The capacitance scale according to any one of claims 1 to 5, characterized in that: There are multiple capacitor groups; the multiple capacitor groups are arranged along the preset direction, and in the preset direction, the monotonic number sequence in each capacitor group is an arithmetic progression with consistent monotonicity.

8. The capacitance scale according to claim 7, wherein: The capacitance scale further includes a capacitance unit located between any adjacent capacitance groups; the capacitance unit located between the adjacent capacitance groups is defined as a reference unit; the reference unit is located in the interval; The capacitance value of the reference unit is greater than the capacitance value of any capacitance unit in each of the capacitance groups, or the capacitance value of the reference unit is smaller than the capacitance value of any capacitance unit in each of the capacitance groups.

9. A capacitive displacement sensor, characterized in that: include: A capacitance ruler according to any one of claims 1 to 8; The counter is displaced relative to the capacitance scale, and is used to detect the capacitance change on the capacitance scale and output displacement data.

10. A method for preparing a capacitance ruler, characterized in that: include: preparing at least one capacitor bank on a substrate; The at least one capacitor group is arranged along a preset direction; Wherein, preparing at least one capacitor group on the substrate includes: A plurality of capacitor units are prepared on the substrate; each of the capacitor groups includes a plurality of the capacitor units arranged continuously along the preset direction; in each of the capacitor groups, the capacitance values ​​of the capacitor units sequentially form a monotonic series, and in the monotonic series, any two adjacent capacitance values ​​are not equal.

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