Comparator type starting circuit and chip for band-gap reference source

Abstract

The invention discloses a comparator type starting circuit and chip for a band-gap reference source, and the circuit comprises a band-gap core circuit, the output end of which generates a reference voltage; the first input end of the comparator receives the reference voltage, the second input end of the comparator receives comparison node voltage, and the output end of the comparator outputs a first control signal; the control signal generation module is used for controlling the first branch circuit, the second branch circuit and the comparator through starting control signals generated by the logic gate combination; the first branch comprises a plurality of resistors and PMOS (P-channel Metal Oxide Semiconductor) tubes which are connected in series, and a first voltage node is led out among the resistors; the second branch comprises a plurality of resistors which are connected in series, and second voltage nodes are led out among the resistors; and the selector is used for connecting the first voltage node or the second voltage node to the second input end of the comparator module according to the state of the first control signal. The starting reliability and robustness of the band-gap reference circuit can be improved, and the circuit power consumption after starting is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of bandgap reference source startup circuits, and in particular relates to a comparator type startup circuit and a chip for a bandgap reference source. Background Art

[0002] As a key module in analog circuit systems, bandgap reference circuits provide a stable reference voltage for various analog integrated circuits, ensuring proper circuit operation. Their output stability directly impacts the performance and reliability of the entire chip. For example, in an ADC (analog-to-digital converter) or DAC (digital-to-analog converter), a bandgap voltage reference circuit provides a stable reference for the conversion process, ensuring accuracy. In an LDO (low drop-out regulator), a bandgap voltage reference circuit ensures output voltage stability, improving power supply quality. In high-precision comparators, a bandgap voltage reference circuit provides a precise reference voltage, making comparison results more accurate and reliable.

[0003] In traditional designs, bandgap circuits often rely on self-biasing structures for startup, or use external current mirrors and auxiliary paths to forcefully establish an operating point. Chinese invention patent application publication number CN102385405A discloses a universal bandgap reference startup circuit. This startup circuit utilizes a current comparison structure, consisting of a self-bias circuit, a current mirror comparator circuit, and a pull-down transistor. When used in a voltage-mode bandgap reference startup circuit, the reference current only needs to fall within a certain range, resulting in a simple circuit structure. When used in a current-mode bandgap reference circuit, if the bandgap reference circuit is operating in an erroneous state due to multiple degenerate points, the current comparison result quickly activates the startup circuit, returning the bandgap reference circuit to normal operation. Simultaneously, the new current comparison result immediately shuts down the startup circuit, without affecting the reference circuit.

[0004] Because these structures typically lack an effective judgment mechanism, whether the system successfully establishes a stable reference voltage during power-up often depends on the device's inherent process consistency and power supply ramp-up characteristics, resulting in a certain degree of uncertainty. Furthermore, under extreme process corners, low temperature, and low voltage operating conditions, the bandgap circuit can easily fail to start up properly or experience excessive startup times, impacting chip performance. Furthermore, continued operation of the startup circuit after startup can result in high static power consumption. Summary of the Invention

[0005] The present invention provides a comparator type startup circuit and chip for a bandgap reference source, aiming to solve the problems of low reliability and robustness, high static power consumption, etc. of the existing bandgap reference source startup circuit.

[0006] In order to solve the above technical problems, the starting circuit proposed by the present invention includes: Bandgap core circuit, generating a reference voltage at the output; a comparator, wherein a first input terminal receives the reference voltage, a second input terminal receives the comparison node voltage, and an output terminal outputs a first control signal; A control signal generating module, which generates a start control signal through a logic gate combination based on the power-on signal, the enable signal and the second control signal, and is used to control the first branch, the second branch and the comparator; The first branch includes a plurality of resistors and PMOS transistors connected in series, one end of which is connected to a power supply and the other end is grounded, and a first voltage node is drawn between the resistors; The second branch includes a plurality of resistors connected in series, one end of which is connected to a power supply and the other end is grounded, and a second voltage node is drawn between the resistors; The selector connects the first voltage node or the second voltage node to the second input terminal of the comparator module according to a state of the first control signal.

[0007] Preferably, the first control signal is converted into a third control signal after passing through an inverter.

[0008] Preferably, the circuit further comprises a delay module for receiving the third control signal and delaying the output of a level stability indication signal to indicate a stable state of the bandgap voltage.

[0009] Preferably, the delay module specifically includes: a current source control structure, further comprising PMOS transistors PM11 and PM12, an NMOS transistor NM11, and a resistor R0, for establishing a delayed current path in response to a third control signal; A logic cascade structure further includes NMOS transistors NM12 and NM13 for responding to the control signal to determine the release of the delay path; a level shaping circuit, comprising a first Schmitt trigger SMT1 and a second Schmitt trigger SMT2, for anti-interference judgment of the level change; An intermediate level buffer structure composed of a PMOS transistor PM13 and an NMOS transistor NM14; An output port outputs a level stability indication signal through an inverter at the rear end of the second Schmitt trigger.

[0010] Preferably, the circuit further comprises a plurality of power-on auxiliary transistors arranged at the rear end of the comparator, for providing a weak current to enable the differential input node of the bandgap core to escape from the 0 level during the startup phase, thereby assisting the bandgap circuit to start quickly and enter a stable working state.

[0011] Preferably, the circuit includes a current mirror structure circuit for providing a comparator bias current during a startup phase.

[0012] Preferably, the current mirror structure circuit is specifically: A pair of PMOS transistors PM0 and PM1 with connected gates, wherein the source of PM0 is connected to the power supply and the drain outputs the bias current; the source of PM1 is connected to the power supply and the drain is connected to its own gate through a PMOS transistor PM4; A PMOS transistor PM6 is capacitively connected between the gate of PM0 and the power supply; Among them, the drain of PM4 is connected to the drain of PM1, the source is connected to the gate of PM1, and the gate is connected to the start control signal.

[0013] Preferably, the first branch includes a PMOS transistor PM1, a resistor R1, a resistor R2, a resistor R3 and a switching transistor Q1 in order from the power supply to the ground; the first voltage node is drawn between the resistors R2 and R3.

[0014] Preferably, the second branch includes a PMOS transistor PM2, a resistor R4, a resistor R5, and a resistor R6 in order from the power supply to the ground; the second voltage node is drawn between the resistors R4 and R5; The source of PM2 is connected to the power supply, the drain is connected to one end of the resistor R4, and the gate is connected to the start control signal.

[0015] Correspondingly, the present invention further provides a near field communication chip, comprising a bandgap reference source, wherein the bandgap reference source is started using the above-mentioned starting circuit.

[0016] Compared with the prior art, the present invention has the following technical effects: 1. The startup circuit proposed in this invention uses logic signals to step-by-step control of the branch resistor network and comparator enable state, forming a clear multi-stage startup path. By managing two auxiliary branches with startup control signals, dynamic control of the comparator input level and bias point is achieved, allowing the bandgap reference circuit to gradually establish its operating state at different stages, significantly improving startup reliability and robustness.

[0017] 2. To ensure the bandgap circuit output reaches a stable state before switching logic, the startup circuit proposed in this invention introduces a MOS capacitor structure (such as PM6) and a delay module into the startup path, implementing a soft delay based on analog timing. This mechanism suppresses short-term oscillations in the bandgap output caused by power supply disturbances or load coupling during the buildup process, effectively preventing false positives and ensuring system stability.

[0018] 3. The startup circuit proposed in this patent differs from some existing technologies, which use a comparator and startup branch that always operate, resulting in static power consumption. This patent design incorporates a complete startup exit mechanism. When the bandgap output voltage stabilizes, a logic control signal (such as the first control signal STB_VFB) automatically shuts down the comparator and auxiliary branch, putting the entire startup circuit into a shutdown state. This minimizes current consumption and is particularly suitable for applications in low-power chips such as NFC, security chips, or battery-powered systems.

[0019] 4. The comparator used in the startup circuit proposed in this invention not only determines the voltage during startup but also controls the switching of analog switch S2. Combining the START_P and START_N signals, this achieves adaptive linkage control of the startup signal and voltage status, effectively preventing "false starts" caused by system delays, drift, and other phenomena.

[0020] 5. The startup circuit proposed in this invention introduces a MOS capacitor isolation structure (such as a PM6 buffer) between the comparator and the bias circuit, achieving the characteristic of gradually building up the bias current. This effectively reduces the sudden current at the initial startup of the comparator, improves the device protection capability, and avoids transient interference to the bandgap core circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a circuit schematic diagram of the starting circuit of the present invention; Figure 2 is a circuit schematic diagram of the control signal generating module according to an embodiment of the present invention; Figure 3 is a circuit schematic diagram of the delay module according to an embodiment of the present invention; Figure 4 1 is a schematic diagram of the internal circuit of the comparator described in this embodiment; Figure 5 4 is a timing diagram of various signals of the startup circuit according to an embodiment of the present invention during startup. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in combination with specific embodiments of the present application and with reference to the accompanying drawings.

[0023] Example 1 This embodiment is a comparator type startup circuit for a bandgap reference source, such as Figure 1 As shown, it includes a bandgap core circuit, a comparator, a first branch, a second branch, a control signal generation module and a selector.

[0024] The output end of the bandgap core circuit generates a reference voltage VREF. Figure 1The bandgap core shown provides a reference voltage, VREF. VP0 and VP1 are the gate voltages for the PMOS current mirrors in the bandgap core circuit. During startup, they provide a small current to the PMOS mirrors, allowing them to escape zero current and thus enabling the bandgap core to operate smoothly. PTAT_0 is the positive temperature coefficient current generated by the bandgap core. In this embodiment, the PTAT_0 signal is transmitted to a delay module, which generates a VBG_OK signal. The VBG_OK signal indicates that the bandgap has entered a stable state. The VBG_OK signal can also be used as an enable signal for power management modules, LDO modules, and so on.

[0025] Figure 1 The comparator CMP is at the lower left, a first input terminal of which receives the reference voltage VREF, a second input terminal of which receives the comparison node voltage VSENX, and an output terminal of which outputs a first control signal START_P.

[0026] The control signal generation module generates a start control signal based on the power-on signal, the enable signal and the second control signal through a logic gate combination, and is used to control the first branch, the second branch and the comparator. Figure 2 As shown, the initial signals include a low-level signal PTAT_PD, power supply AVDD, an enable signal PTAT_P, a second control signal STB_VFB, PTAT_N, and a bandgap enable signal PD. The second control signal STB_VFB is the startup circuit control signal; the low-level signal PTAT_PD can be directly connected to the power ground AVSS; and the PD signal is the enable signal for the entire bandgap module. It is also at a low level by default and can be directly connected to the power ground AVSS.

[0027] The initial low-level signal PTAT_PD passes through two stages of inverters, resulting in a high-level signal PTAT_N at the output of the first-stage inverter and a low-level signal PTAT_P at the output of the second-stage inverter. The default low-level PD signal also passes through two stages of inverters, resulting in a high-level signal PDN at the output of the first-stage inverter and a low-level signal PDP at the output of the second-stage inverter. AVDD and PTAT_P pass through an AND gate, then join the STB_VFB and PTAT_N signals, which have passed through another AND gate, and are input into a NOR gate. The output of this NOR gate, combined with the aforementioned PDP, is then input into another NOR gate and fed into two stages of inverters, producing the signal ST_PDP at the output of the first-stage inverter and the signal ST_PDN at the output of the second-stage inverter.

[0028] The first branch includes several resistors and PMOS transistors connected in series. One end of this branch is connected to the power supply AVDD and the other end is connected to the ground AVSS. A first voltage node is derived between the resistors. Specifically, the first branch includes, in order from the power supply AVDD to the ground AVSS, a PMOS transistor PM1, resistors R1, R2, R3, and a switching transistor Q1. The source of PM1 is connected to the power supply AVDD and the drain is connected to the resistor R1. The first voltage node is derived between resistors R2 and R3.

[0029] The second branch includes several resistors connected in series. One end of this branch is connected to the power supply AVDD and the other end is connected to the ground AVSS. A second voltage node is generated between the resistors. Specifically, the second branch includes a PMOS transistor PM2, a resistor R4, a resistor R5, and a resistor R6 in the direction from the power supply AVDD to the ground AVSS. The source of PM2 is connected to the power supply AVDD, and the drain is connected to the resistor R4. The second voltage node is generated between the resistors R4 and R5.

[0030] The selector connects the first voltage node or the second voltage node to the second input terminal of the comparator module according to a state of the first control signal.

[0031] The startup circuit of this embodiment further includes a delay module configured to receive the third control signal and delay outputting a level stability indication signal indicating the bandgap voltage is stable. In conjunction with the delay module of this embodiment, the output terminal of the comparator receives the first control signal START_P through an inverter to generate the third control signal START_N.

[0032] like Figure 3 As shown, the delay module specifically includes: a current source control structure, a logic cascade structure, a level shaping circuit, an intermediate level buffer structure and an output port.

[0033] A current source control structure further includes PMOS transistors PM11 and PM12, an NMOS transistor NM11, and a resistor R0, configured to establish a delay current path in response to a third control signal. The source of PM11 is connected to the input bias current IB_DELAY of the delay module. In this embodiment, PTAT_0 serves as the input bias current IB_DELAY of the delay module. The drain of PM11 is connected to the source of PM12. The source of NM11 is grounded, and its drain is connected to the drain of PM2. The gate of PM1 is connected to the third control signal START_N, and the gates of PM12 and NM11 are connected to the signal PDP.

[0034] A logic cascade structure further includes NMOS transistors NM12 and NM13, which are used to respond to the control signal to determine the release of the delay path; wherein NM13 is capacitively connected between the gate of PM2 and the ground AVSS.

[0035] A level shaping circuit includes a first Schmitt trigger SMT1 and a second Schmitt trigger SMT2, which are used to detect the level change in an anti-interference manner; an NMOS transistor NM15 is also connected capacitively between the input end of SMT2 and the ground AVSS.

[0036] An intermediate-level buffer structure is formed by a PMOS transistor PM13 and an NMOS transistor NM14; wherein the source of PM13 is connected to the power supply AVDD, the drain is connected to the drain of NM14 and the input terminal of SMT2, and the source of NM14 is grounded; the gates of PM13 and NM14 are both connected to the output terminal of SMT1.

[0037] An output port outputs a level stable indication signal VBG_OK through an inverter at the rear end of the second Schmitt trigger.

[0038] The startup circuit described in this embodiment further includes a plurality of power-on startup auxiliary transistors arranged at the rear end of the comparator. The auxiliary transistors are PMOS tubes, such as Figure 1 PM8 and PM9 are shown. PM8's gate is connected to the first startup signal START_P, its source is connected to signal VP0, and its drain is grounded. PM9's source is connected to VP1 and its drain is grounded. Signals VP0 and VP1 are connected to the gates of the PMOS current mirrors of the bandgap core module. These auxiliary transistors provide a weak current to lift the differential input nodes of the bandgap core from zero during startup, helping the bandgap circuit quickly start up and enter a stable operating state.

[0039] The startup circuit of this embodiment further includes a current mirror structure circuit for providing a comparator bias current during the startup phase. The current mirror structure circuit is specifically: A pair of PMOS transistors PM0 and PM1 with connected gates, wherein the source of PM0 is connected to the power supply and the drain outputs the bias current IB_CMP; the source of PM1 is connected to the power supply and the drain is connected to its own gate through a PMOS transistor PM4; A PMOS transistor PM6 is capacitively connected between the gate of PM0 and the power supply; The drain of PM4 is connected to the drain of PM1 , the source is connected to the gate of PM1 , and the gate is connected to the start control signal ST_PDP.

[0040] In this current mirror structure circuit, the conduction of PM0 depends on the gate voltage control of PM1, and the current is copied to PM0. PM1 needs to form a current mirror connected to the GD terminal to form a gate voltage. Therefore, when PM4 is turned on by the low-level start control signal ST_PDP signal, after connecting the gate and drain of PM1 (GD pole), there is a gate voltage to PM0 and the current is copied to its drain comparator CMP.

[0041] The working process of the startup circuit described in this embodiment is as follows: The power supply AVDD voltage is quickly powered on within 10us. At this time, PD and PTAT_PD are zero, and the second control signal STB_VFB is powered on. After the half-high level, Figure 2 The logic gate shown is evaluated as a high level, and after passing through the logic gate, a start control signal ST_PDP is output; ST_PDP is an enable signal for the first branch L1, the second branch L2 and the comparator CMP. As shown in the waveform, the bias voltages of VSENH and VSENL begin to rise.

[0042] The start control signal ST_PDP is also connected to the inside of the comparator. Inside the comparator, when the power supply voltage is high, ST_PDP also goes high, so that the comparator outputs the first control signal START_P at a high level. Specifically, Figure 4 Figure 2 shows a schematic diagram of the internal circuitry of the comparator according to this embodiment, illustrating how ST_PDP directly controls the comparator to output a high-level first control signal, START_P. When the power supply AVDD voltage rises, PDP and ST_PDP also rise high, turning on NMOS transistor M7 within the comparator and forcibly pulling it to ground. After passing through trigger I4, the comparator outputs a high-level signal, indicating that ST_PDP directly controls the comparator to output the high-level first control signal, START_P.

[0043] After the first control signal START_P is high, the selector S2 selects VSENL, making VSENX equal to the voltage value of VSENH. Since the NMOS tube capacitor of branch L3 is connected to the buffer of NM1, VSENX slowly climbs, and since the capacitively connected PM6 plays a delay role, the first control signal START_P has not yet flipped, and finally the bias current IB_CMP slowly flows into the comparator, and the internal tube of the comparator works with a delay.

[0044] When the comparator is officially working, since VSENX is greater than the reference voltage VREF, the first control signal START_P is output as a low level, and the switch S2 is switched to VSENH. At this time, VSENX=VSENH. Figure 5 This is the startup timing diagram of the startup circuit described in this embodiment. The timing from top to bottom are STB_VFB, PTAT_N, ST_PDP, ST_PDN, VSENH, VSENL, VSENX, START_P, START_N, PV0, PV1, VREF and VBG_OK. Figure 5In the figure, the red line representing VSENH and the gray line representing VSENL show that the two voltages rise synchronously, indicating that the two branches L1 and L2 begin to generate voltage. At the same time as VSENH or VSENL rises high, it can be seen from the purple line representing VSENX that VSENX also rises synchronously and first reaches the voltage of VSENL. This is because the first control signal STSRT_P has been high. When the comparator starts working, since VSENX is higher than the reference voltage VREF, STSRT_P turns to output a low level, which then passes VSENX to VSENH, which is manifested in Figure 5 The VSENX voltage in the circuit rises to the VSENH voltage for the second time. The key to this design is that VSENX increases from low to high. In this embodiment, a relatively high VSENH voltage is set. When the reference voltage VREF exceeds VSENH, the bandgap is considered to have started operating, and the startup circuit of this embodiment has completed its startup task. The delay module then determines when the bandgap reference voltage VREF stabilizes and outputs a stable signal, VBG_OK.

[0045] Specifically, PM8 and PM9 tubes generate a tiny current that causes the bandgap core circuit to break away from zero potential and start working; the bandgap reference voltage VREF begins to rise. When the voltage value exceeds the VSENX value, the first control signal START_P is output as a high level, and the third control signal START_N is output as a low level after passing through the inverter and sent to the delay module. After passing through the delay module, the VBG_OK signal is output to indicate that the bandgap output is stable.

[0046] The second control signal STB_VFB can be normally open or pulled down to ground. When it falls, the start control signal ST_PDP is pulled high to turn off the first branch L1, the second branch L2 and the comparator CMP. The first control signal START_P is controlled by the start control signal ST_PDP and remains at a high level. At this point, the startup circuit is turned off and enters low power consumption mode.

[0047] It should be noted that in Figure 5In the startup timing diagram shown, the horizontal axis is the time axis, with the minimum value being 0.0 and the maximum value being 280.0, in microseconds. The vertical axis is the voltage of each signal, from top to bottom. The first green line represents the voltage of STB_VFB, which ranges from -0.33 to 3.63V in the diagram; the second line represents the voltage of PTAT_N, which ranges from -0.33 to 3.63V in the diagram; the third line represents the voltage of ST_PDP, which ranges from -0.344 to 3.64V in the diagram; the fourth line represents the voltage of ST_PDN, which ranges from -0.344 to 3.66V in the diagram; the fifth line represents the voltage of VSENH, which ranges from -102.8 to 879mV in the diagram; the sixth line represents the voltage of VSENL, which ranges from -76.22 to 772.9mV in the diagram; the seventh line represents V The voltage of SENX ranges from -78.69 to 820.5V in the figure; the eighth line represents the voltage of START_P, which ranges from -0.349 to 3.67V in the figure; the ninth line represents the voltage of START_N, which ranges from -0.359 to 3.68V in the figure; the tenth line represents the voltage of PV0, which ranges from -0.329 to 3.62V in the figure; the eleventh line represents the voltage of VP1, which ranges from -0.328 to 3.61V in the figure; the twelfth line represents the voltage of VREF, which ranges from -0.293 to 3.2V in the figure; the twelfth line represents the voltage of VBG_OK, which ranges from -0.377 to 3.64V in the figure.

[0048] In this embodiment, after VBG_OK is raised, the total operating current of the startup circuit is stabilized at 650 nA, and the circuit enters a low power consumption state.

[0049] like Figure 1 As shown, some other embodiments of the present invention further include a third branch L3, which is a PTAT current branch.

[0050] Example 2 This embodiment is a near field communication chip, including a bandgap reference source, which is started using the starting circuit described in the first embodiment.

[0051] The above description is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this field, several variations and improvements can be made without departing from the creative concept of the present invention, which all fall within the scope of protection of the present invention.

Claims

1. A comparator type startup circuit for a bandgap reference source, characterized in that: include: Bandgap core circuit, generating a reference voltage at the output; a comparator, wherein a first input terminal receives the reference voltage, a second input terminal receives the comparison node voltage, and an output terminal outputs a first control signal; A control signal generating module, which generates a start control signal through a logic gate combination based on the power-on signal, the enable signal and the second control signal, and is used to control the first branch, the second branch and the comparator; The first branch includes a plurality of resistors and PMOS transistors connected in series, one end of which is connected to a power supply and the other end is grounded, and a first voltage node is drawn between the resistors; The second branch includes a plurality of resistors connected in series, one end of which is connected to a power supply and the other end is grounded, and a second voltage node is drawn between the resistors; The selector connects the first voltage node or the second voltage node to the second input terminal of the comparator module according to a state of the first control signal.

2. The circuit according to claim 1, characterized in that The first control signal is converted into a third control signal after passing through an inverter.

3. The circuit according to claim 2, characterized in that The circuit further includes a delay module, configured to receive the third control signal and output a level stability indication signal with a delayed time, indicating a stable state of the bandgap voltage.

4. The circuit according to claim 1, wherein: The delay module specifically includes: a current source control structure, further comprising PMOS transistors PM11 and PM12, an NMOS transistor NM11, and a resistor R0, for establishing a delayed current path in response to a third control signal; A logic cascade structure further includes NMOS transistors NM12 and NM13 for responding to the control signal to determine the release of the delay path; a level shaping circuit, comprising a first Schmitt trigger SMT1 and a second Schmitt trigger SMT2, for anti-interference judgment of the level change; An intermediate level buffer structure composed of a PMOS transistor PM13 and an NMOS transistor NM14; An output port outputs a level stability indication signal through an inverter at the rear end of the second Schmitt trigger.

5. The circuit according to claim 1, wherein: The circuit also includes several power-on startup auxiliary transistors arranged at the back end of the comparator, which are used to provide weak current to enable the differential input nodes of the bandgap core to escape from the 0 level during the startup phase, thereby assisting the bandgap circuit to start quickly and enter a stable working state.

6. The circuit according to claim 1, wherein: The circuit includes a current mirror structure circuit for providing a comparator bias current during a startup phase.

7. The circuit according to claim 6, characterized in that The current mirror structure circuit is specifically: A pair of PMOS transistors PM0 and PM1 with connected gates, wherein the source of PM0 is connected to the power supply and the drain outputs the bias current; the source of PM1 is connected to the power supply and the drain is connected to its own gate through a PMOS transistor PM4; A PMOS transistor PM6 is capacitively connected between the gate of PM0 and the power supply; Among them, the drain of PM4 is connected to the drain of PM1, the source is connected to the gate of PM1, and the gate is connected to the start control signal.

8. The circuit according to claim 1, wherein: The first branch includes a PMOS transistor PM1, a resistor R1, a resistor R2, a resistor R3 and a switching transistor Q1 in order from the power supply to the ground; the first voltage node is drawn between the resistors R2 and R3.

9. The circuit according to claim 1, wherein: The second branch includes a PMOS transistor PM2, a resistor R4, a resistor R5, and a resistor R6 in order from the power supply to the ground; the second voltage node is drawn between the resistors R4 and R5; The source of PM2 is connected to the power supply, the drain is connected to one end of the resistor R4, and the gate is connected to the start control signal.

10. A near field communication chip, comprising a bandgap reference source, characterized in that: The bandgap reference source is started using the starting circuit according to any one of claims 1 to 9.

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