Multi-mode VMID voltage generation circuit and chip

Abstract

The invention discloses a multi-mode VMID voltage generation circuit and a chip, which are used for providing required reference voltage for an NFC chip, and comprise a mode selection circuit used for receiving an externally input control signal and selecting an output mode according to the control signal; the resistance voltage division mode circuit is connected with the mode selection circuit and is selected in the first control mode so as to output the VMID voltage in the resistance voltage division mode; a boost mode circuit selected in the second control mode to output the VMID voltage in the boost mode; a low-level mode circuit selected in a third control mode to output a VMID voltage in a low-level mode; and the floating mode output end is directly connected to the output end in the fourth control mode, so that the output end is in a floating state. The circuit has the advantages of being high in safety and reliability, low in power consumption and simple in implementation circuit, and various output modes can be provided to be matched with different working scenes of the NFC chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of near field communication chips, and in particular relates to a multi-mode VMID voltage generating circuit and chip. Background Art

[0002] In analog and mixed-signal circuits, a voltage midpoint (VMID) provides a stable intermediate reference point within the supply voltage range. It's used for differential signal processing, level biasing, or as a reference voltage for certain low-power modules. It provides a stable reference point for analog circuits. In NFC (Near Field Communication) chips, VMID is primarily used in the following scenarios: It's used as a reference voltage point in the receive signal conditioning circuitry of the radio frequency (RF) analog front-end to help recover weak signals received from the antenna; it provides a stable bias point to maintain the linear operating range of analog signal processing; it provides a reference bias in analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) to ensure input / output signals fluctuate within appropriate levels; it's used as a reference point in low-power states, such as in NFC standby mode, where the VMID is switched to low or floating to save power; and it's used in data communication between different voltage domains to provide an intermediate voltage for matching logic levels.

[0003] Chinese invention patent application publication number CN119276091A discloses a low standby power VMID voltage generator, which is applied to a driver IC to provide a VMID voltage to the driver IC. The VMID voltage generator includes a high-power VMID voltage generating circuit and an ultra-low-power VMID voltage generating circuit. The high-power VMID voltage generating circuit is composed of high-power electronic components. The ultra-low-power VMID voltage generating circuit is composed of ultra-low-power electronic components. When the driver IC operates in normal mode, the high-power VMID voltage generating circuit is turned on and the ultra-low-power VMID voltage generating circuit is turned off, and the VMID voltage is generated by the high-power VMID voltage generating circuit. When the driver IC operates in standby mode, the high-power VMID voltage generating circuit is turned off and the ultra-low-power VMID voltage generating circuit is turned on, and the VMID voltage is generated by the ultra-low-power VMID voltage generating circuit.

[0004] However, the above solution only provides two VMID voltage output modes: normal mode and standby mode, which correspond to the activation of the high-power voltage generation circuit and the low-power voltage generation circuit respectively. However, the design does not take into account the dynamic change of the output VMID current with the load change, and lacks a real-time response mechanism to current surges or overload conditions. It is easy to cause the power tube to be overdriven for a long time under abnormal load conditions, thereby causing voltage drops, power supply interference or system instability. Summary of the Invention

[0005] The present invention provides a multi-mode VMID voltage generating circuit and chip, aiming to solve the problems of insufficient output mode matching and insufficient current protection in the prior art.

[0006] To solve the above technical problems, the VMID voltage generation circuit proposed in the present invention is used to provide the required reference voltage for the NFC chip, including: A mode selection circuit, configured to receive an external control signal and select an output mode according to the control signal; a resistor voltage division mode circuit, connected to the mode selection circuit, and selected in the first control mode to output the VMID voltage in the resistor voltage division mode; a boost mode circuit, connected to the mode selection circuit and selected in the second control mode to output a VMID voltage in a boost mode; a low level mode circuit, connected to the mode selection circuit and selected in a third control mode to output a VMID voltage in a low level mode; Floating mode output end: in the fourth control mode, the mode selection circuit does not select any circuit among the resistance voltage divider mode, the boost mode and the low level mode, and is directly connected to the output end to realize the floating state of the output end.

[0007] Preferably, the control signal is a 3-bit signal with a value range of 000-111.

[0008] Preferably, the resistance voltage divider mode circuit includes a positive voltage side circuit, a ground side circuit and a logic gate; The positive voltage side circuit is connected to the output node after sequentially connecting a PMOS tube and a plurality of resistors in series from the positive power supply node, and is further provided with a plurality of PMOS tubes for selecting different resistor series combinations; The ground side circuit is connected to the output node after sequentially connecting an NMOS transistor and a plurality of resistors in series from the ground node, and is further provided with a plurality of NMOS transistors for selecting different resistor series combinations; The logic gates are four groups of identical circuits, each group of circuits includes two inverters arranged in series, and each group of front-stage inverters receives control signals 000, 001, 010 and 011 respectively. The output of the front-stage inverter is used to control different PMOS to be turned on or off, and the output of the rear-stage inverter is used to control different NMOS to be turned on or off.

[0009] Preferably, the positive voltage side circuit includes four resistors connected in series, which are R3A, R2A, R1A and R0A from the positive power node to the output node, and the resistance ratio is 4:2:1:1; The ground side circuit includes four resistors connected in series, which are R3B, R2B, R1B and R0B from the ground node to the output node, and the resistance ratio is 4:2:1:1.

[0010] Preferably, the positive voltage side circuit includes four PMOS transistors P3, P2, P1 and P0, P3 is connected in series with four resistors, P2 is connected in series with R2A, R1A and R0A, P1 is connected in series with R1A and R0A, and P0 is connected in series with R0A; the equivalent width-to-length ratio of P0, P1, P2 and P3 is 8:4:2:1; The ground side circuit includes four NMOS tubes N3, N2, N1 and N0, N3 branch is connected in series with four resistors, N2 branch is connected in series with R2B, R1B and R0B, N1 branch is connected in series with R1B and R0B, and N0 branch is connected in series with R0B; the equivalent width-to-length ratio of N0, N1, N2 and N3 is 8:4:2:1.

[0011] Preferably, the boost mode circuit includes: a bandgap reference circuit for outputting a stable reference voltage; an error amplifier circuit, one input of which is connected to the reference voltage, the other input of which is connected to the feedback voltage, and the output of which controls the gate voltage of the first NMOS transistor; a current mirror circuit, comprising the first NMOS transistor, the first PMOS transistor, and a second PMOS transistor serving as a power output transistor, for adjusting an output voltage according to an output of an error amplifier; a feedback circuit comprising two resistors connected in series, wherein a voltage division node thereof provides a feedback voltage; a current limiting circuit comprising a third PMOS transistor, a plurality of resistors, and a control transmission gate, for achieving foldback current limiting control by raising the gate voltage of the second PMOS transistor when the output current increases and the output voltage drops; The transmission gate is controlled by an external input control signal and is used to turn on or off the current limiting function.

[0012] Preferably, the boost mode circuit includes: a bandgap reference circuit for outputting a stable reference voltage; an error amplifier circuit, one input of which is connected to the reference voltage, the other input of which is connected to the feedback voltage, and the output of which controls the gate voltages of the second NMOS transistor and the third NMOS transistor; a current mirror circuit, comprising the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and a fifth PMOS transistor serving as a power output transistor, for adjusting the output voltage according to the output of the error amplifier; a feedback circuit comprising two resistors connected in series, wherein a voltage division node thereof provides a feedback voltage; a current limiting circuit comprising a second NMOS transistor, a third NMOS transistor, and two transmission gates connected in series, for selectively turning on NMOS transistors with different width-to-length ratios according to an external control signal to adjust a mirror current; The transmission gate is used to select and turn on the second NMOS transistor or the third NMOS transistor according to an external input control signal; The width-to-length ratio of the second NMOS transistor is greater than that of the third NMOS transistor.

[0013] Preferably, the low level mode circuit includes: At least two inverters connected in series, for performing logic inversion on an input control signal; An NMOS transistor, with its gate connected to the output terminal of the last-stage inverter, its source connected to the ground node, and its drain connected to the output node; A resistor is connected between the output node and the drain of the NMOS tube.

[0014] Preferably, the control signal state for turning on the floating mode is 101.

[0015] Another aspect of the present invention further provides a near field communication chip, which includes the voltage generating circuit described in the first aspect of the present invention.

[0016] Compared with the prior art, the present invention has the following technical effects: 1. The VMID voltage generation circuit proposed in the present invention provides a multi-mode VMID voltage generation circuit that can output VMID voltages in different modes, such as resistance voltage divider mode, low-level mode, floating mode, and boost mode. It can be applied to different working scenarios of NFC chips. For example, when the NFC chip operates under normal communication or stable load conditions, the present invention can provide a stable and low-power intermediate reference voltage, which is suitable for the reference voltage supply of the NFC receiving circuit; it can also provide a low-level mode for test scenarios or specific function logic zeroing operations to ensure that the VMID node level is clear, which helps to avoid malfunction caused by the floating state; through the floating mode, all active devices connected to the VMID are turned off, putting the VMID in a high-impedance state, which is suitable for chip testing, off-chip access detection, or special low-power requirements. It avoids the VMID node introducing additional current paths and reduces the static power consumption of the system.

[0017] 2. The boost mode circuit of the VMID voltage generation circuit proposed in this invention includes a bandgap reference circuit, an error amplifier, a power transistor, and a current-limiting branch, which is used to dynamically limit the output current as the load gradually increases. When the VMID load is large or abnormal, the output current rise rate can be dynamically controlled to avoid overloading the power transistor, ensuring the stability of the NFC receiving circuit in complex electromagnetic environments, while also improving the system's anti-interference capability and reliability, and protecting the circuit module when output abnormalities occur.

[0018] 3. In the low-level mode of the VMID voltage generating circuit proposed in the present invention, the VMID node is pulled to a low level by controlling the conduction of the switch tube, and other power supply paths are turned off, so that the VMID node is only maintained at a low potential without continuous power supply current flowing. The static current consumption in this mode is only at the picoampere (pA) to nanoampere (nA) level, which is significantly lower than the traditional voltage drive method. It has the advantage of extremely low power consumption and is particularly suitable for low-power maintenance voltage requirements when the chip enters the standby state. Compared with the method of maintaining a low level through a constant current source or a resistor network in the prior art, the low-level mode of the present invention realizes the true disconnection of the high-resistance path in the circuit structure, and only retains a very small leakage current channel. Therefore, when maintaining the VMID at a low level, pA-nA level power consumption can be achieved, greatly reducing the overall standby power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of the VMID voltage generating circuit of the present invention; Figure 2 is a circuit schematic diagram of a resistor voltage divider mode circuit according to an embodiment of the present invention; Figure 3 is a circuit schematic diagram of the boost mode circuit according to the first embodiment of the present invention; Figure 41 is a trend diagram of the gate voltage of the power output tube of the foldback current limiting boost circuit according to an embodiment of the present invention; Figure 5 is an output current trend diagram of the boost circuit with foldback current limiting according to an embodiment of the present invention; Figure 6 is a circuit schematic diagram of a low-level mode circuit according to an embodiment of the present invention; Figure 7 is a circuit schematic diagram of a boost mode circuit according to a second embodiment of the present invention; Figure 8 This is a trend diagram of the output current of the boost circuit with simple current limiting according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in combination with specific embodiments of the present application and with reference to the accompanying drawings.

[0021] Example 1 This embodiment is a multi-mode VMID voltage generating circuit for providing the required reference voltage for the NFC chip, such as Figure 1 As shown, it includes a mode selection circuit, a resistor voltage divider mode circuit, a boost mode circuit, a low level mode circuit and a floating mode output terminal.

[0022] The mode selection circuit is used to receive an external control signal and select an output mode according to the control signal.

[0023] The control signal in this embodiment is a 3-bit signal with a value range of 000-111, with a total of 8 states. In other embodiments of the present invention, a 2-bit signal can be used to correspond to the four modes. The 2-bit signal has a total of 4 states and can match the four mode circuits.

[0024] The resistor voltage division mode circuit is connected to the mode selection circuit and is selected in the first control mode to output the VMID voltage in the resistor voltage division mode.

[0025] Specifically, such as Figure 2 As shown, the resistor voltage divider mode circuit includes a positive voltage side circuit, a ground side circuit and a logic gate. Figure 2 In the figure, the upper part is the positive voltage side circuit, and the components are set between the positive power supply AVDD and the VMID output node. The lower part is the ground side circuit, and the components are set between the ground node AVSS and the VMID output node. The M0-M7 related circuits on the left are logic gates.

[0026] The positive voltage side circuit is connected to the VMID output node after sequentially connecting a PMOS transistor and several resistors in series from the positive power supply node AVDD. Several PMOS transistors are also provided for selecting different resistor series combinations. In this embodiment, corresponding to a 3-bit control signal, the positive voltage side circuit is provided with four series resistors R3A, R2A, R1A, and R0A and four PMOS transistors P3, P2, P1, and P0. The specific connection method is as follows: Figure 2 As shown in Figure 1, P3, R3A, R2A, R1A, and R0A are connected in series from the positive power supply node AVDD to the VMID output node. P2 has one end connected to the positive power supply node AVDD and the other end connected between R3A and R2A. P1 has one end connected to the positive power supply node AVDD and the other end connected between R2A and R1A. P0 has one end connected to the positive power supply node AVDD and the other end connected between R1A and R0A. This completes the positive voltage side circuit connection.

[0027] With this connection, the P3 shunt is connected in series with four resistors, the P2 shunt is connected in series with R2A, R1A, and R0A, the P1 shunt is connected in series with R1A and R0A, and the P0 shunt is connected in series with R0A. When P0 is on, the positive voltage circuit is divided only by resistor R0A. When P0 is off and P1 is on, the positive voltage circuit is divided by resistors R0A and R1A in series. When P0 and P1 are off and P2 is on, the positive voltage circuit is divided by resistors R0A, R1A, and R2A in series. When P0, P1, and P2 are off and P3 is on, the positive voltage circuit is divided by resistors R0A, R1A, R2A, and R3A in series.

[0028] Furthermore, in this embodiment, the positive voltage side circuit includes four resistors connected in series, namely R3A, R2A, R1A and R0A from the positive power supply node AVDD to the VMID output node, and the resistance ratio is 4:2:1:1; the equivalent width-to-length ratio of P0, P1, P2 and P3 is 8:4:2:1.

[0029] The ground side circuit is connected to the VMID output node after sequentially connecting an NMOS transistor and several resistors in series from the ground node AVSS. Several NMOS transistors are also provided for selecting different resistor series combinations. In this embodiment, corresponding to a 3-bit control signal, the ground side circuit is provided with four series resistors R3B, R2B, R1B, and R0B and four NMOS transistors N3, N2, N1, and N0. The specific connection method is as follows: Figure 2As shown, N3, R3B, R2B, R1B, and R0B are connected in series from ground node AVSS to the VMID output node. One end of N2 is connected to ground node AVSS, and the other end is connected between R3B and R2B. One end of N1 is connected to ground node AVSS, and the other end is connected between R2B and R1B. One end of N0 is connected to ground node AVSS, and the other end is connected between R1B and R0B. This completes the ground-side circuit connection.

[0030] With this connection, the N3 shunt is connected in series with four resistors, the N2 shunt is connected in series with R2B, R1B, and R0B, the N1 shunt is connected in series with R1B and R0B, and the N0 shunt is connected in series with R0B. When N0 is on, the ground-side circuit is divided solely by resistor R0B. When N0 is off and N1 is on, the ground-side circuit is divided by resistors R0B and R1B in series. When N0 and N1 are off and N2 is on, the ground-side circuit is divided by resistors R0B, R1B, and R2B in series. When N0, N1, and N2 are off and N3 is on, the ground-side circuit is divided by resistors R0B, R1B, R2B, and R3B in series.

[0031] Furthermore, in this embodiment, the ground side circuit includes four resistors connected in series, namely R3B, R2B, R1B and R0B from the ground node AVSS to the VMID output node, and the resistance ratio is 4:2:1:1; the equivalent width-to-length ratio of N0, N1, N2 and N3 is 8:4:2:1.

[0032] In the positive voltage side circuit and the ground side circuit, the resistance relationship is as follows: R3A=R3B=2×R2A=2×R2B=4×R1A=4×R1B=4×R0A=4×R0B; That is, the electrical performance of the resistors in the symmetrical positions in the positive voltage side circuit and the ground side circuit is the same.

[0033] In the resistor voltage divider mode circuit described in this embodiment, corresponding to a 3-bit signal, the logic gate is four groups of identical circuits, each group of circuits includes two inverters arranged in series, and the control signals of the resistor voltage divider mode circuit are 000, 001, 010, and 011, respectively, which are input into the four groups of inverter series circuits. Figure 2As shown, inverters M0 and M4 form the first group, inverters M1 and M5 form the second group, inverters M2 and M6 form the third group, and inverters M3 and M7 form the fourth group. Each group of front-stage inverters receives control signals 000, 001, 010, and 011, respectively. Specifically, the first group of inverter circuits receives a control signal of 000, the second group of inverter circuits receives a control signal of 001, the third group of inverter circuits receives a control signal of 010, and the fourth group of inverter circuits receives a control signal of 011. In each group of inverter circuits, the outputs of the front-stage inverters M0-M3 are used to control the conduction or shutdown of different PMOS transistors, and the outputs of the back-stage inverters M4-M7 are used to control the conduction or shutdown of different NMOS transistors. Specifically, M0's output D0A is connected to the gate of P0, M1's output D1A is connected to the gate of P1, M2's output D2A is connected to the gate of P2, and M3's output D3A is connected to the gate of P3. The output D0B of M4 is connected to the gate of N0, the output D1B of M5 is connected to the gate of N1, the output D2B of M6 is connected to the gate of N2, and the output D3B of M7 is connected to the gate of N3.

[0034] In the resistor voltage divider circuit of this embodiment, when the external input control signal is 000, signal D000 is high. After passing through inverter M0, output signal D0A is low. After passing through inverter M4, output signal D0B is high. Low-level signal D0A turns on PMOS transistor P0, while high-level signal D0B turns on NMOS transistor N0. At this point, the output VMID voltage is R0B / (R0A+R0B)*AVDD=1 / 2AVDD. The forward voltage drops of PMOS transistors P0 and NMOS transistors N0 are negligible. The current flowing through PMOS transistor P0, resistor R0A, resistor R0B, and NMOS transistor N0 is AVDD / (R0A+R0B). The forward internal resistance of PMOS transistors P0 and NMOS transistors M0 is negligible. By analogy, we can conclude that when the external input control signals are 000, 001, 010, and 011, the resistor divider mode circuit outputs a VMID voltage of 1 / 2AVDD, and the currents flowing through it are AVDD / (R0A+R0B), AVDD / (R0A+R0B+R1A+R1B), AVDD / (R0A+R0B+R1A+R1B+R2A+R2B), and AVDD / (R0A+R0B+R1A+R1B+R2A+R2B+R3A+R3B), respectively. Based on the aforementioned resistor ratios and resistance value relationships, the current ratios are 16:8:4:2.

[0035] The boost mode circuit is connected to the mode selection circuit and is selected in the second control mode to output the VMID voltage in the boost mode. Corresponding to the 3-bit control signal, the second control mode selected by the boost mode circuit has a signal state of 110 or 111.

[0036] like Figure 3 As shown, the boost mode circuit is composed of a bandgap reference circuit, an error amplifier circuit, an output power tube circuit, a current limiting circuit, and a feedback circuit, specifically including: a bandgap reference circuit for outputting a stable reference voltage VREF; an error amplifier A1 circuit, one input of which is connected to the reference voltage VREF, the other input of which is connected to the feedback voltage VFB, and the output of which controls the gate voltage of the first NMOS transistor N1; a current mirror circuit, comprising the first NMOS transistor N1, the first PMOS transistor P1, and the second PMOS transistor P2 as a power output transistor, for adjusting the output voltage according to the output of the error amplifier A1; A feedback circuit includes two resistors R4 and R5 connected in series, wherein a voltage dividing node thereof provides a feedback voltage VFB; a current limiting circuit comprising a third PMOS transistor P3, a plurality of resistors R1, R2, R3 and a control transmission gate TG, for achieving foldback current limiting control by raising the gate voltage of the second PMOS transistor P2 when the output current increases and the output voltage drops; The transmission gate TG is controlled by an external input control signal and is used to turn on or off the current limiting function.

[0037] In the boost mode circuit described in this embodiment, please refer to Figure 3 The bandgap reference circuit outputs a reference voltage, VREF. Error amplifier circuit A1 is connected to VREF at one end and feedback voltage, VFB, at the other. VFB is obtained by dividing the output voltage, VMID, through the feedback circuit formed by resistors R4 and R5: VFB = R5 / (R4+R5)*VMID. The output of error amplifier A1 is connected to the gate of the first NMOS transistor N1. The first NMOS transistor N1, the first PMOS transistor P1, and the second PMOS transistor P2 form a current mirror circuit, with the second PMOS transistor P2 acting as a power transistor. The external input control signal controls whether the transmission gate TG enables the current limiting function. When the current limiting function is enabled, the gate voltage VG3 of the third PMOS transistor P3 = R2 / (R1+R2)*(AVDD-VMID)+VMID=(R2*AVDD+R1*VMID) / (R1+R2); the gate-source voltage VGS3 of the third PMOS transistor P3 = (R2*AVDD+R1*VMID) / (R1+R2)-(AVDD-VR3)=(VMID-AVDD)*R1 / (R1+R2)+VR3, where VR3 is the voltage drop across the resistor R3.

[0038] When the boost mode circuit is working, as the output load resistance gradually decreases, the output current gradually increases, the output VMID voltage gradually decreases, the gate voltage VG3 of P3 gradually decreases, and the gate-source voltage VGS3 of P3 also gradually decreases. When VGS3 is less than the turn-on voltage of P3, P3 turns on and pulls up the gate voltage VG2 of the power tube P2. Figure 4 As shown in the figure, the horizontal axis is the value of the output load resistance, which decreases from right to left to 0. When the current limiting function is not enabled, the VG2 voltage decreases as the output load resistance decreases; when the current limiting function is enabled, after P3 is turned on, the VG2 voltage rises, causing the output current to decrease, thus playing the role of foldback current limiting protection. Figure 5 As shown, I3 is the output current when the current limit function is disabled, and I4 is the output current when the foldback current limit protection function is enabled. In this case, the output current is significantly reduced compared to when the current limit function is enabled, protecting the circuit from output abnormalities and ensuring module safety. The current limit function is not required in other resistor divider modes, low-level mode, and floating mode.

[0039] The low-level mode circuit is connected to the mode selection circuit and is selected in a third control mode to output the VMID voltage in the low-level mode. Corresponding to the 3-bit control signal, the signal state of the third control mode selected by the low-level mode circuit is 100.

[0040] Specifically, such as Figure 6 As shown, the low level mode circuit includes: At least two inverters M1 and M2 connected in series, used to perform logic inversion on the input control signal; An NMOS transistor N1, with its gate connected to the output terminal of the last-stage inverter, its source connected to the ground node AVSS, and its drain connected to the VMID output node; A resistor R1 is connected between the VMID output node and the drain of the NMOS transistor N1.

[0041] In this low-level mode circuit, when the external input control signal is 100, D100 is at a high level, and after passing through inverters M1 and M2, a high-level signal is output, turning on the NMOS tube N1, and the output VMID voltage is pulled down to AVSS. The low-level mode circuit outputs a low-level voltage.

[0042] Floating mode output terminal. In the fourth control mode, the mode selection circuit does not select any of the resistor divider mode, boost mode, or low-level mode circuits and is directly connected to the output terminal, achieving a floating output terminal. Under this control signal, the resistor divider mode circuit, boost mode circuit, and low-level mode circuit are all disabled. At this time, the VMID output is in a floating state. This mode is used for NFC chip testing. Corresponding to the 3-bit control signal, the fourth control mode in which the floating mode is selected has a signal state of 101.

[0043] Example 2 This embodiment is a multi-mode VMID voltage generating circuit for providing the required reference voltage for the NFC chip, such as Figure 1 As shown, it includes a mode selection circuit, a resistor voltage divider mode circuit, a boost mode circuit, a low level mode circuit and a floating mode output terminal.

[0044] Among them, the mode selection circuit, the resistor voltage divider mode circuit, the low level mode circuit and the floating mode output terminal are the same as those described in the first embodiment, and the difference lies in the boost mode circuit.

[0045] In this embodiment, if Figure 7 As shown, the boost mode circuit has a simple current limiting function, including: a bandgap reference circuit for outputting a stable reference voltage VREF; an error amplifier circuit A1, one input of which is connected to the reference voltage VREF, the other input of which is connected to the feedback voltage VFB, and the output of which controls the gate voltages of the second NMOS transistor N2 and the third NMOS transistor N3; a current mirror circuit, comprising the second NMOS transistor N2, the third NMOS transistor N3, the fourth PMOS transistor P4, and a fifth PMOS transistor P5 serving as a power output transistor, for adjusting the output voltage according to the output of the error amplifier A1; a feedback circuit comprising two resistors R4 and R5 connected in series, wherein a voltage dividing node thereof provides a feedback voltage; a current limiting circuit comprising a second NMOS transistor N2, a third NMOS transistor N3 and two transmission gates TG connected in series, for selectively turning on NMOS transistors with different width-to-length ratios according to an external control signal to adjust the mirror current; The transmission gate TG is used to selectively turn on the second NMOS transistor N2 or the third NMOS transistor N3 according to an external input control signal; The width-to-length ratio of the second NMOS transistor N2 is greater than that of the third NMOS transistor N3.

[0046] In the boost mode circuit of this embodiment, this circuit is a simple current-limiting circuit that slows down the increase in output current. It consists of a bandgap reference circuit, an error amplifier circuit, an output power transistor circuit, a transmission gate, and a feedback circuit. The bandgap reference circuit outputs a reference voltage, VREF. Error amplifier circuit A1 is connected to VREF at one end and to feedback voltage, VFB, at the other. VFB is obtained by dividing the output voltage, VMID, through a feedback circuit formed by resistors R4 and R5: VFB = R5 / (R4+R5)*VMID. The output of error amplifier A1 is connected to the gates of NMOS transistors N2 and N3. NMOS transistors N2 and N3 and PMOS transistors P4 and P5 form a current mirror circuit, with PMOS transistor P5 acting as a power transistor. NMOS transistor N2 has a larger width-to-length ratio than NMOS transistor N3. Through the transmission gate TG and the external input control signal, NMOS transistors with different width-to-length ratios are selected to be turned on. The NMOS transistor with a larger width-to-length ratio has a larger saturation current. The current flowing through PMOS transistor P4 is equal to the current of NMOS transistor N2 or N3 (determined by the external input control signal. When N2 is turned on, the current of P4 is equal to the current of N2, and when N3 is turned on, the current of P4 is equal to the current of N3). The ratio of the width-to-length ratio of power transistor P5 to that of PMOS transistor P4 is n:1. Through the current mirror circuit, the current of power transistor P5 proportionally copies the current of PMOS transistor P4 with a ratio of n:1. Since the saturation current of NMOS transistor N2 is greater than the saturation current of NMOS transistor N3, the maximum output current of power transistor P5 is greater when NMOS transistor N2 is turned on than when NMOS transistor N3 is turned on. Figure 8 As shown, when the NMOS tube N3 is turned on, the output current of the power tube P5 decreases, which has a simple current limiting function of delaying the increase of the output current. Figure 8 In the figure, I1 is the output current of the VMID voltage generating circuit when the NMOS tube N2 is turned on, I2 is the current when the NMOS tube N3 is turned on, and the horizontal axis is the value of the output load resistance, which decreases to 0 from right to left.

[0047] Example 3 This embodiment is a near field communication chip, which includes the VMID voltage generating circuit described in the first or second embodiment.

[0048] The above description is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this field, several variations and improvements can be made without departing from the creative concept of the present invention, which all fall within the scope of protection of the present invention.

Claims

1. A multi-mode VMID voltage generation circuit for providing the required reference voltage for an NFC chip, characterized in that: include: A mode selection circuit, configured to receive an external control signal and select an output mode according to the control signal; a resistor voltage division mode circuit, connected to the mode selection circuit, and selected in the first control mode to output the VMID voltage in the resistor voltage division mode; a boost mode circuit, connected to the mode selection circuit and selected in the second control mode to output a VMID voltage in a boost mode; a low level mode circuit, connected to the mode selection circuit and selected in a third control mode to output a VMID voltage in a low level mode; Floating mode output end: in the fourth control mode, the mode selection circuit does not select any circuit among the resistance voltage divider mode, the boost mode and the low level mode, and is directly connected to the output end to realize the floating state of the output end.

2. The circuit according to claim 1, wherein: The control signal is a 3-bit signal with a value range of 000-111.

3. The circuit according to claim 2, characterized in that The resistor voltage division mode circuit includes a positive voltage side circuit, a ground side circuit and a logic gate; The positive voltage side circuit is connected to the output node after sequentially connecting a PMOS tube and a plurality of resistors in series from the positive power supply node, and is further provided with a plurality of PMOS tubes for selecting different resistor series combinations; The ground side circuit is connected to the output node after sequentially connecting an NMOS transistor and a plurality of resistors in series from the ground node, and is further provided with a plurality of NMOS transistors for selecting different resistor series combinations; The logic gates are four groups of identical circuits, each group of circuits includes two inverters arranged in series, and each group of front-stage inverters receives control signals 000, 001, 010 and 011 respectively. The output of the front-stage inverter is used to control different PMOS to be turned on or off, and the output of the rear-stage inverter is used to control different NMOS to be turned on or off.

4. The circuit according to claim 3, characterized in that The positive voltage side circuit includes four resistors connected in series, namely R3A, R2A, R1A and R0A from the positive power node to the output node, with a resistance ratio of 4:2:1:1; The ground side circuit includes four resistors connected in series, which are R3B, R2B, R1B and R0B from the ground node to the output node, and the resistance ratio is 4:2:1:

1.

5. The circuit according to claim 4, characterized in that The positive voltage side circuit includes four PMOS transistors P3, P2, P1 and P0, P3 is connected in series with four resistors, P2 is connected in series with R2A, R1A and R0A, P1 is connected in series with R1A and R0A, and P0 is connected in series with R0A; the equivalent width-to-length ratio of P0, P1, P2 and P3 is 8:4:2:1; The ground side circuit includes four NMOS tubes N3, N2, N1 and N0, N3 branch is connected in series with four resistors, N2 branch is connected in series with R2B, R1B and R0B, N1 branch is connected in series with R1B and R0B, and N0 branch is connected in series with R0B; the equivalent width-to-length ratio of N0, N1, N2 and N3 is 8:4:2:

1.

6. The circuit according to claim 2, characterized in that The boost mode circuit comprises: a bandgap reference circuit for outputting a stable reference voltage; an error amplifier circuit, one input of which is connected to the reference voltage, the other input of which is connected to the feedback voltage, and the output of which controls the gate voltage of the first NMOS transistor; a current mirror circuit, comprising the first NMOS transistor, the first PMOS transistor, and a second PMOS transistor serving as a power output transistor, for adjusting an output voltage according to an output of an error amplifier; a feedback circuit comprising two resistors connected in series, wherein a voltage division node thereof provides a feedback voltage; a current limiting circuit comprising a third PMOS transistor, a plurality of resistors, and a control transmission gate, for achieving foldback current limiting control by raising the gate voltage of the second PMOS transistor when the output current increases and the output voltage drops; The transmission gate is controlled by an external input control signal and is used to turn on or off the current limiting function.

7. The circuit according to claim 2, characterized in that The boost mode circuit comprises: a bandgap reference circuit for outputting a stable reference voltage; an error amplifier circuit, one input of which is connected to the reference voltage, the other input of which is connected to the feedback voltage, and the output of which controls the gate voltages of the second NMOS transistor and the third NMOS transistor; a current mirror circuit, comprising the second NMOS transistor, the third NMOS transistor, the fourth PMOS transistor, and a fifth PMOS transistor serving as a power output transistor, for adjusting the output voltage according to the output of the error amplifier; a feedback circuit comprising two resistors connected in series, wherein a voltage division node thereof provides a feedback voltage; a current limiting circuit comprising a second NMOS transistor, a third NMOS transistor, and two transmission gates connected in series, for selectively turning on NMOS transistors with different width-to-length ratios according to an external control signal to adjust a mirror current; The transmission gate is used to select and turn on the second NMOS transistor or the third NMOS transistor according to an external input control signal; The width-to-length ratio of the second NMOS transistor is greater than that of the third NMOS transistor.

8. The circuit according to claim 2, characterized in that The low level mode circuit comprises: At least two inverters connected in series, for performing logic inversion on an input control signal; An NMOS transistor, with its gate connected to the output terminal of the last-stage inverter, its source connected to the ground node, and its drain connected to the output node; A resistor is connected between the output node and the drain of the NMOS tube.

9. The circuit according to claim 2, characterized in that The control signal state for turning on the floating mode is 101.

10. A near field communication chip, characterized in that: The chip includes the voltage generating circuit according to any one of claims 1 to 9.

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