Codeless clock management unit design system and method

Abstract

The invention relates to a system and a method for designing internal functional modules of clock elements constituting a clock management unit and connections between the clock elements in a code-free manner. The system for designing a clock management unit in a code-free manner according to one embodiment of the present invention is a system for designing a clock management unit in a code-free manner, and comprises: a memory for storing at least one instruction; the clock component storage library is used for storing clock component information forming the clock management unit; the hardware code logic storage library is used for storing hardware code logic for generating the designed clock management unit into a hardware code; and at least one processor to execute the at least one instruction stored in the memory.

Description

Technical Field

[0001] The present invention relates to a system and method for designing a clock management unit of a system on chip, and more particularly, to a system and method for designing internal functional modules of clock elements constituting the clock management unit and connection points between clock elements in a codeless manner. Background Art

[0002] A system-on-chip (SoC) refers to a technology or integrated circuit (IC) that integrates multiple functional blocks, such as a central processing unit (CPU), memory, interfaces, digital signal processing circuits, and analog signal processing circuits, into a single semiconductor integrated circuit (IC) to implement a computer or other electronic system. SoCs are evolving into more complex systems that include processors, multimedia, graphics, interfaces, and security.

[0003] Power and clock design is crucial for SoCs. This process includes drawing a power / clock diagram, writing Verilog code and scripting, initial documentation, generating Unified Power Format / Standard Design Constraint (UPF / SDC) files, implementing layout design, secondary documentation, inserting a Design for Testability (DFT) controller, hardware system analysis, and software optimization.

[0004] The power / clock diagram creation step visually represents the power and clock structure and creates a block diagram to represent the power and clock tree. In the power / clock diagram creation step, clock elements and their links are represented only graphically. The Verilog coding and scripting step creates the Verilog code and scripts used to define and implement the system-on-chip's functionality, executing the hardware's register transfer level (RTL) design. In other words, developers manually generate register transfer level (RTL) code based on the power / clock diagram creation artifacts.

[0005] The first textualization step is to textualize the design intent and structure at the beginning of the project, creating various documents such as detailed requirements, architectural designs, power / clock diagrams, etc. required by multiple stakeholders such as the verification team and software development team.

[0006] The Unified Power Format / Standard Design Constraint File Generation Step is a step for generating a Unified Power Format (UPF) and Standard Design Constraint (SDC) file for controlling power management and timing constraints, thereby generating the input required for hardware synthesis.

[0007] The implementation layout design step involves designing the actual SoC chip layout at the gate level and configuring it. The second documentation step involves updating and improving various documents to reflect design and implementation changes. The DFT controller insertion step involves designing the DFT controller and logic circuits for testing and debugging and integrating them into the SoC. The hardware system analysis step involves verifying and analyzing software operation through simulation and verification to confirm the accuracy and effectiveness of the design. The software optimization step involves analyzing and optimizing the software code running on the SoC to maximize software performance.

[0008] Each step of the design process of this system on chip is independently performed by each stakeholder, and the information required in each step may be different. That is, the information required for the first half of the work and the information required for the second half of the work may be different. Therefore, problems with the design work products of the staff in the first half of the project can be discovered through simulation and verification in the second half, and in order to solve such problems, it is necessary to repeatedly perform the work from the first half. Moreover, during the course of the project, when the requirements or design objects change, it is necessary to repeatedly perform the work from the initial design. As mentioned above, in components that repeatedly perform multiple steps, multiple stakeholders need to reflect changes in other steps and repeatedly perform similar tasks. Therefore, the design of the system on chip will consume a lot of time and manpower. Summary of the Invention

[0009] The object of the present invention is to provide the following system and method, taking into account the settings required in the clock design process of the on-chip system for solving the above-mentioned problems, designing hardware code in a codeless manner, wherein the hardware code corresponds to the internal functional modules of the individual clock elements constituting the clock management unit and the connection points between the clock elements.

[0010] The present invention can be implemented in various ways including an apparatus (system), a method, a computer program stored in a computer-readable medium, or a computer-readable medium storing the computer program.

[0011] A codeless clock management unit design system according to an embodiment of the present invention is a system for designing a clock management unit in a codeless manner, comprising: a memory for storing at least one instruction; a clock component repository for storing information about clock components constituting the clock management unit; a hardware code logic repository for storing hardware code logic for generating the designed clock management unit into hardware code; and at least one processor for executing the at least one instruction stored in the memory. The at least one instruction includes the following instructions: setting automatic clock gating for the clock management unit; designing a new clock instance by setting register field values ​​for defining the function of the new clock instance based on already generated clock instance information and clock component information contained in the clock management unit; activating a functional module of the new clock instance based on whether automatic clock gating of the clock management unit is set and the set values ​​of the register fields of the new clock instance; generating hardware code associated with the functional module activated based on the set values ​​of the register fields of the new clock instance, information about the activated functional module of the new clock instance, and the hardware code logic; generating hardware code for a register module for enabling the activated functional module to operate; and generating hardware code for connecting the register module to ports of the activated functional module and hardware code for connection points.

[0012] Preferably, the at least one instruction further includes the following instruction: when setting the automatic clock gating of the clock management unit, activating the adapter functional module of the new clock instance.

[0013] More preferably, the connection point includes a clock line and a handshake signal line.

[0014] Preferably, at least one instruction also includes the following instructions: generating a new clock instance based on the generated clock instance information and clock component information, determining the field value of the basic register for setting the basic function of the clock source corresponding to the new clock instance, and determining the field value of the extended register for setting the extended function of the new clock instance.

[0015] More preferably, the present invention further includes the following instructions: activating a basic function module for executing the basic function of the new clock instance, and activating an extended function module for executing the extended function when the field value of the extended register for setting the extended function of the new clock instance is set to a specific value.

[0016] Preferably, the clock component information includes the basic function module of each clock component for performing basic functions and the extended function module for performing extended functions, the allocated address range, the alignment size of each clock component, the basic register offset size of each component, the extended register offset size of each component and the setting field information of each clock component.

[0017] More preferably, the setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

[0018] More preferably, the start address of the register of the new clock instance is determined by the sum of the start address of the register of the generated clock instance and the alignment size.

[0019] More preferably, the clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0020] More preferably, the clock component is a clock divider component, the fields of the extended register of the new clock instance include at least one of a power-off (DWRDOWN) field, a throttling (THROTTLE) field and a custom (CUSTOM) field, and the clock divider component includes at least one of an overlay function module, a throttling function module and a custom function module.

[0021] More preferably, the clock component is a clock multiplexer component, the fields of the extended register of the new clock instance include at least one of a throttling (THROTTLE) field and a custom (CUSTOM) field, and the clock multiplexer component includes at least one of a throttling function module and a custom function module.

[0022] More preferably, the clock component is a clock gating component, the fields of the extended register of the new clock instance include at least one of a short stop (SHORTSTOP) field, an early wake-up (EWAKEUP) field and a custom (CUSTOM) field, and the clock gating component includes at least one of a short stop function module, an early wake-up function module and a custom function module.

[0023] A codeless clock management unit design method according to an embodiment of the present invention is a method for designing a clock management unit in a codeless manner, executed by at least one processor in a computer system including a clock component repository storing information about clock components constituting the clock management unit and a hardware code logic repository storing hardware code logic for generating the designed clock management unit into hardware code. The codeless clock management unit design method includes the following steps: setting automatic clock gating for the clock management unit; designing a new clock instance by setting register field values ​​for defining the function of the new clock instance based on generated clock instance information and clock component information contained in the clock management unit; activating a functional module of the new clock instance based on whether automatic clock gating of the clock management unit is set and the set value of the register field of the new clock instance; and generating hardware code related to the functional module activated based on the set value of the register field of the new clock instance, the activated functional module information of the new clock instance, and the hardware code logic, generating hardware code for a register module for enabling the activated functional module to operate, and generating hardware code for connecting the register module to a port of the activated functional module and hardware code for a connection point.

[0024] Preferably, the present invention further comprises the following step: when the automatic clock gating of the clock management unit is set, activating the adapter function module of the new clock instance.

[0025] More preferably, the connection point includes a clock line and a handshake signal line.

[0026] Preferably, the present invention also includes the following steps: generating a new clock instance based on the generated clock instance information and clock component information; determining the field value of the basic register used to set the basic function of the clock source corresponding to the new clock instance; and determining the field value of the extended register used to set the extended function of the new clock instance.

[0027] More preferably, the present invention also includes the following steps: activating a basic function module for executing the basic function of the new clock instance; and activating an extended function module for executing the extended function when the field value of the extended register for setting the extended function of the new clock instance is set to a specific value.

[0028] Preferably, the clock component information includes the basic function module of each clock component for performing basic functions and the extended function module for performing extended functions, the allocated address range, the alignment size of each clock component, the basic register offset size of each component, the extended register offset size of each component and the setting field information of each clock component.

[0029] More preferably, the setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

[0030] More preferably, the start address of the register of the new clock instance is determined by the sum of the start address of the register of the generated clock instance and the alignment size.

[0031] More preferably, the clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

[0032] More preferably, the clock component is a clock divider component, the fields of the extended register of the new clock instance include at least one of a power-off (DWRDOWN) field, a throttling (THROTTLE) field and a custom (CUSTOM) field, and the clock divider component includes at least one of an overlay function module, a throttling function module and a custom function module.

[0033] More preferably, the clock component is a clock multiplexer component, the fields of the extended register of the new clock instance include at least one of a throttling (THROTTLE) field and a custom (CUSTOM) field, and the clock multiplexer component includes at least one of a throttling function module and a custom function module.

[0034] More preferably, the clock component is a clock gating component, the fields of the extended register of the new clock instance include at least one of a short stop (SHORTSTOP) field, an early wake-up (EWAKEUP) field and a custom (CUSTOM) field, and the clock gating component includes at least one of a short stop function module, an early wake-up function module and a custom function module.

[0035] An embodiment of the present invention provides a computer program stored in a computer-readable medium for executing the method on a computer.

[0036] In various embodiments of the present invention, connection points between individual clock elements constituting a clock management unit may be designed in a codeless manner, taking into account settings required in a clock design process of a system on chip.

[0037] In various embodiments of the present invention, the clock management unit and the internal functional modules of individual clock elements can be automatically derived to effectively improve the efficiency of the design operation.

[0038] In multiple embodiments of the present invention, even if the staff has no coding knowledge or clock process knowledge, they can design hardware codes in a codeless manner. The hardware codes correspond to the internal functional modules of the individual clock elements constituting the clock management unit and the connection points between the individual clock elements.

[0039] In various embodiments of the present invention, the clock management unit may be designed taking into account the settings required throughout the entire clock design process, thereby easily achieving global optimization.

[0040] The effects of the present invention are not limited to the effects mentioned above, and ordinary technicians in the technical field to which the present invention belongs (referred to as "general technicians") can clearly understand other effects not mentioned from the description of the scope of protection claimed in the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein like reference numerals denote like structural elements, but the present invention is not limited thereto.

[0042] Figure 1 FIG. 1 is a block diagram showing a general system on a chip.

[0043] Figure 2 for Figure 1 Detailed structural block diagram of the clock management unit included in the on-chip system.

[0044] Figure 3 This is a structural diagram of the codeless clock management unit design system of the present invention.

[0045] Figure 4 The following is an illustrative diagram showing a display screen of the codeless clock management unit design system of the present invention.

[0046] Figure 5 This is an example diagram showing the address range of registers allocated to each clock component.

[0047] Figure 6 This is an illustration showing the address allocation status of registers of three clock divider instances.

[0048] Figure 7 FIG. 1 is a block diagram showing the internal functional modules of the clock multiplexer component of the present invention.

[0049] Figure 8 FIG. 1 is a block diagram showing the internal functional modules of the clock divider component of the present invention.

[0050] Figure 9 FIG. 1 is a block diagram showing the internal functional modules of the clock gating component of the present invention.

[0051] Figure 10 The flowchart shows the codeless clock management unit design method of the present invention.

[0052] Figure 11 An exemplary computing device for executing the described methods and / or embodiments is shown.

[0053] Description of Reference Signs

[0054] 310: Screen window processing unit 311: Command window processing unit

[0055] 312: Content window processing unit 313: Design window processing unit

[0056] 314: Setting window processing unit 320: Clock management unit processing unit

[0057] 321: Clock Management Unit Management Section 322: Clock Instance Management Section

[0058] 323: Register setting unit 324: Functional module setting unit

[0059] 330: Data Repository 331: Clock Component Repository

[0060] 332: Clock Management Unit Repository 333: Clock Instance Repository

[0061] 334: Hardware code logic storage 340: Hardware code processing unit

[0062] 341: Functional module code generation unit 342: Register module code generation unit

[0063] 343: Port code generation unit 344: Connection point code generation unit DETAILED DESCRIPTION

[0064] Hereinafter, the specific contents for implementing the present invention will be described in detail with reference to the accompanying drawings. However, in the following description, when there is a concern that it may unnecessarily obscure the main purpose of the present invention, the specific description of known functions or structures will be omitted.

[0065] In the accompanying drawings, identical or corresponding structural elements are given the same reference numerals. Furthermore, in describing the following embodiments, repeated descriptions of identical or corresponding structural elements may be omitted. However, even if the description of a structural element is omitted, it does not mean that such structural element is not included in any embodiment.

[0066] The advantages, features and methods of implementing the embodiments described in this specification will be referred to in the accompanying Figure 1 However, the present invention is not limited to the embodiments disclosed below, but can be embodied in many different forms. However, these embodiments are provided to fully inform those skilled in the art of the scope of the present invention.

[0067] The terms used in this specification are briefly described, and the disclosed embodiments are specifically described. The terms used in this specification take into account their functions in the present invention and are selected as general terms that are currently widely used as much as possible. This may change according to the intentions of technicians in the relevant field, conventions, or the emergence of new technologies. In addition, in certain cases, there is an intention of the applicant to make an arbitrary selection. In this case, its meaning is described in detail in the description section of the corresponding invention. Therefore, the terms used in the present invention are not simple term names, but should be defined based on the meaning of the term and the overall content of the present invention.

[0068] Unless the context clearly specifies the singular, the singular in this specification includes the plural. Furthermore, unless the context clearly specifies the negative, the plural includes the singular. Throughout this specification, when a section includes one structural element, it means that other structural elements are also included, and does not mean that other structural elements are excluded, unless otherwise specified.

[0069] In the present invention, terms such as "include", "comprising" and the like may indicate the existence of features, steps, actions, elements and / or structural elements, and such terms do not exclude the addition of one or more other functions, steps, actions, elements, structural elements and / or combinations thereof.

[0070] In the present invention, when it is mentioned that a specific structural element is "combined," "combined," "connected," "associated," or "reacted" with other structural elements, the specific structural element may be directly combined, combined, connected, and / or associated or reacted with the other structural elements, but is not limited to this. For example, there may be at least one intermediate structural element between the specific structural element and the other structural element. Furthermore, in the present invention, "and / or" may include a combination of at least one item or at least a portion of at least one item listed.

[0071] In the present invention, terms such as "first" and "second" are used to distinguish specific structural elements from other structural elements, and the structural elements are not limited to such terms. For example, a "first" structural element can be used to represent an element with the same or similar form as a "second" structural element.

[0072] In multiple embodiments of the present invention, a "clock component" can be a tool that can be used in the design of a clock management unit. The clock component may include a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component. In the present invention, the clock component can be displayed in a clock component window as an icon, and each clock component may include a basic function module for performing the basic functions of each clock component and an extended function module for performing the extended functions of each clock component. In addition, each clock component may include an address range assigned to each clock component, an alignment size of each clock component, a basic register offset size of each clock component, an extended register offset size of each clock component, and setting field information of each clock component (field name, bit position, bit size, access rights, initial value, etc.). The register field may include an extended function setting field.

[0073] In multiple embodiments of the present invention, a "clock instance" can be a clock component added to the design window through user operations. That is, the clock instance can be a clock component included in the design of the clock management unit. If the user drags and drops (Drag&Drop) any clock component icon in the clock component window to the design window area, a clock instance corresponding to the corresponding clock component can be generated. If a clock instance is generated, the basic registers of the corresponding clock instance can be automatically generated and the extended registers can be selectively generated. The field values ​​​​composing the basic registers and the selectively generated extended registers can be pre-set or changed by user input. At the same time, the clock instance can include a basic function module and an extended function module. When any field value of the extended register of the clock instance is set to a preset value, the extended function module for executing the corresponding extended function can be activated.

[0074] The clock management unit can include multiple clock instances of each clock component type. Clock instances generated by the PLL controller component are called PLL controller instances, clock instances generated by the clock divider component are called clock divider instances, clock instances generated by the clock multiplexer component are called clock multiplexer instances, and clock instances generated by the clock gating component are called clock gating instances.

[0075] Each clock instance may include at least one basic function module and at least one selectively activated extended function module.

[0076] According to the present invention, when a clock instance is generated, basic function modules and basic register field values ​​can be automatically assigned. If the corresponding clock instance includes an extended function, the corresponding clock instance can activate the extended function module for executing the corresponding extended function. Furthermore, a port can be added to connect the extended register field with the extended function module. Furthermore, if the extended function module requires user input, the corresponding clock instance can also add a user input port. Furthermore, hardware code can be generated based on the basic register field values ​​and extended register field values ​​set for the clock instance, as well as the basic function module and the extended function module.

[0077] In multiple embodiments of the present invention, a clock element is a module implemented in hardware coding based on a completely designed clock instance, which can constitute a clock management unit.

[0078] To summarize, a clock component may be a material used to design a clock management unit, a clock instance may be a node that includes the clock management unit in the design, and a clock element may be a module implemented in the form of hardware code based on the clock instance of the completed design and that may work in the clock management unit.

[0079] Figure 1 FIG. 1 is a block diagram showing half of a system-on-chip.

[0080] The system on chip may include an input / output board 11, a clock management unit (CMU) 12, a power management unit (PMU) 13, and at least one intellectual property (IP) block 14, 15, and 16. The clock management unit 12 may generate clock signals that are provided to a first IP block 14, a second IP block 15, and a third IP block 16, respectively. For example, the clock management unit 12 may generate a first clock signal CLK1, a second clock signal CLK2, and a third clock signal CLK3. The clock management unit 12 may provide the first clock signal CLK1 to the first IP block 14, the second clock signal CLK2 to the second IP block 15, and the third clock signal CLK3 to the third IP block 16.

[0081] The first IP block 14, the second IP block 15, and the third IP block 16 can be connected to a system bus and can communicate with each other via the system bus. The first IP block 14, the second IP block 15, and the third IP block 16 can each include a processor, a graphics processor, a memory controller, an input and output interface block, etc.

[0082] The power management unit 13 controls the power supplied to the first to third IP blocks 14 to 16. For example, when the system on chip enters the standby mode, the power management unit 13 interrupts the power supply provided to the first to third IP blocks 14 to 16, thereby reducing the power consumption of the system on chip.

[0083] Figure 2 for Figure 1 Detailed structural block diagram of the clock management unit 12, 200 included in the on-chip system.

[0084] The clock management unit 200 can be Figure 1 The clock management unit 12.

[0085] Reference Figure 2 The clock management unit 200 includes multiple clock elements 211, 212, 213, 214, 215, 216, 217, and 218 (Clock Elements) and a clock management unit controller (CMUController) 220. The multiple clock elements 211, 212, 213, 214, 215, 216, 217, and 218 generate clock signals CLK provided to the IP blocks 14, 15, and 16. The frequencies of the clock signals provided to each IP block 14, 15, and 16 can be different. The clock management unit controller 220 controls the multiple clock elements 211, 212, 213, 214, 215, 216, 217, and 218 to provide clock signals having the frequencies required by the IP blocks 14, 15, and 16. The clock elements may include phase locked loop (PLL) controllers 211 and 212 , clock dividers 213 and 215 , a clock multiplexer 214 , and clock gates 216 , 217 , and 218 .

[0086] Each clock element may include a clock source (CS) and a clock control circuit (CC) that controls the clock source. For example, a clock source may include a multiplexing circuit, a frequency division circuit, a gating circuit, etc. Phase-locked loop controllers 211 and 212 do not include an internal clock source but may control a phase-locked loop (PLL) external to the clock management unit 200.

[0087] Clock dividers 213 and 215 each include a frequency divider circuit as a clock source CS. Clock control circuits CC in each clock divider 213 and 215 control the frequency divider circuits. The frequency divider circuits divide the input clock signal and output it. The clock control circuits CC can control, among other things, the frequency division ratio of the frequency divider circuits. Clock multiplexer 214 includes a multiplexing circuit as a clock source CS. The clock control circuit CC in clock multiplexer 214 controls the multiplexing circuit. The multiplexing circuit selectively outputs one of multiple input clock signals. The clock control circuit CC can control which input clock signal the multiplexing circuit selects for output.

[0088] Clock gating circuits 216, 217, and 218 each include a gating circuit as a clock source CS. Clock control circuits CC within these gating circuits control the gating circuits. The gating circuits activate the clock signal supplied to the IP block only when it is needed. Otherwise, they disable the clock signal to control unnecessary clock signals. This operation is called automatic clock gating. The clock control circuit CC can enable or disable the clock within the gating circuits. Clock gating circuits 216, 217, and 218 are connected to IP blocks 14, 15, and 16 via a Q channel. The clock control circuits within these gating circuits determine whether the corresponding IP block 14, 15, or 16 requires a clock by handshaking with the Q channel of the IP block 14, 15, or 16. If the IP block 14, 15, or 16 requires a clock, the clock signal is enabled; if not, the clock is disabled. This prevents IP block operation errors and reduces power consumption.

[0089] Clock element 211 is the parent element of clock element 213. Clock element 213 is the child element of clock element 211 and the parent element of clock element 214. Clock element 214 is the child element of two clock elements 212 and 213 and the parent element of clock element 215. Clock element 215 is the child element of clock element 214 and the parent element of three clock elements 216, 217, and 218. Meanwhile, clock elements 211 and 212, which include a phase-locked loop controller, are root clock elements, while clock elements 216, 217, and 218, which are located near IP blocks 14, 15, and 16 and include gate control circuits, are leaf clock elements.

[0090] The parent-child relationship described above can be formed between the clock control circuits CC and the clock sources CS based on the parent-child relationship between the clock elements 211, 212, 213, 214, 215, 216, 217, and 218. The clock elements include connection points, which can include clock lines CLK connected between the parent clock source CS and the child clock source CS.

[0091] Traditionally, automatic clock gating was implemented between the clock management unit and the IP block, but not between the clock elements within the clock management unit. Consequently, only the clock line CLK was connected to the clock source CS. In this case, the IP block does not require a clock. Therefore, when clock gates 216, 217, and 218 shut down the clock, the other clock elements continue to operate, resulting in continued power consumption.

[0092] To address this issue, a technology has been developed to implement automatic clock gating between clock elements within the clock management unit. To this end, the connection point may also include a handshake signal line 219 connecting the parent element clock control circuit CC and the child element clock control circuit CC. The parent element clock control circuit and the child element clock control circuit communicate with each other via handshake signal line 219. The parent element clock control circuit can determine whether the child element clock control circuit requires a clock and control each clock source to supply a clock signal to the child element clock control circuit or interrupt the supply of clock signals.

[0093] A clock element may include at least one functional module, at least one port for connecting each functional module to at least one of the user inputs of a register of the clock management unit controller 220, a connection point for connecting to a parent clock element, and a connection point for connecting to a child clock element. Such a connection point may include a clock line and, optionally, a handshake signal line.

[0094] The clock management unit controller 220 includes registers that record information required to control and configure the operation of each clock element of the clock management unit 200, recorded in register transfer-level (RTL) code. Furthermore, the registers of the clock management unit controller 220 contain register transfer-level (RTL) code that describes the operation of the clock control circuitry of each clock element. Register transfer-level (RTL) code for controlling the operation of connection points between the clock elements can also be recorded. This register transfer-level (RTL) code can be implemented as actual clock management unit hardware using hardware design tools. Furthermore, each clock element can include at least one functional module, each of which is written in hardware code and can be implemented as hardware using hardware design tools.

[0095] To construct a clock management unit, the internal functional modules of each clock element are generated using hardware code, and register transfer level RTL code is generated for each clock element and for the connection points between the clock elements. In the past, developers manually generated hardware code using Verilog code based on the clock diagram drawing product.

[0096] The present invention proposes a clock management unit design system and method that can set the connection points between clock elements and the functional modules of each clock element based on a graphical user interface (GUI), derive the hardware code corresponding to the connection points between clock elements in a codeless manner based on the set connection points, and derive the hardware code corresponding to the basic functional modules and the extended functional modules according to the basic functions and extended functions of the clock elements.

[0097] Figure 3 The structure diagram of the clock management unit design system in a codeless manner of the present invention is shown in FIG. The clock management unit design system in a codeless manner of the present invention can be implemented by a computer system.

[0098] The codeless clock management unit design system of the present invention may include: a screen window processing unit 310, which detects user input and outputs the processing results of the user input to the display screen; a clock management unit processing unit 320, which generates at least one clock instance based on clock component information, and generates a connection point between any two clock instances to design a clock management unit; a data repository 330, which stores clock component information for generating hardware code based on the clock component information and the designed clock management unit information; and a hardware code processing unit 340, which uses hardware code logic to generate hardware code corresponding to the designed clock management unit information.

[0099] Figure 4 The following is an illustrative diagram showing a display screen of the codeless clock management unit design system of the present invention.

[0100] The display screen of the codeless clock management unit design system of the present invention may include: a command window 410 for inputting user commands; a clock component window 420 for displaying multiple clock component icons; a content window 430 for providing an environment for adding, deleting, and changing the list of clock management units being designed, displaying a list of clock instances constituting the clock management unit being designed, and basic and extended function information of each clock instance by layer; a design window 440 for displaying a clock diagram of the clock management unit being designed, providing an environment for adding, deleting, and changing clock instances constituting the clock management unit being designed; and a setting window 450 for providing an environment for setting automatic clock gating for the clock management unit being designed, providing an environment for setting extended functions for the clock instance selected in the design window 440. Automatic clock gating of a clock management unit refers to the automatic clock gating function between clock instances constituting the clock management unit. When automatic clock gating of a clock management unit is set, all connection points between clock instances constituting the clock management unit can use automatic clock gating.

[0101] The command window 410 may include: a CHECK button for receiving an instruction to check errors in the clock diagram of the clock management unit being designed, the setting values ​​of multiple clock instances of the clock management unit being designed, and the connection points between parent-child clock instances; an UNCHECK button for receiving an instruction to deactivate the check result; a SAVE button for receiving an instruction to store the clock diagram displayed in the design window 440; and a GENRTL button for receiving an instruction to generate hardware code for the clock diagram displayed in the design window 440.

[0102] Clock component window 420 displays multiple icons listing clock components for a design of a clock-manageable unit. Clock components may include a phase-locked loop control component, a clock divider component, a clock multiplexer component, and a clock gating component. Label components may also be displayed in clock component window 420. Label components are components inserted between the input and output of two clock components to facilitate partial design work when designing a complex clock diagram. When hardware code is generated, the label components may be coded to be ignored, leaving the two clock components connected.

[0103] Content window 430 displays a list of clock management units currently being designed, providing an environment for adding, deleting, and modifying the clock management units currently being designed. Furthermore, beneath the list of each clock management unit currently being designed, a list of clock instances comprising the clock management unit currently being designed can be displayed. Basic register information for each clock instance can be displayed layer by layer, and optionally, extended register information for each clock instance can also be displayed.

[0104] Design window 440 displays the clock diagram of the clock management unit being designed and provides an environment for adding, deleting, and modifying clock instances that make up the clock management unit being designed. When the user drags and drops any clock component from clock component window 420 into design window 440, a corresponding clock instance is generated for the corresponding clock management unit being designed. When a clock instance is generated, a new clock instance list and basic register information for the new clock instance are added layer by layer in content window 430. Optionally, extended register information for the new clock instance can also be added.

[0105] Settings window 450 provides an environment for configuring automatic clock gating (ACG) for the clock management unit being designed, and also provides an environment for configuring the functionality of the clock instance selected in design window 440. When automatic clock gating is enabled for a clock management unit being designed, all connections between any two clock instances that make up the corresponding clock management unit being designed can be subject to automatic clock gating. When automatic clock gating is not enabled between any two clock instances, only the clock line is connected to the two corresponding clock instances. When automatic clock gating is enabled between two clock instances, the clock line and the handshake signal line are connected to the two corresponding clock instances.

[0106] Screen window processing unit 310

[0107] The screen window processing unit 310 may include: a command window processing unit 311, which displays buttons for receiving user instructions in the command window 410, detects input of each button in the command window 410 and performs work corresponding to the input button; a content window processing unit 312, which displays a list of clock management units under design, a list of clock instances included in each clock management unit under design and register information by layer in the content window 430, detects user input in the content window 430 and performs work corresponding to the user input; a design window processing unit 313, which displays a clock diagram of the clock management unit under design selected by the user in the design window 440, detects user input in the design window 440 and performs work corresponding to the user input; and a setting window processing unit 314, which displays automatic clock gating setting information of the clock management unit under design selected by the user and setting information of the clock instance selected by the user in the setting window 450, detects user input in the setting window 450 and performs work corresponding to the user input.

[0108] When the CHECK button is selected, the command window processing unit 311 checks the clock diagram of the clock management unit under design, the setting values ​​of the multiple clock instances of the clock management unit under design, and the connection points between the parent element and the child element clock instances for errors, and displays the error portion. When the UNCHECK button is selected, the error portion of the clock diagram of the clock management unit under design is restored to its original state and displayed. When the SAVE button is selected, the operation content of the clock of the clock management unit under design displayed in the design window 440 is stored in the content data storage 330. When the GENRTL button is selected, the hardware code for the clock diagram of the clock management unit under design displayed in the design window 440 is generated.

[0109] The content window processing unit 312 provides an environment for adding, deleting, and modifying the list of clock management units under design and the list of clock instances included in each clock management unit under design. The content window processing unit 312 displays the list of clock instances, basic register information corresponding to the basic functions of each clock instance, and optionally displays extended register information based on extended functions, layer by layer, under each clock management unit under design. Users can add, delete, or rename clock management units under design in the content window 430. In response to user input, the clock management unit repository 332 allows users to add, delete, or modify the list of clock management units under design, and configure automatic clock gating for each clock management unit. When the user changes the name of a clock management unit under design, the content window processing unit 312 also changes the name of the corresponding clock management unit under design, the name of the underlying clock instance, and the basic and extended register names of the corresponding clock instance.

[0110] The design window processing unit 313 displays the clock diagram of the clock management unit being designed in the design window 440 and provides an environment for adding, deleting, and modifying clock instances that make up the clock management unit being designed. When the user adds any clock component from the clock component window 420 to the design window 440, the design window processing unit 313 detects the addition of the clock instance.

[0111] The settings window processing unit 314 displays the AutoClock Gating (ACG) setting information for the clock management unit being designed, detects user input in the settings window 450, and performs operations corresponding to the user input. Specifically, the settings window processing unit 314 can set or disable the AutoClock Gating setting for the clock management unit being designed based on the user input. Furthermore, the settings window processing unit 314 displays the extended function setting information for the user-selected clock instance in the settings window 450, detects user input in the settings window 450, and performs operations corresponding to the user input. The settings window processing unit 314 can set or disable the extended function of the clock instance based on the user input.

[0112] Data Repository 330

[0113] The data repository 330 may include: a clock component repository 331 storing clock component information; a clock management unit repository 332 storing automatic clock gating (ACG) setting information for a clock management unit under design, a list of clock instances included in the clock management unit under design, and register lists corresponding to the clock instances; a clock instance repository 333 storing basic function information and extended function information for each clock instance included in the clock management unit under design, as well as register information for each clock instance; and a hardware code logic repository 334 storing hardware code logic for generating hardware code based on the automatic clock gating setting information for the clock management unit under design, the basic function information, extended function information, and register information for the designed clock instances. The register lists corresponding to the clock instances may include a basic register list and an extended register list.

[0114] The clock component information stored in the clock component repository 331 may include the address range assigned to each clock component, the alignment size of each clock component, the basic register offset size of each clock component, the extended register offset size of each clock component, and the set field information for each clock component (field name, bit position, bit size, access rights, initial value, etc.). The clock component information specifies the register addresses and field values ​​of clock instances generated based on the corresponding clock component. The maximum number of clock instances for each clock component can be calculated using the register address range assigned to each clock component and the alignment size of each clock component. Clock components may include a phase-locked loop control component, a clock divider component, a clock multiplexer component, and a clock gating component. A clock component may include a basic function module for performing the basic functions of the corresponding clock component and an extended function module for performing the extended functions of the corresponding clock component. When a clock instance corresponding to a clock component is generated, the basic function module is activated. When the user sets an extended function for the corresponding clock instance in the settings window 450, the extended function module corresponding to the set extended function is activated. The basic function module and extended function module of each clock component can be different.

[0115] Figure 5 The following diagram illustrates the address range of registers allocated to each clock component. For example, the phase-locked loop control component can be allocated the address range of 0x0000 to 0x0800, the clock divider component can be allocated the address range of 0x1400 to 0x1800, the clock multiplexer component can be allocated the address range of 0x1000 to 0x1400, and the clock gating component can be allocated the address range of 0x1800 to 0x2000.

[0116] Figure 6 This is an illustration showing the address allocation status of registers of three clock divider instances.

[0117] The addresses of the three clock divider instances are allocated in the address range (0×1400 to 0×1800) allocated to each clock component. The register address of the first clock divider instance DIV_0 can be allocated to the start address (1×1400) of the address range allocated to the clock divider component. The register address of the second clock divider instance DIV_1 can be an address (1×1408) obtained by adding the alignment size (0×8) to the start address of the first clock divider instance. The register address of the third clock divider instance can be an address (0×1414) obtained by adding the alignment size to the start address of the second clock divider instance. The first clock divider instance and the second clock divider instance can only include basic registers, and the third clock divider instance can include basic registers and extended registers. The basic register setting value of the clock divider instance is recorded from the clock divider instance start address to the basic register offset size, and the extended register setting value is recorded in the remaining part.

[0118] The clock component repository 331 stores the field information (field name, bit position, bit size, access rights, initial value, etc.) for each clock component. This field information can be different for each clock component. The bit position is the starting address of the corresponding field in the address assigned to the individual clock instance, the bit size is the range of the corresponding field, the access rights are whether the corresponding field has write permission (read-only / read-write), and the initial value is the initial setting value.

[0119] The phase-locked loop control component may include a select (SELECT) field, a busy (BUSY) field, and a debug (DBG_INFO) field as basic register information, and may include a power-off (DWRDOWN) field and a custom (CUSTOM) field as extended register information. The field name and bit position, bit size, access rights, and initial value of each field may be set. Among them, the select field is a field for selecting the type of phase-locked loop, the busy field is a field for monitoring whether the clock element is working, and the debug field is a field for storing debug information. The phase-locked loop controller component may also include an automatic clock gating field that is activated when the automatic clock gating of the clock management unit is set.

[0120] The clock multiplexer component includes a select (SELECT) field, a busy (BUSY) field, and a debug (DBG_INFO) field as basic register information, and may include a throttle (THROTTLE) field and a custom (CUSTOM) field as extended register information. The field name and bit position, bit size, access rights, and initial value of each field have been set. Among them, the select field is a field for selecting the number of multiplexer inputs, the busy field is a field for monitoring whether the clock element is working, and the debug field is a field for storing debug information. The clock multiplexer component may also include an automatic clock gating field that is activated when the automatic clock gating of the clock management unit is set.

[0121] The clock divider component may include a division ratio (DIVRATIO) field, a busy (BUSY) field, and a debug (DBG_INFO) field as basic register information, and may include a power down (DWRDOWN) field, a throttle (THROTTLE) field, and a custom (CUSTOM) field as extended register information. The field name, bit position, bit size, access rights, and initial value of each field have been set. The division ratio field is a field for setting the division ratio of the clock divider, the busy field is a field for monitoring whether the clock element is working, and the debug is a field for storing debug information. The clock divider component may also include an automatic clock gating field that is activated when the automatic clock gating of the clock management unit is set.

[0122] The clock gating component can include a busy (BUSY) field and a debug (DBG_INFO) field as basic register information, and an enable (ENABLE) field, a short stop (SHORTSTOP) field, an early wake-up (EWAKEUP) field, and a custom (CUSTOM) field as extended register information. The field name, bit position, bit size, access rights, and initial value of each field have been set. The busy field is a field used to monitor whether the clock element is working, and the debug field is a field for storing debug information. The clock gating component may also include an automatic clock gating field that is activated when the automatic clock gating of the clock management unit is set.

[0123] The power-down (DWRDOWN) field is a field that determines whether the function of controlling the corresponding clock element is used during the power-on / power-off sequence of any power domain. In the case of the phase-locked loop controller instance and the clock multiplexer instance, when the power-down field is set to a specific field value, it supports the working feature of forcing the output value to be overridden to 0. In the case of the clock divider instance, when the power-down field is set to a specific field value, it supports the working feature of forcing the output value to be output at a low level.

[0124] The throttling (THROTTLE) field is a field that determines the characteristic of instantly reducing the frequency to reduce the temperature when the temperature of the clock element rises above the specified level. In the case of the clock multiplexer instance and the clock divider instance, when the throttling (THROTTLE) field is set to a specific field value, it supports the operating characteristics of forcibly changing the division ratio and output frequency if a throttling signal is input.

[0125] The Custom field is used to determine whether the corresponding clock element's functionality is controlled by separate custom hardware. The Shortstop field allows you to stop the operating characteristics of a signal for several cycles before and after a signal transitions from 0 to 1 or from 1 to 0. The Shortstop field can be set in a clock gating instance. The Early Wakeup field receives a signal from outside the clock management unit to determine whether to activate automatic clock gating between the clock element and the IP block.

[0126] Figure 7 FIG1 is a block diagram illustrating the internal functional modules of a clock multiplexer component of the present invention. As a basic functional module, clock multiplexer component 700 may include a data synchronization (DATA2SYNC) functional module 701, a select (SELECT) functional module 702, an adapter (ADAPTER) functional module 703, and a clock compensation (CLKCOMP) functional module 704. As an extended functional module, clock multiplexer component 700 may include a custom (CUSTOM) functional module 705, a throttle (THROTTLE) functional module 706, and an override (OVERRIDE) functional module 707.

[0127] Figure 8 1 is a block diagram illustrating the internal functional modules of the clock divider component of the present invention. As a basic functional module, the clock divider component 800 may include a data synchronization (DATA2SYNC) functional module 801, an adapter (ADAPTER) functional module 802, and a clock compensation (CLKCOMP) functional module 803. As an extended functional module, the clock divider component 800 may include a custom functional module 804, a throttling (THROTTLE) functional module 805, and an override (OVERRIDE) functional module 806.

[0128] Figure 91 is a block diagram illustrating the internal functional modules of the clock gating component of the present invention. As a basic functional module, the clock gating component 900 may include a data synchronization (DATA2SYNC) functional module 901, an adapter (ADAPTER) functional module 902, and a clock compensation (CLKCOMP) functional module 903. As an extended functional module, the clock gating component 900 may include a custom (CUSTOM) functional module 904, an enable (ENABLE) functional module 905, a short stop (SHORTSTOP) functional module 906, and an early wakeup (EWAKEUP) functional module 907.

[0129] Data synchronization modules 701, 801, and 901 synchronize the control signals of a clock element's clock control circuit with the clock signal of the clock source. Clock compensation modules 704, 803, and 903 process the clock signal received from the parent element's clock source and then transmit it to the child element's clock source. Adapter modules 703, 802, and 902, activated when automatic clock gating of the clock management unit is enabled, activate the handshake signal lines connected to the parent element's clock control circuit and the handshake signal lines connected to the child element's clock control circuit.

[0130] The selection function module 702 selects the number of multiplexer inputs based on the value set in the selection field. Custom function modules 705, 804, and 904 are activated based on the value set in the custom field and control the corresponding clock element through separate custom hardware. The throttling function modules 706 and 805 are activated based on the value set in the throttling field and sequentially reduce the clock frequency when the temperature of the clock element rises above a specified level. Furthermore, the override function modules 707 and 806 are activated based on the value set in the power-off field and force the output value to 0. The short-stop function module 906 is activated based on the value set in the short-stop field and stops a signal for several cycles before and after the transition from 0 to 1 or vice versa. The early wakeup function module 907 is activated based on the value set in the early wakeup field and receives signals from outside the clock management unit to perform IP block and automatic clock gating functions.

[0131] The clock management unit library 332 stores automatic clock gating (ACG) setting information of the clock management unit being designed and a clock instance list including the clock management unit being designed and a register list corresponding to the clock instance.

[0132] The clock instance repository 333 stores clock instance information and extended function information for each instance of the clock management unit being designed, as well as register information for the clock instance. The clock instance repository 333 can store the name of the clock management unit being designed, the type of clock component for the clock instance, the start address of the corresponding clock instance, the adapter function module activated corresponding to the basic function module and automatic clock gating settings of the clock instance, the extended function module activated corresponding to the extended function of the corresponding clock instance set by the user, and the set values ​​of each register field. The set values ​​of each register field can be set based on the clock component information or reflect user input. There can also be port information for clock instance connection registers, basic function modules, and extended function modules, as well as handshake signal line information and clock line information for connecting the adapter function module to the parent element clock instance and child element clock instances.

[0133] The hardware code logic repository 334 stores hardware code logic for generating hardware codes based on the designed clock management unit information, automatic clock gating setting information of the clock management unit, clock instance information, and register information.

[0134] Clock management unit processing unit 320

[0135] The clock management unit processing section 320 may include: a clock management unit management section 321, which generates a clock management unit and stores the automatic clock gating setting information of the clock management unit in a clock management unit repository 332; a clock instance management section 322, which generates a new clock instance based on the generated clock instance information and clock component information of the same clock component type and stores it in a clock instance repository 333; a register setting section 323, which sets the field values ​​of the basic registers used to define the basic functions of the new clock instance and the field values ​​of the extended registers that define the extended functions of the new clock instance and stores them in the clock instance repository 333; and a function module setting section 324, which activates the basic function module for executing the basic function of the new clock instance and the extended function module for executing the extended function of the new clock instance and the adapter function module based on the automatic clock gating setting of the clock management unit.

[0136] The clock management unit management section 321 allows the user to operate the content window 430 to generate a new clock management unit and store it in the clock management unit repository 332, or to load a clock management unit currently being designed and displayed in the content window 430 from the clock management unit repository 332 and modify it. When a new clock management unit or a clock management unit currently being designed is selected, the automatic clock gating setting screen for the corresponding clock management unit is displayed in the setting window 450. The automatic clock gating setting value based on the user's operation is stored in the clock management unit repository 332. Furthermore, when a clock management unit is selected, the clock diagram for the corresponding clock management unit is displayed in the design window 440, allowing modification of the clock diagram for the clock management unit. In other words, clock instances can be added, deleted, or modified in the clock management unit.

[0137] When a user adds any clock component from the clock component window 420 to the design window 440, the clock instance management unit 322 is executed and a new clock instance is generated. The name of the new clock instance can include the name of the clock management unit used in the design process to include the new clock instance and the clock component type information of the new clock instance. Furthermore, the address of the new clock instance can be set based on the information of the previously generated clock instances and clock component information of the same clock component type. Specifically, the register start address of the new clock component can be determined by combining the register start address of the previously generated clock instance and the alignment size of the clock component information. Initial register field settings can be determined based on the basic register offset size, extended register offset size, and setting field information of the clock component information.

[0138] The register setting unit 323 can display the field name, bit position, bit size, access rights, and initial value of the setting fields contained in the basic registers of the clock instance in the design window 440 or the setting window 450, and can be changed according to user input. This register sets the necessary functions of the clock source of the clock element. That is, for the phase-locked loop controller instance, the phase-locked loop type selection function, the clock element operation monitoring function, and the debugging function can be set, and the setting values ​​of the register fields corresponding to each function can be set. For the clock multiplexer instance, the multiplexer input number selection function, the clock element operation monitoring function and the debugging function can be set, and the setting values ​​of the register fields corresponding to each function can be set. For the clock divider instance, the division ratio function, the clock element operation monitoring function and the debugging function can be set, and the setting values ​​of the register fields corresponding to each function can be set. For the clock gating instance, the clock element operation monitoring function and the debugging function can be set, and the register field values ​​corresponding to each function can be set.

[0139] At the same time, the register setting unit 323 can display the settable extended functions of each clock component on the screen. When the user selects an extended function, the field of the extended register corresponding to the corresponding extended function can be set. For the phase-locked loop controller instance, the power-off (DWRDOWN) function, custom function, etc. can be selected, and the extended register field value corresponding to the extended function selected by the user can be set. For the clock multiplexer instance, the throttling (THROTTLE) function, custom (CUSTOM) function, etc. can be selected, and the confirmation register field value corresponding to the extended function selected by the user can be set. For the clock divider instance, the power-off (DWRDOWN) function, throttling (THROTTLE) function, custom (CUSTOM) function, etc. can be selected, and the confirmation register field value corresponding to the extended function selected by the user can be set. For the clock gating instance, the short stop (SHORTSTOP) function, early wake-up (EWAKEUP) function, custom (CUSTOM) function, etc. can be selected, and the confirmation register field value corresponding to the extended function selected by the user can be set.

[0140] Functional module setting unit 324 activates the basic functional module for each clock instance and the extended functional module for executing the extended functions set in register setting unit 323. Specifically, a clock component includes a basic functional module for executing the basic functions of the corresponding clock component and extended functional modules corresponding to all extended functions that can be set in the corresponding clock component. Consequently, clock instances generated based on the corresponding clock component also include both basic functional modules and extended functional modules. However, depending on the user's extended function settings, the corresponding extended functional module may be activated or deactivated.

[0141] At the same time, the clock component includes an adapter functional module for performing automatic clock gating. Clock instances generated based on the corresponding clock component also include an adapter functional module. However, the adapter functional module for each clock instance can be activated or deactivated depending on whether automatic clock gating is enabled for the clock management unit. When automatic clock gating is enabled for the clock management unit in the clock management unit management unit 321, the functional module setting unit 324 can activate the adapter functional module.

[0142] Hardware code processing unit 340

[0143] The hardware code processing unit 340 may include: a functional module code generation unit 341, which generates hardware code for the functional module corresponding to the clock element based on the designed clock instance information; a register module code generation unit 342, which generates hardware code for the register module of the functional module driving the clock element; a port code generation unit 343, which generates hardware code for the port connecting the functional module of the clock element and the register module; and a connection point code generation unit 344, which generates hardware code for the connection point between the clock element and at least one of the parent element clock element and the child element clock element.

[0144] When the GENRTL button in the command window 410 is selected, the hardware code processing unit 340 can be executed. When the design window 440 displays the clock diagram of the clock management unit being designed, the user can select the GENRTL button and execute it. Before executing the GENRTL button, the user can execute the check button to pre-verify whether there are any errors in the clock diagram.

[0145] The functional module code generation unit 341 generates hardware code for the functional modules based on the clock instance information designed by the hardware code logic transformation stored in the hardware code logic repository 334. The basic functional module of each clock instance must be activated. Depending on the extended function settings of the clock instance, extended functional modules may also be activated. Hardware code is then generated for the activated basic functional modules and extended functional modules.

[0146] The register module code generation unit 342 generates hardware code for the register module based on the register field values ​​of the designed clock instance and according to the hardware code logic. For each activated basic function module and extended function module of the clock element, hardware code for the register module is generated to control the operation of the corresponding basic function module and extended function module.

[0147] The port code generation unit 343 can generate hardware codes for the ports connecting the activated basic function module and the extended function module with the corresponding register modules. The port code generation unit 343 generates hardware codes for communicating with the activated extended function module and register module, but may not generate hardware codes for the ports used to communicate with the activated extended function module and register module. For example, in the case of a clock divider module, it can include a frequency division ratio port, a busy port, and a debug port. The register module corresponding to the clock divider module can also generate corresponding frequency division ratio ports, busy ports, and debug ports.

[0148] The connection point code generation unit 344 can generate hardware code for a clock element's clock line. A clock element's clock line can connect to either a parent clock element or a child clock element. Furthermore, the connection point code generation unit 344 can also generate hardware code for a clock element's handshake signal line. A clock element's handshake signal line can connect to either a parent clock element or a child clock element.

[0149] Figure 10 The flowchart of the codeless clock management unit design method of the present invention is shown in FIG. The codeless clock management unit design method of the present invention can be executed by a processor of a computer system.

[0150] The computer system includes: a clock component repository storing clock component information for specifying register addresses and field values ​​of clock instances generated based on clock components; and a hardware code logic repository storing hardware code logic for generating the designed clock management unit into hardware code.

[0151] The processor generates a clock management unit and sets whether to enable automatic clock gating of the clock management unit (step S1001 ). The processor stores the generated clock management unit information in the clock management unit storage 332 .

[0152] The processor sets field values ​​of registers for defining clock instance functions based on the generated clock instance information and the clock component information and designs a new clock instance.

[0153] The process of the processor designing a new clock instance is described in detail. The processor generates a new clock instance based on the generated clock instance information and clock component information and stores it in the clock instance repository (step S1020), sets the value of the basic register field for setting the basic function of the clock source corresponding to the new clock instance and the value of the register field for setting the extended function of the new clock instance and stores them in the clock instance repository (step S1030).

[0154] The processor activates the functional modules of the new clock instance based on whether the clock management unit's automatic clock gating is set and the set value of the register field of the new clock instance (step S1040). Specifically, the processor activates the basic functional module for performing the basic functions of the new clock instance. When the field value of the extended register for setting the extended functions of the new clock instance is set to a specific value, the processor activates the extended functional module for performing the corresponding extended function. Furthermore, when the clock management unit's automatic clock gating is set, the processor activates the adapter functional module for performing automatic clock gating.

[0155] The processor generates hardware code for the designed clock management unit based on the set values ​​of the register fields of the new clock instance, the information about the activated functional module of the new clock instance, and the hardware code logic (step S1050). Specifically, the processor generates hardware code for the activated functional module, hardware code for the register module for operating the activated functional module, and hardware code for the ports and connection points for connecting the register module to the activated functional module.

[0156] Figure 11 An exemplary computing device 1100 for executing the methods and / or embodiments is shown. According to one embodiment, the computing device 1100 can be implemented using hardware and / or software for interacting with a user. The computing device 1100 may include a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a mainframe, etc., but is not limited thereto. The structural elements of the computing device 1100, their connections, and their functions are exemplary, and the examples of the present invention described in this specification and / or the scope of protection claimed in the invention are not limited thereto.

[0157] Computing device 1100 includes a processor 1110, a memory 1120, a storage device 1130, a communication device 1140, a high-speed port 1150 connected between memory 1120 and a high-speed expansion port, and a low-speed port 1160 connected between a low-speed bus and the storage device. Structural elements 1110, 1120, 1130, 1140, 1150, and 1160 can be connected to each other using various buses, can be installed on the same main board, or can be installed and connected using other appropriate means. Processor 1110 can perform basic arithmetic, logical, and input / output operations, thereby processing computer program instructions. For example, processor 1110 can process instructions stored in memory 1120, storage device 1130, etc. and / or instructions running within computing device 1100, thereby displaying graphical information on an external input / output device 1170, such as a display device, coupled to high-speed port 1150.

[0158] The communication device 1140 may provide a structure or function that enables the input / output device 1170 and the computing device 1100 to communicate with each other via a network, and may provide a structure or function that enables the input / output device 1170 and / or the computing device 1100 to communicate with other external devices, etc. For example, a request or data generated by a processor of an external device based on any program code may be transmitted to the computing device 1100 via a network under the control of the communication device 1140. Conversely, control signals or instructions provided under the control of the processor 1110 of the computing device 1100 may be transmitted to other external devices via the communication device 1140 and the network.

[0159] Figure 11 The computing device 1100 is shown to include a processor 1110, a memory 1120, etc., but is not limited thereto. The computing device 1100 can be implemented using multiple memories, multiple processors and / or multiple buses, etc. Figure 11 The figure shows that there is one computing device 1100, but it is not limited thereto. Multiple computing devices can interact and perform necessary tasks to execute the method.

[0160] Memory 1120 can store information within computing device 1100. According to one embodiment, memory 1120 can be comprised of a volatile memory unit or multiple memory units. Additionally or alternatively, memory 1120 can be comprised of a non-volatile memory unit or multiple memory units. Furthermore, memory 1120 can be comprised of other computer-readable media, such as a magnetic disk or optical disk. Furthermore, memory 1120 can store an operating system and at least one program code and / or instruction.

[0161] The storage device 1130 may be at least one large-capacity storage device for storing data for the computing device 1100. For example, the storage device 1130 may be a computer-readable medium including a hard disk, a magnetic disc such as a removable disk, an optical disc, an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a semiconductor memory device such as a flash memory device, a CD-ROM, or a DVD-ROM, or may include such a computer-readable medium. Furthermore, the computer program may be tangibly embodied in such a computer-readable medium.

[0162] The high-speed interface 1150 and the low-speed interface 1160 may be units for interacting with the input / output device 1170. For example, the input device may include a camera with an audio sensor and / or an image sensor, a keyboard, a microphone, a mouse, and the like. Furthermore, the output device may include a display, a speaker, a haptic feedback device, and the like. In other examples, the high-speed interface 1150 and the low-speed interface 1160 may be units for interfacing with a device that combines input and output functions, such as a touch screen.

[0163] According to one embodiment, the high-speed interface 1150 can manage bandwidth-intensive tasks for the computing device 1100, while the low-speed interface 1160 can manage tasks that are less bandwidth-intensive than the high-speed interface 1150, but this functional allocation is merely illustrative. According to one embodiment, the high-speed interface 1150 can be combined with the memory 1120, the input / output device 1170, and a high-speed expansion port that can accommodate various expansion cards (not shown). Furthermore, the low-speed interface 1160 can be combined with the storage device 1130 and the low-speed expansion port. Additionally, a low-speed expansion card including various communication ports (e.g., USB, Bluetooth, IoT, wireless IoT) can be combined with at least one input / output device 1170 such as a keyboard, a pointing device, or a scanner, or can be combined with a network device such as a router or a switch through a network adapter.

[0164] Computing device 1100 can be implemented in a variety of different forms. For example, computing device 1100 can be implemented as a standard server or as a group of multiple such standard servers. Additionally or alternatively, computing device 1100 can be implemented as part of a rack server system, or can be implemented as a personal computer such as a laptop computer. In this case, the structural elements of computing device 1100 can be combined with other structural elements in any mobile device (not shown). Such computing device 1100 can include at least one other computing device or communicate with at least one other computing device.

[0165] Figure 11 1100, but the present invention is not limited thereto and the input / output device 1170 may be formed into one device together with the computing device 1100. Figure 11 110 . The high-speed interface 1150 and / or the low-speed interface 1160 and the processor 1110 are shown as separate components, but the present invention is not limited thereto. The high-speed interface 1150 and / or the low-speed interface 1160 may be included in the processor 1110 .

[0166] The method and / or various embodiments may be implemented by digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention may be executed by a data processing device, for example, at least one programmable processor and / or at least one computer device, or may be implemented by a computer-readable medium and / or a computer program stored on a computer-readable medium. The computer program may be written in any programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, a subroutine, etc. The computer program may be distributed by a single computing device, multiple computing devices connected via the same network, and / or multiple computing devices distributed in a manner connected via multiple different networks.

[0167] The methods and / or various embodiments may operate or generate output data based on input data, and thus, may be executed by at least one processor that runs at least one computer program that processes, stores, and / or manages any functions, features, etc. For example, the methods and / or various embodiments of the present invention may be executed by special-purpose logic circuits such as field programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and the devices and / or systems for executing the methods and / or embodiments of the present invention may be implemented as special-purpose logic circuits such as field programmable gate arrays or application-specific integrated circuits.

[0168] The at least one processor that executes the computer program may include a general-purpose or special-purpose microprocessor and / or at least one processor of any type of digital computing device. The processor may receive instructions and / or data from a read-only memory, a random access memory, or may receive instructions and / or data from both a read-only memory and a random access memory. In the present invention, the structural elements of the computing device that executes the method and / or embodiment may include at least one processor for executing instructions and at least one memory for storing instructions and / or data.

[0169] According to one embodiment, a computing device can transmit and receive data to at least one mass storage device for storing data. For example, the computing device can receive data from a magnetic disk or an optical disk and can transmit data to the magnetic disk or optical disk. Computer-readable media suitable for storing instructions and / or data related to a computer program may include, but are not limited to, any form of non-volatile memory including semiconductor memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory devices. For example, computer-readable media may include magnetic disks such as internal hard drives or removable disks, photomagnetic disks, CD-ROMs, and DVD-ROMs.

[0170] To provide interaction with a user, a computing device may include a display device (e.g., a cathode ray tube (CRT), a liquid crystal display (LCD), etc.) that provides or displays information to the user, and a pointing device (e.g., a keyboard, a mouse, a trackball, etc.) that allows the user to provide input and / or instructions to the computing device, but the present invention is not limited thereto. That is, a computing device may also include any other type of device for providing interaction with a user. For example, a computing device may provide the user with any form of sensory feedback, including visual feedback, auditory feedback, and / or tactile feedback, in order to interact with the user. In this regard, the user may provide input to the computing device through various gestures, such as vision, voice, and movement.

[0171] In the present invention, various embodiments can be implemented in a computer device including a back-end structural element (e.g., a data server), a middleware structural element (e.g., an application server), and / or a front-end structural element. In this case, the structural elements can be connected to each other via any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network can be composed of a wired network such as Ethernet, a wired home network (Power Line Communication), a telephone line communication device, and RS-serial communication, a mobile communication network, a wireless local area network (WLAN), a wireless LAN, Wi-Fi, Bluetooth, and a cellular communication, or a combination thereof. For example, the communication network may include a local area network (LAN), a wide area network (WAN), and the like.

[0172] The computing device based on the exemplary embodiments described in this specification can be implemented using hardware and / or software including user equipment, user interface (UI) devices, user terminals or client devices to interact with users. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include a personal digital assistant (PDA), a tablet computer, a game console, a wearable device, an Internet of Things (IoT), a virtual reality (VR) device, an augmented reality (AR) device, etc., but is not limited thereto. The computing device may also include other types of devices that interact with the user. Furthermore, the computing device may include a portable communication device (e.g., a mobile phone, a smart phone, a wireless cellular phone, etc.) suitable for wireless communication over a network such as a mobile communication network. The computing device may use wireless communication technologies and protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared ray frequency (IRF) to communicate wirelessly with a network server.

[0173] In the present invention, the various embodiments, including specific structural and functional details, are intended to be illustrative. Therefore, the embodiments of the present invention are not limited to the embodiments described, but can be embodied in a variety of different forms. Furthermore, the terms used in the present invention are intended to describe some embodiments, not to limit them. For example, unless the context clearly indicates otherwise, words in the singular include the plural.

[0174] In the present invention, unless otherwise defined, all terms used in this specification, including technical or scientific terms, have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs. Furthermore, commonly used terms, such as those defined in dictionaries, have the same meanings as those in the same technical context.

[0175] While the present invention is described in this specification with reference to certain embodiments, it is understood that various modifications and variations may be made by persons skilled in the art without departing from the scope of the present invention. Furthermore, such modifications and variations are intended to fall within the scope of the claims appended to this specification.

Claims

1. A codeless clock management unit design system, for designing a clock management unit in a codeless manner, characterized in that: include: a memory for storing at least one instruction; A clock component repository storing information of clock components constituting a clock management unit; a hardware code logic repository storing hardware code logic for generating the designed clock management unit into hardware code; and at least one processor configured to execute the at least one instruction stored in the memory, The at least one instruction includes the following instructions: Set the automatic clock gating of the clock management unit, Designing the new clock instance by setting the values ​​of register fields for defining the functions of the new clock instance based on the generated clock instance information and the clock component information contained in the clock management unit, activating the functional module of the new clock instance based on whether the automatic clock gating of the clock management unit is set or not and the setting value of the register field of the new clock instance, Generate hardware code related to the functional module activated based on the setting value of the register field of the new clock instance, the activated functional module information of the new clock instance and the hardware code logic, generate hardware code for the register module used to enable the activated functional module to work, and generate hardware code for connecting the register module with the port of the activated functional module and hardware code for the connection point.

2. The codeless clock management unit design system according to claim 1, wherein: The at least one instruction further includes an instruction for activating an adapter function module of the new clock instance when automatic clock gating of the clock management unit is set.

3. The codeless clock management unit design system according to claim 2, wherein: The connection points include a clock line and a handshake signal line.

4. The codeless clock management unit design system according to claim 1, wherein: The at least one instruction further comprises the following instruction: generating the new clock instance based on the generated clock instance information and the clock component information, determining a field value of a basic register for setting a basic function of a clock source corresponding to the new clock instance, A field value of an extension register for setting an extended function of the new clock instance is determined.

5. The codeless clock management unit design system according to claim 4, characterized in that: It also contains the following instructions: activating a basic function module for executing the basic functions of the new clock instance, When a field value of an extension register for setting an extended function of the new clock instance is set to a specific value, an extended function module for executing the extended function is activated.

6. The codeless clock management unit design system according to claim 1, wherein: The clock component information includes a basic function module of each clock component for performing basic functions and an extended function module for performing extended functions, the allocated address range, the alignment size of each clock component, the basic register offset size of each component, the extended register offset size of each component and the setting field information of each clock component.

7. The codeless clock management unit design system according to claim 6, characterized in that: The setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

8. The codeless clock management unit design system according to claim 6, wherein: The start address of the register of the new clock instance is determined by the sum of the start address of the register of the generated clock instance and the alignment size.

9. The codeless clock management unit design system according to claim 6, wherein: The clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

10. The codeless clock management unit design system according to claim 9, characterized in that: The clock component is a clock divider component, The fields of the extended register of the new clock instance include at least one of a power-off field, a throttling field, and a custom field. The clock divider component includes at least one of an overlay function module, a throttling function module, and a custom function module.

11. The codeless clock management unit design system according to claim 9, wherein: The clock component is a clock multiplexer component, The field of the extension register of the new clock instance includes at least one of a throttle field and a custom field, The clock multiplexer component includes at least one of a throttling function module and a custom function module.

12. The codeless clock management unit design system according to claim 9, wherein: The clock component is a clock gating component, The fields of the extended register of the new clock instance include at least one of a short stop field, an early wake-up field, and a custom field. The clock gating component includes at least one of a short stop function module, an early wake-up function module and a custom function module.

13. A method for designing a clock management unit in a codeless manner, the method being executed by at least one processor in a computer system comprising a clock component repository storing information of clock components constituting the clock management unit and a hardware code logic repository storing hardware code logic for generating the designed clock management unit into hardware code, wherein: The steps include: Set the automatic clock gating of the clock management unit; Designing the new clock instance by setting values ​​of register fields for defining functions of the new clock instance based on the generated clock instance information and the clock component information contained in the clock management unit; activating a functional module of the new clock instance based on whether the automatic clock gating of the clock management unit is set or not and a setting value of a register field of the new clock instance; as well as Generate hardware code related to the functional module activated based on the setting value of the register field of the new clock instance, the activated functional module information of the new clock instance and the hardware code logic, generate hardware code for the register module used to enable the activated functional module to work, and generate hardware code for connecting the register module with the port of the activated functional module and hardware code for the connection point.

14. The codeless clock management unit design method according to claim 13, wherein: The method further comprises the following steps: when setting the automatic clock gating of the clock management unit, activating the adapter function module of the new clock instance.

15. The codeless clock management unit design method according to claim 14, characterized in that: The connection points include a clock line and a handshake signal line.

16. The codeless clock management unit design method according to claim 13, wherein: The following steps are also included: generating the new clock instance based on the generated clock instance information and the clock component information; determining a field value of a basic register for setting a basic function of a clock source corresponding to the new clock instance; as well as A field value of an extension register for setting an extended function of the new clock instance is determined.

17. The codeless clock management unit design method according to claim 16, wherein: The following steps are also included: activating a basic function module for executing basic functions of the new clock instance; and When a field value of an extension register for setting an extended function of the new clock instance is set to a specific value, an extended function module for executing the extended function is activated.

18. The codeless clock management unit design method according to claim 13, wherein: The clock component information includes a basic function module of each clock component for performing basic functions and an extended function module for performing extended functions, the allocated address range, the alignment size of each clock component, the basic register offset size of each component, the extended register offset size of each component and the setting field information of each clock component.

19. The codeless clock management unit design method according to claim 18, wherein: The setting field information of each clock component includes field name, bit position, bit size, access permission, and initial value.

20. The codeless clock management unit design method according to claim 18, wherein: The start address of the register of the new clock instance is determined by the sum of the start address of the register of the generated clock instance and the alignment size.

21. The codeless clock management unit design method according to claim 18, wherein: The clock component is one of a phase-locked loop controller component, a clock divider component, a clock multiplexer component, and a clock gating component.

22. The codeless clock management unit design method according to claim 21, wherein: The clock component is a clock divider component, The fields of the extended register of the new clock instance include at least one of a power-off field, a throttling field, and a custom field. The clock divider component includes at least one of an overlay function module, a throttling function module, and a custom function module.

23. The codeless clock management unit design method according to claim 21, wherein: The clock component is a clock multiplexer component, The field of the extension register of the new clock instance includes at least one of a throttle field and a custom field, The clock multiplexer component includes at least one of a throttling function module and a custom function module.

24. The codeless clock management unit design method according to claim 21, wherein: The clock component is a clock gating component, The fields of the extended register of the new clock instance include at least one of a short stop field, an early wake-up field, and a custom field. The clock gating component includes at least one of a short stop function module, an early wake-up function module and a custom function module.

25. A computer program, characterized in that The method according to any one of claims 13 to 24 is stored on a computer-readable medium in order to execute it on a computer.

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