A processor, an instruction transmitting method, a chip and an electronic device

Abstract

This application provides a processor, instruction issuing method, chip, and electronic device. The processor includes: an issuing queue for storing multiple instructions to be issued, each instruction including a source operand, the source operand including a first source operand that reuses a wake-up comparison unit; a selector connected to the issuing queue for selecting a currently unready source operand from the first source operand for wake-up comparison; and a wake-up comparison unit including a first wake-up comparison unit configured to be reused by the first source operand and connected to the selector. The first wake-up comparison unit determines whether the currently unready source operand selected by the selector meets a ready condition; if so, it wakes up the currently unready source operand to enter a ready state. The processor can reduce the area and power consumption of the wake-up comparison unit in the issuing queue, thereby reducing the area and power consumption of the issuing queue and improving the processor's performance.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a processor, an instruction issuing method, a chip, and an electronic device. Background Technology

[0002] Modern processors typically employ superscalar out-of-order execution to improve instruction processing efficiency. During out-of-order execution, instructions are issued into the pipeline via a dispatch queue; this process is called instruction dispatch. However, as processor performance improves, the out-of-order window needs to be increased, leading to a gradual increase in the dispatch queue's footprint.

[0003] Against this backdrop, how to provide a processor that reduces the area and power consumption of the launch queue has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a processor, instruction issuing method, chip, and electronic device that can reduce the area and power consumption of the wake-up comparison unit in the issue queue, thereby reducing the area and power consumption of the issue queue and improving the performance of the processor.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a processor, including:

[0007] A transmit queue is used to store multiple instructions to be transmitted. Each instruction to be transmitted includes a source operand, and the source operand includes the first source operand of the multiplexed wake-up comparison unit.

[0008] The selector, connected to the transmit queue, is used to select the currently unready source operand for the wake-up comparison from the first source operand.

[0009] The wake-up comparison unit includes a first wake-up comparison unit, which is configured to be multiplexed by a first source operand. The first wake-up comparison unit is connected to the selector and determines whether the currently unready source operand selected by the selector meets the ready condition. If so, the currently unready source operand is woken up and enters the ready state.

[0010] Optionally, the source operand may further include a second source operand that uses the wake-up comparison unit independently;

[0011] The wake-up comparison unit further includes a second wake-up comparison unit corresponding to the number of the second source operands. The second wake-up comparison unit is used to perform a wake-up comparison on a non-ready second source operand to determine whether the readiness condition is met. If so, the non-ready second source operand is woken up and enters the readiness state.

[0012] Optionally, the selector, used to select the currently unready source operand from the first source operands for the wake-up comparison, includes:

[0013] Determine whether the first source operand is in a ready state. If there are multiple unready first source operands, select the current unready source operand according to the priority of the multiple first source operands.

[0014] Optionally, the number of the first source operands is one. If the first source operand is not ready, the first source operand is determined to be the selected currently unread source operand.

[0015] Optionally, the first source operand includes at least two first source operands. If neither of the at least two first source operands is ready, the first source operand with the higher priority is determined as the selected currently unready source operand according to the priority of the at least two first source operands. The unselected first source operand is set to a virtual ready state, and the first source operand in the virtual ready state is selected as the new currently unready source operand after the current unready source operand is awakened.

[0016] Optionally, the first source operand includes at least two first source operands, and among the at least two first source operands, there is a first source operand whose dependent data has been written back. In this case, the first source operand whose dependent data has been written back does not need to be woken up, and the first source operand whose dependent data has not been written back and is not ready is selected as the current unready source operand.

[0017] Optionally, the launch queue is further configured to, when a currently launched instruction is launched to the execution pipeline, if the currently launched instruction sent to the execution pipeline includes at least one source operand in a virtual ready state, cancel the wake-up and rely on the source operands in other launched instructions of the currently launched instruction.

[0018] Optional, also includes:

[0019] The target physical register stores the destination operand corresponding to the instruction to be issued after the execution unit executes it. The target physical register is connected to the wake-up comparison unit. The number of the target physical register is used to compare with the number of the source physical register of the current unready source operand to determine whether the current unready source operand meets the ready condition.

[0020] Optionally, the launch queue includes:

[0021] Multiple entries, each entry records the instruction information of a command to be issued, the instruction information including the number of the source physical register corresponding to the source operand of the command to be issued.

[0022] Secondly, embodiments of this application provide a command issuing method, including:

[0023] Multiple instructions to be transmitted are stored in the transmission queue. Each instruction to be transmitted includes a source operand, and the source operand includes the first source operand of the multiplexed wake-up comparison unit.

[0024] Select the currently unready source operand from the first source operands that is currently being compared for wake-up;

[0025] For the selected currently unread source operand, determine whether it meets the ready condition. If so, wake up the currently unread source operand and enter the ready state.

[0026] Thirdly, embodiments of this application provide a chip, the chip including the processor as described in the first aspect above.

[0027] Fourthly, embodiments of this application provide an electronic device, which includes the chip described in the third aspect above.

[0028] As can be seen, the processor provided in this application includes a launch queue for storing multiple instructions to be launched. Each instruction to be launched includes a source operand, which includes a first source operand that reuses a wake-up comparison unit. A selector is connected to the launch queue and is used to select a currently unready source operand from the first source operand for wake-up comparison. A wake-up comparison unit includes a first wake-up comparison unit configured to be reused by the first source operand. The first wake-up comparison unit is connected to the selector and determines whether the currently unready source operand selected by the selector meets the ready condition. If so, the currently unready source operand is woken up and enters the ready state. In other words, by configuring a wake-up comparison unit that can be reused by the first source operand and a selector for selecting the currently unready source operand, this application can realize the reuse of the same wake-up comparison unit by multiple first source operands. While realizing the function of the wake-up comparison unit to wake up unready source operands, it can reduce the area and power consumption of the wake-up comparison unit in the launch queue, thereby reducing the area and power consumption of the launch queue and improving the performance of the processor. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is an example diagram of command issuance for a launch queue;

[0031] Figure 2 This is an example diagram of command issuance using another type of issuance queue;

[0032] Figure 3 This is an example diagram of an optional processor structure provided in an embodiment of this application;

[0033] Figure 4 An optional flowchart of the instruction issuance method provided in the embodiments of this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] In modern processors, superscalar out-of-order execution is commonly used to improve instruction processing efficiency. Superscalar execution refers to the processor issuing multiple instructions to different execution units per cycle, such as issuing an addition instruction and a load instruction simultaneously. Out-of-order execution means that when an instruction is blocked due to data incompleteness, the processor can skip that instruction and execute a subsequent instruction whose data is ready. This allows for full utilization of hardware resources, avoids waiting, and improves instruction processing efficiency.

[0036] The issue queue is one of the core components of a processor that uses out-of-order execution. During the out-of-order execution of instructions, instructions need to be issued to the execution pipeline through the issue queue for execution. This process is called instruction issuance.

[0037] However, as processor performance improves, the out-of-order window needs to be increased, leading to a gradual increase in the area of ​​the issue queue. The out-of-order window refers to the range of instructions that the processor can observe simultaneously, i.e., how many instructions can be scheduled out of order. The larger the out-of-order window, the easier it is for the processor to find instructions that can be executed in parallel. This, in turn, leads to a gradual increase in the area and power consumption of the issue queue, which may affect the processor's performance.

[0038] To facilitate understanding, the following section, with reference to the accompanying diagram, will provide a detailed description of the structure of the launch queue for command transmission. Figure 1 This is an example diagram of command issuance in a launch queue. For example... Figure 1 As shown, the launch queue mainly consists of three parts: the wake-up unit, the launch unit (not shown in the figure), and the queue unit.

[0039] The queue unit is used to store basic information about the instruction, such as the destination physical register number (DestPrn); source physical register A, which is the source physical register corresponding to the source operand (Operation) A, where source operand A can be abbreviated as AOp; source physical register B, which is the source physical register corresponding to the source operand B, where source operand B can be abbreviated as BOp; and source physical register C, which is the source physical register corresponding to the source operand C, where source operand C can be abbreviated as COp.

[0040] The wake-up unit is used to detect whether the operand of an instruction is ready and to wake up subsequent instructions that depend on that operand by broadcasting. In a processor, a micro-operation (UOP) executed in fixed-point mode can include two operand objects, such as `ADD reg64, reg64`. Here, `reg64` indicates that the operand is a 64-bit register. The first `reg64` can be used as an AOP, and the second `reg64` can be used as a BOP. `ADD` represents addition. A micro-operation (UOP) executed in fixed-point mode can also include three operand objects, such as `ADC reg64, reg64`. Here, `ADC` (Add with Carry) is a special addition instruction used to perform addition with carry, adding two numbers and adding the previous carry value. The first `reg64` can be used as an AOP, the second `reg64` can be used as a BOP, and the Carry Flag (CF) can be used as a COp. The Carry Flag is a carry flag used to indicate whether the operation result has a carry. For example, `CF` of 1 indicates that there is a carry from the most significant bit to the higher bit, and `CF` of 0 indicates that there is no carry from the most significant bit to the higher bit. Furthermore, each operand, after being renamed, has a corresponding Physical Register Number (PRN) value in its PRF (Physical Register File), for example, AOp->PRNA, BOP->PRNB, COp->PRNC. When entering the launch queue, the PRF Valid Array (PRN) is queried to indicate whether the physical register data corresponding to the specified number is available / valid. If it is valid, it means that the data the corresponding physical register depends on has been written to the PRF and can be used; if invalid, it needs to wait to be woken up in the launch queue. Specifically, the wake-up method is to compare the source physical register number with the DestPrn of all UOPs on all execution pipelines. If the source physical register is the same as the DestPrn of any execution pipeline, it is woken up; otherwise, the comparison continues with the target physical register numbers of all UOPs on all execution pipelines in the next clock cycle. When the source physical registers of all source operands are ready, the entire UOP is ready and waiting to be selected for launch.

[0041] The issuing unit is used to select the earliest issueable instruction from the awakened instructions and issue it to the corresponding execution unit.

[0042] Combination Figure 1For example, the launch queue can include launch queue 0, launch queue 1, launch queue 2, and launch queue 3. Each launch queue can include multiple entries. An entry can be considered a storage unit for storing instructions in the launch queue. One entry records the instruction information of one instruction to be launched. Each entry has a wake-up unit and a queue unit, such as... Figure 1 As shown, a issue queue can have 24 entries, labeled entry0 to entry23 in the diagram. Each issue queue corresponds to an execution pipeline, and each execution pipeline is bound to an Arithmetic Logical Unit (ALU), such as ALU 0, ALU 1, ALU 2, and ALU 3 in the diagram. During wake-up, the issue queue selects the earliest entry from the ready UOPs (e.g., the instruction to be issued corresponding to entry0 in each issue queue) and issues it to the issue execution pipeline (e.g., issue execution pipeline 0, issue execution pipeline 1, issue execution pipeline 2, and issue execution pipeline 3). The DestPrn of the UOP on the issue execution pipeline is compared with the source physical register of each source operand of entry0 in each issue queue. If the numbers are equal, the UOP is woken up. In the next clock cycle, the earliest entry from the woken-up UOPs is selected and issued to the issue execution pipeline for wake-up.

[0043] Furthermore, Figure 2 This is an example diagram of command issuance using another type of issuance queue. For example... Figure 2 As shown, each launch queue corresponds to an execution pipeline. Taking launch queue 0 as an example, each source operand in the launch queue is configured with an independent wake-up comparison unit. The wake-up unit is the unit in the launch queue that triggers the wake-up process, notifying the wake-up comparison unit to start working. The wake-up comparison unit then performs the specific dependency matching and judgment process to determine whether the source operand meets the readiness conditions and is thus woken up. Continuing to refer to... Figure 2Each entry in the launch queue has three source operands. The source physical registers corresponding to these three source operands are numbered PRNA, PRNB, and PRNC. When an entry enters the launch queue, the PRF ValidArray is checked first. If it is invalid, it means that the data in the source physical register corresponding to that number (i.e., the source operand) is unavailable. When a source operand matches a DestPrn (i.e., the ALU DestPrn that stores the ALU operation results) on a certain execution pipeline, it is awakened. In the diagram, this is marked as PRNA Ready, PRNB Ready, and PRNC Ready, indicating that each source operand in entry0 is ready, and thus the entire entry0 is ready (marked as entry0 Ready in the diagram) and can be launched onto the execution pipeline. Each source operand can match the DestPrn of four execution units (e.g., ALU) per clock cycle (including ALU0DestPrn, ALU1DestPrn, ALU2DestPrn, and ALU3DestPrn). The comparison (DestPrn) checks if the comparison units are equal, thus the power consumption in this part is significant. The power consumption is directly proportional to the number of wake-up comparison units, where the number of wake-up comparison units = number of issue queues × number of execution pipelines × number of entries per issue queue × number of source operands. It can be seen that when it is necessary to expand the number of entries in the issue queues or expand the number of execution pipelines, the area and power consumption of the entire wake-up comparison unit will increase proportionally, thereby affecting the processor's performance.

[0044] To address the aforementioned issues, embodiments of this application provide a processor that can reduce the area and power consumption of the wake-up comparison unit in the transmit queue, thereby reducing the area and power consumption of the transmit queue and improving the processor's performance.

[0045] First, the inventors discovered through research that although the launch queue supports UOP launches with three source operands, the proportion of fixed-point UOPs with three source operands is relatively low, as shown in Table 1A below. Among them, the proportion of fixed-point UOPs with three source operands is only 13.9%, which is lower than the proportions with one or two source operands. Furthermore, as shown in Table 1B below, the proportion of cases where three source operands enter the launch queue and none of the three source operands are ready is only 1.6%. This is the lowest proportion, meaning that the proportion of cases where all three source operands require wake-up is low. In other words, only in 1.6% of cases will all three wake-up comparison units corresponding to the three source operands be used.

[0046] Number of source operands Unit: million percentage 0 source operands 7.2 6.4％ 1 source operand 39.9 35.3％ 2 source operands 50.3 44.5％ 3 source operands 15.7 13.9％ total 113.1

[0047] Table 1A

[0048] Number of source operands Unit: million percentage 0 source operands 7.2 6.4％ One source operand and requires wake-up 32.2 28.5％ One source operand and no wake-up required 7.7 6.8％ Two source operands and two that need to be woken up 10.5 9.3％ Two source operands and one that needs to be woken up 21 18.6％ Two source operands, neither requiring wake-up 18.8 16.6％ 3 source operands and 3 operands that need to be woken up 1.8 1.6％ 3 source operands and 2 of them require wake-up 5.9 5.2％ 3 source operands and 1 requiring wake-up 6 5.3％ 3 source operands and none of them require wake-up 2 1.8％ total 113.1

[0049] Table 1B

[0050] Based on this, the inventors of this application, through further research, proposed an improved processor scheme. Since the proportion of cases where multiple source operands need to use the wake-up comparison unit simultaneously is relatively low, it is not necessary to configure an independent wake-up comparison unit for each source operand. Multiple source operands can reuse the same wake-up comparison unit, thereby reducing the area and power consumption of the wake-up comparison unit while realizing the function of waking up unready source operands.

[0051] Specifically, Figure 3 This is an example diagram of an optional processor structure provided in an embodiment of this application, such as... Figure 3 As shown, the processor may include: a launch queue 310 for storing multiple instructions to be launched, each instruction to be launched including a source operand, the source operand including a first source operand multiplexed with a wake-up comparison unit; a selector 320 connected to the launch queue 310 for selecting a currently unready source operand for wake-up comparison from the first source operand; and a wake-up comparison unit including a first wake-up comparison unit 331 configured to be multiplexed with the first source operand, the first wake-up comparison unit 331 being connected to the selector 320, for determining whether the currently unready source operand selected by the selector meets the ready condition, and if so, waking up the currently unready source operand to enter the ready state.

[0052] In this embodiment, the launch queue 310 is used to store multiple commands to be launched, and launches the commands to the execution unit when the commands meet the ready conditions. Figure 3 As shown, the launch queue 310 may include multiple entries (entry0 to entry3 in the example in the figure). Each entry records the instruction information of an instruction to be launched. The instruction information may include the number of the source physical register corresponding to the source operand of the instruction to be launched. The number of the source physical register corresponding to the source operand can be used to compare with the numbers of all target physical registers in the execution pipeline when the source operand needs to be woken up.

[0053] Continue to refer to Figure 3 Each entry in the launch queue contains three source operands, AOp, BOp, and COp, which correspond to the source physical register numbers PRNA, PRNB, and PRNC, respectively. The source operands include a first source operand that reuses the wake-up comparison unit; in an optional implementation, the source operands may also include a second source operand that independently uses the wake-up comparison unit.

[0054] In the embodiments of this application, two source operands may be configured to reuse a wake-up comparison unit, while another source operand may use a wake-up comparison unit independently; or, all three source operands may reuse the same wake-up comparison unit.

[0055] This application's embodiments illustrate the use of two source operands multiplexing a single wake-up comparison unit, while another source operand uses a separate wake-up comparison unit, as an example. Figure 3 As shown in the embodiments of this application, the source operands BOP and COp can reuse a wake-up comparison unit, and the source operands BOP and COp can be referred to as the first source operands; the source operand AOp uses a wake-up comparison unit independently, and the source operand AOp can be referred to as the second source operand.

[0056] Accordingly, in this embodiment, the wake-up comparison unit may include a first wake-up comparison unit 331 and a second wake-up comparison unit 332; wherein, the first wake-up comparison unit 331 is configured to be multiplexed by a first source operand (e.g., source operand BOp and source operand COp), and the first wake-up comparison unit 331 may be connected to a selector 320 to determine whether the currently unready source operand selected by the selector meets the ready condition. If so, the currently unready source operand can be woken up to enter the ready state; wherein the ready condition is the number of the source physical register corresponding to the currently unready source operand, which matches the number of the target physical register on a certain execution pipeline.

[0057] The number of second wake-up comparison units 332 corresponds to the number of second source operands (e.g., source operand AOp). One second wake-up comparison unit can be used to wake up a non-ready second source operand to determine whether the ready condition is met. If so, the non-ready second source operand is woken up and enters the ready state.

[0058] In other embodiments, the source operands AOp and BOp may be configured to reuse a first wake-up comparison unit, while the source operand COp may use a second wake-up comparison unit independently; or, the source operands AOp and COp may reuse a first wake-up comparison unit, while the source operand BOp may use a second wake-up comparison unit independently.

[0059] Furthermore, since multiple source operands reuse one wake-up comparison unit, and only one source operand can use one wake-up comparison unit per clock cycle, this embodiment of the application sets selector 320 to judge and select multiple source operands to ensure that only one source operand can use the first wake-up comparison unit per clock cycle.

[0060] In an optional embodiment, such as Figure 3As shown, selector 320 is connected to transmit queue 310. The source operands BOp and COp of entry0 in the transmit queue are input to selector 320. Selector 320 selects the currently unready source operand that needs to be compared with the wake-up comparison unit from the two source operands of the multiplexed wake-up comparison unit. That is, the source operand that is currently in an unready state.

[0061] In an optional implementation, the selector 320 is used to select the currently unready source operand for wake-up comparison from the first source operands by: determining whether the first source operand is in a ready state; if there are multiple unready first source operands, then selecting the currently unready source operand according to the priority of the multiple first source operands.

[0062] In other words, when selecting the currently unread source operand for the multiplexed wake-up comparison unit from multiple first source operands, it is necessary to first determine whether the current first source operand is in a ready state. If it is in a ready state, there is no need to use the wake-up comparison unit; if it is not in a ready state, the wake-up comparison unit needs to be used. During this process, multiple unread first source operands may occur, all of which require the use of the wake-up comparison unit. In this case, the selection can be made according to the priority of the multiple first source operands.

[0063] The following section details the three possible source operand scenarios when the selector in this application wakes up a currently unread source operand. Table 2 below illustrates these scenarios using source operands in entries 0, 1, and 2 of the transmit queue as examples. Source operands include AOp, BOp, and COp. AOp Ready? indicates whether source operand AOp is ready; BOp Ready? indicates whether source operand BOp is ready; and COp Ready? indicates whether source operand COp is ready.

[0064]

[0065] Table 2

[0066] In an optional embodiment, the number of the first source operands is one, and if the first source operand is not ready, the first source operand is determined to be the selected currently unread source operand.

[0067] As shown in entry0 of Table 2, after querying the PRF Valid Array, it was found that the source operands AOp and BOp are valid in this instruction, while COp is invalid, meaning that this instruction only has two source operands. Combined with... Figure 3In this instruction, there is only one first source operand, namely source operand BOp, and the second source operand is AOp, which can independently use the second wake-up comparison unit. At this time, source operand BOp can independently use the first wake-up comparison unit, and there is no situation of multiplexing with other source operands. If the first source operand BOp is in an unready state, it can be determined that the first source operand BOp is the currently unready source operand selected by the selector.

[0068] In another optional embodiment, the first source operand includes at least two first source operands. If neither of the at least two first source operands is ready, the first source operand with the higher priority is determined as the selected currently unready source operand according to the priority of the at least two first source operands. The unselected first source operand is set to a virtual ready state, and the first source operand in the virtual ready state is selected as the new currently unready source operand after the current unready source operand is awakened.

[0069] As shown in Table 2, entry1 indicates that after querying the PRF Valid Array, it was found that all three source operands in the instruction were valid, but none of them were ready. In other words, when querying the PRF (Physical Register File), none of the source physical registers for the three source operands had been written back. Combined with... Figure 3 In this instruction, the first source operands include two: source operand BOp and source operand COp. If neither source operand is ready, the first source operand with the higher priority is selected as the currently unready source operand. For example, source operand BOp has a higher priority than source operand COp; therefore, source operand BOp is selected as the currently unready source operand. At this time, the unselected source operand COp cannot use the wake-up comparison unit and needs to be set to a fake ready state.

[0070] Furthermore, once both source operands AOp and BOp are awakened, the entire UOP, i.e. the instruction, is considered to meet the execution conditions and can be issued to the execution pipeline. Specifically, as shown in Table 3 below, for example, if the UOP is ADC RAX and RBX, at time T0, the entire UOP is woken up; at time T1, the instruction is issued to the execution pipeline; at time T2, the data of the source physical registers of the three source operands in the PRF is read. At the same time, since the source operand COp is set to the Fake Ready state, the PRF Valid Array needs to be queried to determine if it is truly valid. If invalid, at time T3, the execution is canceled; at the same time, since BOP is ready at this time, the source operand COp is selected as the new currently unready source operand and can be woken up using the first wake-up comparison unit. Thus, at time T3, the entire UOP is woken up again; at time T4, the instruction is issued; at time T5, since COp is not set to the Fake Ready state, there is no need to query the PRF Valid Array, and the data of the source physical registers of the three source operands in the PRF is read; at time T6, the instruction is executed; at time T7, the result after the instruction execution is written back.

[0071]

[0072] Table 3

[0073] In another optional embodiment, the first source operand includes at least two first source operands, and among the at least two first source operands, there is a first source operand whose dependent data has been written back. In this case, the first source operand whose dependent data has been written back does not need to be woken up, and the first source operand whose dependent data has not been written back and is not ready is selected as the current unready source operand.

[0074] As shown in Table 2, entry2 indicates that after querying the PRF Valid Array, it was found that all three source operands in this instruction are valid. Specifically, when entering the launch queue, the data that BOp depends on has already been written back to the PRF, indicating that BOp is ready and does not need to wait for wake-up. The source operands AOp and COp, however, need to wait for wake-up. Figure 3 As shown, the instruction includes two source operands: source operand BOp and source operand COp. The source operand BOp, whose dependent data has been written back, does not need to be woken up. The source operand COp, whose dependent data has not been written back and is not ready, is selected as the current unready source operand. At this time, COp can use the first wake-up comparison unit and does not need to set the fake ready state.

[0075] Furthermore, in the embodiments of this application, when setting the Fake Ready state for the source operand, the dependency chain propagation problem of Fake Ready may occur: Suppose there are two instructions UOP0 and UOP1. When the source operand COp in UOP0 is set to the Fake Ready state, when this instruction is issued, another instruction UOP1 that depends on a source operand in this instruction is awakened. Although there is no source operand set to the Fake Ready state in UOP1, UOP0 may be canceled after querying the PRF Valid Array because COp is set to Fake Ready. Therefore, UOP1 also needs to be canceled. The above situation can be called the dependency chain propagation problem of Fake Ready.

[0076] For ease of understanding, please refer to Table 4A below. There are currently two instructions, such as UOP0 ADC RAX, RBX and UOP1 AND R7, RAX. In UOP0, COp is the Carry Flag, set to Fake Ready state. At time T0, UOP0 RAX and RBX are woken up. At time T1, UOP0 is issued to the execution pipeline. At the same time, since the source operand RAX of UOP1 depends on RAX in UOP0, UOP1 is woken up. At time T2, UOP0 reads the data of the source physical registers of the three source operands in the PRF and queries the PRF Valid Array. Since COp is not ready, at time T3, the execution of UOP0 is canceled. After the execution of UOP0 is canceled, since UOP1 depends on UOP0, at time T4, the execution of UOP1 is also canceled.

[0077]

[0078] Table 4A

[0079] To address the dependency chain issue that arises when setting up Fake Ready, in this embodiment of the application, the launch queue can also be used to cancel wake-up if, when a currently launched instruction is launched to the execution pipeline, it includes at least one source operand in a virtual ready state, and the source operand in other launched instructions that depend on the currently launched instruction.

[0080] In the specific implementation, as shown in Table 4B below, in UOP0, COp is the Carry Flag, set to the Fake Ready state. At time T0, UOP0 RAX and RBX are woken up; at time T1, UOP0 is issued to the execution pipeline. At this time, when UOP0 is issued at time T1, it does not wake up other UOPs.

[0081] At time T2, UOP0 reads the data from the source physical registers of the three source operands in the PRF and queries the PRF ValidArray. At this time, regardless of whether COp is ready, at time T3, the execution of UOP0 is cancelled.

[0082] If COp is in a real ready state at time T3, UOP0 can be woken up again at time T4. At this time, since there is no source operand in UOP0 in a virtual ready state, when the instruction is issued at time T5, waking up UOP1 will not have the aforementioned Fake Ready dependency chain propagation problem.

[0083] If COp is in a Fake Ready state at time T3, COp can use the first wake-up comparison unit to wait for wake-up. After being woken up, when the instruction is issued, since there is no Fake Ready source operand in UOP0, the dependency chain propagation problem of Fake Ready will not occur.

[0084]

[0085] Table 4B

[0086] In other words, when a currently pending instruction is sent to the execution pipeline, if the currently issued instruction sent to the execution pipeline includes at least one source operand in a virtual ready state, the wake-up needs to be canceled. The source operands in other pending instructions that depend on the currently issued instruction should also be canceled for further confirmation and wake-up operations. This ensures that all three source operands are in a real ready state and not in a fake ready state, and then the instruction is issued and executed again. This avoids the dependency chain propagation problem caused by fake ready.

[0087] Furthermore, in embodiments of this application, the processor may further include: a target physical register (e.g., Figure 3 The ALU0 DestPrn, ALU1 DestPrn, ALU2 DestPrn, and ALU3 DestPrn shown represent the destination operands corresponding to the execution unit after executing the instruction to be transmitted. The target physical register is connected to the wake-up comparison unit. The number of the target physical register is used to compare with the number of the source physical register of the current unready source operand to determine whether the current unready source operand meets the ready condition.

[0088] If the source physical register number of the currently unread source operand is equal to the target physical register number, it means that the currently unread source operand meets the readiness condition and has been successfully awakened. For example, PRNAReady and PRNB / PRNC Ready are shown in the figure. When all three source operands are in the readiness state, it means that the instruction is ready (entry0 Ready) and can be issued to the execution pipeline.

[0089] As can be seen, the processor provided in this application includes a launch queue for storing multiple instructions to be launched, each instruction to be launched including a source operand, the source operand including a first source operand that reuses a wake-up comparison unit; a selector connected to the launch queue for selecting a currently unready source operand from the first source operand for wake-up comparison; and a wake-up comparison unit including a first wake-up comparison unit configured to be reused by the first source operand, the first wake-up comparison unit being connected to the selector, and determining whether the currently unready source operand selected by the selector meets the ready condition. If so, the currently unready source operand is woken up and enters the ready state. It can be seen that by configuring a wake-up comparison unit that can be reused by the first source operand and a selector for selecting the currently unready source operand, this application can realize the reuse of the same wake-up comparison unit by multiple first source operands. While realizing the function of the wake-up comparison unit to wake up unready source operands, it can reduce the area and power consumption of the wake-up comparison unit in the launch queue, thereby reducing the area and power consumption of the launch queue and improving the performance of the processor.

[0090] In a further optional implementation, based on the processor provided in the embodiments of this application, the embodiments of this application also provide an instruction issuing method applied to the processor described in the foregoing embodiments. In an optional implementation, Figure 4 An optional flowchart of the command issuance method provided in an embodiment of this application. (Refer to...) Figure 4 The method may include the following steps.

[0091] Step S401: Store multiple instructions to be transmitted into the transmission queue. Each instruction to be transmitted includes a source operand, and the source operand includes the first source operand of the multiplexed wake-up comparison unit.

[0092] Step S402: Select the currently unready source operand from the first source operand for the wake-up comparison;

[0093] Step S403: For the selected currently unread source operand, determine whether it meets the ready condition. If so, wake up the currently unread source operand and enter the ready state.

[0094] It should be noted that the optional and extended implementations of the instruction issuance method provided in this application can be referred to in conjunction with the descriptions in the corresponding sections above, and will not be elaborated here.

[0095] In a further optional implementation, embodiments of this application also provide a chip, the chip including the processor as described in the foregoing embodiments.

[0096] In a further optional implementation, embodiments of this application also provide an electronic device, the electronic device including the chip as described in the foregoing embodiments.

[0097] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0098] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A processor, characterized in that, include: A transmit queue is used to store multiple instructions to be transmitted. Each instruction to be transmitted includes a source operand, which includes a first source operand of a multiplexed wake-up comparison unit. In each clock cycle, only one source operand uses one wake-up comparison unit. The selector, connected to the transmit queue, is used to select the currently unready source operand for the wake-up comparison from the first source operand. A wake-up comparison unit, comprising a first wake-up comparison unit configured to be multiplexed by a first source operand, the first wake-up comparison unit being connected to the selector, determining whether the currently unready source operand selected by the selector meets the ready condition; if so, waking up the currently unready source operand to enter the ready state. The first source operand includes at least two first source operands. If neither of the at least two first source operands is ready, the first source operand with the higher priority is selected as the currently unready source operand according to the priority of the at least two first source operands. The unselected first source operand is set to a virtual ready state. The first source operand in the virtual ready state is selected as the new currently unready source operand after the current unready source operand is woken up. The launch queue is also used to cancel the wake-up when the current instruction to be launched is launched to the execution pipeline. If the current launched instruction sent to the execution pipeline includes at least one source operand in the virtual ready state, the wake-up is canceled, and the source operands in other instructions to be launched depend on the current launched instruction.

2. The processor according to claim 1, characterized in that, The source operand also includes a second source operand that uses the wake-up comparison unit independently; The wake-up comparison unit further includes a second wake-up comparison unit corresponding to the number of the second source operands. The second wake-up comparison unit is used to perform a wake-up comparison on a non-ready second source operand to determine whether the readiness condition is met. If so, the non-ready second source operand is woken up and enters the readiness state.

3. The processor according to claim 1, characterized in that, The selector, used to select from the first source operands the currently unready source operand for the wake-up comparison, includes: Determine whether the first source operand is in a ready state. If there are multiple unready first source operands, select the current unready source operand according to the priority of the multiple first source operands.

4. The processor according to claim 3, characterized in that, The first source operand includes at least two first source operands, and among the at least two first source operands, there is a first source operand whose dependent data has been written back. In this case, the first source operand whose dependent data has been written back does not need to be woken up. The first source operand whose dependent data has not been written back and is not ready is selected as the current unready source operand.

5. The processor according to claim 1, characterized in that, Also includes: The target physical register stores the destination operand corresponding to the instruction to be issued after the execution unit executes it. The target physical register is connected to the wake-up comparison unit. The number of the target physical register is used to compare with the number of the source physical register of the current unready source operand to determine whether the current unready source operand meets the ready condition.

6. The processor according to claim 1, characterized in that, The launch queue includes: Multiple entries, each entry records the instruction information of a command to be issued, the instruction information including the number of the source physical register corresponding to the source operand of the command to be issued.

7. A method for issuing commands, characterized in that, include: Multiple instructions to be transmitted are stored in a transmission queue. Each instruction to be transmitted includes a source operand, which includes a first source operand of a multiplexed wake-up comparison unit. In each clock cycle, only one source operand uses one wake-up comparison unit. Select the currently unready source operand from the first source operands that is currently being compared for wake-up; For the selected currently unread source operand, determine whether it meets the ready condition. If so, wake up the currently unread source operand and enter the ready state. The first source operand includes at least two first source operands. If neither of the at least two first source operands is ready, the first source operand with the higher priority is selected as the currently unready source operand according to the priority of the at least two first source operands. The unselected first source operand is set to a virtual ready state. The first source operand in the virtual ready state is selected as the new currently unready source operand after the current unready source operand is woken up. The launch queue is also used to cancel the wake-up when the current instruction to be launched is launched to the execution pipeline. If the current launched instruction sent to the execution pipeline includes at least one source operand in the virtual ready state, the wake-up is canceled, and the source operands in other instructions to be launched depend on the current launched instruction.

8. A chip, characterized in that, The chip includes the processor as described in any one of claims 1-6.

9. An electronic device, characterized in that, The electronic device includes the chip as described in claim 8.

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