Two-order loading value prediction design method and system based on path historical information

Abstract

The invention discloses a two-order loading value prediction design system based on path history information. The two-order loading value prediction design system comprises a path history register, a loading instruction address prediction table, a loading address reservation station, a value prediction table and a speculation conflict detection table, the invention also discloses a two-order loading value prediction design method based on path historical information. The method comprises the following steps: S1, predicting a memory address possibly accessed by a loading instruction through a loading instruction address prediction table; s2, storing the predicted memory address into a loading address reservation station; s3, when the load assembly line is idle, entering the load assembly line in advance, and accessing the data cache by using the memory address in the loading address reservation station; and S4, when the memory access instruction reaches a renaming stage, checking whether a predicted value exists in the value prediction table or not. The value of the loading instruction is predicted through the path information, and the prediction process can be more accurate.

Description

Technical Field

[0001] The present invention relates to the technical field of value prediction, and in particular to a two-order loading value prediction design method and system based on path history information. Background Art

[0002] Currently, in modern high-performance processors, load instructions are the key bottleneck of pipeline execution because load instructions need to obtain data from memory or cache, and the latency of memory access is usually high, which will cause the load instruction pipeline to stall, thereby reducing the processor throughput.

[0003] There is a method for predicting load values ​​based on the program counter. This method predicts the value of the next load instruction based on the value read by the previous load instruction with the same program counter, without considering whether the memory address actually accessed by the load instruction has changed. Therefore, when two load instructions have the same program counter, if the value read by the first load instruction is 10, then the value predicted by the second load instruction may also be 10. If the store instruction in the meantime writes 20, the prediction of the load instruction will fail. Secondly, if the address of the load instruction changes, it cannot provide a correct prediction. For example, the address of the first load instruction in a loop is 0, and the address of the second load instruction is 4. However, the prediction may be based on the program counter of the load instruction itself, and the same value will be predicted. In fact, the paths of the load instructions are different, and the predicted values ​​should also be different. Summary of the Invention

[0004] In response to the above problems, the purpose of the present invention is to propose a two-stage load value prediction design method and system based on path history information. The value prediction process adopts two stages. The first stage predicts the address of the load instruction. The second stage obtains the value of the load instruction through the predicted address, reducing the influence of the storage instruction on the value prediction, thereby making the prediction process more accurate.

[0005] This is achieved through the following technical solutions: First, a two-stage load value prediction design system based on path history information is proposed, comprising: a path history register for generating an index using a hash function with the starting address of a series of instructions; a load instruction address prediction table for predicting the memory addresses that may be accessed by the load instruction based on the generated index; a load address reservation station for storing the memory addresses predicted by the load instruction address prediction table; a value prediction table for storing a data cache for memory address hits in the load address reservation station; and a speculation conflict detection table for recording the memory addresses of load instructions to prevent store instructions from storing data at updated predicted addresses. The system of the present invention predicts the value of load instructions using path information, making the prediction process more accurate.

[0006] Preferably, the path history register is implemented using a shift register and is used to record dynamic path information of various instructions. The path history register records the dynamic path information of various instructions so as to predict the address accessed by the load instruction later.

[0007] Preferably, the fields of the data structure of the load instruction address prediction table include at least: a tag, a memory address, a confidence bit, and a load data bit width. By using the load instruction address prediction table to predict the memory address that the load instruction may access, the accuracy of the predicted load instruction value can be improved.

[0008] Preferably, the load instruction address prediction table is updated each time a load instruction is executed. By updating the load instruction address prediction table and adjusting the historical records in the load instruction address prediction table, the accuracy of subsequent predictions by the load instruction address prediction table can be improved.

[0009] Preferably, the fields of the speculation conflict detection table data structure include at least a tag, a VId, an offset, and a timestamp. By using the speculation conflict detection table to record the memory addresses of load instructions that result in mispredictions due to load-store conflicts, the impact of uncommitted store instructions on the return value of load instructions is further reduced.

[0010] Preferably, the speculation conflict detection table uses a 32-entry fully associative structure and an LRU replacement strategy. By speculating that the conflict detection table uses a 32-entry fully associative structure and an LRU replacement strategy, the efficiency of detecting Load-Store conflicts can be further improved.

[0011] On the second aspect, a two-stage load value prediction design method based on path history information is also proposed, which includes the following steps: S1. Predicting the memory address that the load instruction may access through the load instruction address prediction table. If the load instruction address prediction table hits and the confidence is greater than the set threshold, the predicted memory address is used, otherwise no prediction is performed; S2. The predicted memory address is stored in the load address reservation station; S3. When there is idle time in the load pipeline, enter the load pipeline in advance and access the data cache with the memory address in the load address reservation station. If the data cache is hit, the data is taken out and stored in the value prediction table. If it does not hit, data prefetching is triggered and no value prediction is performed; S4. When the memory access instruction reaches the renaming stage, check whether the value prediction table already has a predicted value. If the value prediction table has a predicted value, directly use the predicted value and continue to execute subsequent instructions. If the value prediction table does not have a predicted value, the load instruction is executed normally and the memory is accessed. The method of the present invention adopts two stages to perform value prediction. The first stage predicts the address of the load instruction and the second stage obtains the value of the load instruction through the predicted address, reducing the influence of the storage instruction on the value prediction, thereby making the prediction process more accurate.

[0012] Preferably, in step S4, the memory access instruction includes a load instruction and a store instruction. The load instruction and the store instruction can collaboratively complete the prediction process of the value of the load instruction and improve the efficiency of value prediction.

[0013] Preferably, in step S4, when the value prediction table has a predicted value, a check is performed to determine whether the prediction table hits the speculation conflict detection table. If so, no prediction result is provided. If not, a prediction result is provided and returned to the main pipeline. By checking whether a load-store conflict exists through the speculation conflict detection table, the accuracy of predicting the value of the load instruction can be further improved.

[0014] Preferably, when checking whether the speculation conflict detection table is hit, the query is performed by using the starting address of a series of instructions as an index. By using the starting address of a series of instructions as an index to check whether the speculation conflict detection table is hit, Load-Store conflicts can be identified in advance, ensuring the correctness of memory access.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention predicts the value of a load instruction through path information, which can make the prediction process more accurate; wherein, the value prediction process adopts two stages, the first stage first predicts the memory address of the load instruction, the second stage obtains the value of the load instruction through the predicted memory address, and reduces the influence of the storage instruction on the value prediction by speculating the conflict detection table, thereby being able to accurately predict the value of the load instruction and improve the accuracy of predicting the value of the load instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the structure of a two-stage load value prediction design system based on path history information; Figure 2 Flowchart of a two-order load value prediction design method based on path history information. DETAILED DESCRIPTION

[0017] The following is a combination of the embodiments of the present invention Figure 1-2 , the technical solutions in the embodiments of the present invention are described in detail.

[0018] like Figure 1As shown in the figure, it is a structural diagram of a two-stage load value prediction design system based on path history information. The figure includes two parts: the original pipeline stage and the two-stage load value prediction system; the original pipeline stage includes: branch prediction unit, instruction fetch unit, decoding, renaming, physical memory, allocation, emission, other execution units, load pipeline and submission; the two-stage load value prediction system includes: PC, PHR, Hash, load instruction address prediction table, load address reservation station, value prediction table and speculation conflict detection table.

[0019] Among them, PC stands for Program Counter, which is used to store the memory address of the load instruction currently being executed or about to be executed; PHR stands for Path History Register, which is used to record the dynamic path information of various instructions; Hash stands for hash function, which is used to calculate the path history register and the starting address of a series of instructions to obtain the index of the load instruction address prediction table.

[0020] The design system specifically includes the following: Path history register; used to generate an index with the starting address of a series of instructions through a hash function.

[0021] Specifically, the path history register is implemented using a 128-bit shift register, and the path history register is updated during the decoding stage, that is, when a certain instruction is confirmed to be a load instruction. The update rule is to push the low-order memory address of the load instruction into the path history register. The path history register records the dynamic path information of various instructions to facilitate subsequent prediction of the address accessed by the load instruction.

[0022] Load instruction address prediction table; used to predict the memory address that may be accessed by the load instruction based on the generated index.

[0023] Among them, the fields of the data structure of the load instruction address prediction table include at least: Tag, which is an index calculated by the path history register and the starting address of a series of instructions, and is used to match the entries of the load instruction address prediction table; memory address, which refers to the memory address of the predicted load instruction; confidence bit, which refers to the confidence of the prediction result, which is used to indicate whether the prediction is adopted this time; load data bit width, which is used to indicate the size of the accessed data; the present invention can improve the accuracy of the predicted value of the load instruction by using the load instruction address prediction table to predict the memory address that the load instruction may access.

[0024] In this embodiment, the load instruction address prediction table will be updated every time a load instruction is executed; specifically, its update conditions and operations include: the load instruction address prediction table hits and the prediction is correct: the confidence bit ++, that is, the confidence increases; the load instruction address prediction table hits and the prediction is wrong: the prediction content and confidence bit are reset, that is, the prediction address and confidence are cleared to zero; the load instruction address prediction table does not hit and the confidence bit of the load instruction address prediction table entry waiting to be replaced is not 0: the confidence bit of the corresponding item is -, that is, the confidence of the load instruction address prediction table entry waiting to be replaced is decreased; the load instruction address prediction table does not hit and the confidence bit of the load instruction address prediction table entry waiting to be replaced is 0: the prediction content and confidence bit of the corresponding item are reset, that is, the prediction address and confidence of the load instruction address prediction table entry waiting to be replaced are cleared to zero.

[0025] Among them, the load instruction address prediction table entry to be replaced is determined according to the LRU strategy. LRU stands for Least Recently Used, which is a least recently used algorithm for eliminating the data that has not been used for the longest time. In the present invention, when the load instruction address prediction table does not hit and the confidence bit of the load instruction address prediction table entry waiting to be replaced is 0, the predicted memory address is replaced with the memory address that has not been used for the longest time in the load instruction address prediction table. By updating the load instruction address prediction table and adjusting the historical records in the load instruction address prediction table, the accuracy of subsequent predictions of the load instruction address prediction table can be improved.

[0026] Load address reservation station; used to store the memory address predicted by the load instruction address prediction table.

[0027] Value prediction table; a data cache used to store memory address hits in the load address reservation station.

[0028] Speculation conflict detection table; used to record the memory address of the load instruction to prevent the store instruction from storing data to the updated predicted address.

[0029] Specifically, the fields of the data structure of the speculation conflict detection table include at least: Tag, which refers to the index obtained by the starting address of a series of instructions; VId, the full name of which is Version ID, that is, the version number, which is used to indicate that the current data is valid; Offset bit, which refers to the offset of the memory address, which is used to accurately locate the memory address; Timestamp, which records the timing information of the operation, which is used to resolve the timing judgment when the Load-Store conflict occurs; Among them, Load-Store conflict means that: the storage instruction modifies the content of the updated predicted address, and the predicted value of the load instruction is affected by the uncommitted storage instruction; by using the speculation conflict detection table to record the memory address of the load instruction that caused the prediction error due to the Load-Store conflict, the impact of the uncommitted storage instruction on the return value of the load instruction is further reduced.

[0030] In this embodiment, the speculation conflict detection table uses a 32-entry fully connected structure and an LRU replacement strategy; the 32-entry fully connected structure means that each address that needs to be stored can be stored at any position in the speculation conflict detection table; the LRU replacement strategy means that when the speculation conflict detection table is full and a new address needs to be inserted, the address that has not been used for the longest time is selected for replacement; the speculation conflict detection table uses a 32-entry fully connected structure and an LRU replacement strategy, which can further improve the efficiency of detecting Load-Store conflicts.

[0031] like Figure 2 As shown, it is a flow chart of a two-stage load value prediction design method based on path history information. First, the memory address that the load instruction may access is predicted through the load instruction address prediction table; secondly, the predicted memory address is stored in the load address reservation station; then, when there is idle time in the load pipeline, the load pipeline is entered in advance, and the memory address in the load address reservation station is used to access the data cache; finally, when the memory access instruction reaches the renaming stage, the value prediction table is checked to see if there is a predicted value, and whether the speculation conflict detection table is hit; the present invention predicts the value of the load instruction through path information, which can make the prediction process more accurate.

[0032] The method specifically comprises the following steps: S1. Predict the memory address that the load instruction may access through the load instruction address prediction table. If the load instruction address prediction table hits and the confidence level is greater than the set threshold, the predicted memory address is used; otherwise, no prediction is performed.

[0033] S2. Store the predicted memory address into the load address reservation station.

[0034] S3. When there is an idle time in the load pipeline, enter the load pipeline in advance and use the memory address in the load address reservation station to access the data cache. If the data cache is hit, the data is taken out and stored in the value prediction table. If it is not hit, data prefetching is triggered without value prediction. When there is no idle time in the load pipeline, wait in the load address reservation station for the load pipeline to be idle.

[0035] S4. When the memory access instruction reaches the renaming stage, check whether the value prediction table already has a predicted value. If the value prediction table has a predicted value, directly use the predicted value and continue to execute subsequent instructions. If the value prediction table does not have a predicted value, the load instruction is executed normally to access the memory; wherein, the memory access instruction includes: load instructions and store instructions.

[0036] In this embodiment, in step S4, when the value prediction table has a predicted value, it is checked whether the speculation conflict detection table is hit. If it is hit, the prediction result is not provided. If it is not hit, the prediction result is provided and the prediction result is returned to the mainstream pipeline. When checking whether the speculation conflict detection table is hit, the query is performed by using the starting address of a series of instructions as an index. The method of the present invention checks whether there is a Load-Store conflict through the speculation conflict detection table, and can identify the Load-Store conflict in advance, ensure the correctness of memory access, and further improve the accuracy of predicting the value of the load instruction.

[0037] In summary, the present invention predicts the value of the load instruction through path information, which can make the prediction process more accurate; wherein, the value prediction process adopts two stages, the first stage first predicts the memory address of the load instruction, the second stage obtains the value of the load instruction through the predicted memory address, and reduces the influence of the storage instruction on the value prediction by the speculation conflict detection table, thereby being able to accurately predict the value of the load instruction, improve the accuracy of predicting the value of the load instruction, and has significant progress.

[0038] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A two-order load value prediction and design system based on path history information, characterized in that: include: Path history register; used to generate an index with the starting address of a series of instructions through a hash function; Load instruction address prediction table; Used to predict the memory address that the load instruction may access based on the generated index; Load address reservation station; used to store the memory address predicted by the load instruction address prediction table; Value prediction table; A data cache for storing memory address hits in the load address reservation station; Speculation conflict detection table; used to record the memory address of the load instruction to prevent the store instruction from storing data to the updated predicted address.

2. A two-order load value prediction and design system based on path history information according to claim 1, characterized in that: The path history register is implemented using a shift register and is used to record dynamic path information of various instructions.

3. The two-order loading value prediction and design system based on path history information according to claim 1 is characterized in that: The fields of the data structure of the load instruction address prediction table include at least: Tag, memory address, confidence bit and load data bit width.

4. The two-order loading value prediction and design system based on path history information according to claim 1 is characterized in that: Whenever a load instruction is executed, the load instruction address prediction table will be updated.

5. The two-order loading value prediction and design system based on path history information according to claim 1 is characterized in that: It is speculated that the fields of the data structure of the conflict detection table include at least: Tag, VId, offset bit and timestamp.

6. The two-order loading value prediction and design system based on path history information according to claim 1 is characterized in that: The conflict detection table is speculated to use a 32-entry fully connected structure and an LRU replacement strategy.

7. A two-order loading value prediction and design method based on path history information, using a two-order loading value prediction and design system based on path history information according to any one of claims 1 to 6, characterized in that: The method comprises the following steps: S1. Predict the memory address that the load instruction may access through the load instruction address prediction table. If the load instruction address prediction table hits and the confidence level is greater than the set threshold, the predicted memory address is used; otherwise, no prediction is performed. S2. Store the predicted memory address into the load address reservation station; S3. When there is idle time in the load pipeline, enter the load pipeline in advance and use the memory address in the load address reservation station to access the data cache. If the data cache hits, the data is retrieved and stored in the value prediction table. If it does not hit, data prefetching is triggered without value prediction. S4. When the memory access instruction reaches the renaming stage, check whether the value prediction table already has a predicted value. If the value prediction table has a predicted value, use the predicted value directly and continue to execute subsequent instructions. If the value prediction table does not have a predicted value, the load instruction is executed normally to access the memory.

8. The two-order loading value prediction design method based on path history information according to claim 7 is characterized in that: In step S4, the memory access instruction includes: a load instruction and a store instruction.

9. The two-stage load value prediction design method based on path history information according to claim 7 is characterized in that: In step S4, when the value prediction table has a predicted value, it is checked whether it hits the speculation conflict detection table. If it hits, no prediction result is provided. If it does not hit, a prediction result is provided and returned to the main pipeline.

10. A two-order loading value prediction and design method based on path history information according to claim 9, characterized in that: When checking whether the speculation conflict detection table hits, the query is performed using the starting address of a series of instructions as an index.

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