Processor port resource allocation system and server

Abstract

The invention discloses a processor port resource allocation system and a server, and relates to the technical field of processors. According to the processor port resource allocation system provided by the scheme, the basic function fixed resource and the open computing project network card fixed resource are concentrated to the two universal ports of the main processor by utilizing the PCIe / SATA split configuration characteristic of the processor; on the basis of guaranteeing the normal basic functions of the main processor, processor resources occupied by the basic functions are compressed to the greatest extent, so that other universal ports in the main processor and universal ports of the slave processors are used for externally expanding NVMe hard disks or PCIe external plug-in cards, and the external expansion capability of the processors is improved; the problem that a current CPU is unreasonable in configuration of external PCIe resources is solved, and waste of universal port resources is avoided.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a processor port resource allocation system and server. Background Art

[0002] Currently, some servers offer flexible external expansion of the high-speed Peripheral Component Interconnect Express (PCIe) bus standard. To maximize PCIe resource expansion, the design of the server's central processing unit (CPU) motherboard requires careful consideration of its rational utilization.

[0003] Currently, a CPU supports four 16-bit General Purpose Interface (GPI) ports for PCIe resources. Each GPI port can support X16 PCIe resource allocation, X8+X8 PCIe resource allocation, X8+X4+X4 PCIe resource allocation, X4+X4+X4+X4 PCIe resource allocation, X8+X4+X2+X1+X1 PCIe resource allocation, and X8+SATA+SATA resource allocation. However, due to limitations in the CPU's design and the way its basic functions are allocated, its GPI ports do not support X4+X4+X8 resource allocation. Specifically, when the upper 8 bits of a GPI port are used for an X8 device, the lower 8 bits cannot be used for an X4+X4 device. Alternatively, when the lower 8 bits of a GPI port are used for an X4+X4 device, the upper 8 bits cannot support an X8 device. This results in a waste of GPI port resources. Therefore, the current CPU configuration of external PCIe resources is unreasonable, resulting in the inability of some general ports to expand externally, which leads to waste and reduces the utilization rate of processor PCIe resources.

[0004] In view of the above problems, how to solve the current unreasonable configuration of CPU external PCIe resources, which causes some general ports to be unable to expand externally and cause waste, is an urgent problem to be solved by technical personnel in this field. Summary of the Invention

[0005] The purpose of the present invention is to provide a processor port resource allocation system and server to solve the problem that the current CPU's external PCIe resource configuration is unreasonable, resulting in the inability of individual general ports to expand externally and resulting in waste.

[0006] To solve the above technical problems, the present invention provides a processor port resource allocation system, comprising: a master processor and a slave processor; wherein the master processor and the slave processor respectively include a first universal port, a second universal port, a third universal port, and a fourth universal port;

[0007] The fourth general port of the main processor is used to allocate the basic function fixed resources of the main processor; the low 8-bit port resources of the first general port of the main processor are used to allocate the open computing project network card fixed resources of the main processor;

[0008] The third general port of the master processor, the first general port of the slave processor and the second general port of the slave processor are respectively used for allocating high-speed serial computer expansion bus standard resources;

[0009] The upper 8-bit port resources of the first general port of the master processor, the second general port of the master processor, the third general port of the slave processor and the fourth general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors.

[0010] On the one hand, it also includes: complex programmable logic devices;

[0011] The complex programmable logic device is connected to the main processor, the slave processor and each of the preset connectors, and is used to obtain the level status of each of the preset connectors and transmit the level status to the corresponding main processor and the slave processor, so that the main processor and the slave processor can switch the allocation of the high-speed serial computer expansion bus standard resources and non-volatile memory expansion interface resources of the corresponding universal port according to the level status.

[0012] On the other hand, the basic function fixed resources include:

[0013] Onboard network card, baseboard management controller, serial advanced technology attachment interface, serial advanced technology attachment interface based on integrated system storage format, and serial advanced technology attachment based on integrated system storage format / high-speed serial computer expansion bus standard interface;

[0014] Correspondingly, the fourth general port of the main processor is used to allocate basic functional fixed resources of the main processor, including:

[0015] The port resources from bit 0 to bit 3 of the fourth general port of the main processor are used for connecting to the onboard network card;

[0016] The port resources from bit 4 to bit 7 of the fourth general port of the main processor are used for connecting to the baseboard management controller;

[0017] The port resources of bits 8 to 11 of the fourth general-purpose port of the main processor are used to sequentially connect to two of the SATA interfaces, the SATA interface based on the integrated system storage format, and the SATA functional portion of the SATA / high-speed serial computer expansion bus standard interface based on the integrated system storage format;

[0018] The port resources from bits 12 to 15 of the fourth general port of the main processor are used to connect to the high-speed serial computer expansion bus standard function part of the serial advanced technology attachment / high-speed serial computer expansion bus standard interface based on the integrated system storage format.

[0019] On the other hand, the third general port of the master processor, the first general port of the slave processor, and the second general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources, including:

[0020] The 16-bit port resources of the third general port of the master processor, the 16-bit port resources of the first general port of the slave processor and the 16-bit port resources of the second general port of the slave processor are respectively used to connect to a 16-bit high-speed serial computer expansion bus standard slot.

[0021] On the other hand, the third general port of the master processor, the first general port of the slave processor, and the second general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources, including:

[0022] The 16-bit port resources of the third general port of the master processor, the 16-bit port resources of the first general port of the slave processor, and the 16-bit port resources of the second general port of the slave processor are respectively used to connect to an Internet generation connector, so as to facilitate external expansion of a high-speed serial computer expansion bus standard slot through the corresponding Internet generation connector;

[0023] The externally expanded high-speed serial computer expansion bus standard slot is a 16-bit high-speed serial computer expansion bus standard slot, or two 8-bit high-speed serial computer expansion bus standard slots, or four 4-bit high-speed serial computer expansion bus standard slots.

[0024] On the other hand, the upper 8-bit port resources of the first general port of the master processor, the second general port of the master processor, the third general port of the slave processor, and the fourth general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors, including:

[0025] The high 8-bit port resources of the first general port of the main processor, the low 8-bit port resources of the second general port of the main processor, the high 8-bit port resources of the second general port of the main processor, the low 8-bit port resources of the third general port of the slave processor, the high 8-bit port resources of the third general port of the slave processor, the low 8-bit port resources of the fourth general port of the slave processor, and the high 8-bit port resources of the fourth general port of the slave processor are used to respectively connect to the corresponding preset connectors, so as to facilitate connection with a hard disk backplane for expanding non-volatile memory expansion interface resources or an adapter card for expanding high-speed serial computer expansion bus standard resources through a dedicated cable of the preset connector.

[0026] On the other hand, the main processor is specifically configured to:

[0027] When the upper 8-bit port resource of the first general port of the main processor, the lower 8-bit port resource of the second general port of the main processor, and the upper 8-bit port resource of the second general port of the main processor are respectively connected to the hard disk backplane through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are both 1, the upper 8-bit port resource of the first general port of the main processor, the lower 8-bit port resource of the second general port of the main processor, and the upper 8-bit port resource of the second general port of the main processor respectively expand the non-volatile memory expansion interface hard disk externally;

[0028] When the upper 8-bit port resources of the first general port of the main processor, the lower 8-bit port resources of the second general port of the main processor, and the upper 8-bit port resources of the second general port of the main processor are respectively connected to the adapter card through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are both 0 or 0 and 1 respectively, the upper 8-bit port resources of the first general port of the main processor, the lower 8-bit port resources of the second general port of the main processor, and the upper 8-bit port resources of the second general port of the main processor are respectively expanded to an 8-bit high-speed serial computer expansion bus standard slot;

[0029] On the other hand, the slave processor is specifically configured to:

[0030] When the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor are respectively connected to the hard disk backplane through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are 1, the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor respectively expand the non-volatile memory expansion interface hard disk externally;

[0031] When the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor are respectively connected to the adapter card through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are 0 or 0 and 1 respectively, the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor expand a 16-bit high-speed serial computer expansion bus standard slot externally.

[0032] On the other hand, it also includes: a prompting device;

[0033] The prompt device is connected to the main processor and the slave processor, and is used to output first prompt information when the upper 8-bit port resources of the first general port of the main processor, the second general port of the main processor, the third general port of the slave processor and the fourth general port of the slave processor are allocated high-speed serial computer expansion bus standard resources; and output second prompt information when the upper 8-bit port resources of the first general port of the main processor, the second general port of the main processor, the third general port of the slave processor and the fourth general port of the slave processor are allocated non-volatile memory expansion interface resources.

[0034] In order to solve the above technical problems, the present invention further provides a server, comprising the above processor port resource allocation system.

[0035] The processor port resource allocation system provided by the present invention includes a master processor and a slave processor; wherein the master processor and the slave processor respectively include a first universal port, a second universal port, a third universal port and a fourth universal port; the fourth universal port of the master processor is used to allocate the basic function fixed resources of the master processor; the low 8-bit port resources of the first universal port of the master processor are used to allocate the open computing project network card fixed resources of the master processor; the third universal port of the master processor, the first universal port of the slave processor and the second universal port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources; the high 8-bit port resources of the first universal port of the master processor, the second universal port of the master processor, the third universal port of the slave processor and the fourth universal port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors. The beneficial effect of the present invention is that it utilizes the characteristics of the PCIe / SATA split configuration of the processor, concentrates the fixed resources of basic functions and the fixed resources of the open computing project network card on the two universal ports of the main processor, and compresses the processor resources occupied by the basic functions to the greatest extent on the basis of ensuring the normal basic functions of the main processor, so that the other universal ports in the main processor and the universal ports of the slave processor can be used to externally expand NVMe hard drives or PCIe external cards, thereby improving the external expansion capability of the processor, solving the problem of unreasonable configuration of the current CPU external PCIe resources, and avoiding the waste of universal port resources.

[0036] In addition, the present invention also provides a server comprising the above-mentioned processor port resource allocation system, with the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A schematic diagram of a processor port resource allocation system provided by an embodiment of the present invention;

[0039] Figure 2 A schematic diagram of another processor port resource allocation system provided by an embodiment of the present invention.

[0040] Among them, 10 is a master processor, 11 is a slave processor, 12 is a complex programmable logic device, and 13 is a prompt device. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0042] The core of the present invention is to provide a processor port resource allocation system and server to solve the problem that the current CPU's external PCIe resource configuration is unreasonable, resulting in the inability of individual general ports to expand externally and resulting in waste.

[0043] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0044] Currently, some servers offer highly flexible external expansion of PCIe resources. To maximize PCIe resource expansion, the design of the server's CPU motherboard requires careful consideration of optimal PCIe resource utilization. Currently, one CPU supports four PCIe x16 universal ports: GPA, GPB, GPC, and GBD. The PCIe [D0:D15] resources of each universal port can support x16 PCIe resource allocation, x8+x8 PCIe resource allocation, x8+x4+x4 PCIe resource allocation, x4+x4+x4 PCIe resource allocation, x8+x4+x4+x4 PCIe resource allocation, x8+x4+x2+x1+x1 PCIe resource allocation, and x8+SATA+SATA resource allocation.

[0045] However, due to limitations in the CPU's design and the way its basic functions are allocated, its universal ports do not support X4+X4+X8 resource allocation. Specifically, when the upper 8 bits of a universal port are used for an X8 device, the lower 8 bits cannot be used for an X4+X4 device. Alternatively, when the lower 8 bits of a universal port are used for an X4+X4 device, the upper 8 bits cannot support an X8 device. This results in a waste of universal port resources. Based on this, the present invention provides a processor port resource allocation system designed to address the current issue of irrational CPU external PCIe resource allocation, which results in individual universal ports being unable to expand externally and resulting in waste.

[0046] Figure 1 Schematic diagram of a processor port resource allocation system provided by an embodiment of the present invention. Figure 1 As shown, the processor port resource allocation system includes: a master processor 10 and a slave processor 11; wherein the master processor and the slave processor respectively include a first universal port, a second universal port, a third universal port and a fourth universal port;

[0047] The fourth general-purpose port of the main processor is used to allocate the basic function fixed resources of the main processor; the low-order 8-bit port resources of the first general-purpose port of the main processor are used to allocate the Open Compute Project network card fixed resources of the main processor;

[0048] The third general purpose port of the master processor, the first general purpose port of the slave processor and the second general purpose port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources;

[0049] The upper 8-bit port resources of the first general port of the master processor, the second general port of the master processor, the third general port of the slave processor and the fourth general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors.

[0050] Specifically, the processor port resource allocation system is mainly composed of a master processor and a slave processor. It should be noted that the master processor and the slave processor are both processors of the same type, and the two are connected through a bus. The master processor and the slave processor are located in the same server; the server supports both the master processor to work alone and the master processor and the slave processor to work in a dual-path interconnected manner. The master processor and the slave processor respectively include a first general-purpose port GPA[0:15], a second general-purpose port GPB[0:15], a third general-purpose port GPC[0:15], and a fourth general-purpose port GPD[0:15], and each extends its functions externally through its own general-purpose port.

[0051] In this embodiment, the fourth general port GPD[0:15] of the main processor is used to allocate the basic function fixed resources of the main processor. It can be understood that the basic function fixed resources are fixed resources for realizing the basic functions of the server, including but not limited to network cards, baseboard management controllers (Baseboard Management Controller, BMC) and hard disk storage functions. In order to ensure the normal operation of the server, the processor must allocate basic function fixed resources to the outside through the general port. It should be noted that in this embodiment, there is no restriction on the specific content of the basic function fixed resources, nor on the specific allocation method of the basic function fixed resources, which depends on the specific implementation situation.

[0052] The lower 8 bits of the main processor's first general purpose port (GPA[0:7]) are used to allocate the main processor's Open Compute Project (OPC) network card fixed resources. The Open Compute Project (OPC) network card fixed resources are externally standardized OCP SFF 4C+ interfaces, which enable external expansion of OCP 3.0 network card functionality. The OCP 3.0 network card is a server network card with high-speed transmission and excellent performance. It supports dual 100G optical ports and is compatible with Remote Direct Memory Access (RDMA), optimizing server performance and reducing CPU utilization.

[0053] The master processor's third general-purpose port GPC[0:15], the slave processor's first general-purpose port GPA[0:15], and the slave processor's second general-purpose port GPB[0:15] are each used to allocate high-speed serial computer expansion bus standard resources. It is understood that the master processor's third general-purpose port GPC[0:15], the slave processor's first general-purpose port GPA[0:15], and the slave processor's second general-purpose port GPB[0:15] are all 16-bit port resources. Therefore, when allocating PCIe resources, they can be allocated as x16, x8+x8, x4+x4+x4+x4, or other types of PCIe resources. The specific allocation method is not limited in this embodiment and depends on the specific implementation.

[0054] The external interfaces of the high-order 8-bit port resources GPA[8:15] of the master processor's first general-purpose port, GPB[0:15] of the master processor, GPC[0:15] of the slave processor's third general-purpose port, and GPD[0:15] of the slave processor are all preset connectors. Therefore, high-speed serial computer expansion bus standard resources or non-volatile memory express (NVMe) resources can be allocated externally through the corresponding preset connectors. It is understood that externally expanded PCIe resources generally refer to PCIe adapter cards or slots, and externally expanded NVMe resources generally refer to NVMe hard drives.

[0055] It should be noted that this embodiment does not limit the pre-set connectors; for example, a Slimline connector or an MCIO connector may be used, depending on the specific implementation. Furthermore, this embodiment does not limit the specific manner in which PCIe resources or NVMe resources are allocated to the upper 8-bit port resources GPA[8:15] of the master processor's first general-purpose port, the master processor's second general-purpose port GPB[0:15], the slave processor's third general-purpose port GPC[0:15], and the slave processor's fourth general-purpose port GPD[0:15], depending on the specific implementation.

[0056] In this embodiment, the processor port resource allocation system includes a master processor and a slave processor; wherein the master processor and the slave processor respectively include a first universal port, a second universal port, a third universal port and a fourth universal port; the fourth universal port of the master processor is used to allocate the basic function fixed resources of the master processor; the lower 8-bit port resources of the first universal port of the master processor are used to allocate the open computing project network card fixed resources of the master processor; the third universal port of the master processor, the first universal port of the slave processor and the second universal port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources; the upper 8-bit port resources of the first universal port of the master processor, the second universal port of the master processor, the third universal port of the slave processor and the fourth universal port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors. It can be seen that this solution takes advantage of the characteristics of the processor's PCIe / SATA split configuration, and concentrates the fixed resources of basic functions and the fixed resources of the open computing project network card on the two general ports of the main processor. On the basis of ensuring the normal basic functions of the main processor, the processor resources occupied by the basic functions are compressed to the greatest extent, so that the other general ports in the main processor and the general ports of the slave processor can be used to externally expand NVMe hard drives or PCIe external cards, thereby improving the processor's external expansion capabilities, solving the current problem of unreasonable configuration of CPU external PCIe resources, and avoiding waste of general port resources.

[0057] Figure 2 Schematic diagram of another processor port resource allocation system provided by an embodiment of the present invention. Figure 2 As shown, the processor port resource allocation system further includes: a complex programmable logic device 12;

[0058] The complex programmable logic device is connected to the master processor, the slave processor and each preset connector, and is used to obtain the level status of each preset connector and transmit the level status to the corresponding master processor and slave processor, so that the master processor and the slave processor can switch the allocation of high-speed serial computer expansion bus standard resources and non-volatile memory expansion interface resources of the corresponding universal port according to the level status.

[0059] In this embodiment, a complex programmable logic device (CPLD) connects the master processor and the slave processor via an inter-integrated circuit (I2C) bus. The CPLD is also connected to each pre-defined connector. For example, if the pre-defined connector is a Slimline connector, each Slimline connector has two ID pins that can generate two voltage states, 0 or 1.

[0060] In a specific implementation, the CPLD monitors and obtains the power level status transmitted by each Slimline connector, and further transmits the power level status to the corresponding master and slave processors via the I2C bus. After the master processor receives the power level status corresponding to the upper 8-bit port resource GPA[8:15] of the master processor's first general-purpose port and the second general-purpose port GPB[0:15] of the master processor, and after the slave processor receives the power level status corresponding to the third general-purpose port GPC[0:15] of the slave processor and the fourth general-purpose port GPD[0:15] of the slave processor, the allocation of PCIe resources and NVMe resources of the corresponding general-purpose ports is switched according to their respective power level status.

[0061] In this embodiment, a complex programmable logic device is set to detect the level status of the preset connector in the main processor and the slave processor, and the connection status of the universal port where the preset connector is located is obtained, so that the main processor and the slave processor switch the external resource allocation of the universal port according to the corresponding level status.

[0062] Based on the above embodiments, in some embodiments, basic function fixed resources include:

[0063] Onboard network card, baseboard management controller, serial advanced technology attachment interface, serial advanced technology attachment interface based on integrated system storage format, and serial advanced technology attachment based on integrated system storage format / high-speed serial computer expansion bus standard interface;

[0064] In a specific implementation, the basic functional fixed resources of the main processor may include an onboard network card, a BMC, a Serial Advanced Technology Attachment (SATA) interface, a Serial Advanced Technology Attachment interface based on an integrated system storage format (M.2SATA only), and a Serial Advanced Technology Attachment / high-speed serial computer expansion bus standard interface based on an integrated system storage format (M.2SATA / PCIe).

[0065] Therefore, correspondingly, the fourth general-purpose port of the main processor is used to allocate the fixed resources of the main processor's basic functions, specifically: the port resources GPD[0:3] from bits 0 to 3 of the fourth general-purpose port of the main processor are used to connect to the onboard network card; the port resources GPD[4:7] from bits 4 to 7 of the fourth general-purpose port of the main processor are used to connect to the baseboard management controller of PCIe X4; the port resources GPD[8:11] from bits 8 to 11 of the fourth general-purpose port of the main processor are used to connect to the two SATA interfaces, the M.2SATA only interface, and the SATA functional portion of the M.2SATA / PCIe interface in sequence. Finally, the port resources GPD[12:15] from bits 12 to 15 of the fourth general-purpose port of the main processor are used to connect to the PCIe functional portion of the M.2SATA / PCIe interface, specifically PCIe X4.

[0066] In this embodiment, the basic function fixed resources are composed of an onboard network card, a baseboard management controller, a serial advanced technology attachment interface, a serial advanced technology attachment interface based on an integrated system storage format, and a serial advanced technology attachment / high-speed serial computer expansion bus standard interface based on an integrated system storage format. The above basic function resources are fully allocated using the fourth general port GPD[0:15] of the main processor, thereby realizing the centralized allocation of basic function fixed resources, avoiding the occupation of other general ports, and improving the utilization efficiency of port resources.

[0067] Based on the above embodiment, in some embodiments, the third general port of the master processor, the first general port of the slave processor, and the second general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources, including:

[0068] The 16-bit port resources of the third general port of the master processor, the 16-bit port resources of the first general port of the slave processor and the 16-bit port resources of the second general port of the slave processor are respectively used to connect to the 16-bit high-speed serial computer expansion bus standard slot.

[0069] In a specific implementation, the third general port GPC[0:15] of the master processor, the first general port GPA[0:15] of the slave processor, and the second general port GPB[0:15] of the slave processor are respectively used to allocate PCIe resources. Since the above three general ports are all PCIe X16 ports, the 16-bit port resources GPC[0:15] of the third general port of the master processor, the 16-bit port resources GPA[0:15] of the first general port of the slave processor, and the 16-bit port resources GPB[0:15] of the second general port of the slave processor can be specifically connected to a 16-bit high-speed serial computer expansion bus standard slot, that is, to a PCIe X16 slot, so that the above three general ports can externally support PCIe X16 standard cards.

[0070] Furthermore, in some embodiments, the third general port of the master processor, the first general port of the slave processor, and the second general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources, including:

[0071] The 16-bit port resources of the third general-purpose port of the master processor, the 16-bit port resources of the first general-purpose port of the slave processor, and the 16-bit port resources of the second general-purpose port of the slave processor are respectively used to connect to Internet generation connectors, so as to facilitate external expansion of high-speed serial computer expansion bus standard slots through corresponding Internet generation connectors;

[0072] The externally expanded high-speed serial computer expansion bus standard slot is a 16-bit high-speed serial computer expansion bus standard slot, or two 8-bit high-speed serial computer expansion bus standard slots, or four 4-bit high-speed serial computer expansion bus standard slots.

[0073] Specifically, in addition to the resource allocation method for the third general port GPC[0:15] of the master processor, the first general port GPA[0:15] of the slave processor, and the second general port GPB[0:15] of the slave processor in the above embodiment, in a specific implementation, the 16-bit port resources GPC[0:15] of the third general port of the master processor, the 16-bit port resources GPA[0:15] of the first general port of the slave processor, and the 16-bit port resources GPB[0:15] of the second general port of the slave processor can also be connected to the Internet generation connector, that is, the GEN-Z connector, so as to facilitate the external expansion of the PCIe slot through the corresponding GEN-Z connector.

[0074] The GEN-Z connector is a high-speed connector. Primarily used in fifth-generation mobile communications and high-speed data transmission, its key features are speed, precision, and stability. Compared to traditional connectors, the GEN-Z connector offers higher precision, ensuring accurate transmission of high-speed signals. It also features a self-locking function, automatically locking the connector when inserted, ensuring stability.

[0075] It should be noted that another advantage of using the GEN-Z connector is that different types of PCIe resources can be expanded externally through the universal port. Taking the third universal port GPC[0:15] of the main processor as an example, the 16-bit port resource GPC[0:15] of the third universal port of the main processor is connected to the GEN-Z connector. Through the GEN-Z connector, one PCIe X16 slot, two PCIe X8 slots, four PCIe X4 slots, and of course PCIe X2 slots and PCIe X1 slots can also be expanded externally. This will not be repeated in this embodiment.

[0076] In summary, the ports in the master and slave processors dedicated to external expansion of PCIe resources can be directly connected to the PCIe X16 slot, or the types of connectable PCIe slots can be expanded by connecting to the GEN-Z connector, thereby providing more options for the port resource allocation of the master and slave processors and improving the user experience.

[0077] Based on the above embodiments, in some embodiments, the upper 8 bits of the first general port of the master processor, the second general port of the master processor, the third general port of the slave processor, and the fourth general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors, including:

[0078] The high 8-bit port resources of the first general port of the main processor, the low 8-bit port resources of the second general port of the main processor, the high 8-bit port resources of the second general port of the main processor, the low 8-bit port resources of the third general port of the slave processor, the high 8-bit port resources of the third general port of the slave processor, the low 8-bit port resources of the fourth general port of the slave processor, and the high 8-bit port resources of the fourth general port of the slave processor are used to respectively connect to corresponding preset connectors, so as to facilitate connection to a hard disk backplane for expanding non-volatile memory expansion interface resources or an adapter card for expanding high-speed serial computer expansion bus standard resources through a dedicated cable of the preset connector.

[0079] In a specific implementation, seven groups of port resources, including the high-order 8-bit port resources GPA[8:15] of the master processor's first general-purpose port, the low-order 8-bit port resources GPB[0:7] of the master processor's second general-purpose port, the high-order 8-bit port resources GPB[8:15] of the master processor's second general-purpose port, the low-order 8-bit port resources GPC[0:7] of the slave processor's third general-purpose port, the high-order 8-bit port resources GPC[8:15] of the slave processor's third general-purpose port, the low-order 8-bit port resources GPD[0:7] of the slave processor's fourth general-purpose port, and the high-order 8-bit port resources GPD[8:15] of the slave processor's fourth general-purpose port, are connected to corresponding preset connectors. In this embodiment, there is no limitation on the preset connectors; for example, a Slimline connector or an MCIO connector may be used, depending on the specific implementation.

[0080] Furthermore, the above 7 groups of port resources can be connected to the hard disk backplane for expanding the NVMe hard disk function, or to the adapter card for expanding PCIe resources through dedicated cables with their respective preset connectors.

[0081] It should be noted that whether the seven groups of port resources are used to expand NVMe hard drive functions or PCIe resources is determined by the docking object of the dedicated cable of the preset connector; the actual bandwidth of the resources expanded by the seven groups of port resources is determined by the power level status of the corresponding preset connector. In this embodiment, each preset connector has two ID pins (ID1 and ID0) for automatic allocation of NVMe hard drive functions and PCIe resources. At the same time, the dedicated cable of the preset connector has a fixed ID power level status.

[0082] Table 1 A comparison table of actual bandwidth switching

[0083]

[0084] Table 1 is a comparison table of actual bandwidth switching provided by an embodiment of the present invention. In Table 1, GP_ID1 and GP_ID0 are two level states corresponding to a preset connector, which corresponds to the lower 8-bit port resources [0:7] or the upper 8-bit port resources [8:15] of a universal port. When GP_ID1 and GP_ID0 are both 1, the lower 8-bit port resources [0:7] or the upper 8-bit port resources [8:15] of the universal port expand two X4 bandwidth resources. When GP_ID1 and GP_ID0 are 0 and 1, respectively, the lower 8-bit port resources [0:7] or the upper 8-bit port resources [8:15] of the universal port expand one X8 bandwidth resource.

[0085] Table 2 Another practical bandwidth switching comparison table

[0086]

[0087] Table 2 is another actual bandwidth switching comparison table provided by an embodiment of the present invention. In Table 2, GPH_ID1 and GPH_ID0 are two level states corresponding to a preset connector, which corresponds to the upper 8-bit port resource [8:15] of a universal port. GPL_ID1 and GPL_ID0 are two level states corresponding to another preset connector, which corresponds to the lower 8-bit port resource [0:7] of the universal port.

[0088] When GPH_ID1, GPH_ID0, GPL_ID1 and GPL_ID0 are all 0, the lower 8-bit port resources [0:7] and the upper 8-bit port resources [8:15] of the general port jointly expand 1 X16 bandwidth resource externally; when only GPL_ID0 among GPH_ID1, GPH_ID0, GPL_ID1 and GPL_ID0 is 0 and the other level states are all 1, the lower 8-bit port resources [0:7] and the upper 8-bit port resources [8:15] of the general port jointly expand 1 X16 bandwidth resource externally.

[0089] The following describes the specific allocation of seven groups of port resources, namely, the upper 8-bit port resources GPA[8:15] of the first general-purpose port of the master processor, the lower 8-bit port resources GPB[0:7] of the second general-purpose port of the master processor, the upper 8-bit port resources GPB[8:15] of the second general-purpose port of the master processor, the lower 8-bit port resources GPC[0:7] of the third general-purpose port of the slave processor, the upper 8-bit port resources GPC[8:15] of the third general-purpose port of the slave processor, the lower 8-bit port resources GPD[0:7] of the fourth general-purpose port of the slave processor, and the upper 8-bit port resources GPD[8:15] of the fourth general-purpose port of the slave processor, in combination with Table 1 and Table 2:

[0090] (1) Main processor external resource expansion

[0091] The main processor receives the level status of the preset connector corresponding to the high 8-bit port resource GPA[8:15] of the first general port of the main processor, the low 8-bit port resource GPB[0:7] of the second general port of the main processor, and the high 8-bit port resource GPB[8:15] of the second general port of the main processor transmitted by the CPLD, and confirms each level status.

[0092] When the high 8-bit port resources GPA[8:15] of the first general-purpose port of the main processor, the low 8-bit port resources GPB[0:7] of the second general-purpose port of the main processor, and the high 8-bit port resources GPB[8:15] of the second general-purpose port of the main processor are respectively connected to the hard disk backplane through the dedicated cables of the corresponding preset connectors, and the two level states of each preset connector are both 1 (refer to Table 1), the high 8-bit port resources GPA[8:15] of the first general-purpose port of the main processor, the low 8-bit port resources GPB[0:7] of the second general-purpose port of the main processor, and the high 8-bit port resources GPB[8:15] of the second general-purpose port of the main processor respectively expand the NVMe hard disk, supporting a total of up to 6 NVMe hard disks.

[0093] When the high 8-bit port resources GPA[8:15] of the first general-purpose port of the main processor, the low 8-bit port resources GPB[0:7] of the second general-purpose port of the main processor, and the high 8-bit port resources GPB[8:15] of the second general-purpose port of the main processor are respectively connected to the adapter card through the dedicated cables of the corresponding preset connectors, and the two level states of each preset connector are both 0 (refer to Table 2) or 0 and 1 respectively (refer to Table 1), the high 8-bit port resources GPA[8:15] of the first general-purpose port of the main processor, the low 8-bit port resources GPB[0:7] of the second general-purpose port of the main processor, and the high 8-bit port resources GPB[8:15] of the second general-purpose port of the main processor respectively expand the PCIe X8 slot externally; a total of up to 3 PCIe X8 slots are supported.

[0094] In summary, the main processor can expand 6 NVMe hard drives or 4 PCIe standard slots: 1 PCIe X16 slot and 3 PCIe X8 slots.

[0095] (2) Expanding external resources from the processor

[0096] The main processor receives the level status of the preset connector corresponding to the low 8-bit port resources GPC[0:7] of the third general port of the slave processor, the high 8-bit port resources GPC[8:15] of the third general port of the slave processor, the low 8-bit port resources GPD[0:7] of the fourth general port of the slave processor, and the high 8-bit port resources GPD[8:15] of the fourth general port of the slave processor transmitted by the CPLD, and confirms each level status.

[0097] When the low 8-bit port resources GPC[0:7] of the third general port of the slave processor, the high 8-bit port resources GPC[8:15] of the third general port of the slave processor, the low 8-bit port resources GPD[0:7] of the fourth general port of the slave processor, and the high 8-bit port resources GPD[8:15] of the fourth general port of the slave processor are respectively connected to the hard disk backplane through the dedicated cables of the corresponding preset connectors, and the two level states of each preset connector are both 1 (refer to Table 1), the low 8-bit port resources GPC[0:7] of the third general port of the slave processor, the high 8-bit port resources GPC[8:15] of the third general port of the slave processor, the low 8-bit port resources GPD[0:7] of the fourth general port of the slave processor, and the high 8-bit port resources GPD[8:15] of the fourth general port of the slave processor respectively expand the NVMe hard disk externally, supporting a total of up to 8 NVMe hard disks.

[0098] When the lower 8-bit port resources GPC[0:7] of the third general port of the slave processor, the upper 8-bit port resources GPC[8:15] of the third general port of the slave processor, the lower 8-bit port resources GPD[0:7] of the fourth general port of the slave processor, and the upper 8-bit port resources GPD[8:15] of the fourth general port of the slave processor are respectively connected to the adapter card through the dedicated cables of the corresponding preset connectors, and the two level states of each preset connector are both 0 (refer to Table 2) or 0 and 1 respectively (refer to Table 1), the lower 8-bit port resources GPC[0:7] of the third general port of the slave processor, the upper 8-bit port resources GPC[8:15] of the third general port of the slave processor, the lower 8-bit port resources GPD[0:7] of the fourth general port of the slave processor, and the upper 8-bit port resources GPD[8:15] of the fourth general port of the slave processor expand the PCIe X16 slot externally, supporting a maximum of 2 PCIe X16 slots in total.

[0099] In summary, the slave processor can expand 8 NVMe hard drives or 4 PCIe X16 slots.

[0100] It's important to note that this solution can be expanded to achieve a motherboard topology with a 6+6 NVMe balance and a 4+4 PCIe riser card balance. However, since neither the master nor the slave processors support X4+X4+X8, that is, when the high-order X8 is used, the low-order does not support X4+X4, or when the low-order uses X4+X4, the high-order does not support X8. This split should also be avoided in design applications.

[0101] Based on the above embodiments, in some embodiments, such as Figure 2 As shown, the processor port resource allocation system further includes: a prompting device 13;

[0102] In a specific implementation, the prompt device is connected to the main processor and the slave processor, and is used to output a first prompt message when the high 8-bit port resources GPA[8:15] of the first general port of the main processor, the second general port GPB[0:15] of the main processor, the third general port GPC[0:15] of the slave processor, and the fourth general port GPD[0:15] of the slave processor are allocated PCIe resources; and output a second prompt message when the high 8-bit port resources GPA[8:15] of the first general port of the main processor, the second general port GPB[0:15] of the main processor, the third general port GPC[0:15] of the slave processor, and the fourth general port GPD[0:15] of the slave processor are allocated NVMe resources.

[0103] It can be understood that the first prompt information and the second prompt information can respectively indicate the specific circumstances of the external resource allocation of the master and slave processors. Users can determine whether the master and slave processors have expanded PCIe resources or NVMe resources externally based on the prompt information, thereby better utilizing the expanded resources and improving the user experience.

[0104] It should be noted that, in addition to its prompting function, the prompt information may also include specific bandwidth information for externally expanded resources. Taking the first prompt information as an example: the first prompt information is used to prompt the user that the upper 8-bit port resources GPA[8:15] of the first general-purpose port of the master processor, the second general-purpose port GPB[0:15] of the master processor, the third general-purpose port GPC[0:15] of the slave processor, and the fourth general-purpose port GPD[0:15] of the slave processor are allocated PCIe resources. On this basis, the first prompt information may also include information that the upper 8-bit port resources GPA[8:15] of the first general-purpose port of the master processor, the second general-purpose port GPB[0:15] of the master processor, the third general-purpose port GPC[0:15] of the slave processor, and the fourth general-purpose port GPD[0:15] of the slave processor have been externally expanded by one PCIe X8 slot, one PCIe X16 slot, two PCIe X8 slots, and four PCIe X4 slots, respectively, thereby enabling the user to better utilize the resources of each general-purpose port of the master and slave processors.

[0105] Finally, the present invention also provides a server, including the processor port resource allocation system in the above embodiment. The server can realize all the functions of the above processor port resource allocation system when running. The processor port resource allocation system utilizes the characteristics of the PCIe / SATA split configuration of the processor to concentrate the basic function fixed resources and the open computing project network card fixed resources on the two general ports of the main processor. On the basis of ensuring the normal basic functions of the main processor, the processor resources occupied by the basic functions are compressed to the greatest extent, so that the other general ports in the main processor and the general ports of the slave processor can be used for external expansion of NVMe hard drives or PCIe external cards, thereby improving the external expansion capability of the processor, solving the problem of unreasonable configuration of the current CPU external PCIe resources, and avoiding the waste of general port resources.

[0106] The above is a detailed introduction to a processor port resource allocation system and server provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, the present invention can also be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the present invention.

[0107] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A processor port resource allocation system, characterized in that: include: A master processor and a slave processor; wherein the master processor and the slave processor respectively comprise a first universal port, a second universal port, a third universal port, and a fourth universal port; The fourth general port of the main processor is used to allocate the basic function fixed resources of the main processor; the low 8-bit port resources of the first general port of the main processor are used to allocate the open computing project network card fixed resources of the main processor; The third general port of the master processor, the first general port of the slave processor and the second general port of the slave processor are respectively used for allocating high-speed serial computer expansion bus standard resources; The upper 8-bit port resources of the first general port of the master processor, the second general port of the master processor, the third general port of the slave processor and the fourth general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors.

2. The processor port resource allocation system according to claim 1, characterized in that: Also includes: Complex programmable logic devices; The complex programmable logic device is connected to the main processor, the slave processor and each of the preset connectors, and is used to obtain the level status of each of the preset connectors and transmit the level status to the corresponding main processor and the slave processor, so that the main processor and the slave processor can switch the allocation of the high-speed serial computer expansion bus standard resources and non-volatile memory expansion interface resources of the corresponding universal port according to the level status.

3. The processor port resource allocation system according to claim 1, wherein: The basic functional fixed resources include: Onboard network card, baseboard management controller, serial advanced technology attachment interface, serial advanced technology attachment interface based on integrated system storage format, and serial advanced technology attachment based on integrated system storage format / high-speed serial computer expansion bus standard interface; Correspondingly, the fourth general port of the main processor is used to allocate basic functional fixed resources of the main processor, including: The port resources from bit 0 to bit 3 of the fourth general port of the main processor are used for connecting to the onboard network card; The port resources from bit 4 to bit 7 of the fourth general port of the main processor are used for connecting to the baseboard management controller; The port resources of bits 8 to 11 of the fourth general-purpose port of the main processor are used to sequentially connect to two of the SATA interfaces, the SATA interface based on the integrated system storage format, and the SATA functional portion of the SATA / high-speed serial computer expansion bus standard interface based on the integrated system storage format; The port resources from bits 12 to 15 of the fourth general port of the main processor are used to connect to the high-speed serial computer expansion bus standard function part of the serial advanced technology attachment / high-speed serial computer expansion bus standard interface based on the integrated system storage format.

4. The processor port resource allocation system according to claim 1, wherein: The third general port of the master processor, the first general port of the slave processor, and the second general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources, including: The 16-bit port resources of the third general port of the master processor, the 16-bit port resources of the first general port of the slave processor and the 16-bit port resources of the second general port of the slave processor are respectively used to connect to a 16-bit high-speed serial computer expansion bus standard slot.

5. The processor port resource allocation system according to claim 1, wherein: The third general port of the master processor, the first general port of the slave processor, and the second general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources, including: The 16-bit port resources of the third general port of the master processor, the 16-bit port resources of the first general port of the slave processor, and the 16-bit port resources of the second general port of the slave processor are respectively used to connect to an Internet generation connector, so as to facilitate external expansion of a high-speed serial computer expansion bus standard slot through the corresponding Internet generation connector; The externally expanded high-speed serial computer expansion bus standard slot is a 16-bit high-speed serial computer expansion bus standard slot, or two 8-bit high-speed serial computer expansion bus standard slots, or four 4-bit high-speed serial computer expansion bus standard slots.

6. The processor port resource allocation system according to claim 2, characterized in that: The upper 8-bit port resources of the first general port of the master processor, the second general port of the master processor, the third general port of the slave processor, and the fourth general port of the slave processor are respectively used to allocate high-speed serial computer expansion bus standard resources or non-volatile memory expansion interface resources through corresponding preset connectors, including: The high 8-bit port resources of the first general port of the main processor, the low 8-bit port resources of the second general port of the main processor, the high 8-bit port resources of the second general port of the main processor, the low 8-bit port resources of the third general port of the slave processor, the high 8-bit port resources of the third general port of the slave processor, the low 8-bit port resources of the fourth general port of the slave processor, and the high 8-bit port resources of the fourth general port of the slave processor are used to respectively connect to the corresponding preset connectors, so as to facilitate connection with a hard disk backplane for expanding non-volatile memory expansion interface resources or an adapter card for expanding high-speed serial computer expansion bus standard resources through a dedicated cable of the preset connector.

7. The processor port resource allocation system according to claim 6, characterized in that: The main processor is specifically configured to: When the upper 8-bit port resource of the first general port of the main processor, the lower 8-bit port resource of the second general port of the main processor, and the upper 8-bit port resource of the second general port of the main processor are respectively connected to the hard disk backplane through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are both 1, the upper 8-bit port resource of the first general port of the main processor, the lower 8-bit port resource of the second general port of the main processor, and the upper 8-bit port resource of the second general port of the main processor respectively expand the non-volatile memory expansion interface hard disk externally; When the upper 8-bit port resources of the first general port of the main processor, the lower 8-bit port resources of the second general port of the main processor and the upper 8-bit port resources of the second general port of the main processor are respectively connected to the adapter card through the dedicated cables of the corresponding preset connectors, and the two level states of each preset connector are 0 or 0 and 1 respectively, the upper 8-bit port resources of the first general port of the main processor, the lower 8-bit port resources of the second general port of the main processor and the upper 8-bit port resources of the second general port of the main processor respectively expand an 8-bit high-speed serial computer expansion bus standard slot externally.

8. The processor port resource allocation system according to claim 6, wherein: The slave processor is specifically configured to: When the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor are respectively connected to the hard disk backplane through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are 1, the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor respectively expand the non-volatile memory expansion interface hard disk externally; When the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor are respectively connected to the adapter card through the dedicated cables of the corresponding preset connectors, and the two level states of each of the preset connectors are 0 or 0 and 1 respectively, the lower 8-bit port resources of the third general port of the slave processor, the upper 8-bit port resources of the third general port of the slave processor, the lower 8-bit port resources of the fourth general port of the slave processor, and the upper 8-bit port resources of the fourth general port of the slave processor expand a 16-bit high-speed serial computer expansion bus standard slot externally.

9. The processor port resource allocation system according to any one of claims 1 to 8, characterized in that: Also included: a prompt device; The prompt device is connected to the main processor and the slave processor, and is used to output first prompt information when the upper 8-bit port resources of the first general port of the main processor, the second general port of the main processor, the third general port of the slave processor and the fourth general port of the slave processor are allocated high-speed serial computer expansion bus standard resources; and output second prompt information when the upper 8-bit port resources of the first general port of the main processor, the second general port of the main processor, the third general port of the slave processor and the fourth general port of the slave processor are allocated non-volatile memory expansion interface resources.

10. A server, characterized in that: A processor port resource allocation system comprising the processor port resource allocation system according to any one of claims 1 to 9.

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