Memory system, operating method thereof, and computer readable storage medium

Abstract

The invention provides a memory system, an operation method thereof and a computer readable storage medium. The memory system comprises a memory device and a memory controller coupled with the memory device; the memory system comprises a general purpose input / output interface, the general purpose input / output interface comprises a first pin, and the first pin can be used for receiving data transmitted in a serial communication mode; the memory controller is configured to respond to the situation that firmware of the memory system is abnormal in the running process, and interrupt is triggered through the first pin; in response to an interruption triggered by the first pin, an assertion dump mode is triggered.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a memory system and an operating method thereof, and a computer-readable storage medium. Background Art

[0002] With the rapid development of data storage technology, more and more data storage systems, such as solid-state drives (SSDs), are appearing in electronic devices. SSDs, due to their fast read and write speeds, vibration resistance, low power consumption, quiet operation, low heat generation, and lightweight design, have found widespread application in military, automotive, industrial, medical, and aviation applications. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory system and an operating method thereof, and a computer-readable storage medium to solve at least one problem existing in the prior art.

[0004] In a first aspect, an embodiment of the present disclosure provides a memory system comprising: a memory device and a memory controller coupled to the memory device; the memory system comprising a general purpose input / output interface, the general purpose input / output interface comprising a first pin, the first pin being operable to receive data transmitted in a serial communication manner; the memory controller being configured to: trigger an interrupt via the first pin in response to an exception occurring in firmware of the memory system during operation; and trigger an assertion dump mode in response to the interrupt triggered by the first pin.

[0005] In an optional embodiment, the memory controller is further configured to: before triggering an interrupt through the first pin, configure the first pin to a first mode, in which the first pin can be used to receive a level signal; in response to the first pin being in the first mode, trigger an interrupt when the level signal received by the first pin is in a first state.

[0006] In an optional implementation, the first state includes: a rising edge state, a falling edge state, a high level state, or a low level state.

[0007] In an optional embodiment, the memory system also includes a first ground pin; the memory controller is configured to: in response to the first pin and the first ground pin being short-circuited, the level signal received by the first pin is in a rising edge state; in response to the level signal received by the first pin being in a rising edge state, trigger an interrupt.

[0008] In an optional embodiment, the memory system further includes a second pin and a second ground pin, the second pin being used to select a program startup mode when the memory system is powered on; the memory controller is further configured to: in response to the second pin and the second ground pin being short-circuited, the level signal received by the second pin being in a rising edge state; in response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, trigger an interrupt.

[0009] In an optional implementation, the memory controller is configured to: configure the first pin to the first mode during a user use phase.

[0010] In an optional embodiment, the memory system also includes a high-speed serial computer expansion bus standard interface; the memory controller is configured to: during the debugging phase of the memory system, in response to an exception occurring in the high-speed serial computer expansion bus standard interface and an exception occurring in the firmware of the memory system during operation, configure the first pin to the first mode.

[0011] In an optional embodiment, the memory controller is further configured to: in response to triggering the assertion dump mode, perform assertion dump processing; the assertion dump processing includes saving abnormal scene information to the memory device.

[0012] In an optional embodiment, the memory controller is further configured to: during the debugging phase of the memory system, in response to completion of the assertion transfer processing, turn off the interrupt; in response to the interrupt being turned off, configure the first pin to a second mode; in the second mode, the first pin can be used to receive data transmitted in a serial communication manner.

[0013] In an optional embodiment, the memory controller is further configured to: in response to the interrupt being turned off, after the memory system is powered on again, send the abnormal field information to the host coupled to the memory system through the high-speed serial computer expansion bus standard interface.

[0014] In an optional embodiment, the memory system includes a memory card, a solid state drive, or a universal flash memory storage.

[0015] In a second aspect, an embodiment of the present disclosure provides an operating method for a memory system, the operating method comprising: in response to an exception occurring in the firmware of the memory system during operation, triggering an interrupt through a first pin of a general input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner; in response to the interrupt triggered by the first pin, triggering an assertion transfer mode.

[0016] In an optional embodiment, the operating method further includes: before triggering an interrupt through a first pin of the general input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner, configuring the first pin to a first mode; in the first mode, the first pin can be used to receive a level signal; triggering an interrupt through the first pin of the general input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner includes: in response to the first pin being in the first mode, triggering an interrupt when the level signal received by the first pin is in a first state.

[0017] In an optional implementation, the first state includes: a rising edge state, a falling edge state, a high level state, or a low level state.

[0018] In an optional embodiment, the memory system further includes a first ground pin; in response to the first pin being in the first mode, triggering an interrupt when the level signal received by the first pin is in the first state, including: in response to the first pin and the first ground pin being short-circuited, the level signal received by the first pin is in a rising edge state; in response to the level signal received by the first pin being in a rising edge state, triggering an interrupt.

[0019] In an optional embodiment, the memory system further includes a second pin and a second ground pin, the second pin being used to select a program startup mode when the memory system is powered on; in response to the first pin being in the first mode, triggering an interrupt when the level signal received by the first pin is in the first state, and further including: in response to the second pin and the second ground pin being short-circuited, the level signal received by the second pin is in a rising edge state; in response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, triggering an interrupt.

[0020] In an optional implementation manner, configuring the first pin to the first mode includes: configuring the first pin to the first mode during a user use phase.

[0021] In an optional embodiment, the memory system also includes a high-speed serial computer expansion bus standard interface; configuring the first pin to the first mode includes: during the debugging phase of the memory system, in response to an exception occurring in the high-speed serial computer expansion bus standard interface and an exception occurring in the firmware of the memory system during operation, configuring the first pin to the first mode.

[0022] In an optional embodiment, the operating method further includes: in response to triggering the assertion dump mode, performing assertion dump processing; the assertion dump processing includes saving abnormal scene information to the memory device.

[0023] In an optional embodiment, the operating method further includes: during the debugging phase of the memory system, in response to completion of the assertion transfer processing, turning off the interrupt; in response to the interrupt being turned off, configuring the first pin to a second mode; in the second mode, the first pin can be used to receive data transmitted in a serial communication manner.

[0024] In an optional embodiment, the operating method further includes: in response to the interrupt being turned off, after the memory system is powered on again, sending the abnormal field information to a host coupled to the memory system through the high-speed serial computer expansion bus standard interface.

[0025] In a third aspect, an embodiment of the present disclosure provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method described in any of the above embodiments can be implemented.

[0026] In the technical solution provided by the embodiment of the present disclosure, the first pin of the universal input / output interface in the memory system is reused, and an interrupt is triggered through the first pin, thereby triggering the assertion dump mode. In the embodiment of the present disclosure, on the one hand, a new method of triggering the assertion dump mode is provided, so that even in the event of a failure of the high-speed serial computer expansion bus standard interface, abnormal scene information can be saved in a timely manner, thereby avoiding the loss of key abnormal scene information and improving the efficiency of problem solving; on the other hand, in the event of an abnormality during the operation of the firmware, the first pin is in an idle state, and the reuse of the existing first pin by the embodiment of the present disclosure will not affect the performance of the memory system; on the other hand, because the present disclosure reuses the existing first pin, the implementation cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic diagram of an exemplary system having a memory system provided for embodiments of the present disclosure.

[0028] Figure 2 A schematic diagram of an exemplary memory card having a memory system provided for embodiments of the present disclosure.

[0029] Figure 3 A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure.

[0030] Figure 4A schematic diagram of an exemplary memory device including peripheral circuits provided for embodiments of the present disclosure.

[0031] Figure 5 A schematic cross-sectional view of a memory array including memory cell strings provided in an embodiment of the present disclosure.

[0032] Figure 6 A schematic diagram of an exemplary memory device including a memory array and peripheral circuits provided for embodiments of the present disclosure.

[0033] Figure 7 A schematic diagram of a method for operating a memory system according to an embodiment of the present disclosure Figure 1 .

[0034] Figure 8 A schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure Figure 1 .

[0035] Figure 9 A schematic diagram of the structure of a memory system provided in an embodiment of the present disclosure Figure 2 .

[0036] Figure 10 A schematic diagram of a method for operating a memory system according to an embodiment of the present disclosure Figure 2 .

[0037] Figure 11 A schematic diagram of a method for operating a memory system according to an embodiment of the present disclosure Figure 3 .

[0038] Figure 12 A schematic diagram of a method for operating a memory system according to an embodiment of the present disclosure Figure 4 . DETAILED DESCRIPTION

[0039] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0040] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0041] In the drawings, like reference numerals refer to like elements throughout.

[0042] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] The memory system in the embodiments of the present disclosure includes but is not limited to a memory system of a three-dimensional NAND memory. For ease of understanding, the memory system provided by the present disclosure is described by taking a memory system including a three-dimensional NAND memory as an example.

[0045] Figure 1Schematic diagram of an exemplary system with a memory system provided in an embodiment of the present disclosure. In an embodiment of the present disclosure, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1 As shown in , system 100 may include a host device 101 and a memory system 102. Memory system 102 may include one or more memory devices 103 and a memory controller 104. Host device 101 may include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). Host device 101 may be configured to send data to or receive data from memory system 102.

[0046] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host device 101 and is configured to control the memory device 103. The memory controller 104 can manage data stored in the memory device 103 and communicate with the host device 101. In some embodiments, the memory controller 104 is designed to operate in a low duty cycle environment, such as in a secure digital card, a compact flash card (CFC), a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In other embodiments, the memory controller 104 is designed to operate in a high duty cycle environment, such as in a solid-state drive or an embedded multi-media card (eMMC).

[0047] In some embodiments, the memory controller 104 and the one or more memory devices 103 may be integrated into various types of memory devices. That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0048] In such Figure 2In one example shown in FIG, the memory controller 104 and the single memory device 103 can be integrated into a memory card 201. The memory card 201 can be a compact flash card, a smart media card (Smart Media Card, SMC), a memory stick (Memory Stick, MS), a multimedia card (Multi-Media Card, MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as Mini SD card, Micro SD card, SDHC card, etc., or a universal flash memory card. The memory card 201 can also include a device that connects the memory card 201 to a host device (e.g., Figure 1 The host device 101 in FIG. 1 is coupled to the memory card connector 202. Figure 3 In another example shown in , the memory controller 104 and the plurality of memory devices 103 may be integrated into the SSD 203. The SSD 203 may also include a processor that connects the SSD 203 to a host device (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD 203 is greater than the storage capacity and / or operating speed of the memory card 201.

[0049] Figure 4 A circuit diagram of an exemplary memory device 300 including peripheral circuits provided in accordance with an embodiment of the present disclosure. The memory device 300 may be Figure 1 3. An example of a memory device 103 in FIG. Memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to memory array 301. Memory array 301 is described as a three-dimensional NAND memory array, wherein memory cells 305 are NAND memory cells, and memory cells 305 are provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0050] The following describes the principle of data writing to a floating gate type memory cell, taking a floating gate type memory cell as an example. When writing data to a memory cell, a programming voltage can be applied to the control gate of the floating gate field effect transistor (FET) to cause electrons in the channel of the FET to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the magnitude of the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that when the threshold voltage Vth of the floating gate FET is different, the voltage required to be applied to the control gate of the FET to control the conduction of the FET is different. Therefore, the magnitude of the threshold voltage Vth of the FET can reflect the content of the stored data.

[0051] In some embodiments, each memory cell 305 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, for example, a multi-level cell (MLC) that stores two bits per cell, a triple-level cell (TLC) that stores three bits per cell, or a quad-level cell (QLC) that stores four bits per cell.

[0052] like Figure 4As shown in FIG, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source terminal and a top select transistor (TST) 306 at its drain terminal. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and program operations. In some embodiments, the sources of the memory cell strings 304 in the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 in the same memory block 303 have a common source (Array Common Source, ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, and data can be read from or written to the bit line 311 via an output bus (not shown). In some embodiments, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the upper selection tube 306) or a deselection voltage (e.g., 0V) to the corresponding upper selection tube 306 through one or more top selection lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the lower selection tube 307) or a deselection voltage (e.g., 0V) to the corresponding lower selection tube 307 through one or more bottom selection lines (BSL) 309.

[0053] like Figure 4 As shown in FIG, a memory cell string 304 can be organized into a plurality of memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is a basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. In order to erase the memory cells 305 in a selected memory block, a common source line 310 coupled to the selected memory block and unselected memory blocks in the same plane as the selected memory block can be biased with an erase voltage. It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 305 of adjacent memory cell strings 304 can be coupled by word lines 312, which select which row of memory cells 305 is affected by a read or program operation.

[0054] Figure 5 A cross-sectional schematic diagram of a memory array including a memory cell string provided in an embodiment of the present disclosure. Figure 5As shown, a memory array may include a stacked structure 400, which includes a plurality of gate layers 401 and a plurality of insulating layers 402 alternately stacked in sequence, and a channel structure 403 vertically extending through the gate layers 401 and the insulating layers 402. The gate layers 401 and the insulating layers 402 may be alternately stacked, with two adjacent gate layers 401 separated by an insulating layer 402. The number of memory cells included in the memory array is primarily related to the number of pairs of gate layers 401 and insulating layers 402 in the stacked structure 400.

[0055] The constituent material of the gate layer 401 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 401 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 401 includes a doped polysilicon layer. Multiple gate layers 401 surround a channel structure 403 to form a memory cell string. The gate layer 401 at the top of the stacked structure 400 can extend laterally as an upper selection gate line, the gate layer 401 at the bottom of the stacked structure 400 can extend laterally as a lower selection gate line, and the gate layer 401 extending laterally between the upper selection gate line and the lower selection gate line can serve as a word line layer.

[0056] In some embodiments, the stacked structure 400 may be disposed on a substrate 404. The substrate 404 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0057] It should be noted that, in some other embodiments, the memory array may only include the stacked structure 400 but not a substrate. The present disclosure does not limit whether the memory array includes a substrate.

[0058] In some embodiments, the channel structure 403 includes a functional layer, a channel layer, and an insulating filling layer. In some embodiments, the channel layer includes silicon, for example, polysilicon. In some embodiments, the functional layer is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure 403 may have a cylindrical shape (for example, a pillar shape). According to some embodiments, the channel layer, the tunneling layer, the storage layer, and the barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the functional layer may include a silicon oxide / silicon oxynitride / silicon oxide (ONO) composite layer.

[0059] Return Reference Figure 4 , the peripheral circuit 302 can be coupled to the memory array 301 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309 and the upper selection line 308. The peripheral circuit 302 may include any suitable analog, digital and mixed signal circuits to apply a voltage signal and / or a current signal to each target memory cell 305 through the bit line 311, the word line 312, the common source line 310, the lower selection line 309 and the upper selection line 308, and sense the voltage signal and / or the current signal from each target memory cell 305 to implement the operation of the memory array 301. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 501, a column decoder / bit line driver 502, a row decoder / word line driver 503, a voltage generator 504, a control logic unit 505, a register 506, a flash memory interface 507, and a data bus 508. It should be understood that in some examples, the peripheral circuit 302 may also include Figure 6 Additional peripheral circuits not shown.

[0060] The page buffer / sense amplifier 501 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 505. In one example, the page buffer / sense amplifier 501 can store a page of programming data (write data) to be programmed into the memory array 301. In another example, the page buffer / sense amplifier 501 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sense amplifier 501 can also sense a low-power signal from the bit line representing the data bit stored in the memory cell and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 502 can be configured to be controlled by the control logic unit 505 and select one or more memory cell strings by applying a bit line voltage generated from the voltage generator 504.

[0061] The row decoder / word line driver 503 can be configured to be controlled by the control logic unit 505 and select / deselect memory blocks of the memory array 301 and select / deselect word lines of the memory blocks. The row decoder / word line driver 508 can also be configured to drive word lines using word line voltages generated from the voltage generator 504. In some embodiments, the row decoder / word line driver 503 can also select / deselect and drive lower select lines and upper select lines. As described in detail below, the row decoder / word line driver 503 is configured to perform programming operations on memory cells coupled to (one or more) selected word lines. The voltage generator 504 can be configured to be controlled by the control logic unit 505 and generate word line voltages (e.g., read voltage, program voltage, precharge voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0062] The control logic unit 505 can be coupled to each peripheral circuit described above and is configured to control the operation of each peripheral circuit. The register 506 can be coupled to the control logic unit 505 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The flash memory interface 507 can be coupled to the control logic unit 505 and act as a control buffer to buffer control commands received from a host device (not shown) and relay them to the control logic unit 505, as well as buffer status information received from the control logic unit 505 and relay it to the memory controller. The flash memory interface 507 can also be coupled to the column decoder / bit line driver 502 via the data bus 508 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 301 or relay or buffer data from the memory array 301.

[0063] Operations of the memory system (eg, a write data operation, a read data operation, an erase data operation, etc.) may be implemented by running firmware stored in the memory system.

[0064] Exceptions inevitably occur during firmware execution. In some embodiments, the host can send a corresponding command to the memory system via a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) interface to trigger an assertion dump mode, thereby terminating program execution and saving the exception scene information. If a firmware software / hardware / communication failure occurs on the PCIE interface, the host will be unable to send the corresponding command to the memory system to trigger the assertion dump mode. This makes it impossible to obtain the corresponding exception scene information, making it difficult to quickly and effectively locate the problem, affecting customer support efficiency and satisfaction, and leading to difficulties in debugging during the debugging phase and a long problem-solving cycle.

[0065] The present disclosure provides an operating method of a memory system. Figure 7 A flowchart of the operating method provided in the embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the operating method of the memory system includes the following steps.

[0066] Step S10: In response to an exception occurring during the operation of the firmware of the memory system, an interrupt is triggered via a first pin of a general purpose input / output interface of the memory system that is operable to receive data transmitted in a serial communication manner.

[0067] Step S20: in response to an interrupt triggered by the first pin, triggering an assertion dump mode.

[0068] Here, firmware is a program written into an erasable programmable read-only memory or an electrically erasable programmable read-only memory. It refers to the device "driver" stored inside the memory system. Through firmware, the operating system can implement specific operating actions according to standard device drivers. Firmware is the software that performs the most basic and lowest-level work of a system.

[0069] In some specific examples, the firmware is stored in a read-only memory in a memory controller of the memory system or in a memory device.

[0070] Exceptions are inevitable during firmware execution. When an exception occurs, assertion dump mode must be triggered to save information about the exception. This information can include coredump information such as the PC pointer, stack usage information, and registers. Saving this information preserves the fault scene and provides data support for subsequent system recovery.

[0071] The general-purpose input / output (GPIO) interface here includes a first pin, which can be used to receive data transmitted via serial communication, also known as Universal Asynchronous Receiver / Transmitter (UART) data or serial port data. The first pin here can be a UART GPIO pin. UART is an important tool for SSD development and debugging. SSDs use GPIO pins to implement UART data transmission. For security reasons, the firmware in the customer version will disable the UART function.

[0072] In the embodiment of the present disclosure, the first pin of the universal input / output interface in the memory system is reused, and an interrupt is triggered through the first pin, thereby triggering the assertion dump mode. In the embodiment of the present disclosure, on the one hand, a new method of triggering the assertion dump mode is provided, so that even in the event of a failure of the high-speed serial computer expansion bus standard interface, abnormal scene information can be saved in a timely manner, thereby avoiding the loss of key abnormal scene information and improving the efficiency of problem solving; on the other hand, in the event of an abnormality during the operation of the firmware, the first pin is in an idle state, and the reuse of the existing first pin in the embodiment of the present disclosure does not affect the performance of the memory system; on the other hand, because the present disclosure reuses the existing first pin, the implementation cost is low.

[0073] In some embodiments, as Figure 10 As shown, the operating method also includes: step S1001: before triggering an interrupt through a first pin of the universal input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner, configuring the first pin to a first mode; in the first mode, the first pin can be used to receive a level signal; triggering an interrupt through the first pin of the universal input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner in step S10 includes: step S1002: in response to the first pin being in the first mode, triggering an interrupt when the level signal received by the first pin is in a first state.

[0074] In some specific examples, a general-purpose input / output interface can be used to receive data transmitted via serial communication or to receive level signals. The first pin can be configured to have the desired function by setting the corresponding mode in a register. When the first pin is configured in the first mode, it can be used to receive level signals; when the first pin is configured in the second mode, it can be used to receive data transmitted via serial communication. When the first pin is configured in the first mode, when the level signal received by the first pin is in a specific state, a corresponding type of interrupt can be triggered.

[0075] In some embodiments, the first state includes: a rising edge state or a falling edge state or a high level state or a low level state.

[0076] It is understandable that the first state may be any one of a rising edge state, a falling edge state, a high level state, and a low level state, and the first pin may trigger an interrupt in the first state through corresponding configuration.

[0077] The interrupt here can be understood as the interrupt generated by the GPIO module, which can be edge-triggered interrupt or level-triggered interrupt. Among them, edge-triggered interrupt includes rising edge trigger interrupt and falling edge trigger interrupt, and level-triggered interrupt includes high level trigger interrupt and low level trigger interrupt.

[0078] The GPIO module detects whether the initial level on the first pin is 0 or 1 and can change the level from 0 to 1 or vice versa through external expansion. The central processing unit (CPU) receives and processes interrupt requests. When the GPIO module detects a pin level change and meets the interrupt triggering conditions, an interrupt is triggered, and the CPU jumps to the interrupt handling address to handle the interrupt. To avoid corrupting the main task data, the CPU saves the current relevant registers and enters the interrupt service function. After executing the interrupt service function, the CPU restores the relevant registers and returns to the main task to continue program execution.

[0079] The following is an exemplary description using the example of configuring the first pin as a GPIO falling edge triggered interrupt, that is, the first state is a rising edge state.

[0080] In some embodiments, the memory system further includes a first ground pin; Figure 11 As shown, in response to the first pin being in the first mode, step S1002 triggers an interrupt when the level signal received by the first pin is in the first state, including: step S2001: in response to the first pin and the first ground pin being short-circuited, the level signal received by the first pin is in a rising edge state; step S2002: in response to the level signal received by the first pin being in a rising edge state, triggering an interrupt.

[0081] In some specific examples, the solder joint corresponding to the first pin and the solder joint corresponding to the first ground pin may be physically short-circuited, thereby achieving short-circuiting of the first pin and the first ground pin.

[0082] Here, the initial level of the first pin can be set to a high level first. After the solder joint corresponding to the first pin is short-circuited with the solder joint corresponding to the first ground pin, the level signal of the first pin is pulled low, so that the level signal of the first pin is in a rising edge state.

[0083] like Figure 2 as well as Figure 8 As shown, the memory system includes a memory card connector 202, which is used to connect the host to the memory system. The memory card connector 202 includes a high-speed serial computer expansion bus standard interface. The high-speed serial computer expansion bus standard interface enables the memory system to communicate with the host, receive data and commands, and return status and data to the host. The memory system also includes a general-purpose input and output interface 205, which can be connected to external devices such as the host. During the research and development process, the memory system needs to be debugged. The general-purpose input and output interface includes multiple pins 206, each pin corresponding to a solder joint. Figure 8 The following only shows some of the pins in the universal input and output interface. Different pins in the universal input and output interface have different functions. For example, the first pin can be used to receive data transmitted in a serial communication mode for system debugging. The two pins in group b can be the first pin and the first ground pin respectively. It should be noted that Figure 8 The shapes of the pins in the universal input / output interface shown in the figure are only examples and are not used to limit the shapes of the pins in the universal input / output interface. In some embodiments, the shapes of the pins in the universal input / output interface can also be other shapes, such as circular, square, rectangular, irregular, etc.

[0084] In some specific examples, such as Figure 9 As shown, a universal input / output interface in a memory system such as an SSD may include multiple solder joints 207, where B represents a group of solder joints in the SSD. One of the two solder joints in group B is a ground solder joint, which is connected to the first ground pin. The other solder joint in group B is connected to the first pin. The two solder joints in group B can be short-circuited using metal tweezers to place the level signal of the first pin in a rising edge state.

[0085] In some embodiments, the memory system further includes a second pin and a second ground pin, wherein the second pin is used to select a startup mode of a program when the memory system is powered on; Figure 12As shown, in response to the first pin being in the first mode, step S1002 triggers an interrupt when the level signal received by the first pin is in the first state, and also includes: step S3001: in response to the second pin and the second ground pin being short-circuited, the level signal received by the second pin is in a rising edge state; step S3002: in response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, triggering an interrupt.

[0086] In some specific examples, the initial level of the first pin can be set to a high level, and after the solder point corresponding to the first pin is short-circuited with the solder point corresponding to the first ground pin, the level signal of the first pin is pulled low, so that the level signal of the first pin is in a rising edge state; and the initial level of the second pin can be set to a high level, so that when the second pin and the second ground pin are short-circuited, the level signal of the second pin is pulled low, so that the level signal of the second pin is in a rising edge state.

[0087] It can be understood that in the above embodiment, the interrupt is triggered only when the level signals received by the first pin and the second pin are both in the rising edge state, which can prevent false triggering and improve the accuracy of interrupt triggering.

[0088] like Figure 8 As shown, the two pins in group a can be the second pin and the second ground pin respectively. Figure 9 As shown, A and B are two groups of solder joints on the SSD disk. One of the two solder joints in Group A is a ground solder joint, which is connected to the second ground pin, and the other solder joint in Group A is connected to the second pin. One of the two solder joints in Group B is a ground solder joint, which is connected to the first ground pin, and the other solder joint in Group B is connected to the first pin. The two groups of solder joints A and B can be separated by a certain distance to further prevent false triggering. You can first short-circuit the two solder joints in Group A with metal tweezers to put the level signal of the second pin in a rising edge state, and then short-circuit the two solder joints in Group B with metal tweezers to put the level signal of the first pin in a rising edge state.

[0089] In other embodiments, in response to the first pin being in the first mode, triggering an interrupt when the level signal received by the first pin is in the first state, also includes: in response to the second pin and the first ground pin being short-circuited, the level signal received by the second pin is in a rising edge state; in response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, triggering an interrupt.

[0090] In some specific examples, you can first Figure 9The solder point corresponding to the second pin in group A shown is short-circuited with the ground solder point among the two solder points in group B through metal tweezers, so that the level signal of the second pin is in a rising edge state, and then the two solder points in group B are short-circuited through metal tweezers, so that the level signal of the first pin is in a rising edge state.

[0091] In some embodiments, configuring the first pin to the first mode includes: configuring the first pin to the first mode during a user use phase.

[0092] It is understandable that, during the user use phase, the first pin does not need to receive data transmitted in a serial communication manner, and therefore the first pin can be directly configured to the first mode during the user use phase.

[0093] In some embodiments, the memory system further includes a high-speed serial computer expansion bus standard interface; configuring the first pin to the first mode includes: during the debugging phase of the memory system, in response to an exception occurring in the high-speed serial computer expansion bus standard interface and an exception occurring during the operation of the firmware of the memory system, configuring the first pin to the first mode.

[0094] The high-speed serial computer expansion bus standard interface here is used to connect the host and the memory system.

[0095] It is understandable that during the debugging phase of the memory system, the first pin needs to receive data transmitted in a serial communication manner, but if an exception occurs in the firmware of the memory system during operation, debugging will be stopped and the first pin will temporarily not need to receive data transmitted in a serial communication manner. In the event of an exception in the high-speed serial computer expansion bus standard interface, the first pin can be configured to a first mode so that an interrupt can be triggered through the first pin, thereby triggering the assertion transfer mode.

[0096] The solution provided in the embodiments of the present disclosure for triggering an interrupt via the first pin and thereby triggering the assertion dump mode can also be used when no exception has occurred in the high-speed serial computer expansion bus standard interface. That is, when the assertion dump mode needs to be triggered, if no exception has occurred in the high-speed serial computer expansion bus standard interface, the assertion dump mode can be triggered by sending a corresponding command via the high-speed serial computer expansion bus standard interface, or by triggering an interrupt via the first pin and thereby triggering the assertion dump mode, thus providing multiple options.

[0097] In some embodiments, the operating method further includes: in response to triggering the assertion dump mode, executing an assertion dump process; the assertion dump process includes saving exception context information to the memory device.

[0098] In some specific examples, the abnormality scene information may be first saved in a buffer in a memory controller, and then the abnormality scene information in the buffer may be transferred to a memory device.

[0099] In the embodiment of the present disclosure, a GPIO hardware module interrupt is triggered by short-circuiting the first pin and the first ground pin. The interrupt is processed by the interrupt function corresponding to CPU0, triggering the assertion dump mode and notifying CPU1 to execute the assertion dump processing, which is then executed by CPU1.

[0100] In some embodiments, the operating method further includes: during the debugging phase of the memory system, in response to completion of the assertion transfer processing, turning off the interrupt; in response to the interrupt being turned off, configuring the first pin to a second mode; in the second mode, the first pin can be used to receive data transmitted in a serial communication manner.

[0101] It is understandable that during the debugging phase, after the assertion transfer processing is completed, most of the system functions stop. In order to support further debugging, it is necessary to restore the configuration of the first pin and configure the first pin to the second mode so that the first pin can be used to receive serial port commands, thereby enabling the CPU to execute the corresponding Uart commands.

[0102] In some embodiments, the operating method further includes: in response to the interrupt being disabled, after the memory system is powered on again, sending the abnormal field information to a host coupled to the memory system through the high-speed serial computer expansion bus standard interface.

[0103] It is understandable that when a high-speed serial computer expansion bus standard interface fails, the high-speed serial computer expansion bus standard interface can be restored after the memory system is powered on again, so that the abnormal field information stored in the memory device can be read by the host for problem analysis.

[0104] Based on a concept similar to the operating method of the above-mentioned memory system, the present disclosure also provides a memory system, including: a memory device and a memory controller coupled to the memory device; the memory system includes a general-purpose input / output interface, the general-purpose input / output interface includes a first pin, and the first pin can be used to receive data transmitted in a serial communication manner; the memory controller is configured to: trigger an interrupt through the first pin in response to an exception occurring in the firmware of the memory system during operation; and trigger an assertion dump mode in response to the interrupt triggered by the first pin.

[0105] In some embodiments, the memory controller is further configured to: before triggering an interrupt through the first pin, configure the first pin to a first mode, in which the first pin can be used to receive a level signal; in response to the first pin being in the first mode, trigger an interrupt when the level signal received by the first pin is in a first state.

[0106] In some embodiments, the first state includes: a rising edge state or a falling edge state or a high level state or a low level state.

[0107] In some embodiments, the memory system further includes a first ground pin; the memory controller is configured to: in response to the first pin and the first ground pin being short-circuited, the level signal received by the first pin being in a rising edge state; and in response to the level signal received by the first pin being in a rising edge state, trigger an interrupt.

[0108] In some embodiments, the memory system further includes a second pin and a second ground pin, the second pin being used to select a program startup mode when the memory system is powered on; the memory controller is further configured to: in response to the second pin and the second ground pin being short-circuited, the level signal received by the second pin being in a rising edge state; in response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, trigger an interrupt.

[0109] In some embodiments, the memory controller is configured to: configure the first pin to the first mode during a user use phase.

[0110] In some embodiments, the memory system further includes a high-speed serial computer expansion bus standard interface; the memory controller is configured to: during the debugging phase of the memory system, in response to an exception occurring in the high-speed serial computer expansion bus standard interface and an exception occurring in the firmware of the memory system during operation, configure the first pin to the first mode.

[0111] In some embodiments, the memory controller is further configured to: in response to triggering the assertion dump mode, perform an assertion dump process; the assertion dump process includes saving exception context information to the memory device.

[0112] In some embodiments, the memory controller is further configured to: during the debugging phase of the memory system, in response to completion of the assertion transfer processing, turn off the interrupt; in response to the interrupt being turned off, configure the first pin to a second mode; in the second mode, the first pin can be used to receive data transmitted in a serial communication manner.

[0113] In some embodiments, the memory controller is further configured to: in response to the interrupt being turned off, after the memory system is powered on again, send the abnormal field information to the host coupled to the memory system through the high-speed serial computer expansion bus standard interface.

[0114] In some embodiments, the memory system includes a memory card or a solid state drive or a general flash storage.

[0115] The present disclosure also provides a computer-readable storage medium, on which a computer program is stored. The computer-readable storage medium stores the computer program, and when the computer program is executed, the operating method described in any of the above embodiments can be implemented.

[0116] Here, to implement all or part of the processes in the operating methods of the above embodiments, the processes may be completed by hardware related to computer program instructions. The computer program may be stored in a computer-readable storage medium. The execution of the computer program may include the processes of the operating methods in any of the above embodiments. The computer-readable storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD), or a solid-state drive, etc. The computer-readable storage medium may also include a combination of multiple storage media.

[0117] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0118] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0119] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory system, characterized in that: include: a memory device and a memory controller coupled to the memory device; The memory system includes a universal input / output interface, the universal input / output interface includes a first pin, and the first pin can be used to receive data transmitted in a serial communication manner; The memory controller is configured to: In response to an exception occurring during the operation of the firmware of the memory system, triggering an interrupt through the first pin; In response to an interrupt triggered by the first pin, a dump mode is asserted.

2. The memory system according to claim 1, wherein: The memory controller is further configured to: Before triggering an interrupt through the first pin, configuring the first pin to a first mode, wherein the first pin can be used to receive a level signal in the first mode; In response to the first pin being in the first mode, an interrupt is triggered when a level signal received by the first pin is in a first state.

3. The memory system according to claim 2, wherein: The first state includes: a rising edge state, a falling edge state, a high level state, or a low level state.

4. The memory system according to claim 2, wherein: The memory system further includes a first ground pin; and the memory controller is configured to: In response to the first pin and the first ground pin being short-circuited, the level signal received by the first pin is in a rising edge state; In response to the level signal received by the first pin being in a rising edge state, an interrupt is triggered.

5. The memory system according to claim 4, wherein: The memory system further includes a second pin and a second ground pin, wherein the second pin is used to select a startup mode of a program when the memory system is powered on; The memory controller is further configured to: In response to the second pin and the second ground pin being short-circuited, the level signal received by the second pin is in a rising edge state; In response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, an interrupt is triggered.

6. The memory system according to claim 2, wherein: The memory controller is configured to: During the user use phase, the first pin is configured to the first mode.

7. The memory system according to claim 2, wherein: The memory system further includes a high-speed serial computer expansion bus standard interface; the memory controller is configured to: During the debugging phase of the memory system, in response to an exception occurring in the high-speed serial computer expansion bus standard interface and an exception occurring in the firmware of the memory system during operation, the first pin is configured to the first mode.

8. The memory system according to claim 7, wherein: The memory controller is further configured to: In response to triggering the assertion dump mode, an assertion dump process is executed; the assertion dump process includes saving exception context information into the memory device.

9. The memory system according to claim 8, wherein: The memory controller is further configured to: During a debugging phase of the memory system, in response to completion of the assertion dumping process, disabling the interrupt; In response to the interrupt being disabled, configuring the first pin to a second mode; In the second mode, the first pin can be used to receive data transmitted in a serial communication manner.

10. The memory system according to claim 9, wherein: The memory controller is further configured to: In response to the interrupt being disabled, after the memory system is powered on again, the abnormal field information is sent to a host coupled to the memory system through the high-speed serial computer expansion bus standard interface.

11. The memory system according to claim 1, wherein: The memory system includes a memory card, a solid state drive, or a universal flash memory storage.

12. A method for operating a memory system, characterized in that: The operation method includes: In response to an exception occurring during the operation of the firmware of the memory system, triggering an interrupt via a first pin of a general purpose input / output interface of the memory system that is operable to receive data transmitted in a serial communication manner; In response to an interrupt triggered by the first pin, a dump mode is asserted.

13. The operating method according to claim 12, characterized in that: The operation method further includes: Before triggering an interrupt via a first pin of a general purpose input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner, configuring the first pin to a first mode; in the first mode, the first pin can be used to receive a level signal; The triggering of an interrupt by a first pin of a universal input / output interface of the memory system that can be used to receive data transmitted in a serial communication manner includes: In response to the first pin being in the first mode, an interrupt is triggered when a level signal received by the first pin is in a first state.

14. The operating method according to claim 13, characterized in that: The first state includes: a rising edge state, a falling edge state, a high level state, or a low level state.

15. The operating method according to claim 13, characterized in that: The memory system further includes a first ground pin; and in response to the first pin being in the first mode, triggering an interrupt when a level signal received by the first pin is in a first state, comprising: In response to the first pin and the first ground pin being short-circuited, the level signal received by the first pin is in a rising edge state; In response to the level signal received by the first pin being in a rising edge state, an interrupt is triggered.

16. The operating method according to claim 15, characterized in that: The memory system further includes a second pin and a second ground pin, wherein the second pin is used to select a startup mode of a program when the memory system is powered on; In response to the first pin being in the first mode, triggering an interrupt when the level signal received by the first pin is in the first state, further comprising: In response to the second pin and the second ground pin being short-circuited, the level signal received by the second pin is in a rising edge state; In response to the level signal received by the first pin being in a rising edge state, and the level signal received by the second pin being in a rising edge state, an interrupt is triggered.

17. The operating method according to claim 13, characterized in that: Configuring the first pin to the first mode includes: During the user use phase, the first pin is configured to the first mode.

18. The operating method according to claim 13, characterized in that: The memory system also includes a high-speed serial computer expansion bus standard interface; Configuring the first pin to the first mode includes: During the debugging phase of the memory system, in response to an exception occurring in the high-speed serial computer expansion bus standard interface and an exception occurring in the firmware of the memory system during operation, the first pin is configured to the first mode.

19. The operating method according to claim 18, characterized in that: The operation method further includes: In response to triggering the assertion dump mode, an assertion dump process is executed; the assertion dump process includes saving exception context information into the memory device.

20. The operating method according to claim 19, characterized in that: The operation method further includes: During a debugging phase of the memory system, in response to completion of the assertion dumping process, disabling the interrupt; In response to the interrupt being disabled, the first pin is configured to be in a second mode; in the second mode, the first pin can be used to receive data transmitted in a serial communication manner.

21. The operating method according to claim 20, characterized in that: The operation method further includes: In response to the interrupt being disabled, after the memory system is powered on again, the abnormal field information is sent to a host coupled to the memory system through the high-speed serial computer expansion bus standard interface.

22. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed, the operating method according to any one of claims 12 to 21 can be implemented.

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