Address translation and fast mapping table construction method and device, storage medium and program product

Abstract

The embodiment of the invention provides an address conversion and fast mapping table construction method and device, a storage medium and a program product. In the embodiment of the invention, an adaptive first RMAP table is constructed for an EPT table, address information of a last-level page table entry corresponding to at least one GPA in the EPT is stored in the first RMAP table, a rapid mapping relation from the GPA to the HPA is established based on the first RMAP table, and rapid address translation from the GPA to the HPA is realized. Furthermore, a second RMAP table is created for the EPT, at least one piece of address translation information from the HPA to the corresponding GPA is stored in the second RMAP table, the fast mapping relation from the HPA to the GPA is established, and fast address translation from the HPA to the GPA is achieved. Bidirectional rapid mapping can be realized based on the first RMAP table and the second RMAP table, and the address conversion efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of virtualization technology, and in particular to an address translation and fast mapping table construction method, device, storage medium, and program product. Background Art

[0002] Virtualization is a core technology in cloud computing. It achieves the purpose of segmenting and centrally managing physical resources by creating one or more virtualized instances (or clients) on the physical resources of a host machine. The host machine has a host operating system (Host Operating System, Host OS) and physical memory (actual physical memory) seen by the host machine. The address of this physical memory is called the Host Physical Address (HPA). The client machine has a guest operating system (Guest OS) and physical memory seen by the client. The address of this physical memory is called the Guest Physical Address (GPA).

[0003] In a virtualized environment, memory management is performed through EPT (Extended Page Tables). By providing each guest with an independent multi-level page table structure, it is responsible for translating the guest's GPA into the host's HPA, while also achieving isolation between different guests. EPT can convert the guest's GPA into the host's HPA and, through hardware-supported address translation mechanisms, direct access to the correct physical memory location. However, this translation process often requires querying multiple levels of page tables, which is inefficient. Summary of the Invention

[0004] Various aspects of the present application provide an address conversion and fast mapping table construction method, device, storage medium and program product to improve address conversion efficiency and achieve fast address conversion.

[0005] An embodiment of the present application provides an address conversion method, including: pre-constructing a first quick mapping table corresponding to a memory page table, the memory page table including a multi-level page table corresponding to at least one client physical address; storing address information of a last-level page table entry corresponding to at least one client physical address in the first quick mapping table; responding to a first address conversion trigger event, determining a first client physical address that requires address conversion, and querying the first quick mapping table for address information of a last-level page table entry corresponding to the first client physical address; if the address information of the last-level page table entry corresponding to the first client physical address is queried, generating a host machine physical address corresponding to the first client physical address based on the address information of the last-level page table entry corresponding to the first client physical address and the address offset of the first client physical address.

[0006] An embodiment of the present application also provides a method for constructing a fast mapping table, including: dividing the address space of the client physical address corresponding to the memory page table into at least one address space, creating a basic structure for each address space, the basic structure corresponding to a set page table level, and the memory page table including at least one multi-level page table corresponding to each client physical address; for any client physical address in the memory page table, determining the first structure corresponding to any client physical address from each basic structure based on the address information of any client physical address and the address space corresponding to each basic structure; based on the relationship between the level of the last-level page table corresponding to any client physical address and the set page table level, recording the address information of the last-level page table entry corresponding to any client physical address through the first structure to construct a first fast mapping table corresponding to the memory page table, wherein the first fast mapping table stores the address information of the last-level page table entry corresponding to at least one client physical address.

[0007] An embodiment of the present application also provides a physical machine, including: a memory and a processor; the memory is used to store computer programs; the processor is coupled to the memory and is used to execute the computer programs to implement the various steps in the address conversion and fast mapping table construction method provided in the embodiment of the present application.

[0008] An embodiment of the present application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements the steps of the address conversion and fast mapping table construction method provided in the embodiment of the present application.

[0009] An embodiment of the present application also provides a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, the processor implements the steps of the address conversion and fast mapping table construction method provided in the embodiment of the present application.

[0010] In an embodiment of the present application, an adaptive first quick mapping table is constructed for the memory page table, and the address information of the last-level page table entry corresponding to at least one client physical address in the memory page table is stored in the first quick mapping table. In this way, when performing address conversion for the client physical address, the first quick mapping table corresponding to the memory page table can be queried first. If the address information of the last-level page table entry corresponding to the client physical address is queried in the first quick mapping table, the host physical address corresponding to the client physical address can be directly generated based on the address information of the last-level page table entry corresponding to the client physical address and the address offset of the client physical address. There is no need to query level by level in the multi-level page table corresponding to the client physical address contained in the memory page table, which can improve the address conversion efficiency and achieve fast address conversion.

[0011] In some optional embodiments of the present application, an adapted second quick mapping table is also constructed for the memory page table, and the address conversion information of at least one host physical address to the corresponding client physical address is stored in the second quick mapping table to support the address conversion of the host physical address to the corresponding client physical address, thereby solving the deficiency that only the address conversion of the client physical address to the host physical address can be realized based on the memory page table, and meeting the address conversion requirements from the host physical address to the client physical address in various virtualization environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0013] Figure 1a A flowchart of an address conversion method provided by an exemplary embodiment of the present application;

[0014] Figure 1b A flowchart of a method for constructing a fast mapping table provided by an exemplary embodiment of the present application;

[0015] Figure 2a A schematic diagram of the structure of a physical machine provided by an exemplary embodiment of the present application;

[0016] Figure 2b A schematic diagram of the structure of another physical machine provided for an exemplary embodiment of the present application;

[0017] Figure 2c The exemplary embodiments of the present application provide Figure 1b The physical machine shown is a system structure diagram working in root mode;

[0018] Figure 2d The exemplary embodiments of the present application provide Figure 1b The physical machine shown is a system structure diagram working in non-root mode; Figure 3a An exemplary embodiment of the present application provides a flowchart of switching a host operating system from root mode to non-root mode;

[0019] Figure 3b A schematic diagram of a process for creating a memory page table is provided for an exemplary embodiment of the present application;

[0020] Figure 3c A schematic diagram of a process for creating an information bearing object is provided for an exemplary embodiment of the present application;

[0021] Figure 3d A schematic diagram of a mode switching process is provided for an exemplary embodiment of the present application;

[0022] Figure 4 A schematic structural diagram of an address conversion device is provided for an exemplary embodiment of the present application;

[0023] Figure 5 A schematic structural diagram of a fast mapping table construction device provided by an exemplary embodiment of the present application;

[0024] Figure 6 A schematic diagram of the structure of a physical machine provided as an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0025] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0027] In a virtualized environment, address conversion between GPA and HPA is performed through a memory page table. Optionally, the memory page table can be implemented as an EPT. In the following embodiments of this application, the memory page table is implemented as an EPT as an example for description, but it is not limited to this. Among them, the EPT stores a multi-level page table corresponding to at least one GPA. However, there is a problem of low address conversion efficiency. To address this technical problem, in an embodiment of this application, a first rapid mapping (RMAP) table is constructed for the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to at least one GPA, which is used to establish a rapid mapping relationship between the GPA and the HPA, improve the address conversion efficiency, and achieve rapid address conversion.

[0028] Furthermore, EPT only supports address conversion from GPA to HPA, and cannot support reverse address conversion from HPA to GPA. In an embodiment of the present application, a second RMAP table is created for EPT, and the second RMAP table stores address conversion information from at least one HPA to the corresponding GPA, which is used to establish a fast mapping relationship between HPA and GPA, improve address conversion efficiency, and achieve fast address conversion.

[0029] Furthermore, in the embodiments of the present application, the construction process, management process and synchronization update process of the first RMAP table and the second RMAP table with the EPT status are also described in detail. For details, please refer to the detailed description in subsequent embodiments.

[0030] It should be noted that the technical solutions provided in the embodiments of this application are applied to a virtualized environment. A virtualized environment refers to an operating environment generated by virtualizing physical resources on a host computer using virtualization technology and creating one or more virtualized instances on the processed virtualized resources. In the embodiments of this application, the virtualized instances hosted on the virtualized resources are referred to as clients, as opposed to the host computer. The client computer has its own operating system and global presence controller (GPA), while the host computer has its own operating system and high-performance environment (HPA).

[0031] In the embodiments of the present application, the implementation method of the virtualization environment is not limited. In an optional embodiment, implementation method A of the virtualization environment is: a virtualization manager (hypvisor) is added to the host OS, which virtualizes the hardware resources on the host and creates one or more virtual machines based on the virtualized resources. In this virtualization environment, address translation between the client's GPA and the host's HPA is performed through a multi-level page table corresponding to at least one GPA in the EPT.

[0032] In another optional embodiment, the implementation method B of the virtualization environment is: adding a virtualization layer between the hardware resources of the host machine and the host operating system, and implementing the virtual resource provision function in at least the virtualization layer. The virtualization layer switches the running host operating system from root mode (root) to non-root mode (non-root), provides at least one virtual resource in non-root mode and runs at least an application that the host operating system cannot run in root mode due to insufficient resources on the virtual resource. Without reinstalling the operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, solving the problem that the application cannot run due to insufficient resources due to reasons such as the failure to enable or missing system functions, supporting the operation of more applications, and helping to expand the capabilities of the host operating system.

[0033] Among them, root mode is an operating mode in which the host operating system has direct access rights to hardware resources, and non-root mode is an operating mode in which the virtualization layer virtualizes hardware resources and schedules and accesses the virtualized resources on behalf of the host operating system. In non-root mode, the virtualization layer's access to hardware resources is limited. Accordingly, the host operating system in non-root mode can also be called a client operating system. The virtualization layer maintains an EPT, and the memory page table is used to store the mapping relationship between the client physical address in non-root mode and the host physical address in root mode. The virtualization layer can convert the GPA into the HPA based on the multi-level page table of the EPT.

[0034] In an embodiment of the present application, whether in a virtualization environment implemented by method A or in a virtualization environment implemented by method B, a first RMAP table can be created for EPT, and a fast mapping from GPA to HPA can be implemented based on the first RMAP table. Furthermore, a second RMAP table can be created, and a reverse mapping from HPA to GPA can be implemented based on the second RMAP table, thereby solving the problem that EPT cannot implement the reverse mapping from HPA to GPA and meeting the reverse mapping problem from HPA to GPA.

[0035] In approach A, the processes of creating the first RMAP table, performing address translation based on the first RMAP table, and creating the second RMAP table and performing address translation based on the second RMAP table can be performed by the host OS, specifically by the virtualization manager within the host OS. In approach B, the processes of creating the first RMAP table, performing address translation based on the first RMAP table, and creating the second RMAP table and performing address translation based on the second RMAP table can be performed by the virtualization layer in non-root mode. Whether the host OS in approach A or the virtualization layer in approach B, the processes of creating the first RMAP table, performing address translation based on the first RMAP table, and creating the second RMAP table and performing address translation based on the second RMAP table are identical or similar.

[0036] A solution provided by an embodiment of the present application is described in detail below with reference to the accompanying drawings.

[0037] Figure 1a A flowchart of an address conversion method provided by an exemplary embodiment of the present application is shown in FIG. Figure 1a As shown, the method includes:

[0038] R11. Pre-build a first RMAP table corresponding to the EPT, where the EPT includes a multi-level page table corresponding to at least one GPA; the first RMAP table stores address information of a last-level page table entry corresponding to at least one GPA;

[0039] R12. In response to the first address translation trigger event, determine the first GPA that requires address translation, and query the first RMAP table for address information of the last-level page table entry corresponding to the first GPA;

[0040] R13. If the address information of the last-level page table entry corresponding to the first GPA is found, generate the HPA corresponding to the first GPA according to the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA.

[0041] In this embodiment, the EPT adopts a multi-level page table structure on the one hand, and on the other hand, the EPT adopts a hybrid mapping granularity, which supports not only small page granularity but also large page granularity, can meet the needs of different physical page mappings, and improve the flexibility of memory mapping. Specifically, on the one hand, the EPT includes at least one multi-level page table corresponding to each GPA, and the multi-level page table can be a 2-level memory page table, a 4-level memory page table, or a 5-level memory page table. Taking the EPT including a 4-level memory page table as an example, the EPT includes: a Page Global Directory (PGD), a Page Upper Directory (PUD), a Page Middle Directory (PMD), and a Page Table Entry (PTE). The page table entry pgd_t in the PGD records the address information of the next-level page table (e.g., PUD). The page table entry pud_t in the PUD records the address information of the next-level page table (e.g., PMD). The page table entry pmd_t in the PMD records the address information of the next-level page table (e.g., PTE). The page table entry pte_t in the PTE records the starting address of the physical page corresponding to the HPA. Of course, if the PGD, PUD, and PMD are the last-level page tables, then the page table entries corresponding to the PGD, PUD, and PMD, respectively, record the starting address of the physical page corresponding to the HPA. It should be noted that the GPA address can be divided into several parts, each of which serves as an index, resulting in multiple index values ​​and an address offset. The address offset refers to the offset relative to the corresponding physical page. Taking the EPT as an example, which includes four levels of memory page tables, the GPA can be divided into five parts, including: PGD-level index value, PUD-level index value, PMD-level index value, PTE-level index value, and address offset. Typically, the HPA corresponding to the GPA can be obtained by querying the EPT based on the index values ​​and address offsets in the GPA address.

[0042] On the other hand, EPT is created with different page granularities for different address spaces (GPAs). For example, some address spaces create EPT's multi-level page tables with small page granularity. If the small page granularity is 4k (corresponding to PTE page granularity), then the address space corresponds to a 4-level page table, namely PGD, PUD, PMD, and PTE, with the last-level page table being PTE. Other address spaces can use large page granularity to create EPT. If the large page granularity is 2m (corresponding to PMD page granularity), then the address space corresponds to a 3-level page table, namely PGD, PUD, and PMD, with the last-level page table being PMD. Still other address spaces can use large page granularity to create EPT. If the large page granularity is 1G (corresponding to PUD page granularity), then the address space corresponds to a 2-level page table, namely PGD and PUD, with the last-level page table being PUD. In other words, EPT uses a mixed mapping granularity, and the last-level page table corresponding to any GPA in EPT can be PGD, PUD, PMD, or PTE. For a detailed introduction to the EPT page table, please refer to the subsequent embodiments and will not be repeated here.

[0043] In order to facilitate the recording of the fast mapping relationship between GPA and HPA, in this embodiment, a data structure of a first RMAP table is provided. The data structure stores the address information of the last-level page table entry corresponding to at least one GPA, thereby bypassing the multi-level page table translation in the EPT and improving the address translation efficiency.

[0044] In this embodiment, since the last level page table of each GPA in the EPT page table may be of mixed granularity, the address information of the last level page table entry stored in the first RMAP table may be the address information of at least one page table among PGD, PUD, PMD and PTE.

[0045] In this embodiment, the timing for pre-building the first RMAP table corresponding to the EPT is not limited. For example, the first RMAP table may be created after the EPT is created based on the correspondence between the GPA and the last-level page table of the EPT. For another example, when the last-level page table of the EPT is created, the first RMAP table add function may be called to create the corresponding first RMAP table. In this way, the first RMAP table is created along with the EPT.

[0046] In this embodiment, address translation trigger events are maintained. For ease of distinction and description, the address translation trigger event that triggers the GPA to HPA translation is referred to as the first address translation trigger event. The first address translation trigger event can be memory mapping management for the GPA, memory hot and cold management events, and memory swap management events.

[0047] Accordingly, when a first address translation trigger event occurs, the first GPA that requires address translation can be determined in response to the first address translation trigger event, and the address information of the last-level page table entry corresponding to the first GPA can be queried in the first RMAP table. If the address information of the last-level page table entry corresponding to the first GPA is found, the HPA corresponding to the first GPA is generated based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. For example, by parsing the address information of the last-level page table entry corresponding to the first GPA, the starting address of the host physical address recorded in the last-level page table entry and the alignment value (HPA_align) of the host physical address can be obtained. The address offset of the first GPA refers to the offset relative to the starting address. Therefore, the HPA corresponding to the first GPA can be generated by adding the HPA_align to the address offset of the first GPA.

[0048] In an optional embodiment, a basic structure can be created for the GPA address space corresponding to the EPT. Based on the basic structure, a first RMAP table corresponding to the EPT is pre-built. Compared with address conversion step by step through the EPT, address conversion based on the basic structure does not require going through multiple levels of page tables, and the address conversion efficiency is higher.

[0049] Specifically, considering that there are multiple different page table levels in the EPT, a set page table level can be selected as the basic page table level. The set page table level can be any page table level, for example, the set page table level can be the PUD page table level, the PMD page table level, the PTE page table level, or the PGD page table level. The GPA address space corresponding to the EPT is divided into at least one address space, and a basic structure corresponding to the basic page table level (i.e., the set page table level) is created for each of the at least one address spaces. The GPA address space corresponding to the EPT can be divided according to the page granularity corresponding to the set page table level. For example, if the set page table level is the PMD page table level and the granularity of the PMD page table is 2m, the GPA address space corresponding to the EPT can be divided into at least one address space with a granularity of 2m, and a basic structure is created for each 2m address space. For another example, if the set page table level is the PUD page table level and the granularity of the PUD page table is 1G, the GPA address space corresponding to the EPT can be divided into at least one address space with a granularity of 1G, and a basic structure is created for each 1G address space.

[0050] For any GPA in the EPT, the first structure corresponding to any GPA is determined from each basic structure based on the address information of any GPA and the address space corresponding to each basic structure. Among them, the address space corresponding to each basic structure can be understood as an address range, and the size of the address range corresponds to the page granularity corresponding to the set page table level. Any GPA is an address information, and the address information can fall into the address space corresponding to a certain basic structure. For the sake of distinction and description, the basic structure corresponding to the address space to which the address information of any GPA belongs is called the first structure.

[0051] According to the relationship between the level of the last page table corresponding to any GPA and the set page table level, the address information of the last page table entry corresponding to any GPA is recorded by the first structure. The level of the last page table can be the same as the set page table level, or the level of the last page table can be the previous level or the next level of the set page table level. In addition, the address information of the last page table entry corresponding to any GPA can be recorded by the first structure, or the address information of the last page table entry corresponding to any GPA can be recorded by a second structure that is an extension of the first structure. For a detailed introduction to the second structure, please refer to the aforementioned embodiment.

[0052] Optionally, based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, the implementation method of recording the address information of the last-level page table entry corresponding to any GPA through the first structure is not limited. The method provided by this optional embodiment is: if the level of the last-level page table is the same as the set page table level, the first structure is used to record the address information of the last-level page table entry; if the level of the last-level page table is different from the set page table level, other page table levels different from the set page table level are represented by extended mapping. For example, for the first structure, a second structure is expanded, the address information of the last-level page table entry is recorded in the second structure, and the address information of the second structure is recorded in the first structure.

[0053] An exemplary description is given below.

[0054] Example C1:If the level of the last-level page table corresponding to any GPA is the same as the set page table level, it is considered unnecessary to expand the first structure, and the first structure is directly used to record the address information of the last-level page table entry. The address information of the last-level page table entry corresponding to any GPA is added to the information field of the first structure, and the flag information in the first structure is set to a first value, which indicates that the information field of the first structure stores the address information of the last-level page table entry. The basic structure can be a fast mapping header (rmap_head) structure, for example, structrmap_head{unsigned long val}, where struct is a structure, unsigned long indicates that the data type is unsigned long, and val is the information field.

[0055] Example C2: If the level of the last-level page table corresponding to any GPA is different from the set page table level, it is considered that the first structure can be expanded to generate a second structure adapted to the level of the last-level page table corresponding to any GPA, and the address information of the last-level page table entry corresponding to any GPA is added to the information field in the second structure, and the address information of the second structure is added to the information field in the first structure, and the flag information in the first structure is set to the second value, and the second value indicates that the information field of the first structure stores the address information of the second structure.

[0056] Among them, it should be noted that the flag information in the first structure is mainly used to identify the type of address information stored in the information field in the first structure. If the flag information is the first value, it means that the information field of the first structure stores the address information of the last-level page table entry; if the flag information is the second value, it means that the information field of the first structure stores the address information of the second structure. The first value and the second value have different values. For example, the first value and the second value can be represented by different bits in different information fields, and the bit value of 1 indicates which value is valid. For another example, the lower three bits in the information field can be used as flag information, and the value range of the lower three bits is 0-7. The first value and the second value can be any two different values ​​between 0-7.

[0057] Further, optionally, the implementation method of creating a second structure adapted to the level of the last level page table corresponding to any GPA is not limited, and the following is an exemplary description: the address information of the last level page table entry is written into the second structure, and the address information of the second structure is written into the base structure; in this case, all GPAs in the pud

[0058] The corresponding basic structures can share the same second structure, without creating a second structure for each basic structure

[0059] Example D1: In the case where the level of the last-level page table corresponding to any GPA is the previous level of the set page table level, in an optional embodiment, multiple base structures can be created for the last-level page table, and for each base structure, a second structure adapted to the level of the last-level page table is generated, the address information of the last-level page table entry is recorded in each second structure, and the address information of each second structure is written into the corresponding base structure. In another optional embodiment, since the address information of the last-level page table entry is recorded in each second structure, multiple base structures can share the same second structure, and the address information of the shared second structure is recorded in each base structure.

[0060] For example, the page table level is set to the PMD level, that is, the basic structure corresponds to the PMD page table level, the level of the last page table corresponding to any GPA is the previous level of the set page table level, that is, the PUD level, a PUD large page includes 512 PMD pages, each PMD page corresponds to a basic structure, a PUD large page corresponds to 512 basic structures, multiple basic structures can share the same second structure, the second structure stores the address information of the PUD page, and the information field in each basic structure stores the address information of the shared second structure.

[0061] Based on the above, when the level of the last-level page table corresponding to any GPA is the previous level of the set page table level, it can be determined whether the second structure already exists; if the second structure does not exist, create a new structure that is adapted to the level of the last-level page table corresponding to any GPA as the second structure, add the address information of the second structure to the information field in the first structure corresponding to any GPA, and set the flag information in the first structure to the second value.

[0062] Optionally, if the second structure already exists, the address information of the existing second structure is added to the information field in the first structure corresponding to any GPA, and the flag information in the first structure is set to the second value.

[0063] When the last page table level corresponding to any GPA is the level above the set page table level, the second structure can be represented as rmap_cmpt{unsigned long val; atomic_t num;}. struct is a structure, unsigned long indicates the data type is unsigned long, val is an information field, and atomic_t num indicates the number of GPA-HPA fast mappings.

[0064] Example D2:When the level of the last page table corresponding to any GPA is the next level below the preset page table level, a new structure adapted to the level of the last page table corresponding to any GPA is created as the second structure.

[0065] For example, the preset page table level is the PMD page table level, and the level of the last page table corresponding to any GPA is the next level of the preset page table level, that is, the PTE page table level. The page table of the preset page table level can be extended to multiple next-level page tables, such as the 2m page table of the PDM level can map 512 PTE-level page tables. Accordingly, the first structure corresponding to any GPA can be extended to multiple (such as 512) second structures, and the multiple second structures are used to store the address information of the next-level page table (PTE page table) mapped from the page table of the preset page table level (such as the PMD page table). Furthermore, a unified structure can be used to organize and manage the multiple second structures, and the unified structure can organize and manage the multiple second structures in the form of an array, and the address information stored in each second structure is regarded as an element in the array. The unified structure can be a subsequent rapid mapping extension (rmap_extd) structure, and the address information stored in the second structure is the element of the array contained in the rmap_extd structure. The unified structure is represented as rmap_extd{unsigned long val[VAL_EXTD_NR]; atomic_t num;}. "struct" is a structure, "unsigned long" indicates the data type is unsigned long, and "atomic_t num" indicates the number of GPA-HPA rapid mappings. "val[VAL_EXTD_NR]" is an array, and the address information stored in the second structure is the element of the val[VAL_EXTD_NR] array.

[0066] Among them, the offset of the granularity of the next level page table (such as 4k) in the page table of the preset page table level (such as 2m) can be determined, and a new structure corresponding to the offset is created, and the new structure is used as the second structure corresponding to the any GPA. For example, if the any GPA is located at the third 4k page in 2m, a new structure corresponding to the offset 3 is created, and the new structure is used as the second structure corresponding to the any GPA. The address information of the last level page table (such as the PTE page table) corresponding to any GPA can also be added to the information field of the second structure, and the flag information in the second structure is set to the second value.

[0067] In an optional embodiment, when the first RMAP table already exists, operations such as query operation, addition operation, deletion operation, modification operation, expansion operation and contraction operation can be performed on any GPA.

[0068] Example E1 : The following description is made by taking the query operation for the first GPA as an example.

[0069] The situation of querying the HPA corresponding to the first GPA is not limited. For example, when reading and writing data for the first GPA, the query of the HPA corresponding to the first GPA can be triggered, so as to quickly obtain the HPA corresponding to the first GPA based on the first RMAP table.

[0070] When querying the HPA corresponding to the first GPA, the first RMAP table is queried for the address information of the last-level page table entry corresponding to the first GPA. If the address information of the last-level page table entry corresponding to the first GPA is found, the HPA corresponding to the first GPA is generated based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. Alternatively, if the address information of the last-level page table entry corresponding to the first GPA is not found, it is determined that the first GPA does not have an HPA, and a page fault exception may be triggered.

[0071] In an optional embodiment, based on the address information of the first GPA and the address space corresponding to each basic structure included in the first RMAP table, a first structure corresponding to the first GPA is determined from each basic structure, where the first structure is the basic structure corresponding to the first GPA among the basic structures included in the first RMAP table; address information of a last-level page table entry corresponding to the first GPA is obtained using the first structure corresponding to the first GPA; and an HPA corresponding to the first GPA is generated based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA.

[0072] Optionally, obtaining the address information of the last-level page table entry corresponding to the first GPA through the first structure corresponding to the first GPA includes: obtaining flag information from the first structure; depending on the flag information, the method of obtaining the address information of the last-level page table entry corresponding to the first GPA is also different. If the flag information is a first value, it means that the information field of the first structure records the address information of the last-level page table entry, and the address information of the last-level page table entry corresponding to the first GPA can be directly obtained from the information field in the first structure; if the flag information is a second value, it means that the information field of the first structure records the address information of the second structure, and the second structure stores the address information of the last-level page table entry, and the address information of the second structure can be obtained from the information field in the first structure. Based on the address information of the second structure, the address information of the last-level page table entry corresponding to the first GPA is obtained from the information field of the second structure.

[0073] Further optionally, the information field of the first structure stores address information of the unified structure and an offset (offset, oft) of the second structure in the unified structure array. The offset oft represents the offset of the address of any GPA in the last level of page granularity in a page table at a set page table level. For example, if the page table level is set to the PMD level and the last level of page granularity is the PTE level, the offset oft represents the offset of the address of any GPA in the 4k granularity within the 2m of the PMD level. If the offset is oft3, it indicates that the address of any GPA is located in the third 4k address space within the 2m. Accordingly, obtaining the address information of the last level page table entry corresponding to the first GPA from the information field of the second structure includes: selecting the oftth element in the unified structure array (e.g., rmap_extd) based on the offset oft, the value of which is the address information of the last level page table entry corresponding to the first GPA.

[0074] Example E2 : Take the addition operation for the second GPA as an example for explanation.

[0075] Among them, the situation of adding the second GPA is not limited. For example, when the GPA is insufficient, the GPA can be increased. At this time, the increase operation of the GPA address can be triggered. In this embodiment, one or more GPAs can be added. The following description takes the addition of the second GPA as an example.

[0076] In an optional embodiment, when a second GPA is added to the EPT, address information of the last-level page table entry corresponding to the second GPA is added to the first RMAP table.

[0077] Optionally, based on the address information of the second GPA and the address space corresponding to each basic structure included in the first RMAP table, the first structure corresponding to the second GPA is determined from each basic structure; if it is determined that the address information of the last-level page table entry corresponding to the second GPA is not recorded through the first structure, indicating that the address information of the last-level page table entry corresponding to the second GPA is not recorded in the first RMAP table, then based on the relationship between the level of the last-level page table corresponding to the second GPA and the set page table level, the address information of the last-level page table entry corresponding to the second GPA is recorded through the first structure. For detailed implementation methods, please refer to the above introduction of "Recording the address information of the last-level page table entry corresponding to any GPA through the first structure based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level", which will not be repeated here.

[0078] Example E3 : Take the deletion operation on the third GPA as an example for explanation.

[0079] The situation of deleting GPA is not limited. For example, if the virtual memory needs to be reduced, some GPAs can be deleted and the conversion relationship between GPA and HPA can be deleted. The following description takes deleting the third GPA as an example.

[0080] In an optional embodiment, when the third GPA is deleted in the EPT, the address information of the last-level page table entry corresponding to the third GPA is deleted in the first RMAP table.

[0081] Optionally, based on the address information of the third GPA and the address space corresponding to each basic structure contained in the first RMAP table, the first structure corresponding to the third GPA is determined from each basic structure; if the level of the last-level page table corresponding to the third GPA is compatible with the page table level indicated by the flag information of the first structure, then based on the relationship between the level of the last-level page table corresponding to the third GPA and the set page table level, the address information of the last-level page table entry corresponding to the third GPA is deleted through the first structure.

[0082] Among them, the adaptation of the level of the last-level page table corresponding to the third GPA and the page table level indicated by the flag information of the first structure can be understood as follows: the level of the last-level page table is the same as the page table level to which the address information indicated by the flag information belongs. Among them, the flag information of the first structure is not only used to identify the type of address information stored in the information field of the first structure, but also, when the flag information identifies the address information of the last-level page table entry, the flag information can also identify the page table level to which the address information recorded in the information field of the first structure belongs, that is, the address information of which page table level the page table entry belongs. For example, when the flag information identifies the address information of the last-level page table entry, the flag information is a second value, and the second value can be X0 or X1, X1 indicates that the address information is the address information of the page table entry of the next level (such as the PTE level) of the set page table level, and X0 indicates that the address information is the address information corresponding to the page table entry of the previous level (such as the PUD level) of the set page table level.

[0083] Example E4 : Take the modification operation on the fourth GPA as an example for explanation.

[0084] The situation in which the HPA address corresponding to a GPA is modified is not limited. For example, when a memory swap operation is performed, the original HPA page corresponding to the GPA is swapped to disk, and the original HPA corresponding to the GPA can be modified to a new HPA. The following describes the modification of the fourth GPA as an example.

[0085] In an optional embodiment, when the first address information of the last level page table corresponding to the fourth GPA is modified to the second address information in the EPT, the first address information of the last level page table corresponding to the fourth GPA is modified to the second address information in the first RMAP table.

[0086] Optionally, the first structure corresponding to the fourth GPA can be determined from each basic structure based on the address information of the fourth GPA and the address space corresponding to each basic structure contained in the first RMAP table; and the first address information of the last-level page table entry corresponding to the fourth GPA can be modified to the second address information through the first structure.

[0087] Further optionally, flag information is obtained from the first structure; if the flag information is a first value, the first address information recorded in the information field in the first structure is modified to the second address information; if the flag information is a second value, the address information of the second structure is obtained from the information field in the first structure, and according to the address information of the second structure, the first address information recorded in the information field of the second structure is modified to the second address information.

[0088] Example E5 : Expand the last level page table in the EPT to obtain the next level page table. The following describes the expansion of the last level page table as an example.

[0089] In an optional embodiment, when the last-level page table is expanded to the next-level page table in the EPT, the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table is modified to the address information of the corresponding next-level page table.

[0090] Optionally, the address information recorded in each page table entry in the last-level page table (i.e., the address information of the physical page corresponding to the HPA) is cleared in the EPT, and the address information of the last-level page table entry corresponding to each GPA in the last-level page table in the first RMAP table is cleared; a next-level page table corresponding to the last-level page table is created, the address information of the next-level page table is recorded in the page table entry of the last-level page table, and the address information of the physical page corresponding to the corresponding HPA is recorded in the page table entry of the next-level page table; in the first RMAP table, according to the relationship between the level of the next-level page table and the set page table level, the address information of the next-level page table entry corresponding to each GPA in the last-level page table is recorded through the first structure.

[0091] Example E6 : Shrink the last-level page table in the EPT to obtain the previous-level page table. The following describes shrinking the last-level page table as an example.

[0092] In an optional embodiment, when the last-level page table with continuous addresses in the EPT is shrunk to the previous-level page table, the address information of the last-level page table entry is cleared in the first RMAP table, and the address information of the previous-level page table entry corresponding to each GPA in the last-level page table is added.

[0093] Optionally, the address information recorded in each page table entry in the last-level page table with continuous addresses is cleared in the EPT, and the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table is cleared; the previous-level page table corresponding to the last-level page table is created in the EPT, and the base address of the physical page corresponding to the corresponding HPA is recorded in the page table entry of the previous-level page table according to the page granularity corresponding to the previous-level page table entry; in the first RMAP table, the address information of the previous-level page table entries corresponding to each GPA in the last-level page table is recorded through the first structure according to the relationship between the level of the previous-level page table and the set page table level.

[0094] In an optional embodiment, considering that the EPT page table cannot achieve reverse conversion from HPA to GPA, and the underlying memory management mostly uses HPA as the management unit to facilitate subsequent memory management, hot and cold management, and memory swapping, a fast mapping relationship from HPA to GPA is required.

[0095] In this optional embodiment, a second RMAP table corresponding to the EPT is pre-constructed. The second RMAP table stores address translation information from at least one HPA to a corresponding GPA. The address translation information for the corresponding GPA is the base address of the GPA page to which the corresponding GPA belongs, and the size of the GPA page corresponds to the size of the HPA page. For example, the second RMAP table stores the address information of the HPA with a 2m granularity through the third structure. The GPA directly found by reverse lookup also corresponds to the 2m granularity. Other granularities such as 4k or 1G require storage in the next-level extension structure (e.g., the fourth structure). For example, if the size of the HPA page corresponding to the last-level page table entry maintained in the EPT page table is 4k, then the 4k-sized HPA page corresponds to the 4k-sized GPA page. In the second RMAP table, the 2m-granularity GPA page is recorded through the third structure. Further, by expanding the 2m-granularity GPA page, multiple 4k-granularity pages are obtained, and multiple 4k-granularity pages are recorded through the fourth structure. If the size of the HPA page corresponding to the last-level page table entry maintained in the EPT page table is 2m, then the 2m-sized HPA page corresponds to the 2m-sized GPA page. In the second In the RMAP table, the 2MB GPA page is recorded via the third structure. If the HPA page corresponding to the last-level page table entry maintained in the EPT page table is 1GB in size, then the 1GB HPA page corresponds to a 1GB GPA page. The 1GB GPA page is then split into multiple 2MB GPA pages. In the second RMAP table, each 2MB GPA page is recorded via the third structure, and the address information of the GPA huge page to which the 2MB page belongs is recorded via the fourth structure. The 512 2MB pages under the 1GB page share the address information of the same GPA huge page. In response to the second address translation trigger event, the first HPA requiring address translation is determined, and the address translation information from the first HPA to the corresponding GPA is queried in the second RMAP table. The GPA corresponding to the first HPA is obtained based on the first HPA, its address translation information to the corresponding GPA, and the address offset of the first HPA. For example, the GPA corresponding to the first HPA is obtained by adding the offset of the first HPA to the address translation information. The second address translation triggering event may be a memory mapping management event for GPA, a memory hot and cold management event, a memory swap management event, and the like.

[0096] Optionally, an embodiment of pre-building a second RMAP table corresponding to the EPT includes: dividing the HPA address space corresponding to the EPT into at least one address space, creating a base structure for each of the at least one address space, wherein the base structure corresponds to a set page granularity, which may be 4k, 2m, or 1g. For an HPA corresponding to any GPA in the EPT, a third structure corresponding to the HPA is determined from the base structures based on the address information of the HPA and the address space corresponding to each base structure. The third structure is the base structure corresponding to the HPA in the second RMAP table, and the HPA can be considered to be located in the address space corresponding to the third structure. For example, the third structure may be an rmap_head structure. Based on the relationship between the page granularity corresponding to the HPA and the set page granularity, the third structure records address translation information from the HPA to the corresponding GPA. The page granularity corresponding to the HPA is known and may be the same as or different from the set page granularity.

[0097] Further, optionally, if the page granularity corresponding to any HPA is the same as the set page granularity, address translation information from any HPA to the corresponding GPA is recorded via the information field of the third structure, and the first flag information in the third structure is set to a third value. The third value indicates that the information field of the third structure records address translation information from any HPA to the corresponding GPA. The third value can be 0 or 1, etc. If the page granularity corresponding to any HPA is the same as or different from the set page granularity, a fourth structure adapted to the page granularity corresponding to the HPA is created. The granularity of the address space corresponding to the fourth structure is the same as the page granularity corresponding to the HPA. For example, the fourth structure corresponding to a 4KB page granularity can be rmap_extd, and the fourth structure corresponding to a 1GB page granularity can be rmap_cmpt. Address translation information from any HPA to the corresponding GPA is recorded via the information field of the fourth structure, and the address information of the fourth structure is added to the information field of the third structure. The first flag information in the third structure is set to the fourth value. The fourth value indicates that the information field of the third structure records the address information of the fourth structure, and the fourth value can be 0 or 1. The third and fourth values ​​can be represented by the lower three bits of the information field of the third structure. For example, the third and fourth values ​​can be any two different values ​​between 0 and 7. Alternatively, the third and fourth values ​​can be represented by two flag bits, where a flag bit of 1 indicates that the value is valid.

[0098] Further optionally, an implementation method for creating a fourth structure adapted to the page granularity of any HPA includes: when the page granularity of any HPA is one level above the set page granularity, determining whether a fourth structure already exists; if not, creating a new structure adapted to the page granularity of any HPA as the fourth structure. When the page granularity of any HPA is one level below the level of the page table determined by the set page granularity, creating a new structure adapted to the level of the last level page table corresponding to any GPA as the fourth structure. A detailed description of this embodiment can be found in the implementation method for creating a second structure adapted to the level of the last level page table of any GPA, and will not be repeated here. For example, the page granularity can be: 512G, 1G, 2m, and 4k in descending order. If the page granularity of any HPA is 1G and the set page granularity is 2m, then the page granularity of any HPA is considered to be one level above the set page granularity. If the page granularity of any HPA is 4k and the set page granularity is 2m, the page granularity of any HPA is considered to be the next level below the set page granularity.

[0099] In an optional embodiment, the mapping between HPA and GPA can be a one-to-one correspondence or a one-to-many relationship, for example, one HPA corresponds to multiple GPAs. Accordingly, an implementation method for recording the address translation information from any HPA to its corresponding GPA via an information field in a third structure includes: when any HPA corresponds to multiple GPAs, creating a fifth structure, which is an extension of the third structure and is a structure for recording the address translation information from any HPA to multiple GPAs when the page granularity of any HPA is the same as the set page granularity. Adding the address information of the fifth structure to the information field in the third structure, adding the address translation information from any HPA to multiple GPAs to the fifth structure respectively, and adding a flag bit indicating a one-to-many relationship to the third structure; when any HPA corresponds to one GPA, directly adding the address translation information from any HPA to the corresponding GPA to the information field in the third structure without setting a flag bit indicating a one-to-many relationship, assuming a one-to-one relationship between HPA and GPA.

[0100] Accordingly, the address translation information from any HPA to its corresponding GPA is recorded via the information field in the fourth structure, including: when any HPA corresponds to multiple GPAs, a sixth structure is created. The sixth structure is an extension of the fourth structure and is a structure for recording the address translation information from any HPA to multiple GPAs when the page granularity of any HPA differs from the set page granularity. The address information in the sixth structure is added to the information field in the fourth structure, and the address translation information from any HPA to multiple GPAs is added to the sixth structure respectively. A flag indicating a one-to-many relationship is added to the fourth structure. When any HPA corresponds to one GPA, the address translation information from any HPA to the corresponding GPA is directly added to the information field in the fourth structure.

[0101] It should be noted that the fifth and sixth structures can be implemented as rmap_desc structures, namely, rmap_desc{unsigned long val[VAL_DESC_NR]; struct rmap_desc*more;}. Val[VAL_DESC_NR] is used to store address translation information from any HPA to multiple GPAs. Each element in the array represents address translation information from any HPA to a corresponding GPA. The *more pointer can point to the next rmap_desc. The next rmap_desc structure also includes the val[VAL_DESC_NR] array to facilitate storage of address translation information for more GPAs.

[0102] The following examples are used to illustrate the operations of adding, querying, deleting, modifying, expanding, shrinking and expanding based on the first RMAP table and the second RMAP table, but are not limited thereto.

[0103] The EPT page table is a four-level page table structure, including four types of page tables: PGD, PUD, PMD, and PTE. The last-level page table of the EPT may be at least one of PGD, PUD, PMD, and PTE. Accordingly, the last-level page table entry can be pgd_t, pud_t, pmd_t, or pte_t. The basic structure is identified by rmap_head. The unified structure at the PTE level is rmap_extd, and the address information of the last-level page table entry stored in the second structure is the element in the val[VAL_EXTD_NR] array in the unified structure. The second structure at the PUD level is rmap_cmpt.

[0104] 1. Query the HPA corresponding to the first GPA in the first RMAP table.

[0105] 1. First, based on the address information of the first GPA and the address space corresponding to each basic structure contained in the first RMAP table, determine the first structure (rmap_head) corresponding to the first GPA from each basic structure. The first RMAP table can be regarded as a large array, the elements in the large array are basic structures, and the address space corresponding to each basic structure is 2m. Therefore, based on the address information of the first GPA, the basic structure corresponding to the first GPA is selected from the large array with a granularity of 2m, and the selected basic structure is used as the first structure.

[0106] 2. Select different query methods according to the flag information of the information field (val) in the first structure rmap_head.

[0107] 1) If the flag information is the second value corresponding to rmap_cmpt, it means that the page granularity corresponding to the last level page table entry of the second GPA is 1G.

[0108] a) Parse the rmap_cmpt structure from the information field (val) of rmap_head, that is, obtain the address information of rmap_cmpt;

[0109] b) Parsing the information field in rmap_cmpt (the second structure) into a new rmap_head, where rmap_head is a general structure and the new rmap_head can be understood as the value contained in the information field of rmap_cmpt;

[0110] c) Determine whether the val value in the new rmap_head is the address information of the page table entry. For example, the flag information in the val value can be used to determine whether the val value is the address information of the page table entry. If so, based on the last-level address information of the first GPA recorded in the new rmap_head, read the base address of the physical page recorded in the address information, add the address offset of the first GPA to the base address, and generate the HPA corresponding to the first GPA. The address offset is the offset in the 1G memory page. If not, it means that the val value in the new rmap_head has a next-level extension structure, and the val value is the address information of the next-level extension structure. The next-level extension structure can be a structure corresponding to a one-to-many relationship.

[0111] 2) If the flag information is the second value corresponding to rmap_extd, it indicates that the page granularity corresponding to the last-level page table entry corresponding to the second GPA is 4k.

[0112] a) Parse the rmap_extd structure from the information field of rmap_head, that is, obtain the address information of rmap_extd;

[0113] b) According to the offset oft of the second GPA in 4k granularity in 2m, select the oftth val element in rmap_extd from the val[VAL_EXTD_NR] array, that is, the address information of the second structure;

[0114] c) Parse the oftth val element into a new rmap_head;

[0115] d) Determine whether the value val in the new rmap_head is the address information of a page table entry. If so, read the physical page base address recorded in the address information based on the last-level address information of the first GPA recorded in the new rmap_head, add the address offset of the first GPA to the base address, and generate the HPA corresponding to the first GPA. The address offset is the offset in the 4KB memory page. If not, it indicates that the value val in the new rmap_head has a next-level extension structure, and the value val is the address information of the next-level extension structure. The next-level extension structure can be a structure corresponding to a one-to-many relationship.

[0116] 3) If the flag information is the first value corresponding to rmap_head or the flag information is not set, the page granularity corresponding to the last-level page table entry is 2m, and there is no need to parse the lower structure.

[0117] a) Determine whether the value val in the new rmap_head is the address information of a page table entry. If so, the last-level address information of the first GPA recorded in the new rmap_head is read, and the base address of the physical page recorded in this address information is added to the base address of the first GPA to generate the HPA corresponding to the first GPA. The address offset is the offset within the 2M memory page. If not, it indicates that the value val in the new rmap_head has a next-level extension structure, and the value val is the address information of the next-level extension structure. The next-level extension structure can be a structure corresponding to a one-to-many relationship.

[0118] This embodiment also includes querying the GPA corresponding to the first HPA from the second RMAP table. This process is similar to the implementation of querying the HPA corresponding to the first GPA from the first RMAP table, and will not be repeated here.

[0119] In addition, since HPA and GPA are stored in a one-to-many relationship, when querying the GPA corresponding to the first HPA in the second RMAP table, a one-to-many mapping search operation can also be included. The following focuses on the differences between one-to-many and one-to-one, and the others will not be repeated.

[0120] For example, to search for the corresponding GPA for the second HPA. If the flag information in the third structure is the fourth value, and the fourth structure is rmap_cmpt, the flag information in the fourth structure rmap_cmpt indicates a one-to-many mapping relationship, and the fourth structure stores the address information of the fifth structure rmap_desc, it is necessary to loop through each val recorded in rmap_desc to determine whether val is the address information of a page table entry. If so, the val value is directly returned. If not, the val value is the address information of the next-level extension structure, and val can be obtained from the next-level extension structure.

[0121] When querying rmap_desc, all elements in the val[VAL_DESC_NR] array of rmap_desc can be obtained, and the corresponding GPA can be calculated based on the address conversion information of the GPA recorded in each element and the offset of the first HPA. Of course, it is also possible to return a certain element in the array according to the set filtering conditions, add the address conversion information of the GPA recorded in the element to the offset of the first HPA, and obtain the GPA corresponding to the first HPA. If the length of val[VAL_DESC_NR] is 5, it means that the array can store 5 elements. The array is connected to the subsequent array through the *more pointer. To obtain the 13th element of the array, the more pointer in the first rmap_desc can be used to obtain the address information of the second rmap_desc. Based on the address information of the second rmap_desc, the address information of the third rmap_desc pointed to by the more pointer in the second rmap_desc is determined, and the address information of the third rmap_desc is determined based on the address information of the third rmap_desc. Get the third element of val[VAL_DESC_NR] in the third rmap_desc. This third element is the address translation information of the GPA corresponding to the first HPA. Adding this to the address offset of the first HPA yields the GPA corresponding to the first HPA. If the length of val[VAL_DESC_NR] is 5, to get the third element of the array, directly get the third element of val[VAL_DESC_NR] in the first rmap_desc. This is the address translation information of the GPA corresponding to the first HPA. Adding this address translation information to the address offset of the first HPA yields the GPA corresponding to the first HPA.

[0122] 2. Add the HPA corresponding to the second GPA to the first RMAP table.

[0123] 1. First, based on the address information of the second GPA and the address space corresponding to each basic structure contained in the first RMAP table, determine the first structure (rmap_head) corresponding to the second GPA from each basic structure. The first RMAP table can be regarded as a large array, the elements in the large array are basic structures, and the address space corresponding to each basic structure is 2m. Therefore, based on the address information of the second GPA, the basic structure corresponding to the second GPA is selected from the large array with a granularity of 2m, and the selected basic structure is used as the first structure.

[0124] 2. Determine the page table level of the last level page table of the second GPA; obtain the flag information of the first structure, determine whether the address information stored in the information field of the first structure indicated by the flag information corresponds to a structure at the page table level; if so, it is considered that a structure at the page table level already exists; if not, it is considered that a structure corresponding to the page table level does not exist, and a structure corresponding to the page table level is created. For example, if the page table level is PUD level, but the flag information of the first structure is not set to the value corresponding to rmap_cmpt, then an rmap_cmpt structure is allocated and the rmap_cmpt structure is written into the information field of the first structure.

[0125] 3. Determine whether the address information of the last level page table entry corresponding to the second GPA exists in the structure corresponding to the page table level. If it exists, return the address information directly;

[0126] 4. If it does not exist, add HPA to the second GPA. At this time, different adding methods can be selected according to the flag information of the information field (val) in the first structure head rmap.

[0127] 1) If the flag information is the second value corresponding to rmap_cmpt, it means that the page granularity corresponding to the last level page table entry of the second GPA is 1G.

[0128] It should be noted that when establishing a 1GB granularity mapping for a GPA for the first time, an rmap_cmpt structure can be requested. The address information of the HPA aligned with the 1GB GPA can be recorded in the rmap_cmpt structure, and the count can be increased. The address information of the 512 rmap_heads contained in the 1GB memory page can be associated with the rmap_cmpt structure. That is, the address information of the rmap_cmp can be recorded in the information field of each rmap_head. When mapping other GPAs in the 1GB memory page is established later, the mapping count can be increased in the rmap_cmpt structure.

[0129] 2) If the flag information is the second value corresponding to rmap_extd, it indicates that the page granularity corresponding to the last-level page table entry corresponding to the second GPA is 4k.

[0130] a) Parse the rmap_extd structure from the information field of rmap_head, that is, obtain the address information of rmap_extd;

[0131] b) According to the offset oft of the second GPA in 4k granularity in 2m, select the oftth val element in rmap_extd from the val[VAL_EXTD_NR] array, that is, the address information of the second structure;

[0132] c) Parse the oftth val element into a new rmap_head;

[0133] d) Add the map value (ie, the address information of the pte_t page table entry) to the new rmap_head, that is, add the address information of the pte_t page table entry to the information field of the second structure.

[0134] e) Added mapping count num in rmap_extd structure.

[0135] 3) If the flag information is the first value corresponding to rmap_head or the flag information is not set, the page granularity corresponding to the last-level page table entry is 2m, and there is no need to parse the lower-level structure.

[0136] a) Add the map value directly to the information field of rmap_head, that is, the address information of the last level page table entry (pmd_t).

[0137] This embodiment also includes adding the GPA corresponding to the second HPA to the second RMAP table. This process is similar to the implementation of adding the HPA corresponding to the second GPA to the first RMAP table, and will not be repeated here.

[0138] In addition, since HPA and GPA are stored in a one-to-many manner, when the GPA corresponding to the second HPA is added to the second RMAP table, an addition operation of a one-to-many mapping may also be included. The following focuses on the differences between "one-to-many" and "one-to-one", and the others will not be repeated.

[0139] The address conversion information from the second HPA to the corresponding GPA recorded in the third structure is taken as an example for description, wherein the implementation manner of recording the address conversion information corresponding to the GPA in the fourth structure is the same or similar and is not repeated here.

[0140] If the address translation information corresponding to the GPA is added to the third structure for the first time, the address translation information corresponding to the GPA of the second HPA is directly recorded in the information field of the third structure.

[0141] If the second HPA corresponds to multiple GPAs, determine whether the flag information in the third structure contains a "one-to-many" flag. If no flag information is present, indicating the first expansion of the third structure, a fifth structure (rmap_desc) can be allocated. The rmap_desc structure includes: val[VAL_DESC_NR]. This array can be initialized to a special value, as long as the special value is not used as address information. For example, ffffffff, where f represents the maximum hexadecimal number, i.e., 15, and ffffffff represents the last address in the 4GB memory space. The address translation information of the GPA recorded in the third structure is recorded in the first element of val[VAL_DESC_NR]. The address translation information of the GPA to be added is recorded in the second element of val[VAL_DESC_NR]. The address information of the rmap_desc structure is recorded in the information field of the third structure, and a flag indicating a one-to-many relationship is added to the third structure.

[0142] If the third structure contains flag information, indicating that it has been extended at least once, the system first searches rmap_desc for an unused, unrecorded location. If so, it selects that location and records the map value, i.e., the address translation information for the second HPA corresponding to the GPA. If the recorded location is not found in rmap_desc, a new rmap_desc is allocated and attached to the more pointer of the last rmap_desc. Then, an unused location is selected from the array of the newly allocated rmap_desc to record the map value, i.e., the address translation information for the second HPA corresponding to the GPA.

[0143] 3. Delete the HPA corresponding to the third GPA from the first RMAP table.

[0144] 1. First, based on the address information of the second GPA and the address space corresponding to each basic structure contained in the first RMAP table, determine the first structure (rmap_head) corresponding to the second GPA from each basic structure. The first RMAP table can be regarded as a large array, the elements in the large array are basic structures, and the address space corresponding to each basic structure is 2m. Therefore, based on the address information of the second GPA, the basic structure corresponding to the second GPA is selected from the large array with a granularity of 2m, and the selected basic structure is used as the first structure.

[0145] 2. Determine the page table level of the last page table of the second GPA; obtain the flag information of the first structure, and determine whether the address information stored in the information field of the first structure indicated by the flag information of the first structure corresponds to a structure at the page table level. If so, it is assumed that a structure at the page table level already exists, and step 3 is executed. If not, it is assumed that there is no structure corresponding to the page table level, and there is no HPA corresponding to the third GPA, and an error is returned. For example, if the page table level is PUD level, but the flag information of the first structure is not set to the value corresponding to rmap_cmpt, an error is returned.

[0146] 3. Select different deletion methods according to the flag information of the information field (val) in the first structure rmap_head.

[0147] 1) If the flag information is the second value corresponding to rmap_cmpt, it means that the page granularity corresponding to the last level page table entry of the second GPA is 1G.

[0148] a) Parse the rmap_cmpt structure from the information field (val) of rmap_head, that is, obtain the address information of rmap_cmpt;

[0149] b) Parse the information field in the rmap_cmpt structure into a new head_rmap;

[0150] c) Delete the map value, i.e. the address information of pud_t, from the new rmap_head;

[0151] d) Decrement the mapping count num in the rmap_cmpt structure;

[0152] e) If the mapping count num becomes 0, the rmap_cmpt structure is released.

[0153] It should be noted that when the rmap_cmpt structure is released, the rmap_cmpt structure corresponds to a 1G memory page. The val values ​​in the rmap_head corresponding to the 512 2M memory pages under the 1G memory page respectively store the address information of the rmap_cmpt structure. If the rmap_cmpt structure is released, the val values ​​in each rmap_head can be cleared.

[0154] 2) If the flag information is the second value corresponding to rmap_extd, it indicates that the page granularity corresponding to the last-level page table entry corresponding to the second GPA is 4k.

[0155] a) Parse the rmap_extd structure from the information field of head_rmap, that is, obtain the address information of rmap_extd;

[0156] b) According to the offset oft of the second GPA in 4k granularity in 2m, select the oftth val element in rmap_extd from the val[VAL_EXTD_NR] array, that is, the address information of the second structure;

[0157] c) Parse the oftth val element into a new rmap_head;

[0158] d) Delete the map value, that is, the address information of pte_t, from the new rmap_head, and reduce the mapping count by 1. When the count is 0, release the rmap_extd structure. At the same time, the mapping in the rmap_head of the upper layer must also be cleared, that is, the address information of rmap_extd recorded in the val of rmap_head is cleared.

[0159] 3) If the flag information is the first value corresponding to rmap_head or the flag information is not set, the page granularity corresponding to the last-level page table entry is 2m, and there is no need to parse the lower-level structure.

[0160] a) Delete the map value recorded in the information field in rmap_head. The map value is the address information of pmd_t.

[0161] This embodiment also includes deleting the GPA corresponding to the third HPA from the second RMAP table. This process is similar to the implementation of deleting the HPA corresponding to the third GPA from the first RMAP table, and will not be repeated here.

[0162] In addition, since HPA and GPA are stored in a one-to-many relationship, when the GPA corresponding to the third HPA is deleted in the second RMAP table, an addition operation of a one-to-many mapping may also be included. The following focuses on the differences between "one-to-many" and "one-to-one", and the others will not be repeated.

[0163] Deleting the address translation information from the third HPA to the corresponding GPA in the third structure is taken as an example for description, wherein the implementation method of deleting the address translation information from the corresponding GPA in the fourth structure is the same or similar and is not repeated here.

[0164] If the third HPA corresponds to multiple GPAs, the address information of the rmap_desc structure is obtained from the information field of the third structure, and each element recorded in the rmap_desc structure is looped to determine whether the address conversion information from the third HPA to the corresponding GPA needs to be deleted;

[0165] If the address translation information from the third HPA to the corresponding GPA to be deleted (hereinafter referred to as map value) is found and the rmap_desc structure exists, first search for the position j where the last map value exists in rmap_desc;

[0166] Replace the value of the last position j with the position i to be deleted, and delete the value of position j; if j is not 0 at this time, return; if j is 0, it indicates that the entire rmap_desc is empty and the rmap_desc can be deleted; if there is a previous rmap_desc, update the rmap_desc information mounted under the more of the current rmap_desc to the more linked list of the previous rmap_desc; if there is no previous rmap_desc, associate the value of val in rmap_head with the rmap_desc pointed to by the more of the current rmap_desc.

[0167] 4. In the first RMAP table, the first address information of the last level page table corresponding to the fourth GPA is modified to the second address information. In the second RMAP table, the first address translation information of the GPA corresponding to the fourth HPA is modified to the second address translation information. This is explained using the example of the last level page table being the PMD level.

[0168] 1. Clear the original PMD-level HPA-GPA mapping, that is, clear the first address translation information of the GPA corresponding to the fourth HPA recorded in the second RMAP table;

[0169] 2. Create a new PMD-level page table mapping in the EPT and record the physical page corresponding to the new HPA in the PMD-level page table entry;

[0170] 3. At the same time, a new HPA-GPA mapping of the PMD level is established, that is, the second address translation information of the GPA corresponding to the fourth HPA is recorded in the second RMAP table;

[0171] 4. Refresh the EPT page table to make the changes take effect.

[0172] During subsequent operation of the host machine, operations such as expansion, contraction, and update of the page table may be performed. At this time, when the EPT is updated, the first RMAP table and the second RMAP table may be updated synchronously.

[0173] 5. When the last-level page table is extended to the next-level page table in the EPT, the address information of the last-level page table entries corresponding to each GPA in the last-level page table is modified to the address information of the corresponding next-level page table in the first RMAP table.

[0174] The following takes the expansion of the EPT page table at the PMD level to the PTE level as an example for explanation.

[0175] 1. Determine whether the EPT page table needs to be expanded, that is, whether the EPT page table is already at the PTE level; if so, return directly; otherwise, continue;

[0176] 2. Allocate a page EPTP to record the page table of the next level PTE level. EPTP stands for EPT page table pointer (extended-page-table pointer). EPTP is the field that stores the physical address of the EPT page table.

[0177] 3. Clean up the previous PMD-level page table mapping, including cleaning up the address information of the physical pages recorded in the original PMD page table;

[0178] 4. Clear the GPA_HPA mapping (also known as GPA_EPT mapping) and HPA_GPA mapping in the original first RMAP table;

[0179] 5. Establish a corresponding mapping relationship for each PTE-level page table in the next level (that is, write the base address of the physical page in each PTE-level page table entry), and record the address information of the PTE-level page table entry into the allocated page EPTP;

[0180] 6. During the creation of each PTE-level page entry, new GPA_HPA mapping and HPA_GPA mapping are also created synchronously to obtain the expanded first RMAP table and second RMAP table respectively.

[0181] 7. Finally, associate the newly allocated page EPTP with the original PMD level page table entry;

[0182] 8. Refresh the EPT page table to make the update take effect.

[0183] 6. When the last-level page table with continuous addresses in the EPT is shrunk to the previous-level page table, the address information of the last-level page table entry corresponding to each GPA in the last-level page table is modified to the address information of the previous-level page table entry in the first RMAP table.

[0184] The following takes shrinking a PTE page table into a PMD page table as an example for explanation.

[0185] 1. Determine whether the EPT page table needs to be shrunk, that is, whether the EPT page table is already at the PMD level; if so, return directly; otherwise, continue;

[0186] 2. Determine whether the next-level PTE page table can be shrunk, that is, the mapping relationship of the next-level PTE page table is all empty, or the record is a continuous HPA range, and the first HPA address is PMD-level aligned;

[0187] 3. Clean up the corresponding mapping relationship for each PTE level page table in the next level, such as cleaning up the base address of the physical page recorded in each page table entry in the PTE page table;

[0188] 4. During the cleaning of each PTE-level page entry, the old GPA_EPT mapping and HPA_GPA mapping will also be cleaned up synchronously, that is, the corresponding mapping relationships in the first RMAP table and the second RMAP table will be cleaned up;

[0189] 5. Create a new PMD-level page table mapping, record the HPA mapping information in the EPT page table entry, and disassociate the original lower-level PTE page table;

[0190] 6. At the same time, new PMD-level RMAP table information must be established, including the mapping of GPA_EPT and HPA_GPA;

[0191] 7. Refresh the EPT page table to make the update take effect;

[0192] 8. Release the page that originally recorded the PTE level page table.

[0193] 7. It may also include: cleaning up the page table entries at the set page table level, such as updating the HPA_GPA mapping when the page is swapped out;

[0194] The following takes clearing PMD-level page table entries as an example to illustrate.

[0195] 1. Clean up the original PMD level HPA_GPA mapping;

[0196] 2. Clear the old PMD-level page table mapping recorded in the PMD-level page table entry;

[0197] 3. Refresh the EPT page table to make the update take effect.

[0198] In addition to providing the above-mentioned address conversion method, this embodiment also provides a method for constructing a fast mapping table. Figure 1b As shown, the method includes:

[0199] R21. Divide the GPA address space corresponding to the EPT into at least one address space, and create a basic structure for each of the at least one address space. The basic structure corresponds to a set page table level. The EPT includes a multi-level page table corresponding to each of the at least one GPAs.

[0200] R22. For any GPA in the EPT, determine the first structure corresponding to the GPA from the basic structures based on the address information of the GPA and the address space corresponding to the basic structures.

[0201] R23. According to the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, the address information of the last-level page table entry corresponding to any GPA is recorded through the first structure to construct a first RMAP table corresponding to the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to at least one GPA.

[0202] Regarding the embodiments of this application Figure 1a and Figure 1b The detailed implementation and beneficial effects of each step in the method have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0203] In addition to the above method, the embodiments of the present application also include an introduction to the virtualization layer as follows:

[0204] In the embodiments of this application, Figure 2a As shown, the host machine includes hardware resources, on which a host operating system (host OS) runs, and on which various application programs run; relative to the hardware resources, the host operating system and application programs belong to the software resources of the host machine. The host operating system is the most basic system software in the host machine. It is responsible for controlling and managing the hardware resources and software resources of the entire host machine, and can reasonably schedule the work and resource allocation of the host machine, and can provide a convenient interface and environment for users and other software or devices. Among them, the host operating system can provide various system-level functions, such as file management, memory management, various input / output (IO) device management, etc. Based on these system functions, the host operating system can provide the application with various resources required during operation to support the operation of the application.

[0205] Among these system functions, at least some of them need to be configured when installing the host operating system, such as whether to enable them, which mode to enable them, and so on. System functions that are not enabled will not be available during the operation of the host operating system. Since the system functions cannot be used, applications that rely on the system functions will run abnormally or fail to run because they cannot obtain the resources provided by the system functions. However, as the host operating system runs and application requirements change, it may be necessary to use these unenabled system functions, or upgrade the enabled system functions, that is, the host operating system faces the problem of capacity expansion. For traditional hosts, either the host operating system must be reinstalled, or some system functions must be forcibly enabled online. Reinstalling the host operating system requires interrupting the operation of all applications, which is inefficient and costly; forcing the corresponding system functions online will seriously affect the stability of the system.

[0206] In an embodiment of the present application, in order to solve the capacity expansion problem faced by the host operating system without reinstalling the host operating system and without affecting the operating performance of the host operating system, a new physical machine architecture is provided, which provides two operating modes for the host operating system in a running state, namely root mode and non-root mode, inserts a virtualization layer between the hardware resources and the host operating system, implements the virtual resource provision function at least in the virtualization layer, and switches the running host operating system from root mode to non-root mode by the virtualization layer, provides at least one virtual resource in the non-root mode and runs at least an application that the host operating system cannot run in the root mode due to insufficient resources on the virtual resource, without reinstalling the operating system, and can flexibly implement the virtual resource provision function for the running host operating system, thereby solving the problem that the application cannot run due to insufficient resources due to reasons such as the failure to enable or lack of system functions, supporting the operation of more applications, and helping to expand the capabilities of the host operating system.

[0207] For example, assuming that the host operating system supports function A, function B, function C, and function D, etc., when the host operating system is installed, function A, function B, and function C are enabled, function D is not enabled, and function E is missing (i.e., the host operating system does not support function E). Using the physical machine provided in the embodiment of the present application, a virtualization layer is inserted between the hardware resources and the host operating system, and the function of providing virtual resources is implemented at least in the virtualization layer. For example, if the host operating system does not enable function D and lacks function E, the virtualization layer switches the host operating system from root mode to non-root mode, and provides virtual resources corresponding to function D and function E in non-root mode. Applications that were originally unable to run due to the non-enabling of function D and the lack of function E are run on the virtual resources. Without reinstalling the host operating system, the function of providing virtual resources can be flexibly implemented for the running host operating system, solving the problem of the corresponding application being unable to run due to the non-enabling of function D and the lack of function E, which is conducive to expanding the capabilities of the host operating system. Furthermore, in order to compensate for the deficiencies of the host operating system, virtual resources corresponding to function D and function E can be provided preferentially in non-root mode to solve the operation problems of applications that depend on function D and function E; of course, for the compatibility of the host operating system and to avoid frequent mode switching, virtual resources corresponding to function A, function B and function C can also be provided in non-root mode to facilitate the running of corresponding applications that depend on function A, function B and function C on these resources.

[0208] It should be noted that in the embodiments of this application, the focus is on the process of switching the host operating system between the two modes. There are no restrictions on which system functions the virtual resources corresponding to, and how the virtual resources corresponding to, these system functions are provided in non-root mode. The following, combined with the accompanying drawings, details the physical machine architecture provided in the embodiments of this application and the process of switching the host operating system from root mode to non-root mode.

[0209] Figure 2b This is a schematic diagram of the structure of a physical machine provided by an exemplary embodiment of the present application. Figure 2b As shown, the physical machine includes hardware resources 10 and a host operating system 20 running on the hardware resources, with a virtualization layer 30 implemented between the hardware resources 10 and the host operating system 20. Furthermore, an application layer 40 is included above the host operating system 20. The application layer 40 includes various application programs.

[0210] Optionally, hardware resources 10 include at least one physical computing resource object 101 and a physical storage medium 102, with physical storage medium 102 providing a physical address space. In addition, hardware resources 10 on a physical machine may also include other components, not shown, such as I / O devices, communication components, a display, a power supply component, and an audio component.

[0211] The physical computing resource object 101 may be a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a tensor processing unit (TPU), a cloud infrastructure processing unit (CIPU), an application-specific integrated circuit (ASIC), or any other physical resource object with computing capabilities. The host operating system 20 may run on at least one physical computing resource object 101.

[0212] The physical storage medium 102 includes permanent and non-permanent, removable and non-removable media and can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules or other data. The physical storage medium 102 includes, but is not limited to: phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0213] Physical memory refers to the memory chips or modules actually present in a physical machine, used to store data and program code. Physical memory may include non-permanent memory in the physical storage medium 102, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash RAM.

[0214] The physical address space is the address range corresponding to physical memory. It is typically related to the hardware architecture and the host operating system, and describes the physical location and size of the actual memory banks. In virtual memory systems, the physical address space also involves mechanisms such as the memory page table, which is used to map guest physical addresses to host physical addresses.

[0215] In this embodiment, the host operating system 20 corresponds to a root mode and a non-root mode. Root mode is an operating mode in which the host operating system 20 has direct access to the hardware resources 10. Non-root mode is an operating mode in which the virtualization layer 30 virtualizes the hardware resources 10 and schedules and accesses the virtualized resources on behalf of the host operating system 20. In non-root mode, the virtualization layer 30 has limited access to the hardware resources 10. Accordingly, the host operating system 20 in non-root mode can also be referred to as a client operating system.

[0216] In this embodiment, a lightweight, powerful, and efficient virtualization layer 30 is inserted between the hardware resources 10 and the host operating system 20. The virtualization layer 30 can be pre-developed and inserted between the hardware resources 10 and the host operating system 20. The method for inserting the virtualization layer 30 is not limited. For example, the virtualization layer 30 can be inserted after the host operating system 20 is installed on the physical machine and the host operating system 20 is in normal operation.

[0217] Among them, the virtualization layer 30 has the ability to provide virtual resources, and can at least provide virtual resources corresponding to the resources that the host operating system 20 cannot provide in root mode due to unactivated or missing system functions. That is to say, the resources that the host operating system 20 cannot provide in root mode due to unactivated or missing system functions can be provided with corresponding virtual resources by the virtualization layer 30, so as to run the corresponding applications. Specifically, the virtualization layer 30 can switch the running host operating system 20 from root mode to non-root mode, and provide at least one virtual resource in non-root mode, and run at least one application on at least one virtual resource. Without reinstalling the operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, solving the problem that the host operating system 20 cannot provide corresponding resources to run corresponding applications in root mode due to unactivated or missing system functions. It can support the operation of more applications and is conducive to expanding the capabilities of the host operating system. Furthermore, for the sake of compatibility with the host operating system, in order to reduce the frequent mode switching of the host operating system, in non-root mode, not only can corresponding virtual resources be provided for system functions that are not enabled or missing in the root mode of the host operating system 20, but corresponding virtual resources can also be provided for system functions that are enabled in the root mode of the host operating system 20, thereby supporting more functions of the host operating system 20.

[0218] For example, at least one target function implemented in the virtualization layer 30 includes but is not limited to: memory management function, file management function, virtualization function, scheduling optimization function, etc. The memory management function, file management function, scheduling optimization function, etc. here can be a newly expanded function that is not originally supported by the host operating system, or a function that is originally supported by the host operating system but is not enabled during the installation of the host operating system. Regardless of whether it is a newly expanded function or an unenabled function, the memory management function specifically includes but is not limited to: memory page fault management, memory swap management, memory mapping management, etc.; the file management function specifically includes but is not limited to: directory management, permission management, file backup, creation, query, deletion, modification, etc.; the virtualization function includes but is not limited to: virtualization of various elastic resources (such as CPU, GPU, memory, network, etc.); the scheduling and tuning function includes but is not limited to: scheduling of physical computing resource objects and scheduling of various virtualized resources, etc.

[0219] further, Figure 2b The figure shows the overall architecture of the physical machine. Figure 2b As shown, Figure 2c and Figure 2d The internal architecture of a physical machine operating in root mode and non-root mode is shown. Before the mode switch is performed, the host operating system operates in root mode. In this root mode, Figure 2cAs shown, the internal architecture of the running physical machine is hardware resources 10, host operating system 20 and application layer 40 from bottom to top; after the mode is switched, it works in non-root mode. In this non-root mode, as shown in FIG. Figure 2d As shown, the architecture of the running physical machine is hardware resources 10, virtualization layer 30, client operating system and application layer 40 from bottom to top. Among them, the client operating system is the name of the host operating system 20 running in non-root mode.

[0220] In an embodiment of the present application, two operating modes are provided for a host operating system in a running state, namely a root mode and a non-root mode. A virtualization layer is inserted between the hardware resources and the host operating system, and at least the virtualization layer implements the virtual resource provision function. The virtualization layer switches the running host operating system from root mode to non-root mode, provides virtual resources in the non-root mode, and runs at least applications on the virtual resources that the host operating system cannot run in the root mode due to insufficient resources. Without reinstalling the host operating system, the virtual resource provision function can be flexibly implemented for the running host operating system to support the operation of more applications and expand the capabilities of the host operating system.

[0221] It is explained here that, from the perspective of program code, the implementation codes such as "the function of providing virtual resources" and "switching from root mode to non-root mode" involved in the embodiments of the present application belong to the virtualization layer 30, and these codes are located under the host operating system; however, from the perspective of the running state, before the mode switching is actually completed, at least part of the program code in the virtualization layer 30 is executed during the operation of the host operating system. In other words, at least part of the program code in the virtualization layer 30 is executed in root mode, wherein the program code executed in the root mode in the virtualization layer 30 at least includes: program code for switching from root mode to non-root mode, such as the upper half of the switching function mentioned in the following embodiments. Accordingly, after the mode switching is actually completed, part of the program code will be executed in non-root mode, such as the lower half of the switching function mentioned in the following embodiments. In addition, the program code responsible for providing virtual resources in the virtualization layer 30 also runs in root mode, but this part of the code is run after the switch is completed; the virtualization layer 30 also provides some interface codes to the outside world, some of which will run in non-root mode, and some need to be switched to root mode to run, depending on the function of the interface code.

[0222] In an alternative embodiment, if Figure 3a As shown, the virtualization layer 30 switches the running host operating system from root mode to non-root mode, which includes three parts:

[0223] S1. Create a memory page table to store the mapping relationship between the client physical address in non-root mode and the host physical address in root mode;

[0224] S2. Create an information-carrying object required for mode switching. The information-carrying object is used to synchronize context information between the root mode and the non-root mode.

[0225] S3. Based on the information carrying object and the memory page table, the running host operating system is switched from the root mode to the non-root mode.

[0226] The following describes the detailed implementation of the above three parts.

[0227] Step S1: Create a memory page table

[0228] In root mode, the physical address space has a host physical address, which can be represented by HPA (Host Physical Address). The host physical address is the address of the physical memory in the physical memory resource. In non-root mode, the physical address space corresponds to a virtual address space. The virtual address space has a client physical address, which can be represented by GPA (Guest Physical Address). The client physical address is the address of the virtual memory in the virtual memory resource.

[0229] In this embodiment, the virtualization layer 30 can create a memory page table, which is used to store the mapping relationship between the client physical address in non-root mode and the host physical address in root mode. The memory page table can be represented by EPT (Extended Page Tables). It should be noted that when the memory page table is initially established, since the host operating system has not yet run in non-root mode and has not performed operations such as memory recycling or memory swapping, the client physical address in non-root mode is the same as the host physical address in root mode. Subsequently, as the host operating system is used in non-root mode, for example, memory recycling or memory swapping, the client physical address may no longer be equal to the host physical address, and the memory page table can dynamically maintain the mapping relationship between the client physical address and the host physical address.

[0230] In an alternative embodiment, if Figure 3b As shown, the process of creating a memory page table includes: S11, establishing a page table structure corresponding to the memory page table; S12, applying for the root page of the memory page table from the physical address space; S13, generating the entry address of the memory page table according to the host physical address of the root page, and adding it to the page table structure; S14, creating a multi-level memory page table according to the address range of the physical address space and the page granularity used to map the client physical address to the host physical address.

[0231] First, a page table structure is created. This structure stores various information related to the memory page table, such as the memory page table entry address, the address lock array used to operate the memory page table, and the address of a special Advanced Programmable Interrupt Controller (APIC) page. The memory page table entry address is used to access the memory page table. For example, the entry address can be the first address of the memory page table. Each entry in the address lock array corresponds to a page table entry and contains a lock flag that indicates whether the entry is locked. If it is not locked, the process can access the memory space corresponding to the page table entry. The address of the special APIC page is mainly used to access the special APIC page. After creating the page table structure, a physical page is requested from the physical address space provided by the physical storage medium as the root page of the memory page table. The memory page table entry address is generated based on the host physical address of the root page and added to the page table structure. The format of the memory page table entry address varies depending on the type of physical computing resource object and its manufacturer. For example, the host physical address of the root page can be directly used as the entry address of the memory page table. For another example, the host physical address of the root page plus a set offset or flag bit can be used as the entry address of the memory page table, which is not limited to this.

[0232] The physical address space has an address range. For example, the address range of the physical address space can be 0-8G or 0-16G, etc. In addition, in this embodiment, in non-root mode, the single page granularity supported by the host operating system can be broken, allowing the page granularity for address mapping to be set as needed. For example, the page granularity for address mapping can include but is not limited to: 4K (Kilobyte), 2M (Megabyte), or 1G (Gigabyte). In view of this, in an optional embodiment, the virtualization layer 30 can create a multi-level memory page table based on the address range of the physical address space and the page granularity used to map the client physical address to the host physical address. The multi-level memory page table can be a 2-level memory page table, a 4-level memory page table, or a 5-level memory page table, etc., depending on the address range and page granularity of the physical address space. For example, for the same address range, the smaller the page granularity, the more memory page table levels are required; for another example, for the same page granularity, the larger the address range, the more memory page table levels are required.

[0233] Optionally, in this embodiment, the physical address space is divided into a first address space and a second address space. The second address space is larger than the first address space, that is, the address size of the second address space is larger than the address size of the first address space. For example, if the physical address space is 8GB, the address range of the physical address space can be divided into 0GB-4GB and 4GB-8GB. The first address space can be the address space corresponding to 0GB-4GB, and the second address space can be the address space above 4GB. For another example, if the physical address space is 16GB, the physical address space can be divided into 0GB-4GB and 4GB-16GB. The first address space can be the address space corresponding to 0GB-4GB, and the second address space can be the address space above 4GB. Based on this, when creating a multi-level memory page table, corresponding multi-level memory page tables can be created for the first address space and the second address space respectively. The first address space is primarily used as a memory address space, and the second address space can at least be used as an I / O address space. The memory address space is used to describe the storage location of programs and data in memory, and the I / O address space is used to describe the address range of the physical machine's I / O devices. For example, the physical address space is usually divided into several different address ranges. The address space with an address range of 0-4GB is called the first address space, and the address space with an address range of more than 4GB is called the second address space. The first address space is usually called "basic memory" or "system memory", which includes the memory used by the host operating system, applications and basic hardware drivers, that is, the first address space is mainly used as a memory address space. The second address space is usually called "mass memory" or "extended memory". This memory capacity is usually used in high-performance computers, servers, workstations and other devices to support more complex computing tasks and multi-tasking. For example, the second address space can at least be used as an IO address space.

[0234] Among them, for the first address space, a first mapping relationship between the client physical address and the host physical address is formed at a first page granularity, that is, the client physical address and the host physical address are mapped according to the page size of the first page granularity, and a multi-level memory page table corresponding to the first address space is created according to the first mapping relationship; for the IO address space in the second address space, a second mapping relationship between the client physical address and the host physical address is formed at a second page granularity, that is, the client physical address and the host physical address are mapped according to the page size of the second page granularity, and a multi-level memory page table corresponding to the IO address space is created according to the second mapping relationship; the second page granularity is larger than the first page granularity, for example, the first page granularity is 2M and the second page granularity is 1G. Among them, using the first page granularity (small page granularity) for memory mapping can reduce internal fragmentation in memory pages, reduce memory waste, reduce the loss of page table entries in the cache, and improve address conversion efficiency; using the second page granularity (large page granularity) for memory mapping can reduce page table entry data, reduce the level of memory page tables, reduce memory management overhead, and improve the performance of physical computing resource objects.

[0235] Further, optionally, the second address space can also be used as a memory address space. Based on this, the virtualization layer 30 can also form a third mapping relationship between the client physical address and the host physical address at a third page granularity for the memory address space in the second address space. That is, the client physical address and the host physical address are mapped according to the page size of the third page granularity, and a multi-level memory page table corresponding to the memory address space is created based on the third mapping relationship; wherein the third page granularity is smaller than the second page granularity, but the size of the third page granularity is not limited.

[0236] In an optional embodiment, the third page granularity can be equal to the first page granularity. For example, the first page granularity and the third page granularity are both 2M. That is to say, for the memory address space, a smaller page granularity can be used for address space mapping, and for the IO address space, a larger page granularity can be used for address space mapping. The physical address space can be reasonably utilized to improve the performance of memory management.

[0237] Further optionally, in some application scenarios, the memory address space in the second address space includes an APIC page, and the APIC page uses a smaller page granularity, such as the fourth page granularity, and the third page granularity is larger than the fourth page granularity. For example, the third page granularity is 2M, and the fourth page granularity is 4K.

[0238] When the memory address space in the second address space contains an APIC page of a fourth page granularity, it means that the APIC page of the fourth page granularity belongs to a physical page of a third page granularity. The physical page of the third page granularity to which the APIC page of the fourth page granularity belongs is referred to as the first physical page. Then, the first physical page of the third page granularity to which the APIC page belongs and the target memory page table corresponding to the first physical page can be obtained, wherein the target memory page table corresponding to the first physical page is the last level page table in the multi-level memory page table, and the page table entry in the page table points to the address space in the first physical page; in order to adapt to the page granularity of the APIC page, the first physical page can be split into multiple sub-pages of a fourth page granularity, and the next level memory page table is further extended below the target memory page table, that is, the next level memory page table is added under the target memory page table, and the next level memory page table is used to store the host physical addresses of the multiple split sub-pages. For example, the host physical address corresponding to a sub-page is stored in each page table entry of the next level memory page table, and the host physical address is the first address of the sub-page.

[0239] In this embodiment, when creating a memory page table, a mixed mapping granularity method combining the first page granularity, the second page granularity, the third page granularity and the fourth page granularity is adopted, which not only supports small page granularity but also supports large page granularity, can meet the needs of different physical page mappings, and improve the flexibility of memory mapping.

[0240] Furthermore, in the non-root mode provided in the embodiment of the present application, when creating a memory page table, the physical address space of the host machine is no longer limited, and the creation of a memory page table for the entire physical address space is allowed, that is, full memory mapping is supported. Therefore, it is possible to create a memory page table for both user-mode pages and kernel-mode pages. By supporting memory mapping of the full physical address space, a basic framework is provided for various subsequent operations based on memory mapping. For example, when performing memory swapping based on memory mapping, not only the swapping of user-mode pages but also the swapping of kernel-mode pages is supported, that is, full memory swapping is supported.

[0241] In this embodiment, taking the first page granularity of 2M, the second page granularity of 1G, the third page granularity of 2M, the fourth page granularity of 4K, and the multi-level memory page table implemented as a four-level memory page table as an example, the specific process of creating a memory page table is exemplified.

[0242] The following is an example of a four-level memory page table, which includes: Page Global Directory (PGD), Page Upper Directory (PUD), Page Middle Directory (PMD), and Page Table Entry (PTE). Among them, PGD is the highest level directory. PGD includes multiple global page directory entries pgd_t, each pgd_t can map a 512G host physical address (HPA), and pgd_t points to the next level page directory (PUD); PUD includes multiple upper page directory entries pud_t, each pud_t can map a 1G host physical address (HPA), and pud_t points to the next level page directory (PMD); PMD includes multiple intermediate page directory entries pmd_t, each pmd_t can map a 2M host physical address (HPA), and pmd_t points to the next level page directory (PTE). PTE includes multiple direct page directory entries pte_t, each pte_t can map a 4K host physical address (HPA), and each pte_t points to the corresponding physical page in the host physical address (HPA).

[0243] 1) For a first address space with an address range of 0G-4G, a first mapping relationship between a client physical address and a host physical address is formed with a page granularity of 2M, and a multi-level memory page table corresponding to the first address space is created according to the first mapping relationship.

[0244] a1. According to the client physical address (GPA) in the first address space, and according to the index value of PGD corresponding to the client physical address (GPA), determine the page table entry pgd_t in the PGD level page table, where pgd_t points to the PUD level page table.

[0245] b1. According to the flag bit in pgd_t, determine whether the PUD-level page table exists. If not, apply for a page as the PUD-level page table.

[0246] c1. If a PUD-level page table exists, determine whether the PUD-level page table needs to be expanded based on the first page granularity (e.g., 2M). Since each pud_t can map a 1GB host physical address (HPA), and 1GB is larger than the first page granularity (e.g., 2M), it is determined that the next-level PMD-level page table needs to be expanded to prepare for subsequent mapping.

[0247] d1. According to the index value of the PUD corresponding to the client physical address (GPA), the page table entry pud_t in the PUD level page table is determined. The pud_t points to the PMD level page table.

[0248] e1. According to the flag bit in the pud_t, determine whether the next-level PMD level page table exists. If not, apply for a page as the PMD level page table.

[0249] f1. Based on the first page granularity (e.g., 2M), determine whether the PMD-level page table needs to be expanded. Since each pmd_t can map a 2M host physical address (HPA), it is determined that there is no need to expand the next-level PTE-level page table.

[0250] g1. Determine the page table entry pmd_t in the PMD level page table based on the index value of the PMD corresponding to the client physical address (GPA).

[0251] h1. When the mapped page granularity is 2M, a page table entry pmd_t is directly created in the PMD-level page table. pmd_t points to the physical page of the host physical address (HPA), and the size of the physical page is 2M. Therefore, it is necessary to assemble a page table entry pmd_t for the PMD-level page table. pmd_t can include the physical page frame number (PFN) corresponding to the corresponding HPA, set the page table entry to be accessible, and set the large page flag to 1. For example, a large page can be a physical page of size 2M or 1G, and a physical page of size 4K does not belong to a large page.

[0252] i1. Fill the page table entry pmd_t of the combined PMD-level page table into the PMD-level page table, complete the mapping of the first page granularity (e.g., 2M), and record the mapping completion progress and the next client physical address that needs to be mapped, until the mapping of the first page granularity is established for the first address space.

[0253] j1. Determine whether the mapping of the first page granularity (eg, 2M) is completed. If not, return to step b. Otherwise, end.

[0254] 2) For the input / output (IO) address space in the second address space, a second mapping relationship between the client physical address and the host physical address is formed at a second page granularity, and a multi-level memory page table corresponding to the IO address space is created based on the second mapping relationship. That is, based on the address space (i.e., physical memory space and physical IO space) of the host operating system recorded in the IO memory resource (iomem_resource), a multi-level memory page table of a second page granularity (e.g., 1G granularity) is established for the IO address space in the second address space (e.g., memory address space above 4G). The process of establishing a multi-level memory page table is similar to the above-mentioned implementation method of establishing a multi-level memory page table at a first page granularity, with the difference being that: to establish a multi-level memory page table at a second page granularity (e.g., 1G granularity), it is necessary to establish pud_t in the PUD-level page table, and pud_t points to the physical page of the host physical address (HPA), and the size of the physical page is 1G.

[0255] 3) For the memory address space in the second address space, a third mapping relationship between the client physical address and the host physical address is formed at a third page granularity (e.g., 2M), and a multi-level memory page table corresponding to the memory address space is created based on the third mapping relationship; wherein the third page granularity is smaller than the second page granularity. The process of establishing the multi-level memory page table can be referred to the aforementioned implementation method of establishing the multi-level memory page table at the first page granularity, and will not be repeated here.

[0256] 4) When the memory address space includes an APIC page of a fourth page granularity, obtain a first physical page of a third page granularity to which the APIC page belongs and a target memory page table corresponding to the first physical page; split the first physical page into multiple sub-pages of a fourth page granularity, and add a next-level memory page table under the target memory page table, where the next-level memory page table is used to store the host machine physical addresses of the multiple split sub-pages.

[0257] 5) Apply for a special APIC page, the physical address of the APIC page is the client physical address.

[0258] 6) Establish a mapping between the host physical address of the APIC and the fourth page granularity (e.g., 4k granularity) of this special APIC page. The default host physical base address of the APIC (APIC_DEFAULT_PHYS_BASE) is (0xfee00000), which corresponds to the memory address space in the second memory space. This process involves splitting the already established third page granularity (e.g., 2M granularity) page. The mapping process is as follows:

[0259] a2. Execute steps a1-e1 in step 1) in sequence, and determine whether the PMD-level page table needs to be expanded based on the fourth page granularity (e.g., 4K). Since each pmd_t can map a 2M host physical address (HPA), and 2M is not equal to 4K, it is determined that the next-level PTE-level page table needs to be expanded.

[0260] b2. Based on the index value of the PTE corresponding to the client physical address (GPA), the page table entry pte_t in the PTE-level page table is determined, the contents of pte_t are combined, including the physical page frame number corresponding to the HPA, and the page table entry is set to accessible. At this time, the large page flag is not set to 1.

[0261] c2. Fill the page table entry content of the combined PTE-level page table into the corresponding pte_t to complete this mapping.

[0262] S2. Create the information-carrying object required for mode switching

[0263] In this embodiment, in order to switch the mode of the host operating system, on the one hand, a physical descriptor structure is created for any physical computing resource object 101, such as Figure 3c In some subsequent descriptions, the physical descriptor structure may be referred to as pcpu. The physical descriptor structure is used to save the context information of any physical computing resource object running in root mode when the mode is switched. The context information of any physical computing resource object in root mode may include but is not limited to: the values ​​of various registers used by any physical computing resource object, the status information of any physical computing resource object, the status information of the host machine, and related configuration information. Among them, the related configuration information includes but is not limited to: the frequency of the high voltage (HV) timer, etc.

[0264] In this embodiment, the implementation method of the physical descriptor structure is not limited. Any implementation structure that can save the context information of the physical computing resource object running in root mode is applicable to the embodiment of the present application. In an optional embodiment, the physical descriptor structure may include but is not limited to the following parts or fields: a first register structure (regs), a field that carries the status information of the physical computing resource object, a field that carries the status information of the host machine, and a field that carries configuration information. The first register structure may include but is not limited to: a general register field, a debug register field, a stack-related register field, a floating point unit (fpu) register field, a model-specific register (MSR) field, etc.

[0265] In order to switch the mode for the host operating system, on the other hand, a virtualization descriptor structure is created for any physical computing resource object, such as Figure 3c In the following description, the virtualization descriptor structure may be referred to as vcpu. The virtualization descriptor structure is used to synchronize the context information in the physical descriptor structure when switching modes. The virtualization descriptor structure represents a virtual computing resource object obtained by virtualizing the physical computing resource object.

[0266] Among them, the implementation method of the virtualization descriptor structure is not limited, and any implementation structure that can synchronize the context information in the physical computing resource object is applicable to the embodiment of the present application. In an optional embodiment, the vcpu may include but is not limited to the following fields: a second register structure (regs) corresponding to the first register structure. In addition, the vcpu also includes: a field that carries a virtual computing resource object identification instruction (such as cpu_id), a field that carries an interrupt vector number (apic_id), a field that carries the running status of the vcpu, a field that carries a switching mark for the state change during the vcpu switching process, a field that carries relevant configuration information of the APIC register, a field that carries configuration information of a specific model register (such as an MSR register), a field that carries configuration information of a processor opcode (such as CPUID), a field that carries a descriptor of an interrupt (ProgramInterruption, PI), and a field that carries configuration information related to exit events, etc.

[0267] Furthermore, in order to switch the mode of the host operating system, a virtualization control structure is created for any physical computing resource object, such as Figure 3cStep S23 in the process. For example, the virtualization control structure can be implemented as vmcs (Virtual Machine Control System), and the virtualization control structure is used to save the running state information and running control information of any physical computing resource object in non-root mode. For example, the running state information of the physical computing resource object in non-root mode can be the values ​​of some registers, as well as the state of the physical computing resource object, such as active, shutdown (HLT) or shutdown. The running control information mainly refers to the control information of the host operating system in non-root mode. For example, the running control information saved by the virtualization control structure can include but is not limited to the following fields: a field carrying the exit event of the non-root mode, a field carrying the register bitmap (msr_bitmap) of a specific processor model, a field carrying APIC virtualization, a field carrying interrupt virtualization, a field carrying a preemption timer, a field carrying a clock configuration or a field carrying IO control information, etc. The information in the corresponding fields can be configured as needed when initializing the virtualization control structure according to actual conditions.

[0268] In an optional embodiment, the virtualization layer 30 may also create an IO bitmap (io_bitmap), such as Figure 3c The IO bitmap is used to record the access rights of any physical computing resource object to each IO port in non-root mode. The access rights are related to the IO control information in the operation control information. The access rights can default to 0, which allows access to all IO ports. If you need to intercept some IO ports later, you can configure the io_bitmap as needed.

[0269] Furthermore, the virtualization layer 30 may also create a new stack, which is referred to as the first stack for ease of description and distinction. Figure 3c Step S25 in the . The new stack (i.e., the first stack) is relative to the old stack. For the convenience of description and distinction, the old stack is referred to as the second stack. The old stack (i.e., the second stack) is the stack currently used by any physical computing resource object. After switching from root mode to non-root mode, any physical computing resource object will continue to use the old stack to run in non-root mode. It is explained here that after switching from root mode to non-root mode, the physical computing resource object can be implemented as a virtual physical computing resource object. For example, the physical CPU can be implemented as a virtual CPU. The first stack is a stack prepared for the virtualization layer 30, which is used for the virtualization layer 30 to perform memory access based on the new stack (i.e., the first stack) in root mode.

[0270] In an optional embodiment, the virtualization layer 30 may also initialize the virtualization descriptor structure and the virtualization control structure respectively, such as Figure 3cThe initialization process is the process of enabling the required functions, applying for memory pages for the required functions, and configuring initial values. The initialization process for the virtualization descriptor structure may include adding initialization information corresponding to the functions to be enabled to the corresponding fields of the virtualization descriptor structure. The initialization process for the virtualization control structure may include adding initialization information corresponding to the functions to be enabled to the corresponding fields of the virtualization control structure.

[0271] Optionally, the virtualization layer 30 may configure, in the virtualization control structure, operation control information for any physical computing resource object when running in non-root mode. For example, the operation control information may include, but is not limited to, at least one of: MSR control information, PI control information, APIC control information, hardware register operation instruction information, memory page table entry address, and configuration information related to exiting non-root mode.

[0272] Further optionally, when configuring the operation control information, the virtualization layer 30 is specifically configured to perform at least one of the following configuration operations:

[0273] a3. Create a model-specific register bitmap (e.g., msr_bitmap) and allocate a second physical page to store the bitmap;

[0274] b3. Set the PI interrupt function and set the PI notification vector;

[0275] c3. Set the APIC interrupt control function, allocate the third physical page to store the APIC table from the physical address space, and save the base address of the page where the APIC table is located in the APIC field; in addition, set APIC_ID to the apic_id of the current physical computing resource object (such as the CPU), and the APIC Local Vector Register (APIC_LVR) inherits the settings of the current physical computing resource object (such as the CPU); if the APIC timer is intercepted, the timer configuration and processing function can also be configured;

[0276] d3. Set the processor opcode (e.g., CPUID) and establish a cache for virtual computing resource objects;

[0277] e3. Set the PAUSE-Loop Exiting (PLE). The PLE configuration is used to reduce the waste of virtual computing resources caused by loop waiting.

[0278] f3. Save the entry address of the multi-level memory page generated in step S1 in the virtualization control structure. At the same time, set the RIP instruction position executed after exiting the non-root mode.

[0279] g3, default configuration of general registers in root mode and non-root mode.

[0280] The process of initializing each virtualization descriptor structure and virtualization control structure is as follows:

[0281] 1) Load each virtualization descriptor structure (vcpu) in turn and initialize each vcpu structure;

[0282] 2) Load the virtualization control structure (vmcs) structure corresponding to the vcpu as the current vmcs;

[0283] 3) Configure the operation control information for the current vmcs, i.e., execute steps a3 to g3 above;

[0284] 4) Clean up the current vmcs structure;

[0285] 5) Determine whether the vCPU to be initialized has been initialized. If not, repeat steps 1) to 4); if initialization is complete, end initialization.

[0286] In summary, mode switching for the host operating system involves switching from physical computing resource objects to virtual computing resource objects, and also involves synchronization of context information, access control of IO operations, and switching of memory access. Therefore, a physical descriptor structure corresponding to the physical computing resource object and a virtualization descriptor structure corresponding to the virtual computing resource object are created to synchronize context information during the mode switching process, and an IO bitmap is created to facilitate access control of IO operations during the mode switching process, and a first stack is created to facilitate the virtualization layer 30 to switch memory access during the mode switching process.

[0287] Among them, after creating the memory page table and various information-carrying objects, it means that the foundation for mode switching is laid. On this basis, the running host operating system can be switched from root mode to non-root mode based on the information-carrying objects and memory page tables.

[0288] S3, based on the information carrying object and memory page table, switches the running host operating system from root mode to Non-root mode

[0289] In this embodiment, mode switching can be performed for any physical computing resource object, and the process of mode switching for each physical computing resource object is the same. For ease of description and distinction, the following description takes mode switching for a target physical computing resource object as an example, and the target physical computing resource object can be any physical computing resource object.

[0290] like Figure 3dAs shown, the process of performing mode switching on a target physical computing resource object includes: Step S31: When performing mode switching on a target physical computing resource object, the context information of the target physical computing resource object in root mode is saved in a physical descriptor structure corresponding to the target physical computing resource object. Step S32: The values ​​of each register and the configuration information of the segment register in the context information in the physical descriptor structure are synchronized to the virtualization descriptor structure and virtualization control structure corresponding to the target physical computing resource object. Step S33: Based on the virtualization descriptor structure, the virtualization control structure, and the memory page table, the operation of the target physical computing resource object is controlled to switch the running host operating system from root mode to non-root mode.

[0291] For example, the values ​​of each register in the context information in the physical descriptor structure are synchronized to the virtualization descriptor structure corresponding to the target physical computing resource object, and the configuration information of the segment register in the context information in the physical descriptor structure is synchronized to the virtualization control structure corresponding to the target physical computing resource object. The configuration information of the segment register may include, but is not limited to, the size of the segment, the starting address of the segment, and the management attributes of the segment. For example, the management attributes of the segment may include: write-prohibited, execute-prohibited, or system-only.

[0292] In this embodiment, steps S1 and S2 may be executed when the virtualization layer 30 is started or initialized, and step S3 may be executed on demand according to dynamic requirements (external instructions). Whether to switch the mode of the target physical computing resource object may be determined by the external instructions.

[0293] In an optional embodiment, the host operating system 20 of this embodiment provides an external symmetric multi-processing (SMP) call interface, allowing an external party to send an SMP call request to any physical computing resource object on the physical machine. The SMP call request is used to indicate that a mode switch is required for any physical computing resource object. For ease of distinction and description, the example of an external party sending an SMP call request to a target physical computing resource object is used for explanation. For example, an upper-layer application running on the host operating system 20 can initiate an SMP call request to the target physical computing resource object, or a developer can initiate an SMP call request to the target physical computing resource object through the host operating system 20.

[0294] When the target physical computing resource object receives an SMP call request, it can initiate a call request for a switching function to trigger a mode switch. Accordingly, the virtualization layer 30 provides a switching function (such as the switch_vcpu function) for the host operating system to switch the mode, which is used for the target physical computing resource object to run the switching function to switch the host operating system from root mode to non-root mode, specifically referring to the execution of the operation of saving the context information of the target physical computing resource object in root mode to the physical descriptor structure corresponding to the target physical computing resource object and subsequent operations (such as steps S32 and S33) to switch the mode of the physical computing resource object. After entering the non-root mode, the virtualization layer 30 can also control the target physical computing resource object to exit from the non-root mode to the root mode when an exit event configured in the virtualization control structure occurs.

[0295] In an optional embodiment, during the mode switching process, before saving the context information, it can be determined whether the state of the switch mark corresponding to the target physical computing resource object is in the to-be-switched state; if the judgment result is yes, the switch mark is updated to the switching state. For example, the target physical computing resource object can obtain the state of the switch mark. If the state of the switch mark is the unswitched state (such as VMX_OFF), the switch mark is updated to the switching state (such as VMX_SWITCH); if the state of the switch mark is the switching completed state (such as VMX_ON), ​​the SMP call is directly returned without executing the mode switch. Optionally, based on the return of the SMP call, some other finishing work can be done. The virtualization layer 30 can also configure the first instruction after entering the non-root mode for the first time, and the first instruction is the entry address of the switching function.

[0296] The switch function is divided into an upper half and a lower half. For example, the switch function can be entered through a function entry such as switch_vcpu. As the host operating system switches between different modes, the code path after entering the switch function will be different at different times. For the first switch from root mode to non-root mode, an SMP call can be initiated to the target physical computing resource object. This call is used to trigger the mode switch. First, the state of the switch flag is detected. If it is determined to be in the pending state, the mode switch is triggered and the upper half of the switch function is entered. In the upper half, the switch flag is first set to the switching state (e.g., VMX_SWITCH), and the first instruction to be executed after entering non-root mode is set, i.e., the entry address of the switch function. Thereafter, in the upper half of the switch function, the operation of switching the host operating system from root mode to non-root mode is executed. After the target physical computing resource object enters non-root mode, the first instruction set above is executed. This first instruction is the execution of the switch function. At this point, the flag bit has been set to the switching state, and the lower half of the switch function is entered. The switch is completed in the lower half of the switch function, and the SMP call is returned.

[0297] Optionally, for ease of distinction and description, the stack currently used by the target physical computing resource object (i.e., before switching to non-root mode) is referred to as the second stack. When the virtualization layer 30 saves the context information of the target physical computing resource object in the root mode into the physical descriptor structure corresponding to the target physical computing resource object, it is specifically used to: save the value of each register in the context information and the top and bottom addresses of the second stack into the physical descriptor structure. For example, the value of each register in the context information can be saved into the physical descriptor structure, specifically, the control register, segment register, and general register can be saved into the register structure in the physical descriptor structure, and the top and bottom addresses of the second stack can be saved into the stack corresponding fields of the host register of the physical descriptor structure (pcpu), which will be used in subsequent mode switching.

[0298] The virtualization layer 30 may also switch the second stack currently used by the target physical computing resource object to the newly created first stack, so that the virtualization layer 30 can continue to run based on the first stack in the root mode.

[0299] Further optionally, when controlling the execution of the target physical computing resource object based on the virtualization descriptor structure, the virtualization control structure, and the memory page table, the virtualization layer 30 is specifically configured to: load the values ​​of the dedicated registers in the virtualization control structure and the virtualization descriptor structure. Dedicated registers are a group of registers with specific functions and special uses that can be accessed and used by specific instructions or hardware modules. For example, PI registers, debug registers (DR) registers, MSR registers, or segment registers. Furthermore, the segment registers of the PCPU can be saved and the values ​​of the segment registers in the vCPU can be loaded. The execution control information in the virtualization control structure is injected into the target physical computing resource object, and the values ​​of the general registers in the virtualization descriptor structure are loaded. The general registers are a group of registers that can be used by developers to store general information such as data and addresses. General registers can be accessed and used by any instruction in the program. For example, pointer registers or index registers can be accessed and used. Loading the values ​​of the corresponding registers means loading the values ​​of the registers stored in the vCPU into specific hardware registers to enable the target physical computing resource object to run in non-root mode. Execute a mode switching instruction to control the target physical computing resource object to enter the non-root mode and start running from the first instruction, and perform memory management and access based on the memory page table during the running process.

[0300] Further optionally, after switching the running host operating system from root mode to non-root mode, the virtualization layer 30 may also restore the second stack to the addresses of the top and bottom of the stack saved in the physical descriptor structure, and update the switch flag to a switch completion state (e.g., VMX_ON). After switching from root mode to non-root mode, the second stack (i.e., the old stack) is restored to the addresses of the top and bottom of the stack saved in the physical descriptor structure, so that the target physical computing resource object continues to run based on the second stack in non-root mode.

[0301] In an embodiment of the present application, it is considered to utilize the hardware virtualization function to insert a lightweight virtualization layer between the host operating system and the hardware resources, implement the virtual resource provision function in the virtualization layer, and the virtualization layer switches the running host operating system from root mode to non-root mode, thereby providing at least one virtual resource in non-root mode and running at least one application on the at least one virtual resource. The at least one application includes at least an application that the host operating system cannot run in root mode due to insufficient resources. Without reinstalling the host operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, solving the problem of the host operating system being unable to run applications in root mode due to insufficient resources caused by the failure to enable or lack of relevant system functions. This allows the host operating system to support the operation of more applications, which is conducive to expanding the capabilities of the host operating system. Among them, after the host operating system switches from root mode to non-root mode, the at least one application that can be run on the virtual resources provided in non-root mode includes, but is not limited to, performing target functions such as memory management, file management, virtualization functions, and scheduling optimization in non-root mode.

[0302] In the following embodiments, the memory page fault management in memory management is taken as an example to describe the memory page fault management process in non-root mode in detail. It is explained here that one application scenario of memory page fault is memory swap (swap), that is, memory page fault may occur during the memory swap process, but memory page fault is not only used in the memory swap process. In order to facilitate the embodiment of the present application to demonstrate the advantages of memory page fault management implemented in non-root mode, the use of memory page fault for memory swap is used as an example for description, and memory swap is first introduced.

[0303] The memory swap function in a host operating system (e.g., Linux) is a mechanism that uses free hard disk space as memory expansion. When the main memory (e.g., RAM) runs low on memory pages, swapping out infrequently used pages is done by moving them to the hard disk to free up space for other pages. This process is called page swapping. When a process uses the swapped-out pages again, a page swap in is triggered.

[0304] The swap function of the host operating system (such as the Linux system) includes two aspects: swap partition and swap file. The swap partition is used to exchange hard disk space and is also called swap space. It is usually allocated when the host operating system is installed. You can also manually create a swap partition using the fdisk command or mkswap command. After dividing the free disk space into swap partitions, you can mount it as a swap partition using the swapon command. The advantages of swap partitions are fast speed and high stability, but the partition size needs to be planned in advance and cannot be adjusted dynamically. Among them, the fdisk command is used to create, delete, modify, and display disk partitions. The mkswap command is used to create a swap partition. The swapon command is used to enable a swap partition on a physical machine.

[0305] A swap file is a file created on a regular file system that can be used as swap space. Use commands such as dd and fallocate to create a swap file, then use the mkswap command to format it as a swap file system, and finally use the swapon command to mount it as swap space. Both the dd and fallocate commands can be used to create files. Swap files offer the advantages of high flexibility, dynamic resizing, and ease of management, but their performance is slightly inferior to that of a swap partition.

[0306] In host operating systems (such as Linux), the swap space size is typically set to two or three times the physical memory. If physical memory is sufficient, swap space usage will be low and will not significantly impact physical machine performance. If physical memory is insufficient, swap space usage will be high, severely impacting physical machine performance. Therefore, the performance of the swap space is crucial to the stability of physical machine performance.

[0307] Furthermore, the swap function of the host operating system (e.g., Linux) kernel is for user processes and does not directly affect the swapping of kernel pages. If memory is insufficient, the kernel will attempt to reclaim some unnecessary pages and swap them to disk using the swap function to free up memory space. These unnecessary pages include user process pages, cache pages, anonymous memory pages, etc., but not kernel pages, as kernel pages are generally not swappable. Kernel code and data are typically locked in memory and not swapped to disk, so they are not affected by the swap function. Furthermore, the swap function currently only supports small 4KB pages, while large pages (e.g., 2MB or 1GB) are increasingly used in cloud computing scenarios, which do not yet support large page swap. If the running operating system does not have the swap function configured, enabling it online can only use the file method, which has very low performance and can seriously affect system stability.

[0308] Although some system functions that are missing from the host operating system can be implemented by loading functional modules, this is invasive and subject to the constraints of various existing structures and function functions of the operating system. It may not solve all problems, such as the swapping of kernel-mode pages mentioned above. In the embodiment of the present application, based on the virtualization layer, the system switches from root mode to non-root mode, and provides virtual memory resources in non-root mode, so that the memory swap function can be implemented, which is no longer limited by whether the host operating system has the memory swap function enabled. In addition, the solution provided by the embodiment of the present application is more transparent, imperceptible to upper-layer applications, and can achieve more comprehensive functions.

[0309] Furthermore, in an embodiment of the present application, when creating a memory page table, a hybrid mapping granularity combining the first page granularity, the second page granularity, the third page granularity, and the fourth page granularity is adopted, which supports not only small page granularity but also large page granularity, can meet the needs of different physical page mappings, and improve the flexibility of memory mapping. Using small page granularity for memory mapping can reduce internal fragmentation in memory pages and reduce memory waste; using large page granularity for memory mapping can reduce page table entry data, reduce the hierarchy of memory page tables, reduce memory management overhead, and improve the performance of physical computing resource objects.

[0310] Furthermore, in an embodiment of the present application, when creating a memory page table, the physical address space of the host machine is no longer limited, and it is allowed to create a memory page table for the full physical address space, that is, to support full memory mapping. Therefore, it is possible to create a memory page table for both user-mode pages and kernel-mode pages. By supporting memory mapping of the full physical address space, a basic framework is provided for various subsequent operations based on memory mapping. For example, when performing memory swapping based on memory mapping, it not only supports swapping of user-mode pages, but also supports swapping of kernel-mode pages, that is, supports full memory swapping. The following is a brief description of the process of implementing memory page fault management after switching to non-root mode:

[0311] 1) The above-mentioned memory page table (such as ept page table) prepared for the mode switching of the host operating system has a one-to-one correspondence between the client physical address (GPA) and the host physical address (HPA). Among them, normal operation will not trigger a page fault exception in non-root mode. In order to expand the memory management function of the host operating system, some memory pages (the page granularity can be 4K or 2M) can be recovered by recycling free pages, or compressing used pages, or swapping memory pages to disk, or expanding new virtual memory space, and the corresponding memory page table page table entries can be cleared. In this way, subsequent accesses in non-root mode can trigger a page fault exception. At present, the memory page table of a batch of free pages can be directly cleared to trigger a page fault exception.

[0312] 2) Since a batch of memory pages have been cleared and recycled in step 1), a simple memory management system can be used, for example, to manage memory using status bits for subsequent page fault exceptions.

[0313] 3) Before performing page fault exception processing, a processing function may be set in the exit event of the non-root mode, for example, a page fault processing function (ept_handler) associated with the exit reason EPT page fault (EXIT_REASON_EPT_VIOLATION) may be set.

[0314] 4) In the page fault handling function (ept_handler), an unused host physical page can be selected from the underlying memory management system and marked as used.

[0315] 5) Establish a mapping relationship between the physical address (HPA) of the unused host physical page and the guest physical address (GPA) where the page fault occurs, and create a corresponding page table entry in the corresponding memory page table (e.g., ept page table) so that the host operating system can implement memory management in non-root mode. The memory management here includes but is not limited to memory swapping.

[0316] It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, the execution entity of steps R11 to R12 can be device A; for another example, the execution entity of steps R11 and R12 can be device A, and the execution entity of step R13 can be device B; and so on.

[0317] In addition, some of the processes described in the above embodiments and the accompanying drawings include multiple operations that appear in a specific order, but it should be clearly understood that these operations may not be executed in the order in which they appear in this article or may be executed in parallel. The sequence numbers of the operations, such as R11 to step R12, are only used to distinguish between different operations, and the sequence numbers themselves do not represent any execution order. In addition, these processes may include more or fewer operations, and these operations may be executed in sequence or in parallel. It should be noted that the descriptions of "first", "second", etc. in this article are used to distinguish different messages, devices, modules, etc., and do not represent the order of precedence, nor do they limit "first" and "second" to different types.

[0318] Figure 4 A schematic diagram of the structure of an address conversion device provided by an exemplary embodiment of the present application is shown in FIG. Figure 4 As shown, the device includes: a construction module 41, a determination module 42, a query module 43 and a generation module 44.

[0319] A construction module 41 is configured to pre-construct a first RMAP table corresponding to an EPT, wherein the EPT includes a multi-level page table corresponding to at least one GPA; the first RMAP table stores address information of a last-level page table entry corresponding to at least one GPA;

[0320] a determination module 42 for determining a first GPA requiring address translation in response to a first address translation trigger event, and a query module 43 for querying address information of a last-level page table entry corresponding to the first GPA in a first RMAP table;

[0321] The generating module 44 is configured to generate the HPA corresponding to the first GPA according to the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA if the address information of the last-level page table entry corresponding to the first GPA is found.

[0322] In an optional embodiment, the construction module is further configured to pre-construct a second RMAP table corresponding to the EPT, wherein the second RMAP table stores address translation information from at least one HPA to a corresponding GPA. The determination module is further configured to respond to a second address translation trigger event, determine a first HPA requiring address translation, and query the second RMAP table for address translation information from the first HPA to the corresponding GPA. The generation module is further configured to generate a GPA corresponding to the first HPA based on the first HPA and its address translation information to the corresponding GPA and the address offset of the first HPA.

[0323] In an optional embodiment, the construction module is specifically used to: divide the GPA address space corresponding to the EPT into at least one address space, create a basic structure for each address space, and the basic structure corresponds to the set page table level; for any GPA in the EPT, determine the first structure corresponding to any GPA from each basic structure according to the address information of any GPA and the address space corresponding to each basic structure; according to the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, record the address information of the last-level page table entry corresponding to any GPA through the first structure.

[0324] Optionally, the construction module is specifically used to: if the level of the last-level page table corresponding to any GPA is the same as the set page table level, then the address information of the last-level page table entry corresponding to any GPA is added to the information field in the first structure, and the flag information in the first structure is set to the first value; if the level of the last-level page table corresponding to any GPA is different from the set page table level, then a second structure adapted to the level of the last-level page table corresponding to any GPA is created, the address information of the last-level page table entry corresponding to any GPA is added to the information field in the second structure, and the address information of the second structure is added to the information field in the first structure, and the flag information in the first structure is set to the second value.

[0325] Further optionally, the construction module is specifically used to: when the level of the last-level page table corresponding to any GPA is the previous level of the set page table level, determine whether the second structure already exists; if not, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure; when the level of the last-level page table corresponding to any GPA is the next level of the set page table level, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure.

[0326] In an optional embodiment, the construction module is specifically used to: divide the HPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, and the basic structure corresponds to the set page granularity; for the HPA corresponding to any GPA in the EPT, determine the third structure corresponding to any HPA from each of the basic structures according to the address information of any HPA and the address space corresponding to each of the basic structures; and record the address conversion information of any HPA to the corresponding GPA through the third structure according to the relationship between the page granularity corresponding to any HPA and the set page granularity.

[0327] Optionally, the construction module is specifically used to: if the page granularity corresponding to any HPA is the same as the set page granularity, record the address conversion information of any HPA to the corresponding GPA through the information field in the third structure, and set the first flag information in the third structure to a third value; if the page granularity corresponding to any HPA is different from the set page granularity, create a fourth structure adapted to the page granularity of any HPA, record the address conversion information of any HPA to the corresponding GPA through the information field in the fourth structure, add the address information of the fourth structure to the information field in the third structure, and set the first flag information in the third structure to a fourth value.

[0328] Further optionally, the construction module is specifically configured to: when any HPA corresponds to multiple GPAs, create a fifth structure, add address information of the fifth structure to the information field of the third structure, add address translation information from any HPA to multiple GPAs to the fifth structure respectively, and add a flag indicating a one-to-many relationship to the third structure; when any HPA corresponds to one GPA, directly add the address translation information from any HPA to the corresponding GPA to the information field of the third structure;

[0329] The construction module is specifically used to: when any HPA corresponds to multiple GPAs, create a sixth structure, add the address information of the sixth structure to the information field in the fourth structure, and add the address conversion information of any HPA to multiple GPAs to the sixth structure respectively, and add a flag indicating a one-to-many relationship in the fourth structure; when any HPA corresponds to one GPA, directly add the address conversion information of any HPA to the corresponding GPA to the information field in the fourth structure.

[0330] In an optional embodiment, the query module is specifically used to: determine the first structure corresponding to the first GPA from each basic structure based on the address information of the first GPA and the address space corresponding to each basic structure contained in the first RMAP table, and the basic structure corresponds to the set page table level; obtain the address information of the last level page table entry corresponding to the first GPA through the first structure corresponding to the first GPA.

[0331] Optionally, the query module is specifically used to: obtain flag information from the first structure; if the flag information is a first value, obtain the address information of the last level page table entry corresponding to the first GPA from the information field in the first structure; if the flag information is a second value, obtain the address information of the second structure from the information field in the first structure, and according to the address information of the second structure, obtain the address information of the last level page table entry corresponding to the first GPA from the information field of the second structure.

[0332] In an optional embodiment, the following modules are also included:

[0333] A new module is added to add the address information of the last-level page table entry corresponding to the second GPA in the first RMAP table when a second GPA is added to the EPT;

[0334] a deletion module, configured to delete the address information of the last-level page table entry corresponding to the third GPA in the first RMAP table when the third GPA is deleted in the EPT;

[0335] a modification module, configured to modify the first address information of the last-level page table corresponding to the fourth GPA to the second address information in the first RMAP table when the first address information of the last-level page table corresponding to the fourth GPA is modified to the second address information in the EPT;

[0336] An expansion module, configured to modify, in the first RMAP table, address information of the last-level page table entries corresponding to each GPA in the last-level page table to address information of the corresponding next-level page table when the last-level page table is expanded to the next-level page table in the EPT;

[0337] The shrink module is used to modify the address information of the last-level page table entry corresponding to each GPA in the last-level page table to the address information of the previous-level page table entry in the first RMAP table when the last-level page table with continuous addresses in the EPT is shrunk to the previous-level page table.

[0338] Optionally, the adding module is specifically used to: determine the first structure corresponding to the second GPA from each basic structure according to the address information of the second GPA and the address space corresponding to each basic structure contained in the first RMAP table, and the first structure corresponds to the set page table level; if it is determined that the address information of the last-level page table entry corresponding to the second GPA is not recorded through the first structure, then according to the relationship between the level of the last-level page table corresponding to the second GPA and the set page table level, the address information of the last-level page table entry corresponding to the second GPA is recorded through the first structure.

[0339] Optionally, the deletion module is specifically used to: determine the first structure corresponding to the third GPA from each basic structure according to the address information of the third GPA and the address space corresponding to each basic structure contained in the first RMAP table, and the first structure corresponds to the set page table level; if the level of the last-level page table corresponding to the third GPA is compatible with the page table level indicated by the flag information of the first structure, then according to the relationship between the level of the last-level page table corresponding to the third GPA and the set page table level, delete the address information of the last-level page table entry corresponding to the third GPA through the first structure.

[0340] Optionally, the extension module is specifically used to: clear the address information recorded in each page table entry in the last-level page table in the EPT, and clear the address information of the last-level page table entry corresponding to each GPA in the last-level page table in the first RMAP table; create a next-level page table corresponding to the last-level page table, record the address information of the next-level page table in the page table entry of the last-level page table, and record the base address of the physical page corresponding to the corresponding HPA in the page table entry of the next-level page table; in the first RMAP table, according to the relationship between the level of the next-level page table and the set page table level, record the address information of the next-level page table entry corresponding to each GPA in the last-level page table through the first structure.

[0341] Optionally, the shrink module is specifically used to: clean up the address information recorded in each page table entry in the last-level page table with continuous addresses in the EPT, and clean up the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table; create an upper-level page table corresponding to the last-level page table, and record the address information of the physical page corresponding to the corresponding HPA in the page table entries of the upper-level page table; in the first RMAP table, according to the relationship between the level of the upper-level page table and the set page table level, record the address information of the upper-level page table entries corresponding to each GPA in the last-level page table through the first structure.

[0342] In an optional embodiment, the execution body of the device is a virtualization manager in the host operating system OS; or, the execution body of the device is a virtualization layer between the host OS and the host hardware resources, and the virtualization layer is used to switch the running host OS from root mode to non-root mode.

[0343] The present application also provides a fast mapping table construction device, such as Figure 5 As shown, the device includes:

[0344] A partitioning module 51 is configured to partition the GPA address space corresponding to the EPT into at least one address space, and a creation module 52 is configured to create a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page table level, and the EPT includes a multi-level page table corresponding to each of the at least one GPAs;

[0345] a determination module 53 for determining, for any GPA in the EPT, a first structure corresponding to any GPA from among the basic structures according to the address information of the GPA and the address space corresponding to each basic structure;

[0346] The recording module 54 is used to record the address information of the last-level page table entry corresponding to any GPA through a first structure based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, so as to construct a first RMAP table corresponding to the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to at least one GPA.

[0347] Regarding the embodiments of this application Figure 4 and Figure 5 The detailed implementation and beneficial effects of each step in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0348] Figure 6 A schematic diagram of the structure of a physical machine provided by an exemplary embodiment of the present application, the physical machine is also called an address translation device, such as Figure 6As shown, the device includes a memory 64 and a processor 65 .

[0349] The memory 64 is used to store computer programs and can be configured to store various other data to support operations on the address translation device. Examples of such data include instructions for any application program or method operating on the address translation device.

[0350] The processor 65 is coupled to the memory 64 and is configured to execute a computer program in the memory 64 to: pre-construct a first RMAP table corresponding to an EPT, the EPT including a multi-level page table corresponding to at least one GPA; store in the first RMAP table address information of a last-level page table entry corresponding to at least one GPA; in response to a first address translation trigger event, determine a first GPA requiring address translation, query the first RMAP table for address information of a last-level page table entry corresponding to the first GPA; and if address information of the last-level page table entry corresponding to the first GPA is found, generate an HPA corresponding to the first GPA based on the address information of the last-level page table entry corresponding to the first GPA and an address offset of the first GPA.

[0351] In an optional embodiment, the processor 65 is further configured to: pre-construct a second RMAP table corresponding to the EPT, wherein the second RMAP table stores address translation information from at least one HPA to a corresponding GPA; in response to a second address translation trigger event, determine a first HPA requiring address translation, and query the second RMAP table for address translation information from the first HPA to a corresponding GPA; and generate a GPA corresponding to the first HPA based on the first HPA, its address translation information to the corresponding GPA, and the address offset of the first HPA.

[0352] In an optional embodiment, when the processor 65 pre-constructs the first RMAP table corresponding to the EPT, it is specifically used to: divide the GPA address space corresponding to the EPT into at least one address space, create a basic structure for at least one address space, and the basic structure corresponds to the set page table level; for any GPA in the EPT, according to the address information of any GPA and the address space corresponding to each basic structure, determine the first structure corresponding to any GPA from each basic structure; according to the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, record the address information of the last-level page table entry corresponding to any GPA through the first structure.

[0353] Optionally, when the processor 65 records the address information of the last-level page table entry corresponding to any GPA through the first structure based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, it is specifically used to: if the level of the last-level page table corresponding to any GPA is the same as the set page table level, then the address information of the last-level page table entry corresponding to any GPA is added to the information field in the first structure, and the flag information in the first structure is set to the first value; if the level of the last-level page table corresponding to any GPA is different from the set page table level, then a second structure adapted to the level of the last-level page table corresponding to any GPA is created, the address information of the last-level page table entry corresponding to any GPA is added to the information field in the second structure, and the address information of the second structure is added to the information field in the first structure, and the flag information in the first structure is set to the second value.

[0354] Further optionally, when the processor 65 creates a second structure adapted to the level of the last-level page table corresponding to any GPA, it is specifically used to: when the level of the last-level page table corresponding to any GPA is the previous level of the set page table level, determine whether the second structure already exists; if not, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure; when the level of the last-level page table corresponding to any GPA is the next level of the set page table level, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure.

[0355] In an optional embodiment, when pre-building the second RMAP table corresponding to the EPT, the processor 65 is specifically used to: divide the HPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, and the basic structure corresponds to the set page granularity; for the HPA corresponding to any GPA in the EPT, determine the third structure corresponding to any HPA from each basic structure according to the address information of any HPA and the address space corresponding to each basic structure; and record the address conversion information of any HPA to the corresponding GPA through the third structure according to the relationship between the page granularity corresponding to any HPA and the set page granularity.

[0356] Optionally, when recording the address translation information from any HPA to the corresponding GPA through the third structure based on the relationship between the corresponding page table level in any HPA and the set page table level, the processor 65 is specifically configured to: if the page granularity corresponding to any HPA is the same as the set page granularity, record the address translation information from any HPA to the corresponding GPA through the information field in the third structure, and set the first flag information in the third structure to a third value; if the page granularity corresponding to any HPA is different from the set page granularity, create a fourth structure adapted to the page granularity of any HPA, record the address translation information from any HPA to the corresponding GPA through the information field in the fourth structure, add the address information of the fourth structure to the information field in the third structure, and set the first flag information in the third structure to a fourth value.

[0357] Further optionally, when recording the address translation information from any HPA to the corresponding GPA through the information field in the third structure, the processor 65 is specifically configured to: if any HPA corresponds to multiple GPAs, create a fifth structure, add the address information of the fifth structure to the information field in the third structure, add the address translation information from any HPA to the multiple GPAs to the fifth structure respectively, and add a flag indicating a one-to-many relationship in the third structure; if any HPA corresponds to one GPA, directly add the address translation information from any HPA to the corresponding GPA to the information field in the third structure;

[0358] Accordingly, when the processor 65 records the address conversion information from any HPA to the corresponding GPA through the information field in the fourth structure, it is specifically used to: when any HPA corresponds to multiple GPAs, create a sixth structure, add the address information of the sixth structure to the information field in the fourth structure, and add the address conversion information from any HPA to multiple GPAs to the sixth structure respectively, and add a flag indicating a one-to-many relationship in the fourth structure; when any HPA corresponds to one GPA, directly add the address conversion information from any HPA to the corresponding GPA to the information field in the fourth structure.

[0359] In an optional embodiment, when the processor 65 queries the address information of the last-level page table entry corresponding to the first GPA in the first RMAP table, it is specifically used to: determine the first structure corresponding to the first GPA from each basic structure based on the address information of the first GPA and the address space corresponding to each basic structure contained in the first RMAP table, and the basic structure corresponds to the set page table level; obtain the address information of the last-level page table entry corresponding to the first GPA through the first structure corresponding to the first GPA.

[0360] Optionally, when the processor 65 obtains the address information of the last-level page table entry corresponding to the first GPA through the first structure corresponding to the first GPA, it is specifically used to: obtain flag information from the first structure; if the flag information is a first value, obtain the address information of the last-level page table entry corresponding to the first GPA from the information field in the first structure; if the flag information is a second value, obtain the address information of the second structure from the information field in the first structure, and according to the address information of the second structure, obtain the address information of the last-level page table entry corresponding to the first GPA from the information field of the second structure.

[0361] In an optional embodiment, the processor 65 is further configured to perform at least one of the following operations:

[0362] When a second GPA is added to the EPT, the address information of the last-level page table entry corresponding to the second GPA is added to the first RMAP table;

[0363] When the third GPA is deleted in the EPT, the address information of the last-level page table entry corresponding to the third GPA is deleted in the first RMAP table;

[0364] In a case where the first address information of the last-level page table corresponding to the fourth GPA is modified to the second address information in the EPT, the first address information of the last-level page table corresponding to the fourth GPA is modified to the second address information in the first RMAP table;

[0365] When the last-level page table is extended to the next-level page table in the EPT, the address information of the last-level page table entry corresponding to each GPA in the last-level page table is modified to the address information of the corresponding next-level page table in the first RMAP table;

[0366] When the last-level page table with continuous addresses in the EPT is shrunk to the previous-level page table, the address information of the last-level page table entry corresponding to each GPA in the last-level page table is modified to the address information of the previous-level page table entry in the first RMAP table.

[0367] In an optional embodiment, when the processor 65 adds the address information of the last-level page table entry corresponding to the second GPA in the first RMAP table, it is specifically used to: determine the first structure corresponding to the second GPA from each basic structure based on the address information of the second GPA and the address space corresponding to each basic structure contained in the first RMAP table, and the first structure corresponds to the set page table level; if it is determined that the address information of the last-level page table entry corresponding to the second GPA is not recorded through the first structure, then according to the relationship between the level of the last-level page table corresponding to the second GPA and the set page table level, the address information of the last-level page table entry corresponding to the second GPA is recorded through the first structure.

[0368] In an optional embodiment, when the processor 65 deletes the address information of the last-level page table entry corresponding to the third GPA in the first RMAP table, it is specifically used to: determine the first structure corresponding to the third GPA from each basic structure based on the address information of the third GPA and the address space corresponding to each basic structure contained in the first RMAP table, and the first structure corresponds to the set page table level; if the level of the last-level page table corresponding to the third GPA is compatible with the page table level indicated by the flag information of the first structure, then according to the relationship between the level of the last-level page table corresponding to the third GPA and the set page table level, delete the address information of the last-level page table entry corresponding to the third GPA through the first structure.

[0369] In an optional embodiment, when the processor 65 expands the last-level page table into a next-level page table in the EPT, and modifies the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table to the address information of the corresponding next-level page table, it is specifically used to: clear the address information recorded in each page table entry in the last-level page table in the EPT, and clear the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table; create a next-level page table corresponding to the last-level page table, record the address information of the next-level page table in the page table entry of the last-level page table, and record the base address of the physical page corresponding to the corresponding HPA in the page table entry of the next-level page table; in the first RMAP table, record the address information of the next-level page table entries corresponding to each GPA in the last-level page table through the first structure according to the relationship between the level of the next-level page table and the set page table level.

[0370] In an optional embodiment, when the processor 65 shrinks the last-level page table with continuous addresses in the EPT to the previous-level page table, the processor 65 modifies the address information of the last-level page table entries corresponding to each GPA in the last-level page table to the address information of the previous-level page table entry in the first RMAP table. The processor 65 is specifically used to: clear the address information recorded in each page table entry in the last-level page table with continuous addresses in the EPT, and clear the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table; create the previous-level page table corresponding to the last-level page table, and record the address information of the physical pages corresponding to the corresponding HPA in the page table entries of the previous-level page table; and record the address information of the previous-level page table entries corresponding to each GPA in the last-level page table through the first structure in the first RMAP table according to the relationship between the level of the previous-level page table and the set page table level.

[0371] In an optional embodiment, the processor 65 performs the above operations through a virtualization manager in the host operating system OS; or, the processor 65 performs the above operations through a virtualization layer between the host OS and the host hardware resources, and the virtualization layer is used to switch the running host OS from root mode to non-root mode.

[0372] Regarding the embodiments of this application Figure 6 The detailed implementation and beneficial effects of each step in the illustrated device have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0373] Further, if Figure 6 As shown, the address conversion device also includes: a communication component 66, a display 67, a power supply component 68, an audio component 69 and other components. Figure 6 Only some components are shown schematically, which does not mean that the address translation device only includes Figure 6 In addition, Figure 6 The components in the dotted box are optional components, not mandatory components, and the specific product form of the address translation device may be determined. The address translation device of this embodiment can be implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone or an IOT device, or as a server-side device such as a conventional server, a cloud server or a server array. If the address translation device of this embodiment is implemented as a terminal device such as a desktop computer, a laptop computer, a smart phone, etc., it may include Figure 6 If the address translation device of this embodiment is implemented as a conventional server, cloud server or server array and other server-side devices, it may not include Figure 6 Components within the dotted box.

[0374] The embodiment of the present application also provides a fast mapping construction device, the implementation structure of the fast mapping construction device is similar to Figure 6 The implementation structure of the construction device of the fast mapping shown is the same or similar, and can be referred to Figure 6 The structure of the construction device of the fast mapping shown in FIG. Figure 6The difference between the fast mapping construction devices in the illustrated embodiments lies primarily in the different functions implemented by the processor executing a computer program stored in memory. In the address translation device provided in this embodiment, the processor executes a computer program stored in memory, which can be used to: divide the GPA address space corresponding to the memory page table (EPT) into at least one address space; create a base structure for each of the at least one address space, each base structure corresponding to a set page table level; the EPT includes a multi-level page table corresponding to at least one GPA; determine, for each GPA in the EPT, a first structure corresponding to each of the base structures based on the address information of the GPA and the address space corresponding to each base structure; and record the address information of the last-level page table entry corresponding to each GPA in the first structure based on the relationship between the level of the last-level page table corresponding to each GPA and the set page table level, thereby constructing a first RMAP table corresponding to the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to at least one GPA.

[0375] The detailed implementation and beneficial effects of the rapid mapping construction device provided in the embodiments of the present application have been described in detail in the aforementioned embodiments and will not be elaborated on here.

[0376] Accordingly, the present invention also provides a computer-readable storage medium storing a computer program, which can achieve the above-mentioned Figure 4 and Figure 5 The steps in the method embodiment are shown.

[0377] The present application also provides a computer program product, including a computer program / instruction, which, when executed by a processor, causes the processor to implement the Figure 4 and Figure 5 Steps in the method shown.

[0378] The above-mentioned memory can be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0379] The above-mentioned communication component is configured to facilitate wired or wireless communication between the device where the communication component is located and other devices. The device where the communication component is located can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G and other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra wide band (UWB) technology, Bluetooth (BT) technology and other technologies.

[0380] The above-mentioned display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor can not only sense the boundary of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation.

[0381] The power supply assembly provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0382] The above-mentioned audio component can be configured to output and / or input audio signals. For example, the audio component includes a microphone (MIC), and when the device where the audio component is located is in an operating mode, such as call mode, recording mode, and voice recognition mode, the microphone is configured to receive external audio signals. The received audio signal can be further stored in a memory or sent via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals.

[0383] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) that contain computer-usable program code.

[0384] The present application is described with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to the embodiment of the present application. It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one flow chart flow or multiple flows and / or one box or multiple boxes of the block diagram.

[0385] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0386] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram.

[0387] In a typical configuration, a computing device includes one or more processors (Central Processing Unit, CPU), input / output interfaces, network interfaces, and memory.

[0388] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0389] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be used to store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0390] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0391] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. An address conversion method, characterized in that: include: Pre-building a first fast mapping table corresponding to a memory page table, wherein the memory page table includes at least one multi-level page table corresponding to each client physical address; The first fast mapping table stores address information of the last-level page table entry corresponding to each of the at least one client physical addresses; In response to a first address translation triggering event, determining a first client physical address that requires address translation, and querying the first fast mapping table for address information of a last-level page table entry corresponding to the first client physical address; If the address information of the last-level page table entry corresponding to the first client physical address is queried, the host machine physical address corresponding to the first client physical address is generated based on the address information of the last-level page table entry corresponding to the first client physical address and the address offset of the first client physical address.

2. The method according to claim 1, characterized in that Also includes: Pre-building a second fast mapping table corresponding to the memory page table, wherein the second fast mapping table stores address translation information from at least one host machine physical address to a corresponding client machine physical address; In response to a second address translation triggering event, determining a first host machine physical address that needs to be translated, and querying the second fast mapping table for address translation information from the first host machine physical address to a corresponding client machine physical address; A client physical address corresponding to the first host physical address is generated according to the first host physical address and address conversion information thereof to the corresponding client physical address and the address offset of the first host physical address.

3. The method according to claim 1 or 2, characterized in that Pre-building a first fast mapping table corresponding to the memory page table, including: Divide the address space of the client physical address corresponding to the memory page table into at least one address space, and create a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page table level; For any client physical address in the memory page table, determining a first structure corresponding to the any client physical address from each basic structure according to address information of the any client physical address and address spaces corresponding to each basic structure; According to the relationship between the level of the last-level page table corresponding to any client physical address and the set page table level, the address information of the last-level page table entry corresponding to any client physical address is recorded through the first structure.

4. The method according to claim 3, characterized in that According to a relationship between the level of the last-level page table corresponding to any client physical address and the set page table level, recording address information of the last-level page table entry corresponding to any client physical address through the first structure includes: If the level of the last-level page table corresponding to any one of the client physical addresses is the same as the set page table level, adding the address information of the last-level page table entry corresponding to any one of the client physical addresses to the information field in the first structure, and setting the flag information in the first structure to a first value; If the level of the last-level page table corresponding to any client physical address is different from the set page table level, a second structure adapted to the level of the last-level page table corresponding to any client physical address is created, the address information of the last-level page table entry corresponding to any client physical address is added to the information field in the second structure, and the address information of the second structure is added to the information field in the first structure, and the flag information in the first structure is set to the second value.

5. The method according to claim 4, characterized in that Creating a second structure adapted to the level of the last level page table corresponding to any client physical address, including: When the level of the last-level page table corresponding to any client physical address is the level above the set page table level, determining whether the second structure already exists; if not, creating a new structure adapted to the level of the last-level page table corresponding to any client physical address as the second structure; When the level of the last level page table corresponding to any client physical address is the next level of the set page table level, a new structure adapted to the level of the last level page table corresponding to any client physical address is created as the second structure.

6. The method according to claim 2, characterized in that A second fast mapping table corresponding to the memory page table is pre-built, including: Divide the address space of the host machine physical address corresponding to the memory page table into at least one address space, and create a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page granularity; For a host physical address corresponding to any client physical address in the memory page table, determining a third structure corresponding to any host physical address from each basic structure according to address information of the any host physical address and address spaces corresponding to each basic structure; According to the relationship between the page granularity corresponding to any host physical address and the set page granularity, the address conversion information from any host physical address to the corresponding client physical address is recorded through the third structure.

7. The method according to claim 6, characterized in that According to the relationship between the page table level corresponding to any host physical address and the set page table level, the address conversion information from any host physical address to the corresponding client physical address is recorded through the third structure, including: If the page granularity corresponding to any host physical address is the same as the set page granularity, then recording address translation information from any host physical address to the corresponding client physical address through the information field in the third structure, and setting the first flag information in the third structure to a third value; If the page granularity corresponding to any host physical address is different from the set page granularity, a fourth structure adapted to the page granularity of any host physical address is created, and the address conversion information of any host physical address to the corresponding client physical address is recorded through the information field in the fourth structure, and the address information of the fourth structure is added to the information field in the third structure, and the first flag information in the third structure is set to the fourth value.

8. The method according to claim 7, characterized in that The address conversion information from any host physical address to the corresponding client physical address is recorded through the information field in the third structure, including: In a case where any one host physical address corresponds to multiple client physical addresses, creating a fifth structure, adding address information of the fifth structure to the information field of the third structure, adding address translation information from any one host physical address to multiple client physical addresses to the fifth structure, and adding a flag bit indicating a one-to-many relationship to the third structure; In a case where any host physical address corresponds to a client physical address, directly adding address translation information from any host physical address to the corresponding client physical address to the information field in the third structure; Accordingly, the address conversion information from any host physical address to the corresponding client physical address is recorded through the information field in the fourth structure, including: If any host physical address corresponds to multiple client physical addresses, a sixth structure is created, address information of the sixth structure is added to the information field of the fourth structure, address translation information from any host physical address to multiple client physical addresses is added to the sixth structure, and a flag indicating a one-to-many relationship is added to the fourth structure. In the case that any host physical address corresponds to a client physical address, the address conversion information from any host physical address to the corresponding client physical address is directly added to the information field in the fourth structure.

9. The method according to claim 1, characterized in that Querying the first fast mapping table for address information of a last-level page table entry corresponding to the first client physical address includes: Determining, from the base structures, a first structure corresponding to the first client physical address according to address information of the first client physical address and address spaces corresponding to the base structures included in the first fast mapping table, the base structure corresponding to a set page table level; The address information of the last-level page table entry corresponding to the first client physical address is obtained through the first structure corresponding to the first client physical address.

10. The method according to claim 9, characterized in that Obtaining address information of a last-level page table entry corresponding to the first client physical address through a first structure corresponding to the first client physical address includes: Obtaining flag information from the first structure; If the flag information is a first value, obtaining address information of a last-level page table entry corresponding to the first client physical address from the information field in the first structure; If the flag information is a second value, the address information of the second structure is obtained from the information field in the first structure, and according to the address information of the second structure, the address information of the last-level page table entry corresponding to the first client physical address is obtained from the information field of the second structure.

11. The method according to any one of claims 1-2, 4-10, characterized in that: Also includes at least one of the following operations: When a second client physical address is added to the memory page table, address information of a last-level page table entry corresponding to the second client physical address is added to the first fast mapping table; When the third client physical address is deleted from the memory page table, address information of the last-level page table entry corresponding to the third client physical address is deleted from the first fast mapping table; When the first address information of the last-level page table corresponding to the fourth client physical address is modified to the second address information in the memory page table, the first address information of the last-level page table corresponding to the fourth client physical address is modified to the second address information in the first fast mapping table; In a case where the last-level page table in the memory page table is expanded into a next-level page table, address information of the last-level page table entries corresponding to respective client physical addresses in the last-level page table are modified in the first fast mapping table into address information of the next-level page table; When the last-level page table with continuous addresses in the memory page table is shrunk to the previous-level page table, the address information of the last-level page table entries is cleared in the first quick mapping table, and the address information of the previous-level page table entries corresponding to the physical addresses of each client in the last-level page table is added.

12. The method according to claim 11, characterized in that Adding address information of a last-level page table entry corresponding to the second client physical address in the first fast mapping table includes: Determining, from the base structures, a first structure corresponding to the second client physical address, according to address information of the second client physical address and address spaces corresponding to the base structures included in the first fast mapping table, the first structure corresponding to a set page table level; If it is determined that the address information of the last-level page table entry corresponding to the second client physical address is not recorded through the first structure, then the address information of the last-level page table entry corresponding to the second client physical address is recorded through the first structure based on the relationship between the level of the last-level page table corresponding to the second client physical address and the set page table level.

13. The method according to claim 11, characterized in that Deleting address information of a last-level page table entry corresponding to the third client physical address in the first fast mapping table includes: Determining, from the base structures, a first structure corresponding to the third client physical address, according to address information of the third client physical address and address spaces corresponding to the base structures included in the first fast mapping table, wherein the first structure corresponds to a set page table level; If the level of the last-level page table corresponding to the third client physical address is compatible with the page table level indicated by the flag information of the first structure, then the address information of the last-level page table entry corresponding to the third client physical address is deleted through the first structure based on the relationship between the level of the last-level page table corresponding to the third client physical address and the set page table level.

14. The method according to claim 11, characterized in that In a case where the last-level page table in the memory page table is extended to a next-level page table, modifying, in the first fast mapping table, address information of the last-level page table entries corresponding to respective client physical addresses in the last-level page table to address information of the next-level page table includes: clearing, in the memory page table, address information recorded in each page table entry in the last-level page table, and clearing address information in the last-level page table entry corresponding to each client physical address in the last-level page table in the first fast mapping table; Creating a next-level page table corresponding to the last-level page table, recording the address information of the next-level page table in a page table entry of the last-level page table, and recording the base address of the physical page corresponding to the corresponding host machine physical address in the page table entry of the next-level page table; In the first fast mapping table, address information of next-level page table entries corresponding to each client physical address in the last-level page table is recorded through the first structure according to the relationship between the level of the next-level page table and the set page table level.

15. The method according to claim 11, characterized in that When a last-level page table with continuous addresses in the memory page table is shrunk to an upper-level page table, clearing address information of the last-level page table entry in the first fast mapping table and adding address information of the upper-level page table entry corresponding to each client physical address in the last-level page table includes: clearing, in the memory page table, address information recorded in each page table entry in the last level page table of the continuous address, and clearing address information in the last level page table entry corresponding to each client physical address in the last level page table of the first fast mapping table; Creating a previous-level page table corresponding to the last-level page table in the memory page table, and recording the base address of the physical page corresponding to the corresponding host machine physical address in the page table entry of the previous-level page table according to the page granularity corresponding to the previous-level page table entry; In the first quick mapping table, the address information of the last-level page table entry is cleared, and according to the relationship between the level of the previous-level page table and the set page table level, the address information of the previous-level page table entry corresponding to each client physical address in the last-level page table is recorded through the first structure.

16. The method according to any one of claims 1-2, 4-10, 12-15, characterized in that: The execution subject of the method is a virtualization manager in the host operating system (OS); or, the execution subject of the method is a virtualization layer between the host OS and the host hardware resources, and the virtualization layer is used to switch the running host OS from root mode to non-root mode.

17. A method for constructing a fast mapping table, characterized in that: include: Divide the address space of the client physical address corresponding to the memory page table into at least one address space, create a basic structure for each of the at least one address space, the basic structure corresponding to a set page table level, the memory page table including a multi-level page table corresponding to at least one client physical address; For any client physical address in the memory page table, determining a first structure corresponding to the any client physical address from each basic structure according to address information of the any client physical address and address spaces corresponding to each basic structure; According to the relationship between the level of the last-level page table corresponding to any client physical address and the set page table level, the address information of the last-level page table entry corresponding to any client physical address is recorded through the first structure to construct a first quick mapping table corresponding to the memory page table, wherein the first quick mapping table stores the address information of the last-level page table entry corresponding to each of the at least one client physical addresses.

18. A physical machine, characterized in that: include: memory and processor; The memory is used to store a computer program; the processor is coupled to the memory and is used to execute the computer program to implement the steps in the method according to any one of claims 1 to 16 and claim 17.

19. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 16 and claim 17.

20. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 16 and claim 17.

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