Method for improving PDN impedance simulation efficiency

Abstract

The invention relates to a method for improving PDN impedance simulation efficiency. The method comprises the following steps: determining an initial coverage block diagram according to the distribution of a power supply plane and a target device; by taking the maximum distance between the adjacent power supply plane and the ground plane as a reference value, externally expanding the boundary of the initial coverage block diagram by 7 times of the reference value, and generating an optimized coverage block diagram; cutting the simulation model based on the boundary of the optimized coverage block diagram, and reserving a model part in the range of the optimized coverage block diagram; and simulating the cut model and acquiring an impedance curve of the target frequency band. According to the method, the initial coverage block diagram is determined by analyzing the power plane and target device distribution, a main power supply path and a peripheral key area are focused, the initial coverage block diagram is expanded by 7 times by taking the maximum distance between the adjacent power plane and the ground plane as a reference value based on an electromagnetic field distribution theory, and more than 99% of effective field intensity is ensured to be covered; the precision loss caused by model cutting is avoided, and the technical problem in complex PCB single board simulation is effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of power distribution network simulation, and in particular to a method for improving the efficiency of PDN impedance simulation. Background Art

[0002] Printed circuit boards (PCBs) serve as the physical support and signal transmission carrier for electronic products. The performance of their power distribution networks (PDNs) directly impacts the stability of electronic systems. As single-board circuit complexity and power consumption increase, the variety and number of components, the number of stacked layers, and the size of PCBs increase significantly, leading to an exponential increase in the computational complexity of PDN impedance simulations.

[0003] Traditional PDN impedance simulation typically uses the entire board as input and performs a full model analysis of the target power supply. While this method ensures simulation accuracy, it requires processing a large number of electromagnetic parameters of irrelevant areas, including those of blank copper foil and non-target power networks, resulting in low simulation efficiency. For example, in one power supply design, traditional methods took 65 minutes to simulate PDN impedance in the 1 kHz to 2 GHz frequency band. This time cost further increases as the complexity of the board increases.

[0004] Some have proposed solutions to improve efficiency by simplifying the model. For example, by cutting model boundaries based on empirical evidence, critical electromagnetic field distribution areas can be easily missed, resulting in significant impedance curve deviations and failure to meet engineering design requirements. Consequently, these solutions often suffer from poor handling of edge field effects, leading to reduced simulation accuracy. Therefore, efficiently reducing model size while maintaining simulation accuracy has become a technical challenge in PCB design.

[0005] The above problems are worth solving. Summary of the Invention

[0006] To overcome the dual problems of low PDN impedance simulation efficiency and loss of accuracy due to simplified models in the existing technology, the present invention provides a method for improving PDN impedance simulation efficiency. This method significantly improves simulation efficiency while ensuring simulation accuracy through a combination of technologies including precise positioning of the core area, moderate expansion, and boundary condition optimization.

[0007] The technical solution of the present invention is as follows: A method for improving the efficiency of PDN impedance simulation includes the following steps: Step 1: Determine the initial coverage diagram based on the distribution of the power plane and target devices; Step 2: Taking the maximum distance between adjacent power planes and ground planes as a reference value, the boundary of the initial coverage frame is expanded by 7 times the reference value to generate an optimized coverage frame; Step 3: based on the boundary of the optimized coverage block diagram, cutting the simulation model and retaining the model portion within the scope of the optimized coverage block diagram; Step 4: Perform PDN impedance simulation on the trimmed model to obtain the impedance curve of the target frequency band.

[0008] As a preferred technical solution of the present invention, step 1 includes: Step 101: parse the PCB design file and identify the power plane layer and the ground plane layer; Step 102: Determine a main power supply path from the power module to the target device based on the power network topology. Step 103: Define the main power supply path and its surrounding preset area as an initial coverage frame diagram.

[0009] Furthermore, the step 102 includes: Build a power network topology diagram and mark the shortest current path from the power module to the target device; Identify the critical decoupling capacitor network on the path and calculate the equivalent decoupling impedance of each node; The hotspot path with current density exceeding a preset threshold is extracted as the main power supply path.

[0010] As a preferred technical solution of the present invention, in step 2, the step of taking the maximum distance between adjacent power planes and ground planes as a reference value includes: Step 201: extracting the spacing values ​​between all adjacent power planes and ground planes from the PCB stack structure parameters; Step 202: Take the maximum value of the interval values ​​as a reference value.

[0011] As a preferred technical solution of the present invention, in step 2, the step of expanding the boundary of the initial coverage frame by 7 times the reference value includes: Step 203: Expand the four boundaries of the initial coverage frame by 7 times the reference value along the positive and negative directions of the X and Y axes respectively. Step 204: If the boundary after expansion exceeds the physical boundary of the PCB, truncation is performed based on the physical boundary of the PCB.

[0012] As a preferred technical solution of the present invention, in step 3, after cutting the simulation model, the following steps are further included: Step 301: applying a second-order Mur absorbing boundary condition on the boundary of the optimized coverage block diagram; Step 302: Configure the electromagnetic parameters of the boundary layer so that the reflection coefficient at the boundary is less than 0.05; Step 303: a gradient absorption layer with a thickness of 3H is provided in the boundary region to smoothly transition the electromagnetic field.

[0013] As a preferred technical solution of the present invention, in step 4, the target frequency band is 0 kHz to 2 GHz, and the impedance curve includes impedance values ​​at key frequency points of power integrity.

[0014] As a preferred technical solution of the present invention, it also includes: Step 5: Verify the simulation results; Compare the optimized simulation results with the full model simulation results to calculate the impedance deviation at the key frequency points.

[0015] Furthermore, when the impedance deviation exceeds an allowable deviation threshold, the expansion parameters of the initial coverage block diagram are adjusted, and steps 2 to 4 are re-executed.

[0016] Furthermore, the step of adjusting the expansion parameters of the initial coverage frame includes: Increase the preset area range of the initial coverage frame; Alternatively, the preset threshold of the current density is lowered to expand the range of the main power supply path.

[0017] As a preferred technical solution of the present invention, a method for improving the efficiency of PDN impedance simulation is implemented by the following device, which includes: PCB analysis module, used to analyze the distribution of power planes and target devices; A parameter extraction module is used to obtain the spacing value between adjacent power planes and ground planes; Boundary processing module, used to generate an initial coverage frame diagram and expand it to generate an optimized coverage frame diagram; Model tailoring module, used to tailor the simulation model based on the optimized coverage block diagram; Simulation execution module, used to perform PDN impedance simulation on the trimmed model; Verification and adjustment module, used to compare simulation results and adjust expansion parameters.

[0018] The present invention according to the above scheme has the following beneficial effects: The present invention locates the initial coverage diagram through the distribution of power planes and target devices, focuses on the core area, eliminates irrelevant areas, and only expands the edge field of the core area by 7 times the baseline value, effectively reducing the simulation model area, shortening the simulation time, and improving the simulation efficiency; In addition, the present invention adopts an expansion strategy of 7 times the benchmark value, which can ensure coverage of more than 99% of the effective field strength and avoid the loss of accuracy caused by model tailoring. Through comparative data verification, it can be seen that the impedance curves before and after optimization basically coincide, and the deviation of the key frequency point is ≤0.12%. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the present invention;

[0020] Figure 2 This is the PDN impedance simulation curve before model optimization using the traditional method; Figure 3 This is a PDN impedance simulation curve diagram after model optimization using the method of the present invention; Figure 4 This is a comparison chart of the PDN impedance simulation curves before and after model optimization. DETAILED DESCRIPTION

[0021] To better understand the objectives, technical solutions, and technical effects of the present invention, the present invention is further explained below with reference to the accompanying drawings and embodiments. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. It should also be noted that the embodiments described below are intended only to illustrate the present invention and are not intended to limit the present invention.

[0022] It should be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may also be an intermediate element; when an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0023] like Figure 1 As shown, a method for improving the efficiency of PDN impedance simulation includes the following steps: Step 1: Determine the initial coverage diagram based on the distribution of the power plane and target devices; Step 2: Taking the maximum distance between adjacent power planes and ground planes as a reference value, the boundary of the initial coverage frame is expanded by 7 times the reference value to generate an optimized coverage frame; Step 3: based on the boundary of the optimization coverage block diagram, the simulation model is cropped. Specifically, the model outside the optimization coverage block diagram is cut off through Boolean operations, and the model part within the optimization coverage block diagram is retained, including the power plane, ground plane, decoupling capacitor, target device, etc. Step 4: Perform PDN impedance simulation on the trimmed model to obtain the impedance curve of the target frequency band.

[0024] Taking a 10-layer PCB structure of a power supply as an example, the electromagnetic field distribution of the power plane (VCC layer) and the ground plane (GND layer) directly affects the PDN impedance. The target device (such as the CPU and FPGA) is the main load of the power network, and the decoupling capacitors and power pins around it are areas of electromagnetic field concentration.

[0025] Wherein, step 1 includes: Step 101: Parse the PCB design file, which can be a Gerber file or an Altium Designer project file. The file has clear network name identification, and distinguishes the power plane layer and the ground plane layer based on the network name.

[0026] Step 102: Determine a main power supply path from the power module to the target device based on the power network topology; specifically, the steps include: Step 1021: Construct a power network topology diagram, trace the path of current from the power module to the target device based on Kirchhoff's current law and Ohm's law, and mark the shortest current path, that is, the shortest current path from the power module to the target device; Step 1022: Identify the key decoupling capacitor network on the path, with high-frequency decoupling capacitors close to the device pins and low-frequency decoupling capacitors far away from the device, and calculate the equivalent decoupling impedance Z decouple =1 / jwC, determine the node with the greatest impact on impedance; Step 1023: Extract the hotspot path where the current density exceeds the preset threshold as the main power supply path. The current density threshold is based on the PCB current carrying capacity standard. For example, when the conventional copper foil thickness is 1oz, the safe current density is about 10A / mm².

[0027] Step 103: With the main power supply path as the center and the edge field around the path, the range is about 3H, where H is the maximum distance between the power plane and the ground plane, and the area is extended to ±5mm in all directions to form an initial coverage frame.

[0028] Step 1 allows us to focus on the core areas of the power network, eliminate irrelevant areas such as blank copper foil and non-target components, and reduce the ineffective model area by over 75%, laying the foundation for subsequent efficiency improvements. Furthermore, through topology analysis and current density screening, we ensure that the initial block diagram contains over 90% of the effective electromagnetic field distribution, avoiding the omission of critical paths.

[0029] In step 2, the steps of using the maximum distance between adjacent power planes and ground planes as a reference value include: Step 201: extracting the spacing values ​​between all adjacent power planes and ground planes from the PCB stack structure parameters; Step 202: Take the maximum value of the interval values ​​as a reference value.

[0030] According to the principle of electromagnetic field mirroring, the fringe field between power and ground planes is primarily distributed within a 3H radius from the conductor. Field strength outside of 7H decays to less than 0.1% of the peak value and can be ignored. The maximum spacing, H, is used, rather than the average spacing. Specifically, extract the spacing between all adjacent power and ground planes from the PCB stackup parameters. For example, if the spacing between L1-VCC and L2-GND is 0.1mm, and the spacing between L3-VCC and L4-GND is 0.3mm, then use the maximum value, H = 0.3mm, as the baseline.

[0031] In step 2, the step of expanding the boundary of the initial coverage frame by 7 times the reference value includes: Step 203: Expand the four boundaries of the initial coverage frame by 7 times the reference value along the positive and negative directions of the X and Y axes respectively. Step 204: If the boundary after expansion exceeds the physical boundary of the PCB, truncation is performed based on the physical boundary of the PCB.

[0032] In practice, the model is expanded by 7H = 2.1mm along both the X and Y axes. Any expansion beyond the physical boundaries of the PCB is truncated to that boundary, balancing model integrity with the actual PCB structure. This 7H expansion ensures coverage of over 99% of the effective field strength. Furthermore, the maximum spacing expansion strategy makes the solution applicable to PCBs with any stacking structure, avoiding inconsistent edge field processing due to stacking variations.

[0033] In step 3, after cutting the simulation model, the following steps are also performed: Step 301: applying a second-order Mur absorbing boundary condition on the boundary of the optimized coverage block diagram; Step 302: Configure the electromagnetic parameters of the boundary layer so that the reflection coefficient at the boundary is less than 0.05. A reflection coefficient less than 0.05 reduces reflection by 90% compared to an unprocessed boundary, simulating an infinite space at the boundary. Step 303: a gradient absorption layer with a thickness of 3H is provided in the boundary area for smooth transition of the electromagnetic field; this step realizes smooth transition of the electromagnetic field by linearly decreasing the dielectric constant and avoids sudden changes in field strength at the boundary.

[0034] In step 4, the target frequency range is 0kHz to 2GHz, and the impedance curve includes impedance values ​​at key power integrity frequency points. This target frequency range, from DC to high frequencies, meets the requirements of power integrity (PI) analysis. A single simulation covers the entire frequency range, eliminating the time-consuming nature of traditional segmented simulations. The output includes a complete curve with features such as DC impedance and resonant peaks, providing comprehensive data support for power filter design.

[0035] A method for improving PDN impedance simulation efficiency of the present invention also includes: Step 5: Verify the simulation results; Compare the optimized simulation results with the full model simulation results to calculate the impedance deviation at the key frequency points.

[0036] Specifically, for a certain power supply design, the PDN impedance simulation frequency range is 1KHz to 2GHz. According to the traditional design method, the simulation time (the time from the start of the simulation to the completion of the simulation, the same below) is 65 minutes. The PDN impedance curve simulation results refer to Figure 2After the model optimization of the present invention, the simulation time is shortened to 23 minutes. The simulation results of the PDN impedance curve are shown in Figure 2. Figure 3 Compare the two simulation results in the same figure, refer to Figure 4 , the impedance of the two curves at the key frequencies (1MHz, 10MHz, 100MHz) are as follows: At 1MHz, they are 0.00178484 (ohm) and 0.00178475 (ohm) respectively; At 10MHz, they are 0.00264024 (ohm) and 0.00263969 (ohm) respectively; At 100MHz, they are 0.00233957 (ohm) and 0.00233689 (ohm) respectively; Therefore, it can be concluded that the PDN impedance curves before and after the optimization model are basically consistent, and the impedance deviation of the two curves at the key frequency points does not exceed 0.12%.

[0037] In summary, the area of ​​a traditional full-board model is 111.15mm*254.00mm. Using the method presented in this paper, we focus on the core area, eliminate irrelevant areas, and perform boundary expansion only on the edges of the core area. The optimized coverage area is 65.00mm*102.20mm, a reduction of approximately 76.47%. Simulation time is positively correlated with model size. The attached data shows that a traditional full-board simulation takes 65 minutes, while the optimized method only takes 23 minutes, a 64.6% efficiency improvement.

[0038] In addition, the present invention adopts an expansion strategy of 7 times the benchmark value, which can ensure coverage of more than 99% of the effective field strength and avoid the loss of accuracy caused by model trimming. Through comparative data verification, it can be seen that the impedance curves before and after optimization basically coincide, and the deviation of the key frequency point is ≤0.12%.

[0039] However, any simulation method is subject to model simplification errors. In extreme cases, such as very large boards or unusual electromagnetic field distributions, slight deviations may be introduced. Alternatively, the expansion parameters of the initial overlay diagram require fine-tuning based on the specific board characteristics, potentially leading to deviations during the initial simulation. Therefore, if the impedance deviation exceeds the allowable deviation threshold, the expansion parameters of the initial overlay diagram are adjusted, and steps 2 through 4 are repeated.

[0040] The step of adjusting the extended parameters of the initial coverage frame includes: Step A. Expand the preset area of ​​the initial coverage frame. This step is aimed at scenarios with large low-frequency deviations, and the initial frame is expanded to capture more low-frequency fields. Alternatively, in step B, lower the preset current density threshold, for example, from 10A / mm² to 8A / mm², to expand the range of the main power supply path. This step targets scenarios with large deviations in the high-frequency band and incorporates more high-frequency current paths.

[0041] The present invention also provides a method and apparatus for realizing the above-mentioned improvement of the efficiency of PDN impedance simulation, the apparatus comprising: PCB analysis module, used to analyze the distribution of power planes and target devices; A parameter extraction module is used to obtain the spacing value between adjacent power planes and ground planes; Boundary processing module, used to generate an initial coverage frame diagram and expand it to generate an optimized coverage frame diagram; Model tailoring module, used to tailor the simulation model based on the optimized coverage block diagram; Simulation execution module, used to perform PDN impedance simulation on the trimmed model; Verification and adjustment module, used to compare simulation results and adjust expansion parameters.

[0042] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0043] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for improving the efficiency of PDN impedance simulation, characterized in that: The following steps are involved: Step 1: Determine the initial coverage diagram based on the distribution of the power plane and target devices; Step 2: Taking the maximum distance between adjacent power planes and ground planes as a reference value, the boundary of the initial coverage frame is expanded by 7 times the reference value to generate an optimized coverage frame; Step 3: based on the boundary of the optimized coverage block diagram, cutting the simulation model and retaining the model portion within the scope of the optimized coverage block diagram; Step 4: Perform PDN impedance simulation on the trimmed model to obtain the impedance curve of the target frequency band.

2. The method for improving PDN impedance simulation efficiency according to claim 1, wherein: The step 1 comprises: Step 101: parse the PCB design file and identify the power plane layer and the ground plane layer; Step 102: Determine a main power supply path from the power module to the target device based on the power network topology. Step 103: Define the main power supply path and its surrounding preset area as an initial coverage frame diagram.

3. The method for improving PDN impedance simulation efficiency according to claim 2, characterized in that: The step 102 includes: Build a power network topology diagram and mark the shortest current path from the power module to the target device; Identify the critical decoupling capacitor network on the path and calculate the equivalent decoupling impedance of each node; The hotspot path with current density exceeding a preset threshold is extracted as the main power supply path.

4. The method for improving PDN impedance simulation efficiency according to claim 1, wherein: In step 2, the step of taking the maximum distance between adjacent power planes and ground planes as a reference value includes: Step 201: extracting the spacing values ​​between all adjacent power planes and ground planes from the PCB stack structure parameters; Step 202: Take the maximum value of the interval values ​​as a reference value.

5. The method for improving PDN impedance simulation efficiency according to claim 1, wherein: In step 2, the step of expanding the boundary of the initial coverage frame by 7 times the reference value includes: Step 203: Expand the four boundaries of the initial coverage frame by 7 times the reference value along the positive and negative directions of the X and Y axes respectively. Step 204: If the boundary after expansion exceeds the physical boundary of the PCB, truncation is performed based on the physical boundary of the PCB.

6. The method for improving PDN impedance simulation efficiency according to claim 1, wherein: In the step 3, after cutting the simulation model, the following steps are further included: Step 301: applying a second-order Mur absorbing boundary condition on the boundary of the optimized coverage block diagram; Step 302: Configure the electromagnetic parameters of the boundary layer so that the reflection coefficient at the boundary is less than 0.05; Step 303: a gradient absorption layer with a thickness of 3H is provided in the boundary region to smoothly transition the electromagnetic field.

7. The method for improving PDN impedance simulation efficiency according to claim 1, wherein: In step 4, the target frequency range is 0 kHz to 2 GHz, and the impedance curve includes impedance values ​​at key frequency points of power integrity.

8. The method for improving PDN impedance simulation efficiency according to claim 1, wherein: Also includes: Step 5: Verify the simulation results; Compare the optimized simulation results with the full model simulation results to calculate the impedance deviation at the key frequency points.

9. The method for improving PDN impedance simulation efficiency according to claim 8, characterized in that: When the impedance deviation exceeds the allowable deviation threshold, the expansion parameters of the initial coverage block diagram are adjusted, and steps 2 to 4 are re-executed.

10. The method for improving PDN impedance simulation efficiency according to claim 9, characterized in that: The step of adjusting the expansion parameters of the initial coverage frame includes: Increase the preset area range of the initial coverage frame; Alternatively, the preset threshold of the current density is lowered to expand the range of the main power supply path.

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