Rom memory and data reading method thereof, electronic device

Abstract

The application relates to the technical field of memories, and particularly provides a ROM memory, a data reading method thereof and an electronic device, which comprise a storage circuit, a reference circuit and a comparison circuit; the storage circuit comprises a multiplexer and a storage array; the reference load of the reference circuit is greater than the minimum load of a reading bit line and smaller than the maximum load; the voltage-time variation slope of a reference voltage generated during reading is smaller than the slope when a storage unit reads 0 and greater than the slope when the storage unit reads 1; the reading bit line is a bit line corresponding to the multiplexer; the comparison circuit compares the reference voltage and a reading voltage, determines an output reading digital signal, and the reading voltage is an output voltage of a reading storage unit. The application solves the problem that a large-capacity ROM read-only memory has a high load and is prone to reading errors due to slow reading speed in the prior art.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a ROM memory and its data reading method, and an electronic device. Background Technology

[0002] In related technologies, ROM memory includes: multiplexing circuits, storage matrix, inverters, such as... Figure 1 As shown, the multiplexer circuit can select to enable one column of BL (Bit Line) and one row of WL (Word Line), thus locking a specific memory cell in the memory matrix. The memory matrix consists of multiple memory cells arranged in an array, each composed of field-effect transistors (FETs). These transistors can be programmed to determine whether their gates are connected to the word lines and whether their sources or drains are connected to the bit lines. If the transistor's source or drain is programmed to be grounded, it stores 0; otherwise, it stores 1. The inverter's flip-flop voltage is a fixed threshold. After the GBL output voltage reaches the inverter's flip-flop voltage, it passes through two inverter stages to output the corresponding signal.

[0003] However, the large memory capacity of ROM and the heavy load on BL result in a large slope of the voltage signal at the input of the inverter, and the voltage change at the input of the inverter is slow, resulting in a slow reading speed of the inverter. In small-size processes, the leakage of MOSFETs is more obvious, which may cause the GBL to leak to a low level when reading 1, causing the inverter to flip and thus reading an incorrect value.

[0004] There is currently no effective solution to the problem that ROM read-only memory, due to its large capacity and high load, results in slow voltage changes at the input inverter, slow inverter read speed, and a tendency to read errors. Summary of the Invention

[0005] The present invention provides a ROM memory and its data reading method and electronic device, which at least solves the problem in the related art that the large capacity and high load of the ROM read-only memory result in slow voltage change of the input inverter, slow reading speed of the inverter, and easy reading errors.

[0006] According to one aspect of the present invention, a ROM memory is provided, comprising: a storage circuit, a reference circuit, and a comparison circuit; the storage circuit includes a multiplexer and a storage array, the storage array including a plurality of storage cells arranged in an array; the reference circuit is used to generate a reference voltage based on a reference load during reading, the reference load being greater than the minimum load of any read bit line and less than the maximum load of any read bit line, such that the voltage-time slope of the reference voltage is less than the voltage-time slope when the storage cell reads 0 and greater than the voltage-time slope when the storage cell reads 1, wherein the read bit line is the bit line corresponding to the multiplexer during reading; the two input terminals of the comparison circuit are respectively connected to the reference circuit and the storage circuit, used to compare the magnitudes of the reference voltage and the read voltage to determine a corresponding output read digital signal, wherein the read voltage is the output voltage of the storage circuit when reading data stored in the storage cell.

[0007] As an optional solution, the reference circuit includes the same number of first MOS transistors on the read bit lines and a preset number of memory cells as reference cells; one end of the source or drain of the reference cell is connected to the bit line, and the other end is grounded, so that all reference cells are stored as 0; the enable signal of the gate of one memory cell in the reference cell is the corresponding virtual word line, so that if any corresponding word line in the memory array is turned on, the virtual word line is turned on; the gates of the remaining memory cells in the reference cell are all set to a low level to ensure that the NMOS is in the off state.

[0008] As an optional approach, the preset number is greater than the number of storage units of the bit line, and the preset number is twice the number of storage units of the bit line.

[0009] As an optional solution, the reference circuit includes the same number of first MOS transistors on the read bit lines and the same number of memory cells as reference cells; the enable signal of the gate of one memory cell in the reference cell is the corresponding virtual word line, so that if any corresponding word line in the memory array is turned on, the virtual word line is turned on, and one end of the source or drain of the memory cell is connected to the bit line, and the other end is grounded, so that the reference cell is stored as 0; the source or drain of the other memory cells in the reference cell is connected to the bit line, so that the reference cell is stored as 1, and the gates of all of them are set to a low level to ensure that the NMOS is in the off state.

[0010] As an optional solution, a pre-charging device is also included, which is connected to both the reference circuit and the storage circuit; two pre-charging devices are provided, and the two pre-charging devices are respectively connected to the reference circuit and the storage circuit.

[0011] As an alternative, the comparator circuit includes two second MOS transistors; the gates of the two second MOS transistors are connected to the reference circuit and the storage circuit respectively, the sources of the second MOS transistors are connected, the drains of the second MOS transistors are connected to the first NMOS transistor, and the drain output terminal of the first MOS transistor is used to output a digital signal.

[0012] As an optional solution, the comparator circuit further includes two first PMOS transistors and two first NMOS transistors; the gate of the first PMOS transistor is connected to the drain of the other first PMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the corresponding first NMOS transistor; the gate of the first NMOS transistor is connected to the drain of the other first NMOS transistor, and the source of the first NMOS transistor is connected to the corresponding second MOS transistor; and each first PMOS transistor and the drain of the first NMOS transistor are provided with an independent pull-up circuit.

[0013] As an optional solution, the pre-charge device is a second PMOS transistor; the gate of the second PMOS transistor is connected to an enable pre-charge signal, the source of the second PMOS transistor is connected to a high-voltage terminal, and the drain of the second PMOS transistor is connected to a pre-charge circuit.

[0014] As an alternative, the comparison circuit is a sense amplifier.

[0015] According to another aspect of the present invention, a data reading method for a ROM memory is also provided, comprising: selecting a memory cell to be read based on a multiplexer of a memory circuit, and the read voltage of the bit line where the selected memory cell is located, wherein the memory circuit includes a multiplexer and a memory array, the memory array including a plurality of memory cells arranged in an array; obtaining a reference voltage in a reference circuit, wherein the reference circuit is configured to generate a reference voltage based on a reference load, the reference load being greater than the minimum load of any read bit line and less than the maximum load of any read bit line, such that the voltage-time slope of the reference voltage is less than the voltage-time slope when the memory cell is read as 0, and greater than the voltage-time slope when the memory cell is read as 1, wherein the read bit line is the bit line corresponding to the multiplexer during reading; inputting the reference voltage and the read voltage into a comparison circuit, and outputting a corresponding read digital signal from the comparison circuit, wherein the two input terminals of the comparison circuit are respectively connected to the reference circuit and the memory circuit.

[0016] As an optional approach, before the multiplexer based on the storage circuit selects the memory cell to be read and the read voltage of the bit line, the method further includes: independently pre-charging the reference circuit and the storage circuit through two independent pre-charging devices, wherein two pre-charging devices are provided, and the two pre-charging devices are respectively connected to the reference circuit and the storage circuit.

[0017] According to another aspect of the present invention, an electronic device is also provided, comprising any of the aforementioned ROM memories.

[0018] The ROM memory provided in this invention employs a comparator circuit and a reference circuit. When reading data, the reference circuit can generate a voltage change signal with a slope between reading 0 and reading 1 of the memory cell. During data reading, the output data signal can be quickly determined based on the magnitude of the reference voltage and the reading voltage. This avoids the reading voltage at reading 1 decaying to the inverter's flip threshold when the reading time is long, thus preventing read errors. This solves the problem in related technologies where the ROM memory has a high load, a large slope at the inverter's input terminal, and a slow voltage change at the input inverter, resulting in slow reading speed and easy read errors. It achieves the technical effect of faster data reading and avoiding read errors after comparing the reference voltage and the reading voltage. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other embodiments based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a ROM memory structure in the prior art.

[0021] Figure 2 This is a schematic diagram of the ROM memory structure according to an embodiment of the present invention.

[0022] Figure 3-1 This is a schematic diagram of a reference circuit structure for a ROM memory according to an embodiment of the present invention.

[0023] Figure 3-2 This is a schematic diagram of another reference circuit structure of the ROM memory according to an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the GBL and RBL voltage states in the ROM memory created by this invention.

[0025] Figure 5 This is a flowchart illustrating the implementation process of the ROM memory according to an embodiment of the present invention.

[0026] Figure 6 This is a flowchart illustrating the specific implementation process of the ROM memory in an embodiment of the present invention.

[0027] The reference numerals in the above figures are as follows: 100, storage array; 100*, storage matrix; 200, multiplexer; 200*, multiplexing circuit; 300, sense amplifier; 400, reference circuit; 500, precharge device. Detailed Implementation

[0028] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present invention. It should be understood that the drawings and embodiments of the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.

[0029] like Figure 1 As shown, a traditional ROM (Read-Only Memory) memory includes: a pre-charge device, a multiplexer circuit 200*, a storage matrix 100*, and an inverter.

[0030] The precharge device pulls the precharge enable low to turn on the PMOS (P-channel metal-oxide-semiconductor field-effect transistor) for precharge. After pulling the bit line to VDD (power supply voltage), the precharge enable is pulled high to turn the PMOS off.

[0031] Multiplexer 200 can select to enable one column of BL (Bit Line) and WL (Word Line), and can select to enable one row, thus locking a specific storage cell in storage matrix 100*.

[0032] The storage matrix 100* comprises multiple storage cells arranged in an array. These cells are composed of field-effect transistors (FETs), which can be programmed to determine whether their gates are connected to the word line WL and whether their sources or drains are connected to the bit line BL. If the transistor source or drain is grounded after programming, a 0 is stored; otherwise, a 1 is stored. A GBL (Global Bit Line) output of 0 is passed through two inverters before being output as 0. If the output is 1, because BL is high after pre-charging, the high level on BL is maintained before passing through two inverters before being output as 1.

[0033] Therefore, the time to read 0 depends on the inverter's speed. Since ROM memory capacity is typically large, the load on the input gate (BL) is heavy, resulting in a steep input slope for the inverter and a slow voltage change, leading to a slow read speed. In small-size manufacturing processes, leakage current in MOS (Metal-Oxide-Semiconductor) transistors can be significant. This can cause the GBL to leak to a low level when reading 1, causing the inverter to flip and resulting in an incorrect value being read.

[0034] To improve ROM read speed and avoid read errors, embodiments of this invention provide a ROM memory, its data read method, and an electronic device, such as... Figure 2 As shown, the system includes: a storage circuit, a reference circuit 400, and a comparator circuit. The storage circuit includes a multiplexer 200 and a storage array 100, which includes multiple storage cells arranged in an array. The reference circuit 400 generates a reference voltage based on a reference load during reading. The reference load is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time slope of the reference voltage is less than the voltage-time slope when the storage cell reads 0 and greater than the voltage-time slope when the storage cell reads 1. The read bit line is the bit line corresponding to the multiplexer 200 during reading. The two input terminals of the comparator circuit are connected to the reference circuit 400 and the storage circuit, respectively, and are used to compare the magnitudes of the reference voltage and the read voltage to determine the corresponding output read digital signal. The read voltage is the output voltage of the storage circuit when reading data stored in the storage cell.

[0035] The storage circuit provided in the embodiments of the present invention, such as Figure 2 As shown, the array includes a multiplexer 200 and a memory array 100. The multiplexer 200 consists of multiple NMOS transistors arranged in rows, including N21, N22, and N23. The gates of these NMOS transistors are selected by the SEL (select function) to enable one column of bit lines. Their drains are connected to the GBL (Gateway Block Layer), and their sources are connected to each bit line. The memory array 100 includes multiple memory cells arranged in an array. These memory cells include NMOS transistors N11, N12, N13, N14, N15, N16, N17, N18, and N19. These NMOS transistors can be programmed to determine whether their gates are connected to word lines and whether their sources or drains are connected to bit lines. If the transistor's source or drain is grounded after programming, a 0 is stored; otherwise, if the transistor's source or drain is not grounded after programming, a 1 is stored.

[0036] The first MOSFET can be either a PMOS or an NMOS. In this embodiment, an NMOS is used as the first MOSFET, which has advantages over a PMOS, such as faster switching speed, higher energy efficiency, and higher integration density.

[0037] The reference circuit 400 provided in the embodiments of the present invention, such as... Figure 2 As shown, the drain of N41 in the reference circuit 400 is connected to the drain of P51 in the precharge device, and the drain of N41 in the reference circuit 400 is connected to the gate of N32 in the comparator circuit.

[0038] In related technologies, the scheme using inverters for reading data suffers from increased read time and significant leakage due to the limitations of the inverter's flip point and flip time. This can lead to a situation where, when reading a 1, the GBL leaks to a low level, causing the inverter to flip and resulting in an incorrect reading of a 0. For example... Figure 4 As shown, the black line of RBL (Read Bit-Line) represents the reference voltage change, the red line of GBL represents the voltage change when reading 0 from the memory cell, and the blue line of GBL represents the voltage change when reading 1 from the memory cell. When reading data, the reference circuit 400 can generate a voltage change signal with a slope that is always between reading 0 and reading 1 from the memory cell. When reading data, the output data signal can be quickly determined based on the magnitude of the reference voltage and the reading voltage of the memory cell, avoiding the reading voltage at the time of reading 1 decaying to the toggling threshold of the inverter when the reading time is long, which would lead to reading errors.

[0039] The comparator circuit has two input terminals, connected to the drain of reference circuit 400 (N41) and the drain of storage circuit (N23), respectively. The comparator circuit compares the magnitudes of two voltages and can be categorized into three main types: analog comparator circuits, digital comparator circuits, and mixed-signal comparator circuits. This example uses a digital comparator circuit, which offers advantages such as low cost, flexibility, and seamless integration with digital systems.

[0040] The ROM memory provided in this embodiment employs a comparator circuit and a reference circuit 400. When reading data, the reference circuit 400 generates a voltage change signal with a slope between the read 0 and read 1 values ​​of the memory cell. During data reading, the output data signal can be quickly determined based on the magnitude of the reference voltage and the read voltage, avoiding read errors caused by the read voltage at read 1 decaying to the inverter's flip-flop threshold when the read time is long. This solves the problem in related technologies where high ROM memory load, a large input slope of the inverter, and slow voltage change at the input inverter lead to slow read speeds and frequent read errors. It achieves the technical effect of faster data reading and avoiding read errors by comparing the reference voltage and the read voltage.

[0041] As an optional solution, the reference circuit 400 includes the same number of first MOS transistors N41 on the read bit lines, and a preset number of memory cells N42 and N43 as reference cells; one end of the source or drain of the reference cells N42 and N43 is connected to the bit line, and the other end is grounded, so that all reference cells are stored as 0; the enable signal of the gate of one memory cell N42 in the reference cell is the corresponding virtual word line, so that if any corresponding word line in the memory array 100 is turned on, the virtual word line is also turned on; the gates of the remaining memory cells N43 in the reference cell are all set to a low level to ensure that the memory cells are in a turned-off state.

[0042] Designing the same number of first MOSFETs allows for a complete match of the PVT (PVT is an abbreviation for three key environmental parameters, representing process, voltage, and temperature) sensitivity parameters between the two, thus offsetting the effects of external environmental changes and ensuring consistent attenuation characteristics between the reference signal and the bit line signal.

[0043] The reference cells are preset to store 0, with the aim of providing a reference voltage representing 0. The preset number matches the number of storage cells on the bit line, which can simulate the actual load conditions of the bit line, so that the reference voltage accurately reflects the real voltage of the bit line in the 0 state, avoiding comparison errors caused by load differences.

[0044] The purpose of designing virtual word lines is to ensure that when any word line corresponding to a bit line in the memory array 100 is turned on, the virtual word line is simultaneously turned on, causing the corresponding MOS transistor N42 in the reference cell to conduct, and the reference circuit 400 to enter the working state. This synchronous design ensures that the reference signal and the bit line signal are in sync, avoiding misreading caused by the reference signal being ahead or behind.

[0045] TIE0 indicates that the gate of transistor N43 is permanently connected to a logic low level, forcing it to be off or held in a fixed state. On the bit line, except for the selected memory cell, the select transistors of the unselected cells are all in the off state, but these cells still affect the rate of voltage change on the bit line through their off select transistors. It can simulate the unselected load on the bit line, ensuring that the load on the reference bit line perfectly matches the actual bit line.

[0046] As an optional approach, the preset number is greater than the number of storage units in the bit line, and the preset number is twice the number of storage units in the bit line.

[0047] The reference circuit 400 provided in the embodiments of the present invention, such as... Figure 3-1As shown, if the number of reference cells is equal to the number of memory cells on the bit line (assumed to be N) and all are 0, the reference voltage is essentially the reference voltage after pulling down N 0-cells. This may be too close, leading to insufficient margin for distinguishing between 0 and 1, especially in low-voltage scenarios. The pull-down capability of 2N 0-cells is twice that of N cells, and the total pull-down current is larger after parallel connection, pulling the reference bit line voltage lower than that of N 0-cells. This lower reference voltage can create a larger voltage difference with the read voltage of the 1 state on the bit line, while maintaining a reasonable distance from the 0 state, making the comparator's read bit line voltage more balanced with the reference voltage, reducing misjudgments caused by close voltages.

[0048] The pull-down capability of a single memory cell can exhibit random process variations, leading to unstable voltage characteristics in that cell. When the number of reference cells is small, these random variations directly impact the stability of the reference voltage. However, by using 2N reference cells, the characteristics of multiple cells are statistically averaged to offset the random variations, thus diluting the impact of anomalies in a single cell on the overall reference voltage.

[0049] In high-density memories, bit lines may be slightly pulled down by other cells due to adjacent channel interference, effectively increasing the load. Setting the number of reference cells to 2N better adapts to the actual load on the bit lines, ensuring read reliability in complex scenarios.

[0050] As an alternative, reference circuit 400, such as Figure 3-2 As shown, the array includes the same number of first MOS transistors N41* on the read bit lines and the same number of memory cells, including N42* and N43* as reference cells. The enable signal of the gate of one memory cell N42* in the reference cells is the corresponding virtual word line, so that when any corresponding word line in the memory array 100 is turned on, the virtual word line is turned on. The source or drain of other reference cells, such as N43*, is connected to the bit line at one end and grounded at the other end, so that the reference cell is stored as 0. The source or drain of other memory cells in the reference cells is connected to the bit line, so that the reference cell is stored as 1, and the gate of each cell is set to a low level to ensure that the memory cell is in the off state.

[0051] The design of partially storing 0 and partially storing 1 is to make the reference voltage closer to the bit line voltage characteristics of random data in the actual storage array 100, and to avoid misjudgment caused by extreme data distribution (such as all 0 or all 1). The reference cell simulates the average effect of this random distribution by mixing the cells storing 0 and the cells storing 1, so that the reference voltage is exactly at the middle value between the all 0 bit line voltage and the all 1 bit line voltage.

[0052] The reference cell storing 0 is hard-connected with its source and drain ends grounded to ensure its state is stable at 0; the reference cell storing 1 is connected to TIE0 through its gate, keeping it always in the on state and stably storing 1. This design avoids state fluctuations caused by noise, charge leakage, or other issues in the reference cell itself, ensuring a stable output of the reference voltage. If the reference cell state is unstable, the reference voltage will fluctuate drastically, directly leading to read errors.

[0053] If the source or drain of the reference cell MOSFET is either unconnected or both connected to bit lines, a value of 1 is read. This can be controlled by programming. In this example, it is preferable to use a configuration where both the source and drain of the MOSFET are grounded to store the reference cell as 1. Connecting both the source and drain to bit lines allows the 1 state of the reference cell to share the same electrical environment, synchronize dynamic response, and share PVT changes with the 1 state of the actual storage cell. This ensures a high degree of consistency in their characteristics, achieving stable reference voltage and accurate signal determination by the read circuit.

[0054] As an optional solution, a pre-charge device 500 is also included, which is connected to both the reference circuit 400 and the storage circuit; two pre-charge devices 500 are provided, and the two pre-charge devices 500 are connected to the reference circuit 400 and the storage circuit respectively.

[0055] like Figure 2 As shown, the drain of P51 in the precharge device 500 is connected to the reference bit line RBL in the reference circuit 400, and the drain of P52 in the precharge device 500 is connected to the global bit line GBL in the storage circuit.

[0056] The precharge device 500 precharges the storage circuit bit lines and the reference circuit 400 bit lines, sets the PREEN signal to low level to enable P51 and P52 for precharging, and pulls the GBL and RBL levels high to VDD.

[0057] The storage circuit connected to the precharge device 500 quickly charges the bit line to a high position in preparation for reading the 0 state; the reference circuit 400 connected to the precharge device 500 charges the reference bit line to VDD, which needs to be stable and accurate.

[0058] If a single pre-charge device 500 is used, inconsistent charging times may occur due to load differences, and the charging and discharging noise of the storage circuit may interfere with the stability of the reference voltage. Setting up two pre-charge devices 500 with independent pre-charging ensures that their timing does not affect each other, and the charging current or timing can be adjusted according to their respective needs.

[0059] The precharge power consumption of the storage circuit is typically high, while the reference circuit 400 only needs to maintain a stable low current. In standby mode, only the precharge of the reference circuit 400 can be activated to maintain a stable reference voltage, while the precharge of the storage circuit can be paused, further reducing power consumption. Independent power supply avoids over-designing the power supply of the reference circuit 400 to meet the storage precharge requirements, thus achieving the effect of reducing overall power consumption.

[0060] As an alternative, the comparator circuit is as follows: Figure 2 As shown, it includes two second MOS transistors N32 and N33; the gates of the two second MOS transistors N32 and N33 are connected to the RBL of the reference circuit 400 and the GBL of the storage circuit, respectively; the sources of the second MOS transistors N32 and N33 are connected; the drains of the second MOS transistors N32 and N33 are connected to the first NMOS transistors N34 and N35; and the drain output terminals of the first NMOS transistors N34 and N35 are used to output digital signals.

[0061] An inverter is also provided at the output. The gate of NMOS transistor N31 is connected to the enable precharge signal, and the drain of N31 is connected to the source of the second MOS transistors N32 and N33. The source of N31 is grounded. N31 is turned on by the NMOS transistor at a low level to quickly discharge the input circuit.

[0062] During memory reads, the voltage difference between the bit lines of the memory cell and the reference cell is typically very small, making direct identification prone to errors. The structure of two first PMOS transistors P38 and P39 and two first NMOS transistors N34 and N35 forms a positive feedback mechanism, amplifying the initial small voltage difference step by step until it quickly stabilizes at a defined level. This circuit rapidly amplifies the small voltage difference to a digital level, achieving high sensitivity. This structure ensures accurate differentiation between 0 and 1 states, avoiding read errors.

[0063] The second MOS transistors N32 and N33 directly convert the bit line voltage difference into a current difference, reducing intermediate conversion steps; the two first PMOS transistors P38 and P39 and the two first NMOS transistors N34 and N35 directly drive the subsequent circuits, further shortening the delay and improving the memory read speed.

[0064] As an optional solution, the comparator circuit also includes two first PMOS transistors P38 and P39 and two first NMOS transistors N34 and N35; the gate of the first PMOS transistor P38 is connected to the drain of the other first PMOS transistor P39, and the drain of the first PMOS transistor P38 is connected to the drain of the corresponding first NMOS transistor N34; the gate of the first NMOS transistor N34 is connected to the drain of the other first NMOS transistor N35, and the source of the first NMOS transistor N34 is connected to the corresponding second MOS transistor N32; and each of the first PMOS transistors P38 and P39 and the drain of the first NMOS transistors N34 and N35 is provided with an independent pull-up circuit.

[0065] The structure provided by the embodiments of the present invention, such as Figure 2 As shown, the gate of P38 is connected to the drain of P39, and the drain of P38 is connected to the drain of N34; the gate of P39 is connected to the drain of P38, and the drain of P39 is connected to the drain of N35; the gate of N34 is connected to the drain of N35, and the source of N34 is connected to the drain of the corresponding second MOSFET N32; the gate of N35 is connected to the drain of N34, and the source of N35 is connected to the drain of the corresponding second MOSFET N33.

[0066] P36 and P37 pull the drain nodes A and C of P38 and P34 high, respectively, and the drains of P36 and P37 are connected to the drains of P38 and P34, respectively. P40 and P41 pull the drain nodes B and D of P39 and P35 high, respectively, and the drains of P40 and P41 are connected to the drains of P39 and P35, respectively. The sources of P36, P40, P37, and P41 are connected to the positive terminal of the power supply. In the pull-up circuit, the gates of PMOS P36, P40, P37, and P41 are all controlled by the enable signal.

[0067] The symmetrical design of the two first PMOS transistors P38 and P39 and the two first NMOS transistors N34 and N35 allows the effects of process deviations on both sides to cancel each other out, further improving stability.

[0068] An independent pull-up circuit can pull the input node up to a preset voltage, allowing the circuit to operate in the most sensitive region, maximizing its response to small input voltage differences, and achieving precise control of the comparison bias point.

[0069] The gates of the second MOSFETs N32 and N33 draw almost no current, avoiding interference with the voltage of the read bit line and ensuring that the detected state is the true state of the memory cell, thus achieving accurate reading.

[0070] The drains of the second MOSFETs N32 and N33 are connected only to the gates of N34 and N35, reducing the load on the bit lines and increasing the bit line charging and discharging speed, thereby improving the ROM read speed.

[0071] As an optional solution, the pre-charge device 500 is a second PMOS transistor P51 and P52; the gates of the second PMOS transistors P51 and P52 are connected to the enable pre-charge signal, the sources of the second PMOS transistors P51 and P52 are connected to the high-voltage terminal, and the drains of the second PMOS transistors P51 and P52 are connected to the pre-charge circuit.

[0072] The pre-charging device 500 provided in the embodiments of the present invention, such as... Figure 2 As shown, the gate of the second PMOS transistor P51 is connected to the enable precharge signal, the source of P51 is connected to the high voltage terminal, the drain of P51 is connected to the RBL of the reference circuit 400, and the drain of P52 is connected to the GBL of the memory circuit.

[0073] PMOS transistors are typically used to pull the precharged node high to VDD, while NMOS transistors are suitable for quickly pulling the node to GND. In the precharge device 500, the precharge device uses a PMOS transistor to precharge the memory bit line to VDD, and then discharges it through the memory cell to determine 0 or 1. In the comparator circuit, a PMOS transistor is used to pull the level high to establish a reference voltage.

[0074] As an alternative, the comparator circuit is a sense amplifier.

[0075] The sensing amplifier can be a voltage-type sensing amplifier or a current-type sensing amplifier; this embodiment uses a voltage-type sensing amplifier. A sensing amplifier is a circuit that rapidly amplifies the weak voltage difference output from the memory cell to a standard logic level, thereby enabling accurate data reading. It has a relatively sensitive and accurate voltage comparison function and can be directly applied to ROMs without requiring changes to the ROM design circuit, resulting in low modification costs.

[0076] When a memory cell is read, the signal output through the bit line is often very weak. These weak signals cannot be directly recognized by subsequent circuits and are susceptible to noise interference during transmission. A sensing amplifier can quickly detect minute voltage differences on the bit line, efficiently amplify them to standard logic levels, accelerate bit line discharge and charging, shorten the read cycle, and thus improve memory read speed.

[0077] like Figure 5 As shown, according to another aspect of the present invention, a data reading method for a ROM memory is also provided, comprising: step S101, selecting the memory cell to be read based on the read voltage of the bit line of the memory cell to be read based on the multiplexer 200 of the memory circuit, wherein the memory circuit includes the multiplexer 200 and the memory array 100, and the memory array 100 includes a plurality of memory cells arranged in an array.

[0078] Step S102: Based on the reference circuit 400, obtain a reference voltage. The reference circuit 400 is configured to generate a reference voltage based on a reference load. The reference load is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time change slope of the reference voltage is less than the voltage-time change slope when the memory cell reads 0 and greater than the voltage-time change slope when the memory cell reads 1. The read bit line is the bit line corresponding to the memory circuit during reading.

[0079] Step S103: Input the reference voltage and the read voltage into the comparison circuit, and the comparison circuit outputs the corresponding read digital signal. The two input terminals of the comparison circuit are connected to the reference circuit and the storage circuit, respectively.

[0080] The data reading method for the ROM memory provided in this embodiment uses a comparison circuit to compare the reference voltage and the read voltage. Since the slope of the voltage change signal of the reference circuit is between the read 0 and read 1 of the memory cell, the output data signal can be quickly determined according to the magnitude of the reference voltage and the read voltage when reading data. This avoids the problem of read error caused by the read voltage at the read 1 position decaying to the flip threshold of the inverter when the read time is long. Thus, it solves the problem of slow reading speed and easy read error caused by the high load of the ROM memory, the large slope of the inverter input terminal, and the slow voltage change of the input inverter in the related technology. It achieves the technical effect of faster data reading after comparing the reference voltage and the read voltage and avoiding read error.

[0081] The embodiments of this invention also provide a specific data reading process for a ROM memory, such as... Figure 6 As shown, data reading begins. First, the row and column of the storage array 100 are selected according to the address. Then, one of the multiplexers 200 is enabled according to the address lines. By enabling SEL0, the corresponding bit line BL0 is enabled, and the SEL of the reference circuit 400 is simultaneously enabled to activate the reference circuit 400. Since the source and drain of N11 in the storage array 100 are connected to BL0 and VSS respectively, the data to be read is 0. In this embodiment, the example of enabling N11 and N21 is used for illustration.

[0082] Precharge the memory bit lines and reference lines by setting the PREEN signal low to enable P51 and P52 for precharging, pulling the GBL and RBL levels high to VDD, and pulling nodes A, B, C, and D high.

[0083] Pre-charging is disabled while ensuring the word line is open for data reading. During data reading, the PREEN signal is set high to terminate charging of GBL and RBL, and N31 is simultaneously turned on to initiate the comparison process of the sense amplifier. After WL0 is turned on, transistor N11 pulls down BL0 and transmits the BL0 signal to GBL through the transmission gate of multiplexer 200, which is then coupled to the input of sense amplifier N33. At the same time, DWL and WL0 are turned on simultaneously, and transistor N42 pulls down RBL through the already turned-on N41, coupling it to the input of sense amplifier N32.

[0084] The sensing amplifier ultimately achieves rail-to-rail output. In the case of a zero read (discharge process), the load on RBL in reference circuit 400 is greater than the load on BL in memory array 100. Therefore, the slope of RBL is greater than the slope of GBL. Figure 4 In the black and red lines, the voltage of RBL is greater than that of GBL within the same time period, and the voltage of the gate terminal of N32 is greater than that of the gate terminal of N33. This makes the voltage of node D slightly higher than that of C, and the voltage of node B greater than that of node A. As a result, the turn-on time of P39 is earlier than that of P38, which further increases the voltage of node B to achieve rail-to-rail output: out1 outputs 1, out2 outputs 0.

[0085] In the case of reading 1 (discharge process), RBL in reference circuit 400 is the process of reading 0. The leakage rate of GBL is definitely less than that of RBL. Figure 4 The black and blue lines in the middle indicate that, within the same time frame, the voltage of RBL is less than that of GBL, and the gate voltage of N32 is less than that of N33. This causes the voltage of node D to be lower than that of C, and the voltage of node B to be lower than that of node A. Consequently, the turn-on time of P39 is later than that of P38, further lowering the voltage of node B to achieve rail-to-rail output: out1 outputs 0, and out2 outputs 1.

[0086] The aforementioned rail-to-rail output refers to the ability of a device's output voltage to closely approximate the upper and lower limits of its input voltage, where "rail" refers to the circuit's input voltage. In this circuit, the rail-to-rail output utilizes a positive feedback structure of two first PMOS transistors (P38 and P39) and two first NMOS transistors (N34 and N35) to amplify a small input voltage difference. This structural characteristic ensures that the amplified voltage reaches the voltage rail limits. Combined with a pre-charge device to eliminate intermediate-state interference, this ultimately achieves a stable output at VDD or 0V. This characteristic is crucial for data comparison; only rail-to-rail output can clearly distinguish between "0" and "1," avoiding reading errors.

[0087] As an optional approach, before the storage circuit-based multiplexer 200 selects the storage cell to be read and the read voltage of the bit line, the method further includes: independently precharging the reference circuit 400 and the storage circuit through two independent precharging devices, wherein two precharging devices are provided and the two precharging devices are connected to the reference circuit 400 and the storage circuit respectively.

[0088] If a precharge device is shared, the bit lines of the storage circuit may connect to multiple storage cells. Current fluctuations and charge transfers during precharge may interfere with the reference circuit 400 through the shared path. Precharge noise in the reference circuit 400 may also affect the precharge stability of the storage circuit bit lines.

[0089] During independent pre-charging, the pre-charging paths of the two circuits are completely isolated. Load changes and charge fluctuations in the storage circuit will not be transmitted to the reference circuit 400, ensuring that the reference voltage is always maintained at the preset accurate value, providing a reliable benchmark for subsequent sensing comparison.

[0090] Independent pre-charging allows for parameter optimization tailored to the characteristics of both circuits. The storage circuit aims for rapid and stable large capacitance, while the reference circuit 400 aims for precise achievement of the reference value. This avoids slow pre-charging of the storage circuit due to shared pre-charging, which slows down the overall process, or overcharging of the reference circuit 400 due to high current pre-charging. This shortens the total pre-charging time and improves read speed.

[0091] Independent precharge, through a physically isolated path, makes the charge of the storage circuit bit line and the reference circuit 400 completely independent. Even if there is local leakage or noise, they will not affect each other, ensuring that both are in a stable initial voltage state when reading starts, reducing sensing errors caused by voltage drift and increasing the accuracy of ROM memory reading.

[0092] According to another aspect of the present invention, an electronic device is also provided, comprising any of the aforementioned ROM memories.

[0093] ROM memory is an important type of non-volatile storage device in electronic devices. Non-volatile means that data is not lost after power is turned off. The characteristic of ROM memory is that once information is written or preset by the factory, it can still be stored for a long time after power is turned off. During normal operation, it is mainly used to read data, and the write operation is usually limited by factory programming, high voltage programming, etc.

[0094] The aforementioned factory programming refers to the process of writing or configuring programs on electronic devices in a factory production environment. High-voltage programming is a memory programming technique that primarily utilizes higher voltages to perform programming operations.

[0095] Embodiments of the present invention also provide a non-transitory machine-readable medium storing a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform a method according to an embodiment of the present invention.

[0096] Embodiments of the present invention also provide a computer program product, including a computer program, wherein the computer program, when executed by a computer's processor, is used to cause the computer to perform the method of an embodiment of the present invention.

[0097] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor. The memory stores a computer program executable by the at least one processor, which, when executed by the at least one processor, causes the electronic device to perform the method of the embodiment of the present invention.

[0098] It should be noted that the term "comprising" and its variations used in the embodiments of this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The modifications of "one" and "a plurality" mentioned in the embodiments of this invention are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated otherwise in the context, they should be understood as "one or more".

[0099] The steps described in the method embodiments provided by the present invention can be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of protection of the present invention is not limited in this respect.

[0100] The term "embodiment" in this specification refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply the same embodiment, nor does it imply independence or alternativeity from other embodiments. The various embodiments in this specification are described in a related manner, with reference to each other for similar or identical parts. In particular, for apparatus, device, and system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, and relevant details are referred to in the description of the method embodiments.

[0101] The above-described embodiments are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A ROM memory, characterized in that, Includes: storage circuit, reference circuit, and comparator circuit; The storage circuit includes a multiplexer and a storage array, the storage array including a plurality of storage cells arranged in an array; The reference circuit is used to generate a reference voltage based on a reference load during reading. The reference load is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time change slope of the reference voltage is less than the voltage-time change slope when the memory cell is read as 0 and greater than the voltage-time change slope when the memory cell is read as 1. The read bit line is the bit line corresponding to the multiplexer during reading. The two input terminals of the comparison circuit are respectively connected to the reference circuit and the storage circuit, and are used to compare the magnitudes of the reference voltage and the read voltage to determine the corresponding output read digital signal. The read voltage is the output voltage of the storage circuit when reading data stored in the storage unit. The reference circuit includes the same number of first MOS transistors on the read bit line, and a preset number of memory cells as reference cells; one end of the source or drain of the reference cell is connected to the bit line, and the other end is grounded, so that all reference cells are stored as 0. The enable signal of the gate of one memory cell in the reference unit is the corresponding virtual word line, so that when any corresponding word line in the memory array is turned on, the virtual word line is also turned on; the gates of the remaining memory cells in the reference unit are all set to a low level to ensure that the memory cells are in a turned-off state.

2. The ROM memory according to claim 1, characterized in that, The preset number is greater than the number of storage units of the bit line, and the preset number is twice the number of storage units of the bit line.

3. The ROM memory according to claim 1, characterized in that, It also includes a pre-charging device, which is connected to both the reference circuit and the storage circuit; Two pre-charge devices are provided, and the two pre-charge devices are respectively connected to the reference circuit and the storage circuit.

4. The ROM memory according to claim 3, characterized in that, The pre-charge device is a second PMOS transistor; The gate of the second PMOS transistor is connected to the enable precharge signal, the source of the second PMOS transistor is connected to the high voltage terminal, and the drain of the second PMOS transistor is connected to the precharge circuit.

5. The ROM memory according to claim 1, characterized in that, The comparator circuit includes two second MOSFETs; The gates of the two second MOS transistors are connected to the reference circuit and the storage circuit, respectively. The sources of the second MOS transistors are connected to ground through an NMOS transistor. The drains of the second MOS transistors are connected to the first NMOS transistor. The drain output terminal of the first NMOS transistor is used to output the digital signal.

6. The ROM memory according to claim 5, characterized in that, The comparator circuit also includes two first PMOS transistors and two first NMOS transistors; The gate of the first PMOS transistor is connected to the drain of another first PMOS transistor, and the drain of the first PMOS transistor is connected to the drain of the corresponding first NMOS transistor. The gate of the first NMOS transistor is connected to the drain of another first NMOS transistor, and the source of the first NMOS transistor is connected to the drain of the corresponding second MOS transistor. Each of the first PMOS transistors and the first NMOS transistors has an independent pull-up circuit at its drain.

7. The ROM memory according to claim 6, characterized in that, The comparison circuit is a sensing amplifier.

8. A ROM memory, characterized in that, Includes: storage circuit, reference circuit, and comparator circuit; The storage circuit includes a multiplexer and a storage array, the storage array including a plurality of storage cells arranged in an array; The reference circuit is used to generate a reference voltage based on a reference load during reading. The reference load is greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time change slope of the reference voltage is less than the voltage-time change slope when the memory cell is read as 0 and greater than the voltage-time change slope when the memory cell is read as 1. The read bit line is the bit line corresponding to the multiplexer during reading. The two input terminals of the comparison circuit are respectively connected to the reference circuit and the storage circuit, and are used to compare the magnitudes of the reference voltage and the read voltage to determine the corresponding output read digital signal. The read voltage is the output voltage of the storage circuit when reading data stored in the storage unit. The reference circuit includes the same number of first MOS transistors on the read bit lines and the same number of memory cells as reference cells; the enable signal of the gate of one memory cell in the reference cell is the corresponding virtual word line, so that if any corresponding word line in the memory array is turned on, the virtual word line is turned on, and one end of the source or drain of the memory cell is connected to the bit line and the other end is grounded, so that the reference cell is stored as 0. The source or drain of the other memory cells in the reference cell is connected to the bit line so that the reference cell is stored as 1, and the gate is set to low level to ensure that the memory cell is in a closed state.

9. A method for reading data from a ROM memory, characterized in that, include: The storage circuit uses a multiplexer to select the storage cell to be read and the read voltage of the bit line where it is located. The storage circuit includes a multiplexer and a storage array, and the storage array includes multiple storage cells arranged in an array. A reference voltage is obtained based on a reference circuit, wherein the reference circuit is configured to generate a reference voltage based on a reference load, the reference load being greater than the minimum load of any read bit line and less than the maximum load of any read bit line, so that the voltage-time change slope of the reference voltage is less than the voltage-time change slope when the memory cell reads 0 and greater than the voltage-time change slope when the memory cell reads 1, wherein the read bit line is the bit line corresponding to the multiplexer during reading; The reference voltage and the read voltage are input to the comparison circuit, and the comparison circuit outputs the corresponding read digital signal. The two input terminals of the comparison circuit are respectively connected to the reference circuit and the storage circuit. The reference circuit includes the same number of first MOS transistors on the read bit lines and a preset number of memory cells as reference cells. One end of the source or drain of the reference cell is connected to the bit line, and the other end is grounded, so that all reference cells are stored as 0. The enable signal of the gate of one memory cell in the reference cell is the corresponding virtual word line, so that if any corresponding word line in the memory array is turned on, the virtual word line is turned on. The gates of the remaining memory cells in the reference cell are all set to a low level to ensure that the memory cells are in a turned-off state. Alternatively, the reference circuit includes the same number of first MOS transistors on the read bit lines and the same number of memory cells as reference cells; the enable signal of the gate of one memory cell in the reference cell is the corresponding virtual word line, so that if any corresponding word line in the memory array is turned on, the virtual word line is turned on, and one end of the source or drain of the memory cell is connected to the bit line, and the other end is grounded, so that the reference cell is stored as 0; the source or drain of the other memory cells in the reference cell is connected to the bit line, so that the reference cell is stored as 1, and the gate of each memory cell is set to a low level to ensure that the memory cell is in a closed state.

10. The method according to claim 9, characterized in that, Before the read voltage of the bit line where the memory cell to be read is selected by the multiplexer based on the memory circuit, the method further includes: The reference circuit and the storage circuit are precharged independently by separate precharge devices. Two precharge devices are provided, and the two precharge devices are respectively connected to the reference circuit and the storage circuit.

11. An electronic device, characterized in that, Includes the ROM memory as described in any one of claims 1 to 8.

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