Resistive memory device and writing method thereof

Abstract

The invention provides a resistive memory device and a writing method thereof. Included in a resistive memory device is: at least one memory cell; a reference resistance value of the reference resistance circuit is adjusted; a sense amplifier configured to read data stored in the at least one memory cell by comparing a resistance value of the at least one memory cell with a reference resistance value of a reference resistance circuit; a write driver configured to program data requested to be written into the at least one memory cell; and a selective write controller. The selective write controller performs a pre-write read operation by adjusting a reference resistance value of the reference resistance circuit according to write data during the selective write operation.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0039536 filed on March 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a memory device, and more particularly, to a semiconductor memory device, and more particularly, to a resistive memory device capable of improving selective writing performance and a writing method thereof. Background Art

[0003] Semiconductor memory devices can be broadly categorized as volatile memory and non-volatile memory. Volatile memory (e.g., DRAM or SRAM) offers fast read and write speeds but loses stored data when power is cut off. On the other hand, non-volatile memory (e.g., magnetoresistive random access memory (MRAM) or flash memory) retains data even when power is interrupted.

[0004] A magnetic random access memory (MRAM) memory cell consists of a magnetic tunnel junction (MTJ) element whose resistance changes according to data, and an access transistor. MRAM write operations are performed by activating the access transistor via a word line and applying a large current, which changes the data in the MTJ element. The value of the data recorded in the MTJ element changes depending on the direction of the current.

[0005] Writing data into an MRAM memory cell requires a large current, as well as high wordline and write voltages. Consequently, a significant amount of power is consumed during MRAM write operations. A selective write method can be used to reduce the power required for MRAM write operations. This method skips data writing when the data stored in the memory cell is the same as the write data. To use the selective write method, a read-before-write operation must be performed to read the data stored in the MRAM memory cell before the write operation. However, the low reliability of MRAM read-before-write operations due to various factors is becoming a problem. Summary of the Invention

[0006] Embodiments of the present disclosure provide a resistive memory device and a writing method thereof capable of improving the reliability of a selective writing operation.

[0007] A resistive memory device that performs a selective write operation is provided herein, the resistive memory device comprising: at least one memory cell; a reference resistance circuit having an adjusted reference resistance value; a sense amplifier configured to read existing data stored in the at least one memory cell by comparing the resistance value of the at least one memory cell with the reference resistance value of the reference resistance circuit; a write driver configured to program write data into the at least one memory cell; and a selective write controller configured to perform a read-before-write operation by adjusting the reference resistance value of the reference resistance circuit according to the write data during the selective write operation.

[0008] A method for performing a selective write operation in a resistive memory device is also provided herein, the method comprising: receiving write data to be written into a selected memory cell; increasing or decreasing a reference resistance for a read-before-write operation on the selected memory cell according to a value of the write data to obtain a changed reference resistance; performing a read-before-write operation on the selected memory cell according to the changed reference resistance; and writing the write data into the selected memory cell according to a result of the read-before-write operation.

[0009] A resistive memory device is also provided herein, comprising: a cell array including a plurality of MRAM cells; a row decoder configured to drive word lines of the plurality of MRAM cells in response to a row address; a read / write circuit connected to a bit line or a source line of the cell array and configured to perform a read-before-write operation on a selected memory cell based on a reference resistance value of a reference resistance circuit during a selective write operation; and a control circuit configured to adjust a reference resistance value of the reference resistance circuit according to write data during the selective write operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a resistive memory device according to example embodiments.

[0012] Figure 2 It shows Figure 1 Schematic diagram of an exemplary configuration of a cell array.

[0013] Figure 3 Shows how data is written Figure 2 Schematic diagram of a memory cell.

[0014] Figure 4 is a diagram illustrating a structure of a read / write circuit that performs a selective write operation of example embodiments.

[0015] Figure 5 is a diagram illustrating a reference resistance that varies according to write data during a read-before-write operation of example embodiments.

[0016] Figure 6 is a block diagram illustrating a construction of a selective write controller according to example embodiments.

[0017] Figure 7 It shows that according to Figure 6 Flowchart of a selective write operation in which data is written in a separate write phase.

[0018] Figure 8 is a block diagram illustrating a selective write controller according to another example embodiment.

[0019] Figure 9 It is shown by Figure 8 Flowchart of a selective write operation performed by a selective write controller.

[0020] Figure 10 It is shown in accordance with Figure 6 FIG1 is a timing diagram of the internal operation of a resistive memory device during a selective write operation of writing data in a separate write phase.

[0021] Figure 11 is shown in Figure 8 1 is a timing diagram of the internal operation of a resistive memory device during a selective write operation performed by a selective write controller shown in FIG. DETAILED DESCRIPTION

[0022] It will be understood that both the foregoing general description and the following detailed description are exemplary. Reference symbols are indicated in detail in the embodiments, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals are used in the specification and drawings to represent the same or similar parts.

[0023] Hereinafter, the advantages of the embodiments will be explained using magnetoresistive random access memory (MRAM) as an example. However, those skilled in the art will readily understand other advantages and capabilities of the embodiments based on the content described herein. The embodiments may be implemented or applied in various ways. Furthermore, the detailed description may be modified or changed depending on the viewpoint and application without significantly departing from the scope and technical spirit of the embodiments provided herein.

[0024] Figure 1 is a block diagram showing a resistive memory device according to an embodiment. Figure 1, the resistive memory device 1000 may include a cell array 1100 , a row decoder 1200 , a column decoder 1300 , a read / write circuit 1400 , an input / output (I / O) circuit 1500 , a control circuit 1600 , and a voltage generator 1700 .

[0025] The cell array 1100 may include a plurality of MRAM cells or bit cells that store data. Each of the plurality of bit cells included in the cell array 1100 may be arranged at a point where a plurality of word lines WL, a plurality of bit lines BL, and a source line SL intersect. For example, each bit cell may be connected to a corresponding word line among the plurality of word lines WL. Each bit cell may be connected to a corresponding bit line and source line among the plurality of bit lines BL and source lines SL. A bit cell may be selected by providing a word line voltage VWL to a selected word line. Each bit cell may include an access transistor and a magnetic tunnel junction (MTJ) element. Data may be stored in the selected bit cell via a bit line or a source line, or sensing of the stored data may be performed.

[0026] Here, each bit cell is a magnetic random access memory (MRAM) element (such as STT-MRAM (spin transfer torque magnetic random access memory), Spin-RAM (spin torque transfer magnetization switching RAM), and SMT-RAM (spin momentum transfer RAM). Alternatively, each bit cell may include a device structure (such as, but not limited to, phase change random access memory (PRAM) and ferroelectric random access memory (FRAM)).

[0027] The row decoder 1200 decodes the row address R_ADDR and selects one of the multiple word lines based on the decoding result. During a write operation or a read operation, the row decoder 1200 can transmit the word line voltage VWL to any word line selected by the row address R_ADDR. The access transistor of the memory cell selected by the row decoder 1200 will be turned on. In some embodiments, the row decoder 1200 can be configured to drive the word lines of multiple MRAM cells or bit cells in response to the row address R_ADDR.

[0028] The column decoder 1300 may be connected to the cell array 1100 through source lines SL and / or bit lines BL. The column decoder 1300 may select the source lines SL or the bit lines BL in response to a column address C_ADDR provided from the control circuit 1600. The column decoder 1300 may select the source lines SL or the bit lines BL using a plurality of switches or a plurality of NMOS transistors (not shown) that are switched in response to the column address C_ADDR.

[0029] The read / write circuit 1400 is connected to the column decoder 1300 via a data line and exchanges data with the outside through the input / output circuit 1500. During a program operation, the read / write circuit 1400 can receive write data from the input / output circuit 1500 and write it to a selected memory cell. During a read operation, the read / write circuit 1400 can sense a selected memory cell of the cell array 1100 and output the sensed data to the input / output circuit 1500. The read / write circuit 1400 can perform a selective write operation under the control of the control circuit 1600.

[0030] The read / write circuit 1400 may include a write driver (WD) 1420 and a sense amplifier (SA) 1440. Under the control of the control circuit 1600, the write driver 1420 writes write data provided from the input / output circuit 1500 into a selected memory cell. The write driver 1420 may receive control signals from the control circuit 1600 and supply a programming current or programming voltage to a data line. During a read operation, the sense amplifier 1440 may read the data stored in the selected memory cell by detecting the difference between the voltage of the source line SL and a reference voltage. A reference resistor (or reference resistor circuit) Rref may be used to generate the reference voltage. The reference resistor may be connected to a reference cell of the cell array 1100. In some embodiments, the write driver 1420 may be configured to program the write data into the selected memory cell based on the results of a read-before-write operation, and the sense amplifier 1440 may be configured to detect the existing data stored in the selected memory cell by comparing the reference resistance value of the reference resistor with the resistance value of the selected memory cell.

[0031] Specifically, in a normal read operation and a read-before-write operation performed during a selective write operation, reference resistors Rref having different resistance values ​​are applied to the sense amplifier 1440. In a normal read operation, the sense amplifier 1440 senses a selected memory cell using the reference resistor Rref having a preset default resistance. On the other hand, in a read-before-write operation, the sense amplifier 1440 senses data using the reference resistor Rref, which is set to a value obtained by adding or subtracting a specific margin (or difference) from a base resistance value according to the logic value of the write data.

[0032] For example, when programming a selected memory cell using first data D0, a read-before-write operation is performed for a selective write operation. At this time, the reference resistor Rref used by sense amplifier 1440 can be set to a value obtained by subtracting a specific margin from a default resistance. On the other hand, when programming a selected memory cell using second data D1, the reference resistor Rref used in the read-before-write operation can be set to a value increased by a specific margin from the default resistance. By adjusting the margin of this reference resistor, the reliability of the read-before-write operation can be improved.

[0033] The input / output circuit 1500 can exchange data DATA with an external device (e.g., a memory controller). For example, during a write operation, the input / output circuit 1500 can transmit data DATA received from the external device to the write driver 1420 of the read / write circuit 1400. During a read operation, the input / output circuit 1500 can output read data transmitted from the sense amplifier 1440 of the read / write circuit 1400 to the external device.

[0034] The control circuit 1600 receives control signals including a command CMD, an address ADDR, and a clock signal from an external device (e.g., a host or a CPU) of the resistive memory device 1000. The control circuit 1600 may control the operation of the resistive memory device 1000 based on the command or address received from the external device. The control circuit 1600 may extract a row address R_ADDR from the received address ADDR and transmit the row address R_ADDR to the row decoder 1200, and transmit the column address C_ADDR to the column decoder 1300.

[0035] Specifically, the control circuit 1600 includes a selective write controller 1620. The selective write controller 1620 controls the write driver 1420 and the sense amplifier 1440 to perform a selective write operation. When a write command is provided, the selective write controller 1620 performs a read-before-write operation to read the data stored in the selected memory cell. In addition, the selective write controller 1620 determines whether to perform a data write operation on the selected memory cell by comparing the write data with the sense data obtained as a result of the read-before-write operation.

[0036] During a read-before-write operation, the selective write controller 1620 can adjust the size of the reference resistor Rref used by the sense amplifier 1440 based on the logic value of the write data. In other words, the selective write controller 1620 sets the reference resistor Rref of the sense amplifier 1440 to a value obtained by adding or subtracting a specific margin from a base resistance value based on the logic value of the write data. When a selected memory cell needs to be programmed with the first data D0, the selective write controller 1620 adjusts the reference resistor Rref to a value that "reduces the read margin for the first data D0" for the read-before-write operation. For example, the selective write controller 1620 may set the reference resistor Rref to a value that "subtracts the specific margin." On the other hand, when a selected memory cell needs to be programmed with the second data D1, the selective write controller 1620 adjusts the reference resistor Rref to a value that "reduces the read margin for the second data D1" for the read-before-write operation. In other words, the selective write controller 1620 may set the reference resistor Rref used by the sense amplifier 1440 to a value that increases the specific margin from the base resistance value.

[0037] The voltage generator 1700 may generate a word line voltage VWL required for reading or writing data under the control of the control circuit 1600. The word line voltage VWL may be provided to a selected word line through the row decoder 1200.

[0038] The configuration of the resistive memory device 1000 has been briefly described above. In the resistive memory device 1000, a reference resistor for sensing a selected memory cell is adjusted according to the bit value of write data. In a read-before-write operation, the reliability of the read-before-write operation is improved by adjusting the resistance value of the reference resistor Rref according to the write data.

[0039] Figure 2 It shows Figure 1 Schematic diagram of an exemplary configuration of a cell array. Figure 2 , the cell array 1100 may include a plurality of memory cells MC arranged along the row direction and the column direction. Figure 2 In FIG, a memory cell MC among a plurality of memory cells is indicated by a dotted line frame. Each memory cell MC may include a magnetic tunnel junction MTJ element and an access transistor ATr. When the MTJ element constituting each memory cell MC is programmed to have a specific resistance value, data corresponding to the specific resistance value may be stored in each memory cell MC.

[0040] A plurality of memory cells may be connected to word lines WL0 to WLm-1, bit lines BL0 to BLn-1, and source lines SL0 to SLn-1. One end of each MTJ element may be connected to bit lines BL0 to BLn-1, and the other end of the MTJ element may be connected to one end of an access transistor ATr. The other end of the access transistor ATr may be connected to source lines SL0 to SLn-1, and the gate electrode of the access transistor ATr may be connected to word lines WL0 to WLm-1.

[0041] A word line voltage VWL is applied to a memory cell selected by row decoder 1200 from among a plurality of memory cells. Subsequently, when access transistor ATr is turned on by the word line voltage, the MTJ element is in a parallel state or an antiparallel state depending on the direction of the current applied through bit line BL and source line SL. Hereinafter, the parallel state, in which the resistance value of the MTJ element is relatively small, is referred to as the first data (D0, or logic 0), and the antiparallel state, in which the resistance value is relatively large, is referred to as the second data (D1, or logic 1).

[0042] Figure 3 Shows how data is written Figure 2 Schematic diagram of a memory cell. Figure 3 , the memory cell MC may include an access transistor ATr activated by the word line WL0 and an MTJ element.

[0043] The MTJ element may include a free layer FL, a barrier layer BaL, and a pinned layer PL. The barrier layer BaL is located between the free layer FL and the pinned layer PL. The free layer FL may be connected to a bit line BL0. The pinned layer PL may be connected to the other end of the access transistor ATr.

[0044] The magnetization direction of the pinned layer PL can be fixed to a specific direction, and the magnetization direction of the free layer FL can be changed according to specific conditions (for example, the direction of the write current). According to embodiments, the MTJ element may further include an antiferromagnetic layer to fix the magnetization direction of the pinned layer PL.

[0045] The free layer FL may include a material having a variable magnetization direction. The magnetization direction of the free layer FL may be changed by an electric / magnetic factor provided externally and / or internally to the memory cell MC. The free layer FL may include a ferromagnetic material containing at least one of cobalt (Co), iron (Fe), and nickel (Ni). For example, the free layer FL may include FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O. 12 However, the scope of the present disclosure is not limited thereto.

[0046] The thickness of the barrier layer BaL may be thinner than the spin diffusion distance. The barrier layer BaL may include a non-magnetic material. For example, the barrier layer BaL may include at least one of an oxide of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn), or magnesium boron (MgB), and a nitride of titanium (Ti) or vanadium (V). However, the scope of the present disclosure is not limited thereto.

[0047] The pinned layer PL may have a magnetization direction fixed by the antiferromagnetic layer. The pinned layer PL may include a ferromagnetic material. For example, the pinned layer PL may include CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O 12 According to an embodiment, the antiferromagnetic layer may include an antiferromagnetic material. For example, the antiferromagnetic layer may include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr. However, the scope of the embodiment is not limited thereto.

[0048] The magnetization direction of the free layer FL can be changed according to the direction of the write current I1 and I2 flowing through the MTJ element. For example, when the current (such as Figure 4 When a first write current (such as I1) shown in FIG2 flows from source line SL0 to bit line BL0, the magnetization direction of the free layer FL is opposite to that of the pinned layer PL, and this state may be an antiparallel state AP. Conversely, when a current (such as a second write current I2) flows from bit line BL0 to source line SL0, the magnetization direction of the free layer FL is the same as that of the pinned layer PL, and this state may be a parallel state P.

[0049] When the MTJ element is in the antiparallel state AP, the MTJ element may have an antiparallel resistance Rap. When the MTJ element is in the parallel state P, the MTJ element may have a parallel resistance Rp. In some embodiments, the resistive memory device 1000 may use the magnitude of the resistance value of the MTJ element to store the first data D0 or the second data D1. For example, when the MTJ element is in the parallel state P with a relatively small resistance value, logic "0" or the first data D0 may be considered to be programmed. On the other hand, when the MTJ element is in the antiparallel state AP with a relatively large resistance value, logic "1" or the second data D1 may be considered to be programmed.

[0050] The resistive memory device 1000 can perform a read operation by comparing with a reference resistor Rref having an intermediate value between the first data D0 and the second data D1. The reference resistor Rref can be adjusted according to the written data rather than using a fixed value. The reference resistor Rref can be determined through a test operation. Data can be stored in the memory cell MC according to the resistance value of the MTJ element, and the data stored in the memory cell MC can be sensed by reading the resistance value of the MTJ element.

[0051] Figure 4 is a diagram showing the structure of a read / write circuit that performs a selective write operation of the present disclosure. Figure 4 , assuming that the memory cells selected for programming are memory cells 1115 and 1125 corresponding to input / output cells IO_0 and IO_1, respectively. Memory cells 1115 and 1125 can be selected by activating word lines WL2 in array units 1110 and 1120 of input / output cells, respectively.

[0052] For a selective write operation of the memory cells 1115 and 1125, a column address C_ADDR is provided as a value for selecting the column of the memory cells 1115 and 1125. Thereafter, column decoders 1301 (CD_0) and 1302 (CD_1) corresponding to each of the input / output units IO_0 and IO_1 may connect the bit lines and source lines of the memory cells 1115 and 1125 to the first read / write circuit 1401 and the second read / write circuit 1402.

[0053] The first read / write circuit 1401 applies a selective write operation to program write data WDT_0 corresponding to input / output cell IO_0 into the selected memory cell 1115. For the selective write operation, the first read / write circuit 1401 includes a first write driver (WD0) 1421, a first switch SW0, a first sense amplifier (SA0) 1441, a first reference resistor Rref_0, and a first comparator (COM0) 1461. To program the write data WDT_0 into the selected memory cell 1115 according to the selective write operation, the first read / write circuit 1401 reads the data stored in the memory cell 1115. This operation will be referred to as a read-before-write operation. At this point, the first sense amplifier 1441 uses the first reference resistor Rref_0 to sense the data stored in the memory cell 1115. The first sense amplifier 1441 then outputs the result of comparing the resistance value of the first reference resistor Rref_0 with the resistance value of the memory cell 1115 as read data. The first comparator 1461 controls the first switch SW0 by comparing the read result from the first sense amplifier 1441 with the write data WDT_0. In some embodiments, the first comparator 1461 may control the first switch SW0 using a switch control signal SWC_0.

[0054] Here, it is assumed that the data stored in the memory cell 1115 is the same as the write data WDT_0, and the data stored in the memory cell 1125 is different from the write data WDT_1. Afterwards, because the data read from the memory cell 1115 is the same as the write data WDT_0, the first comparator 1461 blocks the first switch SW0. Therefore, the program operation of writing the data WDT_0 to the memory cell 1115 can be skipped.

[0055] The second read / write circuit 1402 applies a selective write operation to program write data WDT_1 corresponding to input / output cell IO_1 into the selected memory cell 1125. For the selective write operation, the second read / write circuit 1402 includes a second write driver (WD1) 1422, a second switch SW1, a second sense amplifier (SA1) 1442, a second reference resistor Rref_1, and a second comparator (COM1) 1462. To program the write data WDT_1 into the selected memory cell 1125 according to the selective write operation, the second read / write circuit 1402 first performs a read-before-write operation on the data stored in the memory cell 1125. At this point, the second sense amplifier 1442 senses the data stored in the memory cell 1125 using the second reference resistor Rref_1. The second sense amplifier 1442 then outputs the result of comparing the resistance value of the second reference resistor Rref_1 with the resistance value of the memory cell 1125 as read data. The second comparator 1462 controls the second switch SW1 by comparing the read result from the second sense amplifier 1442 with the write data WDT_1. In some embodiments, the second comparator 1462 may control the second switch SW1 using a switch control signal SWC_1.

[0056] The data stored in memory cell 1125, read by second sense amplifier 1442, has a different value than write data WDT_1. For a selective write operation, write data WDT_1 must be physically written to memory cell 1125. Therefore, second comparator 1462 turns on second switch SW1. A write current corresponding to write data WDT_1 can then be applied to memory cell 1125 by second write driver 1422. Memory cell 1125 is programmed using write data WDT_1 by the write current.

[0057] According to the present disclosure, each of the first reference resistor Rref_0 and the second reference resistor Rref_1 used during a read-before-write operation performed for a selective write operation can be increased or decreased by a specific margin according to the write data WDT_0 and WDT_1. For example, when the write data WDT_0 corresponds to the first data D0, the first reference resistor Rref_0 can be adjusted to a resistance value that reduces the margin of a specific value. That is, if the write data WDT_0 is the first data D0, the first reference resistor Rref_0 can be adjusted to a value that reduces the margin of the first data D0. In other words, if the write data WDT_0 is the first data D0, the first reference resistor Rref_0 can be adjusted to have a resistance value that increases the margin of the second data D1.

[0058] In addition, when the write data WDT_0 is the second data D1, the first reference resistor Rref_0 can be adjusted to have a resistance value that reduces the margin of the second data D1. In other words, if the write data WDT_0 is the second data D1, the first reference resistor Rref_0 can be adjusted to have a resistance value that increases the margin of the first data D0. During this read-before-write operation, the control method of the first reference resistor Rref_0 can be similarly applied to all reference resistors including the second reference resistor Rref_1.

[0059] Here, the first reference resistor Rref_0 and the second reference resistor Rref_1 are indicated by variable resistor symbols, but the embodiments are not limited to the disclosure herein. The first reference resistor Rref_0 and the second reference resistor Rref_1 may be configured as a resistor-switch combination whose resistance value is changed by the selective write controller 1620 described above. In addition, each of the first reference resistor Rref_0 and the second reference resistor Rref_1 may be connected to a source line or a bit line of a reference cell.

[0060] As described above, during the read-before-write operation performed for the selective write operation, the sizes of the first reference resistor Rref_0 and the second reference resistor Rref_1 for identifying the data of the first sense amplifier 1441 and the second sense amplifier 1442 are adjusted according to the write data WDT_0 and WDT_1. Therefore, the reliability of the read-before-write operation can be increased.

[0061] Figure 5 is a diagram showing a reference resistance that varies according to write data during a read-before-write operation of the present disclosure. Figure 5 , the MTJ element of the memory cell MC has a resistance value corresponding to the parallel state P and the antiparallel state AP according to the magnetization state of the free layer FL. The parallel state P represents the resistance distribution of the MTJ element when the magnetization directions of the pinned layer PL and the free layer FL are the same. And in the antiparallel state AP, the MTJ element shows the resistance distribution when the magnetization directions of the pinned layer PL and the free layer FL are opposite. The resistance value in the parallel state P is relatively smaller than the resistance value in the antiparallel state AP. In the present disclosure, the parallel state P is defined as being mapped to the first data D0, and the antiparallel state AP is defined as being mapped to the second data D1. Figure 5 , the y-axis direction represents the number of cells having a given resistance value indicated at a point on the x-axis. Figure 5 Corresponding to the histogram, a cell programmed with a logic value of D1 has a resistance R greater than X. A cell programmed with a logic value of D0 has a resistance R less than X.

[0062] like Figure 5As shown in item (a) of FIG, during a normal read operation, the resistive memory device 1000 uses a reference resistance value (Rref=X) corresponding to an intermediate value between the first data D0 and the second data D1 to distinguish between the first data D0 and the second data D1. In other words, in response to a read command, the resistive memory device 1000 may apply a predetermined reference resistance value (X) to a selected memory cell. The reference resistance value (X) may be determined using test or accumulated data. During a read operation, the reference resistance value (X) provided as a default value will be referred to as a base resistance value or a default resistance value.

[0063] Figure 5 Items (b) and (c) provide examples of reference resistance values ​​(Rref=XZ, X+Z) of the resistive memory device 1000 applied during a read-before-write operation according to an embodiment. Item (b) shows the reference resistance value (Rref=XZ) applied during a read-before-write operation when the write data corresponds to the first data D0. If the data requested to be written is the first data D0 corresponding to a relatively small resistance state, the selective write controller 1620 (see Figure 1 ) sets the reference resistor Rref to a resistance value (XZ) reduced by a specific margin (Z) with respect to the first data (D0).

[0064] During a read-before-write operation, if a reference resistor Rref having a resistance value (XZ) reduced by a specific margin (Z) is used, the read margin is reduced when the data stored in the memory cell MC is the first data (D0). On the other hand, if a reference resistor Rref having a resistance value (XZ) reduced by the specific margin (Z) is used, the read margin is increased when the data stored in the memory cell MC is the second data D1. Therefore, the detection reliability of the memory cell to which the first data D0 is to be written can be increased during the selective write operation, which improves the reliability of the write operation. The size of the specific margin (Z) can be determined by considering various variables, such as the bit error rate of the resistive memory device 1000, process variations, and temperature.

[0065] Before determining whether to perform a write, the read-before-write algorithm first checks the data present in the memory cell. Because this is the data present in the memory cell before the read-before-write operation, this original data may be referred to herein as "existing data."

[0066] Embodiments address the issue of a cell being read if its current resistance is different from the logic value being written but is close to the threshold for comparison (see Figure 5Items (b) and (c)) of the present invention skip the write operation to save current. The current resistance of the cell corresponds to the logic value of the existing data. To avoid skipping the write operation when the current resistance is close to the threshold, the embodiment moves the threshold toward the typical value of the resistance of the logic value to be written. Figure 5 In item (b), when the data to be written is D0, the threshold value is moved closer to the position where the peak of the cell read with the value D0 appears (in Figure 5 Item (b) is moved closer to the left). This increases the likelihood that the resistance of the logic cell will be detected as corresponding to D1. Later, in some instances, the write will not be skipped, and the cell will be programmed using a resistance value D0 that is close to the typical value of the logic value to be written. When a read of this memory cell is performed later, the resistance value will not be close to the threshold value X used for comparison, but will be closer to the peak value of the cell read using the value D0. This reduces the read error value (after an earlier write to D0, Figure 5 The possibility of item (b) D1) in the example. A similar description with D0 and D1 reversed applies to Figure 5 Item (c). Figure 5 Item (c) shows the reference resistance value (Rref=X+Z) applied during the pre-write read operation when the write data corresponds to the second data D1. If the data requested to be written is the second data D1 corresponding to a relatively high resistance state, the selective write controller 1620 sets the reference resistor Rref to a resistance value (X+Z) that is increased by a specific margin (Z) relative to the second data D1.

[0067] During a read-before-write operation, using a reference resistor Rref having a resistance value (X+Z) increased by a specific margin (Z) increases the read margin when the data stored in the memory cell MC is the first data D0. On the other hand, using a reference resistor Rref having a resistance value (X+Z) increased by a specific margin (Z) decreases the read margin when the data stored in the memory cell MC is the second data D1. Therefore, the detection reliability of the memory cell to which the second data D1 is to be written can be increased during the selective write operation.

[0068] Figure 6 is a block diagram showing the configuration of a selective write controller according to an embodiment. Figure 6 , the selective write controller 1620a can perform a selective write operation on the memory cell by separating the write phases of each write data D0 and D1. For example, the selective write controller 1620a can program the first data D0 among the write data into the selected memory cell, and then program the second data D1. Figure 6, array units 1101 , 1102 , and 1103 may correspond to input / output units IO_0 , IO_1 , and IO_2 , respectively.

[0069] To write data in separate write phases, the selective write controller 1620a can set the reference resistor Rref according to the operating mode OP and the type of write data. The selective write controller 1620a may include a multiplexer 1622 and an adder / subtractor 1624 for setting the reference resistor Rref according to the operating mode OP and the type of write data. The adder / subtractor 1624 may be implemented using a mixture of digital logic gates and analog components (such as resistors, transistors, and operational amplifiers). The write steps performed by the selective write controller 1620 will be explained below using an example in which the write steps are performed separately as a write step for first data D0 and a subsequent write step for second data D1.

[0070] The multiplexer 1622 selects the write mode W or the read mode R according to the operation mode OP. In the read mode R, the zero margin (0) to be added or subtracted from the reference resistor Rref is selected and sent to the adder / subtractor 1624. The multiplexer 1622 can be implemented by a mixture of digital logic gates and analog components (such as resistors, transistors, and operational amplifiers). On the other hand, in the write mode W, the multiplexer 1622 selects a specific margin (Z) to be added or subtracted from the reference resistor Rref and sends it to the adder / subtractor 1624. The selective write operation is included as part of the write operation. Therefore, in the write phase of the first data D0 and the subsequent write phase of the second data D1, the multiplexer 1622 will select the write mode W. As a result, in the read-before-write operation performed in the selective write operation, the multiplexer 1622 selects the specific margin (Z) and transmits it to the adder / subtractor 1624.

[0071] During a normal read operation, the adder / subtractor 1624 is provided with a reference resistance value (Rref=X) of a base or default value to be applied. And the adder / subtractor 1624 receives a specific margin (Z) provided from the multiplexer 1622. The adder / subtractor 1624 can add or subtract the specific margin (Z) from the base resistance value (X) according to the write data. For example, in the normal read operation mode, the adder / subtractor 1624 adds a zero margin (0) to the default resistance value (Rref=X), or subtracts a zero margin (0) from the default resistance value (Rref=X), and provides it as the set value of the reference resistor Rref. On the other hand, in the write operation mode, the adder / subtractor 1624 adds or subtracts a specific margin (Z) from the default resistance value (Rref=X), and provides it as the set value of the reference resistor Rref. Specifically, in a write operation of the first data D0, the adder / subtractor 1624 may set the reference resistor Rref to a resistance value (XZ) obtained by subtracting a specific margin (Z) from a default resistance value (X). On the other hand, in a write operation of the second data D1, the adder / subtractor 1624 may set the reference resistor Rref to a resistance value (X+Z) obtained by adding the specific margin (Z) to the default resistance value (X).

[0072] When the first data D0 write phase begins, multiplexer 1622 selects a specific margin (Z) and sends it to adder / subtractor 1624. Since the write data is the first data D0, adder / subtractor 1624 sets the reference resistor Rref to a resistance value (Rref=XZ) obtained by subtracting the specific margin (Z) from the default resistance value (Rref=X). Then, using the reference resistance value (Rref=XZ) with a reduced margin, sense amplifier (SA) 1451 performs a read-before-write operation on the selected memory cell. The data sensed by sense amplifier 1451 (e.g., existing data) is compared with the write data (i.e., D0) by comparator (COMP) 1431. Based on the comparison result of comparator 1431, switch control signals SWC_0, SWC_1, and SWC_2 are generated to connect or disconnect the write driver 1420 from the memory cell. Comparator 1431 generates switch control signals SWC_0, SWC_1, and SWC_2 to turn off switches SW0, SW1, and SW2 when the sensed data and the written data are the same. Comparator 1431 generates switch control signals SWC_0, SWC_1, and SWC_2 to turn on switches (SW0, SW1, and SW2) when the sensed data and the written data are different. Therefore, switches SW0, SW1, and SW2 connect or disconnect write driver 1420 to the selected memory cell according to switch control signals SWC_0, SWC_1, and SWC_2.

[0073] When the second data D1 write phase begins, multiplexer 1622 selects a specific margin (Z) and transmits it to adder / subtractor 1624. Since the write data is the second data D1, adder / subtractor 1624 sets reference resistor Rref to the resistance value (X+Z) obtained by adding the specific margin (Z) to the default resistance value (X). Sense amplifier 1451 then performs a pre-write read operation on the selected memory cell using the margined resistance value (Rref=X+Z). The data sensed by sense amplifier 1451 is compared with the write data (i.e., D1) by comparator 1431. Based on the comparison result of comparator 1431, switch control signals SWC_0, SWC_1, and SWC_2 are generated to connect or disconnect write driver 1420 from the memory cell. The switches SW0 , SW1 , and SW2 connect or disconnect the write driver 1420 to the memory cells according to switch control signals SWC_0 , SWC_1 , and SWC_2 .

[0074] Figure 7 It shows that according to Figure 6 Flowchart of a selective write operation for writing data in a separate write phase. Figure 7 , selectively write to controller 1620a (see Figure 6 ) can sequentially program selected memory cells using different reference resistance values ​​according to the write phase. The selective write controller 1620a can be implemented by a mixture of digital logic gates and analog components (such as resistors, transistors, and operational amplifiers).

[0075] In step S110, the resistive memory device 1000 receives write data requested for writing. The write data is provided along with a write command and address from outside the resistive memory device 1000. The write data received by the input / output circuit 1500 is divided into input / output cells (IO cells) and sent to the read / write circuit 1400.

[0076] In steps S120 to S140 , a first data writing phase ( D0 writing phase) is performed, and in subsequent steps S150 to S170 , a second data writing phase ( D1 writing phase) is performed.

[0077] In step S120, the selective write controller 1620a sets the reference resistor Rref for the read-before-write operation. Specifically, the multiplexer 1622 of the selective write controller 1620a selects the specific margin (Z) and transmits it to the adder / subtractor 1624. The adder / subtractor 1624 sets the reference resistor Rref to the resistance value (XZ) obtained by subtracting the specific margin (Z) from the default resistance value (X).

[0078] In step S130, sense amplifier 1451 performs a pre-write read operation on the selected memory cell using a reference resistance value (Rref = XZ) obtained by subtracting a specific margin from the default resistance value. The data sensed by sense amplifier 1451 is compared with the write data (i.e., D0) by comparator 1431. Based on the comparison result of comparator 1431, switch control signals SWC_0, SWC_1, and SWC_2 are generated to connect or disconnect the write driver 1420 from the memory cell. Comparator 1431 generates switch control signals SWC_0, SWC_1, and SWC_2 to open switches SW0, SW1, and SW2 if the sensed data matches the write data. Comparator 1431 generates switch control signals SWC_0, SWC_1, and SWC_2 to close switches SW0, SW1, and SW2 if the sensed data differs from the write data. Therefore, the switches SW0 , SW1 , and SW2 connect or disconnect the write driver 1420 to or from the selected memory cells according to the switch control signals SWC_0 , SWC_1 , and SWC_2 .

[0079] In step S140, write driver 1420 programs the first data D0 for the selected memory cells. At this point, programming is performed only on the memory cells connected via write driver 1420 and switches SW0, SW1, and SW2. Programming may be skipped for memory cells blocked from write driver 1420 by switches SW0, SW1, and SW2. In some embodiments, write driver 1420 may write the first data D0 to failed cells (e.g., where the existing data of the failed cells differs from the data to be written (first data D0)).

[0080] In step S150, a selective write operation for the second data D1 begins. Selective write controller 1620a sets reference resistor Rref for the read-before-write operation. Specifically, multiplexer 1622 of selective write controller 1620 selects a specific margin (Z) and transmits it to adder / subtractor 1624. Adder / subtractor 1624 sets reference resistor Rref to the resistance value (X+Z) obtained by adding the specific margin (Z) to the default resistance value (X).

[0081] In step S160, sense amplifier 1451 performs a read-before-write operation on the selected memory cell using a reference resistance value (Rref = X + Z) with a margin added to the default resistance value. The data sensed by sense amplifier 1451 is compared with the write data (i.e., D1) by comparator 1431. Based on the comparison result of comparator 1431, switch control signals SWC_0, SWC_1, and SWC_2 are generated to connect or disconnect write driver 1420 from the memory cell. Comparator 1431 generates switch control signals SWC_0, SWC_1, and SWC_2 to open switches SW0, SW1, and SW2 if the sensed data matches the write data. Comparator 1431 generates switch control signals SWC_0, SWC_1, and SWC_2 to close switches SW0, SW1, and SW2 if the sensed data differs from the write data. Therefore, the switches SW0 , SW1 , and SW2 connect or disconnect the write driver 1420 to or from the selected memory cells according to the switch control signals SWC_0 , SWC_1 , and SWC_2 .

[0082] In step S170, write driver 1420 programs the second data D1 for the selected memory cells. At this point, programming is performed only on the memory cells connected via write driver 1420 and switches SW0, SW1, and SW2. Programming may be skipped for memory cells blocked from write driver 1420 by switches SW0, SW1, and SW2. In some embodiments, write driver 1420 may write the second data D1 to failed cells (e.g., where the existing data of the failed cells differs from the data to be written (second data D1)).

[0083] The above briefly explains a selective write operation for programming memory cells by separating the write phases for each data (D0, D1). While an example has been described in which the first data D0 is written before the second data D1, embodiments are not limited to this order. That is, even when the second data D1 is written to the memory cell before the first data D0, the reference resistance setting method used in a read-before-write operation can still be effectively applied.

[0084] Figure 8 FIG. 1 is a block diagram illustrating a selective write controller according to another embodiment. Figure 8, selective write controller 1620b can simultaneously program selected memory cells without distinguishing between the write phase for the first data D0 and the write phase for the second data D1. Selective write controller 1620b can be implemented using a mix of digital logic gates and analog components (such as resistors, transistors, and operational amplifiers). In other words, selective write controller 1620b can simultaneously set a reference resistance value corresponding to the write data and perform a read-before-write operation. Additionally, selective write controller 1620b can simultaneously write the first data D0 and the second data D1 to the selected memory cells based on the results of the read-before-write operation.

[0085] The selective write controller 1620b may set a first reference resistor (Rref_0) corresponding to the input / output unit (IO_0) according to the operation mode OP and the type of write data. The selective write controller 1620b may include a first multiplexer 1642, an adder 1644, and a subtractor 1646 for setting the first reference resistor Rref_0 according to the operation mode OP and the type of write data. The selective write controller 1620b, the first multiplexer 1642, the adder 1644, and the subtractor 1646 may be implemented using a mixture of digital logic gates and analog components (such as resistors, transistors, and operational amplifiers).

[0086] The first multiplexer 1642 selects a write mode W or a read mode R according to the operation mode OP. In the read mode R, the first multiplexer 1642 selects (0) as the margin to be added to or subtracted from the reference resistor Rref and sends it to the adder 1644 or the subtractor 1646. On the other hand, in the write mode W, the first multiplexer 1642 selects a specific margin (Z) to be added to or subtracted from the reference resistor Rref and sends it to the adder 1644 or the subtractor 1646. The selective write operation is a type of write operation. Therefore, in the selective write operation, the first multiplexer 1642 will select the write mode W. In the read-before-write operation performed in the selective write operation, the first multiplexer 1642 will select the specific margin (Z) and send it to the adder 1644 or the subtractor 1646. On the other hand, in the normal read operation, the first multiplexer 1642 selects the read mode R. Therefore, the first multiplexer 1642 will send the margin (0) to the adder 1644 or the subtractor 1646 in normal read mode.

[0087] During normal read operation, adder 1644 is supplied with a default resistance value (X) to be applied. Additionally, a margin (0 or Z) supplied from first multiplexer 1642 is supplied to adder 1644. In read mode R, margin (0) is supplied to adder 1644. On the other hand, in read-before-write mode, a specific margin (Z) is supplied to adder 1644. Adder 1644 adds the default resistance value (X) and margin (0 or Z) depending on the operating mode and supplies the sum to second multiplexer 1648.

[0088] During normal read operation, subtractor 1646 is also supplied with a default resistance value (X) to be applied, as is adder 1644. Additionally, a margin (0 or Z) supplied from first multiplexer 1642 is supplied to subtractor 1646. In read mode R, margin (0) is supplied to subtractor 1646. On the other hand, in read-before-write mode, margin (Z) is supplied to subtractor 1646. Subtractor 1646 subtracts the default resistance value (X) from the margin (0 or Z), depending on the operating mode, and supplies the difference to second multiplexer 1648.

[0089] Selective write controller 1620b simultaneously calculates the sum of the default resistance value (X) and the margin (0 or Z), as well as the difference between the margin (0 or Z) and the default resistance value (X). In other words, adder 1644 adds the default resistance value (X) and the specific margin (Z) to form a resistance value (X+Z). Simultaneously, subtractor 1646 calculates a resistance value (Rref=XZ) by subtracting the specific margin (Z) from the default resistance value (X). The calculated resistance value (X+Z, XZ) is then sent to a second multiplexer 1648 corresponding to each input / output unit (IO_0, IO_1, IO_2, ...).

[0090] Second multiplexer 1648 for each input / output unit (IO_0, IO_1, IO_2, ...) sets reference resistor Rref by applying a margin based on the written data. When the written data corresponds to first data D0, second multiplexer 1648 sets first reference resistor Rref_0 to a reference resistance value (XZ) obtained by subtracting a specific margin (Z) from a default resistance value (X). On the other hand, when the written data corresponds to second data D1, second multiplexer 1648 sets first reference resistor Rref_0 to a resistance value (X+Z) obtained by adding the margin (Z) to the default resistance value (X).

[0091] Once the first reference resistor Rref_0 is set, a read-before-write operation is performed on each input / output unit (IO_0, IO_1, IO_2, ...) for the selected memory cell. Sense amplifier 1451 senses the data of the selected memory cell using the first reference resistor Rref_0 set according to the write data. The data sensed by sense amplifier 1451 is compared with the write data (Write Data (IO_0)) by comparator 1431. Based on the comparison result of comparator 1431, a switch control signal SWC_0 is generated to connect or disconnect the write driver 1420 from the memory cell. This read-before-write operation using the adjusted reference resistor is also performed simultaneously on each input / output unit (IO_1, IO_2, ...). Therefore, the switch control signals (SWC_1, SWC_2, ...) are also generated simultaneously with the switch control signal SWC_0. If the sensed data is identical to the write data, comparator 1431 generates the switch control signal SWC_0 to disconnect switch SW0. On the other hand, if the sensed data is different from the written data, the comparator 1431 will generate a switch control signal SWC_0 to turn on the switch SW0 .

[0092] Figure 9 It is shown by Figure 8 Flowchart of the selective write operation performed by the selective write controller. Figure 9 , the selective write controller 1620b can simultaneously perform a read-before-write operation regardless of the bit value of the write data provided in the input / output unit.

[0093] In step S210, the resistive memory device 1000 receives write data requested for writing. The write data is provided together with a write command and address from outside the resistive memory device 1000. The write data received by the input / output circuit 1500 is divided into input / output units and sent to the read / write circuit 1400.

[0094] In step S220, the selective write controller 1620b sets the reference resistors (Rref_0, Rref_1, Rref_2, ...) used for the read-before-write operation. In other words, the first multiplexer 1642 of the selective write controller 1620b sets the reference resistors Rref to resistance values ​​(XZ, X+Z) obtained by adding or subtracting a specific margin (Z) from a default resistance value (X) based on the write data. At this point, the selective write controller 1620b simultaneously sets the reference resistors (Rref_0, Rref_1, Rref_2, ...) to reference resistance values ​​classified according to the write data.

[0095] In step S230, when the setting of the reference resistors (Rref_0, Rref_1, Rref_2, ...) is completed, a read-before-write operation is performed on each input / output cell for the selected memory cell. The data stored in the selected memory cell is sensed using the reference resistors (Rref_0, Rref_1, Rref_2, ...) set according to the write data. The data sensed in the input / output cell is compared with the write data. As a result of sensing the data sensed by the read-before-write operation with the write data, a switch control signal (SWC_0, SWC_1, SWC_2, ...) is generated to switch the write driver (1420, see Figure 1 ) is connected or blocked to the memory cell.

[0096] In step S240, write driver 1420 simultaneously programs the first data D0 and the second data D1 for the selected memory cells. At this point, programming is performed only on the memory cells connected via write driver 1420 and switches SW0, SW1, and SW2. Programming is skipped for memory cells blocked by switches SW0, SW1, and SW2. In some embodiments, write driver 1420 may write the first data D0 or the second data D1 to all failed cells.

[0097] In the above, the selective write operation of the embodiment in which each write phase of the data D0 and D1 is performed simultaneously is briefly described.

[0098] Figure 10 It is shown in accordance with Figure 6 A timing diagram of the internal operation of a resistive memory device during a selective write operation of writing data in a separate write phase. Figure 10 , selectively write to controller 1620a (see Figure 6 ) Programming can be performed on the selected memory cell by setting the reference resistor Rref for each write phase. Here, the write operation will be described only for three input / output units IO_0, IO_1, and IO_2.

[0099] At time T0, a normal read command is issued for a selected memory cell. The read / write circuit 1400 then sets the reference resistor Rref to read each selected memory cell in the input / output cells IO_0, IO_1, and IO_2. At this point, the read / write circuit 1400 sets the reference resistor Rref for the input / output cells IO_0, IO_1, and IO_2 to a default resistance value (X) that does not increase or decrease margin. The data stored in the memory cell selected by the normal read operation is output as "010" for each of the input / output cells IO_0, IO_1, and IO_2.

[0100] At time T1, a write command is provided to the selected memory cell. That is, the write data "101" is provided along with the write command to the same memory cell as the one selected at time T0. Thereafter, the write phase for the first data D0 begins at time T1, and the write phase for the second data D1 begins at time T3.

[0101] At time T1, a read and compare operation is performed on the memory cells used to write the first data D0. Selective write controller 1620a sets reference resistor Rref for the read and compare operation. Specifically, selective write controller 1620a sets reference resistor Rref to a resistance value (XZ) obtained by subtracting a specific margin (Z) from a default resistance value (X) for the selective write operation of the first data D0. The memory cells whose read margins have substantially increased correspond to the memory cells of input / output unit IO_1 storing the second data D1. On the other hand, since the first data D0 is stored in the memory cells of input / output units IO_0 and IO_2, the read margins have substantially decreased. A comparison is performed between the written data D0 and the read result. At this point, the read results for the memory cells of input / output units IO_0 and IO_2 are identical to the first data D0. The read result for the memory cells of input / output unit IO_1 corresponds to the second data D1 and is therefore different from the first data D0.

[0102] At time T2, a determination is made as to whether to write the first data D0 based on the results of the read and compare operations. The read results for the memory cells of input / output units IO_0 and IO_2 are identical to the first data D0, which serves as the write data. Therefore, the comparison results for the memory cells of input / output units IO_0 and IO_2 are determined to be a passed comparison. The read results for the memory cells of input / output unit IO_1 are detected differently from the first data D0, which serves as the write data. Therefore, the comparison results for the memory cells of input / output unit IO_1 are determined to be a failed comparison. For the selective write operation, the first data D0, which serves as the write data, is applied only to the memory cells corresponding to the failed comparison (i.e., the failed cells). Therefore, the first data D0, which serves as the write data, is programmed only to the memory cells of input / output unit IO_1. The write operation is skipped for the memory cells of input / output units IO_0 and IO_2 that are determined to have passed the comparison.

[0103] At time T3, the write phase for the second data D1 begins. At time T3, a read and compare operation is performed on the memory cells to which the second data D1 is to be written. The selective write controller 1620a sets the reference resistor Rref for the read and compare operation. The selective write controller 1620a sets the reference resistor Rref to a resistance value (X+Z) obtained by adding a specific margin (Z) to a default resistance value (X) for the selective write operation of the second data D1. The memory cells whose read margins are substantially increased then correspond to the memory cells of input / output units IO_0 and IO_2 storing the first data D0. On the other hand, during the write operation of the second data D1, the memory cells of input / output unit IO_1 to which data has already been written can be excluded from the read and compare operation, as well as the write operation (i.e., the read and compare operation, as well as the write operation, are not performed on the memory cells of input / output unit IO_1).

[0104] A comparison is performed between the second data D1 as the write data and the read result. At this time, the read results of the memory cells of the input / output units IO_0 and IO_2 each correspond to the first data D0. The data stored in the memory cells of the input / output units IO_0 and IO_2 is different from the second data D1 as the write data.

[0105] At time T4, a determination is made as to whether to write the second data D1 based on the results of the read and compare operations. The read results for the memory cells of input / output units IO_0 and IO_2 differ from the second data D1, which serves as the write data. Therefore, the comparison result for the memory cells of input / output units IO_0 and IO_2 is determined to be a comparison failure. For the selective write operation, the second data D1, which serves as the write data, is applied only to the memory cells of input / output units IO_0 and IO_2 corresponding to the comparison failure. Therefore, the second data D1, which serves as the write data, is programmed only into the memory cells of input / output units IO_0 and IO_2. At time T5, the write operation ends.

[0106] In the above, a selective write operation for programming memory cells by separating the write phase for each data D0 and D1 is briefly explained. Here, an example of writing the first data D0 before the second data D1 has been described, but the embodiment is not limited to this order.

[0107] Figure 11 is shown in Figure 8 A timing diagram of the internal operation of a resistive memory device during a selective write operation performed by a selective write controller shown in FIG. Figure 11, the selective write controller 1620b can simultaneously perform read, compare, and write operations regardless of the bit values ​​of the write data provided in the input / output unit. Here, for ease of explanation, the write operation performed on three input / output units IO_2, IO_1, and IO_0 will be described.

[0108] At time T0, a normal read command is issued to the selected memory cell. The read / write circuit 1400 then sets the reference resistor Rref to read each selected memory cell in the input / output cells IO_2, IO_1, and IO_0. At this point, the read / write circuit 1400 sets the reference resistor Rref for the input / output cells IO_2, IO_1, and IO_0 to a default resistance value (X) without increasing or decreasing the margin. The data stored in the memory cell selected by the normal read operation is output as "010" for each of the input / output cells IO_2, IO_1, and IO_0.

[0109] At time T1, a write command is provided to the selected memory cell. That is, the write data "101" is provided along with the write command to the same memory cell as the memory cell selected at time T0. Thereafter, starting at time T1, read and compare operations are performed on the memory cells corresponding to each of the input / output units IO_2, IO_1, and IO_0. Selective write controller 1620b sets reference resistor Rref for the read and compare operations.

[0110] To set the reference resistor Rref, the selective write controller 1620b applies a margin (Z) to the reference resistor Rref for each input / output cell IO_2, IO_1, and IO_0 based on the write data "101." For example, the reference resistor Rref of the second input / output cell IO_2, where the second data D1 is written, can be set to a resistance value (X+Z) obtained by adding a specific margin (Z) to a default resistance value (X). The reference resistor Rref of the first input / output cell IO_1, where the first data D0 is written, will be set to a resistance value (XZ) obtained by subtracting the specific margin (Z) from the default resistance value (X). Furthermore, the reference resistor Rref of the zeroth input / output cell (IO_0), where the second data D1 is written, will be set to a resistance value (X+Z) obtained by adding the specific margin (Z) to the default resistance value (X). Thus, the margin (Z) is added or subtracted from the reference resistor to read all selected memory cells.

[0111] Data stored in each memory cell is output through a read-before-write operation using a reference resistor Rref to which a margin is applied. The stored data '010' is sensed from each memory cell of the input / output units IO_2, IO_1, and IO_0.

[0112] At time T2, based on the results of the read and compare operations, a write operation is performed on the memory cells of each of the input / output units IO_2, IO_1, and IO_0. The read result "010" for each memory cell of the input / output units IO_2, IO_1, and IO_0 corresponds to the inverse of the write data "101." Therefore, the comparison result for each memory cell of the input / output units IO_2, IO_1, and IO_0 is judged to be a comparison failure. Therefore, for the selective write operation, the write data "101" is programmed into each memory cell of the input / output units IO_2, IO_1, and IO_0.

[0113] At time T3, a write command is provided for the selected memory cell. That is, the write data "100" is provided along with the write command to the same memory cell as the memory cell selected at time T0. Thereafter, starting at time T3, a read and compare operation is performed on the memory cell corresponding to each of the input / output units IO_2, IO_1, and IO_0. Selective write controller 1620b sets reference resistor Rref for the read and compare operations.

[0114] To set the reference resistor Rref, the selective write controller 1620b applies a margin (Z) to the reference resistor Rref for each input / output unit IO_2, IO_1, and IO_0 based on the write data "100." For example, the reference resistor Rref of the second input / output unit IO_2, where the second data D1 is written, will be set to the resistance value (X+Z) obtained by adding the margin (Z) to the default resistance value (X). The reference resistor Rref of the input / output units IO_1 and IO_0, where the first data D0 is written, will be set to the resistance value (XZ) obtained by subtracting the margin (Z) from the default resistance value (X). Thus, the margin (Z) is added to or subtracted from the reference resistor to read all selected memory cells. The data stored in each memory cell is output through a read-before-write operation using the reference resistor Rref to which the margin is applied. The stored data "101" is sensed from each memory cell of the input / output units IO_2, IO_1, and IO_0.

[0115] At time T4, a write operation is performed on the memory cells of each of the input / output units IO_2, IO_1, and IO_0 based on the results of the read and compare operations. Compared to the written data "100," the read result "101" for each of the memory cells of the input / output units IO_2, IO_1, and IO_0 has only the least significant bit (LSB) inverted. Therefore, the first data D0 can be programmed only in the memory cells of the input / output unit IO_0, and programming of the remaining memory cells can be skipped. The write operation ends at time T5.

[0116] In the above, the selective write operation of an embodiment has been described. In this embodiment, the data D0 and D1 are not written separately but are programmed into the memory cells simultaneously. For the selective write operation, a read-before-write operation is performed, which applies a read margin in a direction unfavorable for writing data. Therefore, the reliability of the read-before-write operation can be improved, and the reliability of the write operation can also be improved.

Claims

1. A resistive memory device for performing a selective write operation, comprising: at least one memory unit; A reference resistor circuit, wherein a reference resistance value of the reference resistor circuit can be adjusted; a sense amplifier configured to read existing data stored in the at least one memory cell by comparing a resistance value of the at least one memory cell with a reference resistance value of a reference resistance circuit; a write driver configured to program write data into the at least one memory cell; as well as The selective write controller is configured to perform a read-before-write operation by adjusting a reference resistance value of the reference resistance circuit according to write data during the selective write operation.

2. The resistive memory device according to claim 1, wherein First data corresponding to the first resistance value or second data corresponding to a second resistance value greater than the first resistance value is stored in the at least one memory cell, and The selective write controller is configured to, in response to a first request for writing first data, set the reference resistance circuit to a first changed reference resistance value obtained by subtracting a specific margin from a default resistance value.

3. The resistive memory device according to claim 2, wherein The selective write controller is configured to, in response to a second request to write second data, set the reference resistance circuit to a second changed reference resistance value obtained by adding a specific margin to a default resistance value.

4. The resistive memory device according to claim 3, wherein The selective write controller includes: a multiplexer configured to select one of a specific margin and zero margin according to an operation mode; and The adder / subtractor is configured to set a reference resistance circuit by adding or subtracting an output of the multiplexer to a default resistance value according to written data.

5. The resistive memory device according to claim 4, wherein The selective write controller is configured to program write data by distinguishing a first write phase in which first data is to be written in the first memory cell and a second write phase in which second data is to be written in the second memory cell.

6. The resistive memory device according to claim 3, wherein The selective write controller includes: a first multiplexer configured to select one of a specific margin and a zero margin according to an operation mode; an adder configured to add the output of the first multiplexer and a default resistance value; a subtractor configured to subtract the output of the first multiplexer from a default resistance value; and The second multiplexer is configured to set the reference resistance circuit by selecting the output of the adder or the output of the subtractor according to the written data.

7. The resistive memory device according to claim 6, wherein: The selective write controller simultaneously writes first data into the first memory cell and second data into the second memory cell.

8. The resistive memory device according to any one of claims 1 to 7, further comprising: a switch configured to connect the write driver to the at least one memory cell; as well as A comparator is configured to compare existing data with write data to generate a switch control signal that connects or disconnects the write driver to the at least one memory cell, wherein the existing data is output from the sense amplifier.

9. The resistive memory device according to any one of claims 1 to 7, wherein: The at least one memory cell includes a magnetic tunnel junction element and an access transistor.

10. A method for performing a selective write operation on a resistive memory device, comprising: receiving write data to be written into the selected memory cell; increasing or decreasing a reference resistance for a pre-write read operation on a selected memory cell according to a value of write data to obtain a changed reference resistance; performing a read-before-write operation on the selected memory cell based on the changed reference resistance; as well as Write data is written to the selected memory cell according to the result of the read-before-write operation. The writing method according to claim 10 , wherein: During a read operation, the reference resistor is set to a default resistance value, and during a selective write operation, the reference resistor is set to have a first resistance value subtracted from the default resistance value by a specific margin or a second resistance value increased from the default resistance value by a specific margin.

12. The writing method according to claim 11, wherein: If the write data is first data corresponding to a first resistance state lower than a default resistance value, the reference resistance is set to the first resistance value, and If the write data is second data corresponding to a second resistance state higher than or equal to a default resistance value, the reference resistance is set to the second resistance value.

13. The writing method according to claim 12, further comprising: The write data is compared with existing data stored in the selected memory cells detected by a read-before-write operation.

14. The writing method according to claim 13, wherein: Based on the existing data being identical to the write data, a program operation of the write data on the selected memory cell is skipped.

15. The writing method according to claim 14, wherein: The write data is programmed into the selected memory cells based on the existing data being different from the write data.

16. A resistive memory device comprising: a cell array comprising a plurality of magnetoresistive random access memory cells; a row decoder configured to drive word lines of the plurality of magnetoresistive random access memory cells in response to a row address; a read / write circuit connected to a bit line or a source line of the cell array and configured to perform a read-before-write operation on a selected memory cell based on a reference resistance value of the reference resistance circuit during a selective write operation; as well as The control circuit is configured to adjust a reference resistance value of the reference resistance circuit according to write data during a selective write operation.

17. The resistive memory device according to claim 16, wherein: The read / write circuitry includes: a sense amplifier configured to detect existing data stored in a selected memory cell by comparing a reference resistance value of a reference resistance circuit with a resistance value of the selected memory cell; and The write driver is configured to program write data into the selected memory cells according to the result of the read-before-write operation.

18. The resistive memory device according to claim 16, wherein During a read operation, the reference resistance value of the reference resistance circuit is set to a default resistance value, and during a selective write operation, the reference resistance value of the reference resistance circuit is set to one of a first resistance value having a specific margin subtracted from the default resistance value and a second resistance value having a specific margin increased from the default resistance value.

19. The resistive memory device according to any one of claims 16 to 18, wherein: The control circuit includes: a multiplexer configured to select a specific margin or zero margin depending on an operating mode; and The adder / subtractor is configured to set a reference resistance circuit by adding or subtracting an output of the multiplexer from a default resistance value according to written data.

20. The resistive memory device according to any one of claims 16 to 18, wherein The control circuit includes: a first multiplexer configured to select a specific margin or zero margin depending on an operating mode; an adder configured to add the output of the first multiplexer and a default resistance value; a subtractor configured to subtract the output of the first multiplexer from a default resistance value; and The second multiplexer is configured to set the reference resistance circuit by selecting the output of the adder or the output of the subtractor according to the written data.

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