Erasing method of memory, memory device and storage equipment

Abstract

The invention discloses an erasing method of a memory, a memory device and storage equipment. The erasing method comprises the following steps: acquiring the cycle index of executing an erasing sub-operation of the last erasing operation by a current storage block of the memory; configuring the erase voltage of the current erase operation based on the cycle index; and performing a current erasure operation on the current memory block based on the configured erasure voltage. Through the mode, the erasing method of the memory can dynamically adjust the erasing voltage of the current erasing operation according to the cycle index of the erasing sub-operation of the last erasing operation of the memory, so that the erasing capability of the memory block of the memory is improved, and the problem that the erasing operation time of the memory is long is solved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory erasing method, a memory device, and a storage device. Background Art

[0002] With the development of technology, the application of memory is becoming more and more widespread. Take flash memory as an example. Flash memory is a non-volatile semiconductor memory (simply put, it can retain stored data even when the power is off). Its advantages include small size, low power consumption, and resistance to physical damage, making it an ideal storage medium for mobile digital products. Flash memory stores data in storage cells.

[0003] However, as flash memory is used more frequently, its erase speed slows down and erase time increases. This is because the threshold voltage of the memory cells within the memory block increases with increasing use. Furthermore, if the erase capacity is insufficient, the threshold voltage of the memory cell may not be reduced to the appropriate threshold voltage, making the erase operation impossible. Summary of the Invention

[0004] In order to solve the above problems, the present application provides a memory erasing method, a memory device and a storage device, so as to improve the erasing capability of the memory blocks and improve the problem of long memory erasing operation time.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a memory erasing method, which includes: obtaining the number of cycles of the erase sub-operation of the previous erase operation performed by the current storage block of the memory; configuring the erase voltage of the current erase operation based on the number of cycles; and performing the current erase operation on the current storage block based on the configured erase voltage.

[0006] The step of configuring the erase voltage of the current erase operation based on the number of cycles includes: obtaining a preset erase voltage and a step-increase voltage; and configuring the erase voltage of the erase sub-operation in the current erase operation based on the preset erase voltage, the step-increase voltage and the number of cycles.

[0007] Among them, the erase voltage includes an initial erase voltage, and the step-increase voltage includes a first step-increase voltage; the step of configuring the erase voltage of the erase sub-operation in the current erase operation based on the preset erase voltage, the step-increase voltage and the number of cycles includes: configuring the initial erase voltage based on the preset erase voltage, the first step-increase voltage and the number of cycles; wherein the initial erase voltage is the erase voltage corresponding to the first erase sub-operation of the current storage block in the current erase operation.

[0008] Among them, the erase voltage includes multiple erase sub-voltages, the step-increase voltage includes a second step-increase voltage, and the step of configuring the erase voltage of the erase sub-operation in the current erase operation based on the preset erase voltage, the step-increase voltage and the number of cycles also includes: configuring multiple erase sub-voltages based on the initial erase voltage and the second step-increase voltage; wherein the multiple erase sub-voltages are erase voltages corresponding to subsequent erase sub-operations on the current storage block after the first erase sub-operation.

[0009] The step of obtaining the preset erase voltage and the step-increase voltage includes: obtaining the preset erase voltage and the step-increase voltage by looking up a preset lookup table based on the number of cycles.

[0010] Among them, the step of configuring the initial erase voltage based on the preset erase voltage, the first step boost voltage and the number of cycles includes: calculating the difference between the number of cycles and one, and calculating the first product of the difference and the first step boost voltage; calculating the sum of the first product and the preset erase voltage to obtain the initial erase voltage.

[0011] Among them, the steps of configuring multiple erase sub-voltages based on the initial erase voltage and the second-step boost voltage include: obtaining the number of repetitions of the erase sub-operation in the current erase operation, calculating the difference between the number of repetitions and one and the second product of the second-step boost voltage; calculating the sum of the second product and the initial erase voltage to obtain the erase sub-voltage corresponding to the current erase sub-operation.

[0012] Among them, the steps of configuring multiple erase sub-voltages based on the initial erase voltage and the second-step boost voltage include: obtaining the temperature fine-tuning voltage and the number of repetitions of the erase sub-operation in the current erase operation; calculating the second product of the difference between the number of repetitions and one and the second step boost voltage; calculating the sum of the second product, the temperature fine-tuning voltage and the initial erase voltage to obtain the erase sub-voltage corresponding to the current erase sub-operation.

[0013] The step of performing a current erase operation on the current storage block based on the configured erase voltage includes: generating an erase pulse signal based on the configured erase voltage, and performing an erase sub-operation on the storage cells of the current storage block based on the erase voltage corresponding to the erase pulse signal; performing an erase verification operation to determine whether each storage cell in the storage block is erased; and in response to the erase verification operation determining that any storage cell in the storage block is not erased, performing the erase sub-operation again, increasing the number of erase sub-operation cycles by one until each storage cell in the storage block is erased. The number of erase sub-operation cycles in the erase operation is stored.

[0014] In order to solve the above technical problems, another technical solution adopted in the present application is: providing a storage device, which includes multiple storage blocks and a control unit; the storage block includes multiple storage cell pages and multiple virtual cell pages, and the virtual cell page is used to record the number of cycles of the erase sub-operation of the last erase operation performed by the storage block; the control unit is used to configure the erase voltage of the current erase operation based on the number of cycles; and the current erase operation is performed on the current storage block based on the configured erase voltage.

[0015] At least one virtual unit page is adjacent to the memory unit page, or the virtual unit page is arranged on both sides of the memory unit page.

[0016] In order to solve the above technical problems, another technical solution adopted in the present application is: providing a storage device, which includes any one of the above storage devices.

[0017] Different from the prior art, the present application adopts the above-mentioned method. The memory erasing method of the present application first obtains the number of cycles of the erase sub-operation of the previous erase operation performed by the current storage block of the memory, and configures the erase voltage of the current erase operation based on the number of cycles; finally, the current erase operation is performed on the current storage block based on the configured erase voltage. Through the above-mentioned method, the memory erasing method of the present application can dynamically adjust the erase voltage of the current erase operation by the number of cycles of the erase sub-operation of the previous erase operation of the memory, thereby improving the erase capability of the memory storage block and improving the problem of long erase operation time of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0019] Figure 1 It is a simplified structural diagram of a storage unit of a flash memory;

[0020] Figure 2 It is a waveform diagram of erase time and number of uses;

[0021] Figure 3 This is a flow chart of an embodiment of a method for erasing a memory device of the present application;

[0022] Figure 4 yes Figure 3 A flow chart of an embodiment of step S102;

[0023] Figure 5 yes Figure 4 Flow chart of step S201 in an embodiment;

[0024] Figure 6 yes Figure 5 A flow chart of an embodiment of step S301;

[0025] Figure 7 yes Figure 5 Flowchart of step S302 in the first embodiment;

[0026] Figure 8 yes Figure 5 Flow chart of step S302 in the second embodiment;

[0027] Figure 9 yes Figure 3 A flow chart of an embodiment of step S103;

[0028] Figure 10 1 is a schematic structural diagram of an embodiment of a memory device of the present application;

[0029] Figure 11 It is a structural diagram of an embodiment of the storage device of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some, rather than all, structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0031] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0032] With the development of technology, the application of memory is becoming more and more extensive. Take flash memory as an example. Flash memory is a non-volatile semiconductor memory (simply put, it can retain stored data even when the power is off). It has the advantages of small size, low power consumption, and resistance to physical damage, making it an ideal storage medium for mobile digital products.

[0033] See also Figure 1 , Figure 1 This is a simplified structural diagram of the storage unit of the flash memory. The data information of the flash memory is stored in the storage unit. Figure 1 As shown, the memory cell includes a floating gate field effect transistor, and the memory cell stores data information through electrons in the floating gate (FG) 12. When more electrons are stored in the floating gate 12 of the memory cell of the flash memory through programming operations, the threshold voltage of the memory cell increases; when electrons are removed from the floating gate 12 of the memory cell through erasing operations, the threshold voltage of the memory cell decreases accordingly. The erasing method of the flash memory is based on the tunneling effect of electrons, by applying a negative word line voltage V to the control gate (G) 11. Wl , and at the same time, a positive erase voltage V is applied to the substrate 13 B At this time, electrons on the floating gate 12 enter the substrate 13 through the tunneling effect under the action of the electric field. After the floating gate 12 loses electrons, the threshold voltage of the memory cell decreases. When the threshold voltage drops to the reference voltage of the erased state, it indicates that the memory cell is in the erased state.

[0034] In addition, please refer to Figure 2 , Figure 2 This is a waveform diagram of the erase time and the number of times used. Figure 2 As shown in Figure 1, as flash memory is used more frequently, its erase speed slows down and the erase time increases. This is because the threshold voltage of the internal memory cells increases with increasing use. Furthermore, if the erase capacity is insufficient, the threshold voltage of the memory cells may not be erased to the appropriate threshold voltage, making the erase operation impossible.

[0035] In order to solve the above problems, this application first proposes a memory erasing method, see Figure 3 , Figure 3 FIG. 1 is a flow chart of an embodiment of a method for erasing a memory device of the present invention. For example, Figure 3 As shown, the storage erasing method of this embodiment includes steps S101 to S103:

[0036] Step S101: obtaining the number of cycles of the erase sub-operation of the last erase operation executed by the current storage block of the memory.

[0037] When performing an erasing operation on a storage block of a memory, in order to ensure that the erasing speed does not become slower and slower, the erasing voltage applied to the substrate of the storage cell of the storage block needs to be a positive step-like rising pulse voltage, that is, the erasing voltage needs to be gradually increased from the minimum initial erasing voltage at the beginning; in other embodiments, the erasing voltage can be a plurality of step-like rising pulse voltages, which can be gradually increased, or can be set to increase at intervals, for example, the erasing voltage can be increased once every 5 pulses, which is not limited here.

[0038] For example, in an erase operation, one pulse voltage can be considered as one erase sub-operation, and the number of cycles of the erase sub-operation is the number of pulses. Alternatively, N pulse voltages can be considered as one erase sub-operation, and the total number of pulses divided by N is the number of cycles of the erase sub-operation. For example, every five pulses can be considered as one erase sub-operation.

[0039] In this embodiment, this embodiment uses the virtual unit page in the current storage block to record the number of cycles of the erase sub-operation of the current storage block performing the last erase operation, and when the current storage block performs the current erase operation, obtains the number of cycles of the erase sub-operation of the current storage block of the memory in the virtual unit page performing the last erase operation.

[0040] Step S102: configuring the erase voltage of the current erase operation based on the number of cycles.

[0041] After obtaining the number of cycles of the erase sub-operation of the last erase operation performed on the storage block, the erase voltage of the current erase operation can be configured based on the number of cycles. In this embodiment, the initial erase voltage of the erase operation can be configured based on the number of cycles, that is, when the erase operation is performed on the storage block, its erase voltage can be configured based on the number of cycles, without having to start from the minimum voltage and rise in a step-like manner. In this way, the erase time of the storage block can be reduced. The configuration method of the erase voltage is described below and will not be described in detail here.

[0042] Step S103: performing a current erasing operation on the current memory block based on the configured erasing voltage.

[0043] After configuring the erase voltage corresponding to the erase sub-operation in the erase operation, the current erase operation can be performed on the current storage block, that is, the erase sub-operation is performed on the current storage block; each time the erase sub-operation is performed, an erase verification operation is performed to determine whether each storage cell in the storage block is erased; in response to the erase verification operation, if it is determined that any storage cell in the storage block is not erased, the erase voltage is adjusted to return to continue executing the erase sub-operation until each storage cell in the storage block is erased.

[0044] Different from the prior art, the present application adopts the above-mentioned method. The memory erasing method of the present application first obtains the number of cycles of the erase sub-operation of the previous erase operation performed by the current storage block of the memory, and configures the erase voltage of the current erase operation based on the number of cycles; finally, the current erase operation is performed on the current storage block based on the configured erase voltage. Through the above-mentioned method, the memory erasing method of the present application can dynamically adjust the erase voltage of the current erase operation by the number of cycles of the erase sub-operation of the previous erase operation of the memory, thereby improving the erase capability of the memory storage block and improving the problem of long erase operation time of the memory.

[0045] Optionally, the method for configuring the erase voltage of the current erase operation based on the number of cycles is as follows: Figure 4 See Figure 4 , Figure 4 yes Figure 3 Schematic diagram of the process of step S102 in an embodiment. Figure 4 As shown, this embodiment can be Figure 3 The method shown implements step S102, and the implementation steps include steps S201 to S202:

[0046] Step S201: Obtain a preset erase voltage and a step-up voltage.

[0047] In this embodiment, when configuring the erase voltage for the current erase operation, it is first necessary to obtain a preset erase voltage and a step-up voltage. The preset erase voltage can be set to the minimum erase voltage, and the step-up voltage is a constant voltage difference obtained by increasing the minimum erase voltage in a step-like manner. Furthermore, in this embodiment, the step-up voltage can be set based on actual conditions and is not limited here.

[0048] Step S202: configuring an erase voltage for an erase sub-operation in a current erase operation based on a preset erase voltage, a step-increase voltage, and a cycle count.

[0049] After obtaining the preset erase voltage and the step-increase voltage, the erase voltages for the erase sub-operations in the current erase operation can be configured based on the preset erase voltage, the step-increase voltage, and the number of cycles. First, the initial erase voltage for the first erase sub-operation in the current erase operation can be configured based on the number of cycles, the preset erase voltage, and the step-increase voltage. Then, multiple erase sub-voltages for subsequent erase sub-operations can be configured in a step-like manner based on the initial erase voltage and the step-increase voltage. When every memory cell in the memory block is erased, the current erase operation ends.

[0050] Optionally, a method for configuring the erase voltage of the erase sub-operation in the current erase operation based on the preset erase voltage, the step-increase voltage and the number of cycles is as follows: Figure 5 See Figure 5 , Figure 5 yes Figure 4 In this embodiment, the erase voltage includes an initial erase voltage and a plurality of erase sub-voltages, and the step-up voltage includes a first step-up voltage and a second step-up voltage. For example, Figure 5 As shown, this embodiment can be Figure 5 The method shown implements step S201, and the implementation steps include steps S301 to S302:

[0051] Step S301: configuring an initial erase voltage based on a preset erase voltage, a first step voltage increase, and a number of cycles.

[0052] As previously mentioned, an erase operation includes multiple erase sub-operations. The initial erase voltage is the erase voltage corresponding to the first erase sub-operation performed on the current memory block during the current erase operation, and the multiple erase sub-voltages are the erase voltages corresponding to subsequent erase sub-operations performed on the current memory block after the first erase sub-operation. Before every memory cell in the memory block is erased, the erase sub-operations must be repeated. During these repeated erase sub-operations, the erase voltages corresponding to each erase sub-operation increase in a step-like manner to ensure that the memory cells are erased.

[0053] When configuring the erase voltage for the current erase operation, in order to improve the problem of long erase operation time of the memory, it is necessary to increase the initial erase voltage of the first erase sub-operation of the current erase operation. In this embodiment, this embodiment configures the initial erase voltage based on the preset erase voltage, the first step voltage increase, and the number of erase sub-operation cycles of the previous erase operation. The configuration method is illustratively described below and will not be repeated here.

[0054] Step S302 : configuring a plurality of erasing sub-voltages based on the initial erasing voltage and the second step voltage boost.

[0055] After the current initial erasing voltage is configured, a plurality of corresponding erasing sub-voltages for subsequent erasing sub-operations can be configured based on the initial erasing voltage and the second-step boost voltage in a step-like manner.

[0056] Among them, the first step-up voltage and the second step-up voltage can be set to the same step-up voltage or different step-up voltages, that is, the first step-up voltage and the second step-up voltage can be set based on actual needs and are not limited here.

[0057] Optionally, based on Figure 4 In this embodiment, illustratively, step S201 can be implemented as follows:

[0058] A preset erase voltage and a step-increase voltage are obtained by looking up a preset lookup table based on the number of cycles.

[0059] That is, in this embodiment, a preset query table of the number of cycles of the erase sub-operation of the previous erase operation, the step-increase voltage and the preset erase voltage can be constructed and stored in the control unit. When the current erase operation is performed, the preset query table can be looked up by the number of cycles of the erase sub-operation of the previous erase operation to obtain the preset erase voltage and step-increase voltage of the current erase operation.

[0060] Furthermore, in other embodiments, the preset erase voltage and the step-increase voltage may also be set to default values, which is not limited here.

[0061] Optionally, the method for configuring the initial erase voltage based on the preset erase voltage, the first step voltage and the number of cycles is as follows: Figure 6 See Figure 6 , Figure 6 yes Figure 5 Schematic diagram of the process of step S301 in an embodiment. Figure 6 As shown, this embodiment can be Figure 6 The method shown implements step S301, and the implementation steps include steps S401 to S402:

[0062] Step S401: Calculate the difference between the number of cycles and one, and calculate a first product of the difference and the first step voltage increase.

[0063] In this embodiment, when the preset erase voltage V ini 、The first step is to increase the voltage V step1 After the number of cycles N1, the difference between the number of cycles N1 and one can be calculated, and the difference and the first step voltage V step1 The first product of (N1-1)*V step1 .

[0064] Step S402 : calculating the sum of the first product and the preset erase voltage to obtain an initial erase voltage.

[0065] Calculate the first product (N1-1)*V step1 and preset erase voltage V ini The sum of the values ​​can be used to obtain the initial erase voltage V0.

[0066] For example, in this embodiment, after obtaining the preset erase voltage V ini 、The first step is to increase the voltage V step1 After the number of cycles N1, the initial erase voltage V0 can be configured based on the following formula (1), which is as follows:

[0067] V0=V ini +(N1-1)*V step1 (1)

[0068] Optionally, a method for configuring multiple erase sub-voltages based on the initial erase voltage and the second step voltage increase is as follows: Figure 7 See Figure 7 , Figure 7 yes Figure 5 Flowchart of step S302 of the first embodiment. Figure 7 As shown, this embodiment can be Figure 7 The method shown implements step S302, and the implementation steps include steps S501 to S503:

[0069] Step S501: Obtain the number of repetitions of the erase sub-operation in the current erase operation.

[0070] After configuring the initial erase voltage V based on the above formula (1) ini After that, if the current erasing operation is to repeat the subsequent erasing sub-operation, the number of repetitions N2 of the erasing sub-operation in the current erasing operation is obtained, that is, the number of times the erasing sub-operation in the current erasing operation has been executed (including the current number) is obtained.

[0071] Step S502: Calculate the second product of the difference between the number of repetitions and one and the second step voltage increase.

[0072] Calculate the difference between the number of repetitions N2 and 1 and the second step voltage V step2 The second product of (N2-1)*V step2 .

[0073] Step S503: Calculate the sum of the second product and the initial erase voltage to obtain an erase sub-voltage corresponding to the current erase sub-operation.

[0074] When obtaining the second product (N2-1)*V step2 Then, calculate the second product (N2-1)*V step2 The sum of the initial erase voltage V0 and the erase sub-voltage V corresponding to the current erase sub-operation can be obtained. n .

[0075] For example, in this embodiment, after obtaining the initial erase voltage V0 and the second step voltage V step2 After the number of repetitions N2, the erase voltage V can be configured based on the following formula (2): n , formula (2) is as follows:

[0076] V n =V0+(N2-1)*V step2 (2)

[0077] Optionally, a method for configuring multiple erase sub-voltages based on the initial erase voltage and the second step voltage increase is as follows: Figure 8See Figure 8 , Figure 8 yes Figure 5 Schematic diagram of the flow chart of the second embodiment of step S302 in FIG. Figure 8 As shown, this embodiment can be Figure 8 The method shown implements step S302, and the implementation steps include steps S601 to S603:

[0078] Step S601: obtaining the temperature fine-tuning voltage and the number of repetitions of the erase sub-operation in the current erase operation.

[0079] In this embodiment, in order to better avoid the influence of ambient temperature on the erase operation, a temperature fine-tuning voltage V is set. tcoshift When configuring multiple erase sub-voltages, it is necessary not only to obtain the number of repetitions of the erase sub-operation in the current erase operation, but also to obtain the temperature fine-tuning voltage V tcoshift Among them, the temperature fine-tuning voltage V tcoshift It can be set according to actual situation.

[0080] Step S602: Calculate the second product of the difference between the number of repetitions and one and the second step voltage increase.

[0081] Step S602 is the same as step S502 and will not be described again.

[0082] Step S603: Calculate the sum of the second product, the temperature fine-tuning voltage, and the initial erase voltage to obtain an erase sub-voltage corresponding to the current erase sub-operation.

[0083] When obtaining the second product (N2-1)*V step2 Then, calculate the second product (N2-1)*V step2 , Temperature fine-tuning voltage V tcoshift The sum of the initial erase voltage V0 and the erase sub-voltage V corresponding to the current erase sub-operation can be obtained. n .

[0084] For example, in this embodiment, after obtaining the initial erase voltage V0 and the temperature fine-tuning voltage V tcoshift , the second step increases the voltage V step2 After the number of repetitions N2, the erase voltage V can be configured based on the following formula (3): n , formula (3) is as follows:

[0085] V n =V0+(N2-1)*V step2 +V tcoshift (3)

[0086] Optionally, a method for performing a current erase operation on a current storage block based on the configured erase voltage is as follows: Figure 9 See Figure 9 , Figure 9 yes Figure 3 Schematic diagram of the process of step S103 in an embodiment. Figure 9 As shown, this embodiment can be Figure 9 The method shown implements step S103, and the implementation steps include steps S701 to S703:

[0087] Step S701 : generating an erase pulse signal based on the configured erase voltage, and performing an erase sub-operation on the memory cells of the current memory block based on the erase voltage corresponding to the erase pulse signal.

[0088] In this embodiment, the control unit of this embodiment includes an erase voltage configuration module and an erase voltage generation module. The erase voltage configuration module is used to implement the step of configuring the erase voltage of the current erase operation based on the number of cycles of the erase sub-operation in the previous erase operation in the above embodiment. The erase voltage generation module generates an erase pulse signal based on the configured erase voltage, and performs an erase sub-operation on the storage unit of the current storage block based on the erase voltage corresponding to the erase pulse signal.

[0089] That is, the erase voltage generation module outputs the erase sub-voltage corresponding to the erase sub-operation to the Figure 1 The substrate of the memory cell shown is used to implement an erase sub-operation on the memory cells of the current memory block.

[0090] Step S702: performing an erase verification operation to determine whether each memory cell in the memory block is erased.

[0091] After each erase sub-operation, an erase verification operation needs to be performed on the current storage block to determine whether each storage cell in the storage block has been erased. That is, after each erase sub-operation, it is necessary to determine whether the threshold voltage of each storage cell in the current storage block is less than the reference voltage corresponding to the erase state. If the threshold voltage of each storage cell is less than the reference voltage corresponding to the erase state, it means that each storage cell in the current storage block has been erased. If the threshold voltage of any storage cell is greater than the reference voltage corresponding to the erase state, it means that the storage cell has not been erased.

[0092] Step S703: In response to the erase verification operation determining that any memory cell in the memory block is not erased, the erase sub-operation is performed again, and the number of cycles of the erase sub-operation is increased by one until every memory cell in the memory block is erased.

[0093] As previously mentioned, if the threshold voltage of any memory cell is greater than the reference voltage corresponding to the erase state, it indicates that the memory cell has not been erased. That is, if the erase verification operation determines that any memory cell in the memory block has not been erased, the erase sub-operation is performed again, and the number of erase sub-operation cycles is increased by one until every memory cell in the memory block is erased. When the erase sub-operation is performed again, the current erase pulse signal needs to be adjusted, and the current erase voltage needs to be adjusted for the next erase sub-operation, and the erase voltage is increased by one step voltage.

[0094] Step S704: storing the number of cycles of the erase sub-operation in the erase operation.

[0095] When each storage cell in the storage block is erased, the count of the number of cycles of the erase sub-operation can be obtained, and the count is stored as the number of cycles of the erase sub-operation in the virtual cell page corresponding to the storage block. When the storage block performs the next erase operation, the next erase operation can be performed based on the number of cycles of the erase sub-operation.

[0096] Optionally, this application further proposes a storage device, see Figure 10 , Figure 10 FIG. 1 is a schematic diagram of the structure of an embodiment of the memory device of the present application. Figure 10 As shown, the memory device 100 of this embodiment includes a plurality of memory blocks 101 and a control unit 102 .

[0097] Among them, the storage block 101 includes multiple storage cell pages 1011 and multiple virtual cell pages 1012, wherein the storage cell page 1011 includes multiple storage cells, the virtual cell page 1012 includes multiple virtual cells, and the virtual cell page 1012 is used to record the number of cycles of the erase sub-operation of the last erase operation performed by the storage block 101; the control unit 102 is used to configure the erase voltage of the current erase operation based on the number of cycles; and perform the current erase operation on the current storage block based on the configured erase voltage.

[0098] like Figure 10As shown, in this embodiment, the memory device 100 of this embodiment includes multiple memory blocks 101, each of which is connected to a bit line. GSL and SS1 correspond to two switching transistors. By controlling these two switching transistors, the memory cell pages 1011 in the middle portion thereof are selected, i.e., the memory cell pages 1011 corresponding to WL0, WL1, ..., WLN. WL0, WL1, ..., WLN can be referred to as data word lines (data WLs). Once selected, read, write, or erase operations can be performed. In memory block 101, to ensure that the edge data WLs, i.e., WL0 and WLn, have the same environment as the middle memory cell page 1011, dummy cell pages 1012, i.e., DDWL1 and DDWL2, are added to the edge data WLs. During operation, the dummy cell pages 1012 record the number of erase sub-operation cycles of the previous erase operation performed by the memory block 101.

[0099] In addition, if Figure 10 As shown, the control unit 102 includes an erase voltage generating module 1021 and an erase voltage configuration module 1022. The erase voltage configuration module 1022 is used to configure the erase voltage of the current erase operation based on the number of cycles of the erase sub-operation of the previous erase operation. The erase voltage generating module 1021 is used to perform the current erase operation on the current storage block based on the configured erase voltage, that is, to load the generated erase voltage onto the substrate of the storage unit 1011 as described above.

[0100] Alternatively, as Figure 10 As shown, dummy cell pages 1012 can be provided on both sides of the memory cell page 1011. In this embodiment, two dummy cell pages 1012 are provided, namely DDWL1 and DDWL2. In this embodiment, the dummy cell pages 1012 are not only used to ensure that the environment of the memory cell pages 1011 at the edge is the same as that of the memory cell page 1011 in the middle, but also used to record the number of erase sub-operations of the previous erase operation.

[0101] In other embodiments, at least one virtual unit page 1012 may be adjacent to the memory unit page 1011 , that is, at least one virtual unit page 1012 may be disposed on one side of the memory unit page 1011 , which is not limited here.

[0102] Optionally, this application further proposes a storage device, see Figure 11 , Figure 11 This is a schematic diagram of the structure of an embodiment of the storage device of the present application. Figure 11 As shown, the storage device 200 of this embodiment includes the storage device 100 of any of the above embodiments.

[0103] In this embodiment, the memory device 100 may be a flash memory device.

[0104] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for erasing a memory, characterized in that: include: Obtaining the number of cycles of the erase sub-operation of the last erase operation performed on the current storage block of the memory; configuring an erase voltage for a current erase operation based on the number of cycles; The current erasing operation is performed on the current storage block based on the configured erasing voltage.

2. The erasing method according to claim 1, wherein: The step of configuring the erase voltage of the current erase operation based on the number of cycles includes: Get the preset erase voltage and step-up voltage; An erase voltage of an erase sub-operation in the current erase operation is configured based on the preset erase voltage, the step-increase voltage, and the number of cycles.

3. The erasing method according to claim 2, wherein: The erase voltage includes an initial erase voltage, and the step-increase voltage includes a first step-increase voltage; and the step of configuring the erase voltage of the erase sub-operation in the current erase operation based on the preset erase voltage, the step-increase voltage, and the number of cycles includes: configuring the initial erase voltage based on the preset erase voltage, the first step-up voltage, and the number of cycles; The initial erasing voltage is an erasing voltage corresponding to the first erasing sub-operation performed on the current storage block in the current erasing operation.

4. The erasing method according to claim 3, wherein: The erase voltage includes a plurality of erase sub-voltages, the step-increase voltage includes a second step-increase voltage, and the step of configuring the erase voltage of the erase sub-operation in the current erase operation based on the preset erase voltage, the step-increase voltage, and the number of cycles further includes: configuring the plurality of erase sub-voltages based on the initial erase voltage and the second step-up voltage; The multiple erasing sub-voltages are erasing voltages corresponding to subsequent erasing sub-operations performed on the current storage block after the first erasing sub-operation.

5. The erasing method according to claim 2, wherein: The step of obtaining the preset erase voltage and the step-increase voltage includes: The preset erase voltage and the step-increase voltage are acquired by looking up the preset lookup table based on the number of cycles.

6. The erasing method according to claim 3, wherein: The step of configuring the initial erase voltage based on the preset erase voltage, the first step voltage increase, and the number of cycles includes: Calculating a difference between the number of cycles and one, and calculating a first product of the difference and the first step voltage increase; The sum of the first product and the preset erase voltage is calculated to obtain the initial erase voltage.

7. The erasing method according to claim 4, wherein: The step of configuring the plurality of erase sub-voltages based on the initial erase voltage and the second-step boost voltage includes: Get the number of repetitions of the erase sub-operation in the current erase operation, Calculating a second product of a difference between the number of repetitions and one and the second step voltage increase; The sum of the second product and the initial erase voltage is calculated to obtain an erase sub-voltage corresponding to a current erase sub-operation.

8. The erasing method according to claim 4, wherein: The step of configuring the plurality of erase sub-voltages based on the initial erase voltage and the second-step boost voltage includes: Acquire a temperature fine-tuning voltage and the number of repetitions of an erase sub-operation in the current erase operation; Calculating a second product of a difference between the number of repetitions and one and the second step voltage increase; A sum of the second product, the temperature fine-tuning voltage, and the initial erase voltage is calculated to obtain an erase sub-voltage corresponding to a current erase sub-operation.

9. The erasing method according to claim 1, wherein: The step of performing the current erasing operation on the current storage block based on the configured erasing voltage includes: generating an erase pulse signal based on the configured erase voltage, and performing an erase sub-operation on the storage cells of the current storage block based on the erase voltage corresponding to the erase pulse signal; Performing an erase verification operation to determine whether each of the storage cells in the storage block is erased; In response to the erase verification operation determining that any of the storage cells in the storage block has not been erased, the erase sub-operation is performed again, and the number of cycles of the erase sub-operation is increased by one until each of the storage cells in the storage block is erased and the number of cycles of the erase sub-operation in the erase operation is stored.

10. A memory device, characterized in that: include: A plurality of storage blocks, each storage block including a plurality of storage unit pages and a plurality of virtual unit pages; The virtual unit page is used to record the number of cycles of the erase sub-operation of the last erase operation performed by the storage block; A control unit is configured to configure an erase voltage of a current erase operation based on the number of cycles; and perform the current erase operation on the current storage block based on the configured erase voltage.

11. The memory device according to claim 10, wherein: At least one of the virtual unit pages is adjacent to the memory unit page, or the virtual unit pages are arranged on both sides of the memory unit page.

12. A storage device, characterized in that: A storage device comprising any one of claims 10-11.

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