Driving method, driving circuit and random access memory thereof

Abstract

The invention provides a driving method, a driving circuit and a random access memory thereof, the driving method is used for driving a write-in auxiliary circuit of a target random access memory, and the method comprises the following steps: obtaining a current working voltage of the target random access memory; determining whether to drive a write-in auxiliary circuit to work according to the current working voltage and a preset reference voltage; wherein the preset reference voltage is obtained by calibrating the working voltage of the target random access memory under the condition that a writing error occurs, so that the writing auxiliary circuit is driven to start working only when the current working voltage of the random access memory is lower than or equal to the preset reference voltage; and when the current working voltage is higher than the preset reference voltage, the write auxiliary circuit is driven to stop working, so that the purpose of saving the power consumption of the random access memory is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a driving method, a driving circuit and a random access memory thereof. Background Art

[0002] With the current Central Processing Unit (CPU) single-core frequency increase limited, increasing the number of computing cores has become the mainstream. As the number of CPU cores increases, the proportion of static random-access memory (SRAM) storage arrays used on the chip continues to increase. Larger SRAM arrays consume more power. To reduce chip area and power consumption, the size of the basic storage unit (bitcell) needs to be minimized, and the supply voltage needs to be lowered as much as possible. However, in recent years, the reduction in storage unit (bitcell) size and the reduction in SRAM array supply voltage have clearly reached a bottleneck, the main limiting factor being insufficient bitcell write capability.

[0003] To address the issue of insufficient SRAM bitcell write capability, a write-assist circuit is typically incorporated into current SRAM IP designs. This circuit can improve bitcell write capability by reducing the bitcell supply voltage, raising the wordline voltage, or providing a negative voltage to the bitline / complementary bitline bar.

[0004] The above-mentioned write assist circuit is actually only necessary to be turned on when the SRAM operating voltage is low. After the operating voltage is raised, the write capability of the SRAM is also enhanced. At this time, there is no need to turn on the write assist circuit. However, once the current write assist circuit is turned on through the fuse, regardless of whether the SRAM power supply voltage is high or low, the write assist circuit will be fixedly triggered during the write operation, resulting in power waste. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a driving method, a driving circuit and a random access memory thereof, so as to solve the current problem of power consumption waste caused by the write assist circuit being turned on regardless of whether the SRAM operating voltage changes after the write assist circuit is turned on.

[0006] In the first aspect, the present application provides a driving method for driving a write assist circuit of a target random access memory, the method comprising: obtaining the current operating voltage of the target random access memory; determining whether to drive the write assist circuit to operate based on the current operating voltage and a preset reference voltage; wherein the preset reference voltage is obtained by calibrating the operating voltage of the target random access memory in the event of a write error.

[0007] The driving method of the above design calibrates the working voltage of the random access memory in the event of a write error as a preset reference voltage, and then implements different driving of the write assist circuit of the random access memory based on the working voltage and the reference voltage of the random access memory, so that the write assist circuit is driven to start working only when the current working voltage of the random access memory is lower than or equal to the preset reference voltage, and the write assist circuit is driven to stop working when the current working voltage is higher than the preset reference voltage, thereby achieving the purpose of saving the power consumption of the random access memory.

[0008] In an optional implementation of the first aspect, whether to drive the write assist circuit to work is determined based on the current operating voltage and the preset reference voltage, including: judging whether the current operating voltage is less than or equal to the preset reference voltage; if it is determined that the current operating voltage is less than or equal to the preset reference voltage, sending a first drive signal to the write assist circuit; wherein the first drive signal includes a signal for driving the write assist circuit to work.

[0009] In an optional implementation of the first aspect, after determining whether the current operating voltage is less than or equal to the preset reference voltage, determining whether to drive the write assist circuit to work is performed based on the current operating voltage and the preset reference voltage, and also including: if it is determined that the current operating voltage is greater than the preset reference voltage, sending a second drive signal to the write assist circuit; wherein the second drive signal includes a signal for driving the write assist circuit to stop working.

[0010] In the above-mentioned implementation mode, this scheme drives the write assist circuit to start working when the current operating voltage of the random access memory is lower than or equal to the reference voltage, thereby driving the write assist circuit of the target random access memory to improve the write capability of the target random access memory; when the current operating voltage is higher than the preset reference voltage, the write assist circuit is driven to stop working, thereby reducing the power consumption of the write assist circuit of the random access memory that continues to work under high operating voltage.

[0011] In an optional implementation of the first aspect, the method for obtaining the preset reference voltage includes: performing a yield test on the target random access memory; and obtaining the preset reference voltage based on the operating voltage of the target random access memory at which a write error occurs during the yield test.

[0012] In an optional implementation of the first aspect, a yield test is performed on the target random access memory, including obtaining test data; controlling the target random access memory to write the test data at a nominal operating voltage; when it is detected that no error occurs in the test data written to the target random access memory at the nominal operating voltage, sequentially reducing the operating voltage of the target random access memory according to a preset voltage step size, and detecting the test data written to the target random access memory after each reduction in the operating voltage until an error is detected in the test data written to the target random access memory; obtaining a preset reference voltage based on the operating voltage of the target random access memory where a write error occurs during the yield test, including: recording the operating voltage of the target random access memory when a write error occurs for the first time when the test data written to the target random access memory, and obtaining the preset reference voltage.

[0013] In the above implementation mode, this scheme can calibrate and adapt the voltage (reference voltage) for turning on the write assist circuit according to the yield test results of the random access memory, and thus can adjust the reference voltage accordingly according to the actual production situation of the random access memory while saving power consumption, thereby realizing the driving of the write assist circuit of random access memory with different model parameters, thereby improving the applicability of the designed driving method.

[0014] In a second aspect, the present application provides a driving circuit for driving a write assist circuit of a target random access memory; comprising: a comparison control module and a signal driving module; the first input end of the comparison control module is used to receive the current operating voltage of the target random access memory, and the second input end of the comparison control module is used to receive a preset reference voltage; the output end of the comparison control module is electrically connected to the input end of the signal driving module; the output end of the signal driving module is electrically connected to the write assist circuit; wherein, the preset reference voltage is obtained by calibrating the operating voltage of the target random access memory in the event of a write error; the comparison control module is used to determine whether to drive the write assist circuit to work based on the current operating voltage and the preset reference voltage.

[0015] The driving circuit designed above calibrates the working voltage of the random access memory in the event of a write error as a preset reference voltage, and then implements different drives for the write assist circuit of the random access memory based on the working voltage and the reference voltage of the random access memory based on the comparison control module, so that the write assist circuit is driven to start working only when the current working voltage of the random access memory is lower than or equal to the preset reference voltage, and the write assist circuit is driven to stop working when the current working voltage is higher than the preset reference voltage, thereby achieving the purpose of saving the power consumption of the random access memory.

[0016] In an optional embodiment of the second aspect, the comparison control module includes a voltage comparator; the positive input terminal of the voltage comparator is used to receive the current operating voltage, the reverse input terminal of the voltage comparator is used to receive a preset reference voltage, and the output terminal of the voltage comparator is electrically connected to the input terminal of the signal driving module; the voltage comparator is used to send a first drive signal to the signal driving module when the current operating voltage is less than or equal to the preset reference voltage; wherein the first drive signal includes a signal for driving the write assist circuit to work; the voltage comparator is also used to send a second drive signal to the signal driving module when the current operating voltage is greater than the preset reference voltage; wherein the second drive signal includes a signal for driving the write assist circuit to stop working.

[0017] In the above implementation manner, this solution uses a simple voltage comparator to compare the current working voltage of the random access memory with a preset reference voltage and drive the output, thereby simplifying the driving circuit structure and saving device costs.

[0018] In an optional embodiment of the second aspect, the signal driving module includes a first inverter, a CMOS inverter, a second inverter and a first NAND gate; the input end of the first inverter is electrically connected to the output end of the voltage comparator; the input end of the CMOS inverter is electrically connected to the input end of the first inverter, and the output end of the CMOS inverter is electrically connected to the input end of the second inverter; the output end of the second inverter is connected to the first input end of the first NAND gate, and the second input end of the first NAND gate is used to receive an activation signal of the write assist circuit.

[0019] In an optional implementation of the second aspect, the driving circuit also includes an isolation module; the isolation module is arranged between the signal driving module and the write assist circuit; the isolation module is used to shield the driving signal transmitted by the signal driving module to the write assist circuit when receiving the isolation signal.

[0020] In the above implementation manner, the isolation module designed in this solution can shield and control the driving signal transmitted between the signal driving module and the write assist circuit, so that the signal output by the driving circuit can be controlled, thereby improving the controllability of the designed driving circuit.

[0021] In a third aspect, the present application provides a random access memory comprising a driving circuit and a write assist circuit according to any optional embodiment of the second aspect, wherein an output end of a signal driving module of the driving circuit is electrically connected to the write assist circuit.

[0022] The random access memory of the above-mentioned design includes the driving circuit described above. Therefore, the comparison control module in the driving circuit of the random access memory can realize different driving of the write assist circuit of the random access memory based on the operating voltage and reference voltage of the random access memory, so that the write assist circuit is driven to start working only when the current operating voltage of the random access memory is lower than or equal to the preset reference voltage, and the write assist circuit is driven to stop working when the current operating voltage is higher than the preset reference voltage, thereby achieving the purpose of saving the power consumption of the random access memory.

[0023] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of a first flow chart of a driving method provided in an embodiment of the present application; Figure 2 A second flow chart of the driving method provided in an embodiment of the present application; Figure 3 A third flow chart of the driving method provided in an embodiment of the present application; Figure 4 A schematic diagram of a first circuit structure of a driving circuit provided in an embodiment of the present application; Figure 5 A schematic diagram of a second circuit structure of a driving circuit provided in an embodiment of the present application; Figure 6 A third circuit structure diagram of the driving circuit provided in an embodiment of the present application; Figure 7 A fourth circuit structure diagram of the driving circuit provided in an embodiment of the present application; Figure 8 A schematic diagram of a negative voltage generation and column selection circuit provided in an embodiment of the present application; Figure 9 A schematic diagram of the structure of a random access memory provided in an embodiment of the present application; Figure 10 A schematic diagram of the internal module connections of the random access memory provided in an embodiment of the present application.

[0026] Icon: 1-driving circuit; 10-comparison control module; 20-signal driving module; 30-isolation module; A-write auxiliary circuit; L1-voltage comparator; F1-first inverter; F2-second inverter; D1-first NAND gate; N1-CMOS inverter; MPX1-first PMOS transistor; MPX2-second PMOS transistor; MNX1-first NMOS transistor; MNX2-second NMOS transistor; MNX3-third NMOS transistor. DETAILED DESCRIPTION

[0027] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0029] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.

[0030] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0032] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0033] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0034] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0035] With the current Central Processing Unit (CPU) single-core frequency increase limited, increasing the number of computing cores has become the mainstream. As the number of CPU cores increases, the proportion of static random-access memory (SRAM) storage arrays used on the chip continues to increase. Larger SRAM arrays consume more power. To reduce chip area and power consumption, the size of the basic storage unit (bitcell) needs to be minimized, and the supply voltage needs to be lowered as much as possible. However, in recent years, the reduction in storage unit (bitcell) size and the reduction in SRAM array supply voltage have clearly reached a bottleneck, the main limiting factor being insufficient bitcell write capability.

[0036] To address the issue of insufficient SRAM bitcell write capability, a write-assist circuit is typically incorporated into current SRAM IP designs. This circuit can improve the bitcell write capability by reducing the bitcell supply voltage, raising the wordline voltage, or providing a negative voltage on the bitline / complementary bitline bar.

[0037] The above-mentioned write assist circuit is actually only necessary to be turned on when the SRAM operating voltage is low. After the operating voltage is raised, the write capability of the SRAM is also enhanced. At this time, there is no need to turn on the write assist circuit. However, once the current write assist circuit is turned on through the fuse, regardless of whether the SRAM power supply voltage is high or low, the write assist circuit will be fixedly triggered during the write operation, resulting in power waste.

[0038] Based on the above problems, the present application designs a driving method, a driving circuit, and a random access memory thereof. By calibrating the operating voltage of the random access memory in the event of a write error as a reference voltage, the write assist circuit of the random access memory is then driven based on the operating voltage and reference voltage of the random access memory. As a result, the present solution only turns on the write assist circuit when the operating voltage of the random access memory is lower than or equal to the reference voltage, and turns off the write assist circuit when the operating voltage is higher than the reference voltage, thereby saving power when the write assist circuit of the random access memory operates at a high operating voltage. In addition, the present solution can calibrate and adapt the voltage (reference voltage) at which the write assist circuit is turned on based on the yield test results of the random access memory. Thus, while saving power, the reference voltage can be adjusted accordingly based on the actual production conditions of the random access memory, thereby improving the applicability of the present solution.

[0039] Based on the above ideas, this application first provides a driving method, which can be applied to a driving controller, a driving chip, a driving circuit, etc. Figure 1 As shown, the driving method can be implemented by the following methods, including: Step S100: obtaining the current operating voltage of the target random access memory.

[0040] Step S110 : determining whether to drive the write assist circuit to operate according to the current operating voltage and the preset reference voltage.

[0041] The target random access memory refers to a static random access memory (SRAM) whose write assist circuit currently needs to be driven and adjusted. The target random access memory is equipped with a write assist circuit, which is a circuit module used to assist the SRAM in completing write operations, aiming to improve the speed, stability and reliability of write operations. Specifically, it can be a negative voltage generating circuit for providing a negative voltage to improve the bit cell write capability. The write assist circuit can assist the target random access memory in writing data when the operating voltage of the target random access memory is low.

[0042] In the above-described embodiment, this solution can collect / acquire the current operating voltage of the target RAM in real time. The specific acquisition method can be adaptively adjusted according to the specific application scenario. For example, as a possible implementation, the power management chip converts the power supply output voltage to the operating voltage required by the target RAM, such as 1.2V, 0.9V, or 0.6V, based on system requirements, and transmits the voltage to the target RAM via a power supply line. If the target RAM uses a power management chip for power voltage conversion, this solution can collect the output voltage of the power management chip in real time to obtain the real-time operating voltage of the target RAM.

[0043] In the case of obtaining the current operating voltage of the target random access memory, this solution can also obtain a preset reference voltage. The preset reference voltage is obtained by calibrating the operating voltage of the target random access memory when a write error occurs. As a possible implementation method, the preset reference voltage can be obtained by performing a yield test on the target random access memory.

[0044] Specifically, as a possible implementation method, Figure 2 As shown, the method for obtaining the preset reference voltage may include: Step S200: performing a yield test on the target random access memory.

[0045] Step S210: Obtain a preset reference voltage according to the operating voltage at which a write error occurs in the target random access memory during the yield test process.

[0046] In the above embodiment, the yield test of static random access memory is a test method for evaluating the proportion of qualified products in the production process of SRAM chips, aiming to detect whether there are various manufacturing defects and functional abnormalities in the chips to ensure that product quality and performance meet the requirements.

[0047] In the yield test process of the above-mentioned embodiment, this scheme can first obtain test data, then control the target random access memory to write the test data at the nominal operating voltage, and then detect whether the test data written by the target random access memory at the nominal operating voltage has an error. If no error occurs, the operating voltage of the target random access memory is sequentially reduced according to the preset voltage step size, and the test data written by the target random access memory after each reduction in the operating voltage is detected until an error is detected in the test data written by the target random access memory, and finally record the operating voltage of the target random access memory when the test data written by the target random access memory has a write error for the first time, thereby obtaining the preset reference voltage.

[0048] As a specific example, this solution may utilize the following test process on the target random access memory: First, install the target random access memory on the test circuit board, ensure that the pins are connected correctly and firmly, connect the power supply module, logic analyzer or oscilloscope, data acquisition equipment and other hardware devices, connect them according to the correct electrical connection method, and ensure that they are well grounded.

[0049] The power supply module is started and the output voltage is set to the nominal operating voltage of the target random access memory. For example, when the nominal voltage of the target random access memory is 1.0V, the output voltage of the power supply module is adjusted to 1.0V in this solution.

[0050] Then run the test program to control the target random access memory to write test data under the nominal operating voltage. For example, the test data can be test data of all 0s, test data of all 1s, or test data consisting of alternating 0s and 1s, etc. Then read the data written by the target random access memory and compare it with the test data itself to ensure that the target random access memory can work normally under the nominal voltage and no write errors occur.

[0051] The output voltage of the power supply module is gradually reduced by a preset voltage step size, for example, by 0.05V each time. Each time the voltage is reduced, a test program is run, test data is written to the target random access memory, and then read for verification. The current voltage value and the result of whether a write error occurs are recorded.

[0052] Continue to lower the voltage until the test program detects a write error and records the voltage value at this time. This voltage value is the approximate critical voltage value of the target random access memory from normal write function to write error occurrence, that is, the voltage value is calibrated as the preset reference voltage.

[0053] In the above implementation mode, this solution can calibrate and adapt the voltage (reference voltage) for turning on the write assist circuit according to the yield test results of the random access memory, and then, while saving power consumption, the reference voltage can be adjusted accordingly according to the actual production situation of the random access memory, thereby improving the applicability of this solution.

[0054] When the current operating voltage and the preset reference voltage of the target random access memory are obtained in the above manner, the present solution executes step S110 , ie, determining whether to drive the write assist circuit to operate according to the current operating voltage and the preset reference voltage.

[0055] As a possible implementation method, this solution can compare the current operating voltage of the target random access memory with a preset reference voltage to determine whether to drive the write assist circuit to work, such as Figure 3 Shown, including: Step S300: Determine whether the current operating voltage is less than or equal to a preset reference voltage. If so, go to step S310; if not, go to step S320.

[0056] Step S310: Sending a first driving signal to the write assist circuit.

[0057] Step S320: Sending a second driving signal to the write assist circuit.

[0058] In the above embodiment, this scheme compares the current operating voltage of the target random access memory with the preset reference voltage. When the current operating voltage is less than or equal to the preset reference voltage, it means that the current operating voltage of the target random access memory is low, and the target random access memory cannot complete the write function by itself. In this case, this scheme sends a first drive signal to the write assist circuit. The first drive signal includes a signal for driving the write assist circuit to work, thereby driving the write assist circuit of the target random access memory to improve the write capability of the target random access memory.

[0059] When the current operating voltage is greater than the preset reference voltage, it means that the write capability of the target random access memory at the current operating voltage can meet the write function requirements. In this case, the present solution sends a second drive signal to the write assist circuit. The second drive signal is used to drive the write assist circuit to stop working, thereby driving the write assist circuit of the target random access memory to stop working, thereby saving the power consumption of the write assist circuit of the random access memory under high operating voltage.

[0060] The driving method of the above design calibrates the working voltage of the random access memory in the event of a write error as a preset reference voltage, and then implements different driving of the write assist circuit of the random access memory based on the working voltage and the reference voltage of the random access memory, so that the write assist circuit is driven to start working only when the current working voltage of the random access memory is lower than or equal to the preset reference voltage, and the write assist circuit is driven to stop working when the current working voltage is higher than the preset reference voltage, thereby achieving the purpose of saving the power consumption of the random access memory.

[0061] The present application also provides a driving circuit, through which the driving method for the write assist circuit of the target random access memory described above can be implemented. Specifically, as a specific implementation method, Figure 4 As shown, the driving circuit includes a comparison control module 10 and a signal driving module 20, the first input end of the comparison control module 10 is used to receive the current operating voltage of the target random access memory, and the second input end of the comparison control module 10 is used to receive a preset reference voltage; the output end of the comparison control module 10 is electrically connected to the input end of the signal driving module 20; the output end of the signal driving module 20 is used to be electrically connected to the write assist circuit A.

[0062] In the driving circuit designed as described above, the comparison control module 10 can compare the current operating voltage VDD of the received target random access memory with the preset reference voltage VREF, and then transmit the corresponding driving signal to the signal driving module 20 based on the comparison result of the current operating voltage VDD and the preset reference voltage VREF to drive the write auxiliary circuit A, wherein the signal driving module 20 can process and enhance the driving signal transmitted by the comparison control module 10 so that it can effectively transmit and control the load or meet the requirements of subsequent circuits.

[0063] The above-mentioned driving circuit, this solution calibrates the working voltage of the random access memory in the event of a write error as a preset reference voltage, and then based on the comparison control module, implements different drives for the write assist circuit of the random access memory based on the working voltage and the reference voltage of the random access memory, so that the write assist circuit is driven to start working only when the current working voltage of the random access memory is lower than or equal to the preset reference voltage, and the write assist circuit is driven to stop working when the current working voltage is higher than the preset reference voltage, thereby achieving the purpose of saving the power consumption of the random access memory.

[0064] As a possible implementation, Figure 5 As shown, the comparison control module 10 designed in this scheme can be specifically a voltage comparator L1, the positive input terminal of the voltage comparator L1 receives the current working voltage, the inverting input terminal of the voltage comparator L1 receives the preset reference voltage, and the output terminal of the voltage comparator L1 is electrically connected to the input terminal of the signal driving module 20.

[0065] In the above embodiment, when the current operating voltage VDD is less than or equal to the preset reference voltage VREF, the voltage comparator L1 sends a first drive signal VDECT1 to the signal driving module 20. The signal driving module 20 effectively transmits the first drive signal VDECT1 to the write assist circuit A. The first drive signal VDECT1 can drive the write assist circuit A to work, thereby driving the write assist circuit of the target random access memory to improve the write capability of the target random access memory.

[0066] When the current operating voltage VDD is greater than the preset reference voltage VREF, the voltage comparator L1 sends a second drive signal VDECT2 to the signal driver module 20. The signal driver module 20 effectively transmits the second drive signal VDECT2 to the write assist circuit A. The second drive signal VDECT2 can drive the write assist circuit A to stop operating, thereby saving power consumption of the write assist circuit of the random access memory under high operating voltage conditions. The operation of the voltage comparator L1 can be controlled by the voltage comparator enable signal NBlen. When the voltage comparator L1 needs to operate, the NBlen enable signal is input to it.

[0067] In the above implementation manner, this solution uses a simple voltage comparator to compare the current working voltage of the random access memory with a preset reference voltage and drive the output, thereby simplifying the driving circuit structure and saving device costs.

[0068] It should be noted here that in addition to the above-mentioned voltage comparator, the comparison control module 10 designed in this solution can also use other circuit components that can compare the operating voltage with the reference voltage, such as an operational amplifier, a voltage comparator integrated circuit or a voltage comparison chip, etc.

[0069] In an optional implementation manner of this embodiment, as a possible implementation manner, Figure 6 As shown, the signal driving module 20 designed in this solution may include a first inverter F1, a CMOS inverter N1, a second inverter F2 and a first NAND gate D1. The input end of the first inverter F1 is electrically connected to the output end of the voltage comparator L1; the input end of the CMOS inverter N1 is electrically connected to the input end of the first inverter F1, and the output end of the CMOS inverter N1 is electrically connected to the input end of the second inverter F2; the output end of the second inverter F2 is connected to the first input end of the first NAND gate D1, and the second input end of the first NAND gate D1 is used to receive the activation signal of the write assist circuit, and the output end of the first NAND gate D1 is electrically connected to the input end of the write assist circuit A. Among them, the CMOS inverter N1 designed in this solution can be as follows Figure 6 The CMOS inverter shown is composed of a first NMOS transistor MNX1, a second NMOS transistor MNX2, a first PMOS transistor MPX1, and a second PMOS transistor MPX2. The gate of the first PMOS transistor MPX1 connected to the reference voltage VDD can receive a fixed low-level signal FUSE, and the gate of the second NMOS transistor MNX2 connected to the ground terminal can receive a fixed high-level signal FUSEX. Of course, it can also be other forms of CMOS inverters, for example, a CMOS inverter formed by a combination of three NMOS transistors and three PMOS transistors. The number and structure of the MOS transistors in the CMOS inverter can be adaptively adjusted according to actual conditions.

[0070] The signal driving module 20 designed above assumes that the write assist circuit A of the target random access memory is turned on by a low-level signal and turned off by a high-level signal. When the current operating voltage VDD is less than or equal to the preset reference voltage VREF, the voltage comparator L1 sends a low-level first drive signal VDEC1 to the first inverter F1. This first drive signal VDEC1 is converted to a high-level signal VDECTB1 by the first inverter F1. Since signal VDECTB1 is a high-level signal, the gate of the NMOS transistor connected to the ground terminal also receives the high-level signal FUSEX. As a result, the two NMOS transistors in the CMOS inverter N1 are turned on and grounded. The high-level signal VDECTB1 is pulled down by the two NMOS transistors of the CMOS inverter N1 to form a low-level signal WAENX1. The low-level signal WAENX1 is converted to a high-level signal WAEN1 after passing through the second inverter F2. The high-level signal WAEN1 is input to one input terminal of the first NAND gate D1. When the activation signal WACTIV1 at the other input terminal of the first NAND gate D1 jumps from a low level to a high level, the signal WACTIVX1 output from the output terminal of the first NAND gate D1 jumps from a high level to a low level, thereby controlling the write assist circuit A to start operation.

[0071] When the current operating voltage VDD is greater than the preset reference voltage VREF, the voltage comparator L1 sends a second drive signal VDEC2 to the first inverter F1, which is a high-level signal. The second drive signal VDEC2 passes through the first inverter F1 to form a low-level signal VDECTB2. Since the signal VDECTB2 is a low-level signal, the two PMOS tubes in the CMOS inverter N1 are turned on, and the low-level signal VDECTB2 is pulled high by the two PMOS tubes of the CMOS inverter N1 to form a high-level signal WAENX2. The high-level signal WAENX2 passes through the second inverter F2 to form a low-level signal WAEN2. Since the first NAND gate D1 inputs the low-level signal WAEN2, the signal WACTIVX2 output from the output end of the first NAND gate D1 is converted from a low level to a high level, thereby controlling the write assist circuit A to stop working.

[0072] In an optional implementation of this embodiment, if Figure 7 As shown, the driving circuit designed in this scheme can also include an isolation module 30, which can be arranged between the signal driving module 20 and the write assist circuit A. The isolation module 30 can shield the driving signal transmitted by the signal driving module 20 to the write assist circuit A when receiving the isolation signal, wherein the isolation signal can be the same signal as the FUSE signal described above.

[0073] For details, please refer to Figure 7The isolation module 30 may specifically be a third NMOS transistor MNX3. The output end of the CMOS inverter N1 is grounded through the third NMOS transistor MNX3. When the isolation signal FUSE received by the gate of the third NMOS transistor MNX3 changes from a low level to a high level, the third NMOS transistor MNX3 is turned on. At this time, the drive signal transmitted by the CMOS inverter N1 is transmitted to the ground end through the third NMOS transistor MNX3, thereby always maintaining the signal input to the second inverter F2 at a low level. In addition, the control of the write auxiliary circuit A is independently controlled by its activation signal, thereby achieving shielding of the drive circuit.

[0074] In the above embodiment, the isolation module 30 designed in this solution can shield and control the driving signal transmitted between the signal driving module 20 and the write auxiliary circuit A, so that the signal output by the driving circuit can be controlled, thereby improving the controllability of the designed driving circuit.

[0075] In addition, it should be noted that the above-mentioned driving circuit designed in this scheme is only one of the specific implementation circuits for implementing the driving method described above. The specific driving current can be adaptively adjusted according to the actual application scenario. It is only necessary to compare the current operating voltage of the target random access memory with the preset reference voltage to output a corresponding driving signal.

[0076] The present application also provides a random access memory, such as Figure 8 and Figure 9 As shown, Figure 8 Schematic diagram of negative voltage generation and column selection circuit. Figure 9 This is a simplified structural diagram of a random access memory; the random access memory includes a driving circuit 1 and a write assist circuit A of any optional embodiment described above, wherein the output end of the signal driving module 20 of the driving circuit 1 is electrically connected to the write assist circuit A.

[0077] Specifically, if Figure 10 The figure is a structural diagram of a specific unit of a random access memory. The random access memory includes multiple input and output units (IO units). Each IO unit includes a storage cell array, a bit line precharge circuit, a column selection circuit, a write assist circuit, a write input circuit, a sense amplifier output circuit, etc. The drive circuit 1 is connected to the write assist circuit of each input and output unit, thereby simultaneously driving the write assist circuits of each input and output unit in the random access memory.

[0078] The memory cell array may be composed of multiple transistors, for example, 6 transistors, specifically including two cross-coupled inverters (4 MOS tubes) and two access transistors (NMOS). The memory cell array may form a bistable circuit through the cross-coupled inverters to latch 1 bit of data (0 or 1), and control the conduction of the access transistors through the word line (WL). Figure 8 The bit lines (BL / BLB) in the MCU transmit data.

[0079] The bit line precharge circuit precharges the bit line (BL / BLB) to a fixed voltage (such as VDD) before read and write operations to ensure that the voltage difference is quickly established during read and write operations; the column select circuit selects a specific column for read and write operations based on the column address; the write input circuit converts external input data into a drive signal to force the storage cell state to flip; the sense amplifier output circuit amplifies the tiny voltage difference of the bit line (BL / BLB) during reading and converts it into a logic level output circuit.

[0080] Taking reading as an example, the working process of the above-mentioned random access memory is that the bit line pre-charging circuit charges BL / BLB to a high level, the word line WL is activated, the access transistor of the memory cell array is turned on, and the memory cell array discharges the bit line on one side according to the storage state. The column selection circuit connects the selected local bit line to the global bit line, and the sense amplifier output circuit detects the global bit line voltage difference and amplifies it, outputting the logic level. The amplified signal is transmitted to the data bus through the output buffer.

[0081] Taking writing as an example, the working process of the above-mentioned random access memory is that the bit line pre-charging circuit charges BL / BLB to a high level, the word line WL is activated, and the column selection circuit connects the selected local bit line to the global bit line. The global bit line is connected to the write input circuit, ready to receive external write data. The external write data is converted into a complementary signal through the write input circuit. When the random access memory is in low-voltage operation, the drive circuit designed in this article drives the write auxiliary circuit to work. For example, in the case of negative bit line technology, the write auxiliary circuit briefly pulls the bit line on the non-write side to a negative voltage to increase the flip driving force of the inverter inside the memory cell; the write input circuit transmits the write data to the corresponding memory cell array through the global bit line to realize data writing.

[0082] The random access memory of the above-mentioned design includes the driving circuit described above. Therefore, the comparison control module in the driving circuit of the random access memory can realize different driving of the write assist circuit of the random access memory based on the operating voltage and reference voltage of the random access memory, so that the write assist circuit is driven to start working only when the current operating voltage of the random access memory is lower than or equal to the preset reference voltage, and the write assist circuit is driven to stop working when the current operating voltage is higher than the preset reference voltage, thereby achieving the purpose of saving the power consumption of the random access memory.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A driving method, characterized in that: The driving method is used to drive a write assist circuit of a target random access memory, and the method includes: Get the current operating voltage of the target random access memory; determining whether to drive the write assist circuit to operate according to the current operating voltage and a preset reference voltage; The preset reference voltage is obtained by calibrating the operating voltage of the target random access memory when a write error occurs.

2. The method according to claim 1, characterized in that The determining whether to drive the write assist circuit to operate according to the current operating voltage and the preset reference voltage includes: Determining whether the current operating voltage is less than or equal to the preset reference voltage; If it is determined that the current operating voltage is less than or equal to the preset reference voltage, a first drive signal is sent to the write assist circuit; wherein the first drive signal includes a signal for driving the write assist circuit to operate.

3. The method according to claim 2, characterized in that After determining whether the current operating voltage is less than or equal to the preset reference voltage, determining whether to drive the write assist circuit to operate according to the current operating voltage and the preset reference voltage further includes: If it is determined that the current operating voltage is greater than the preset reference voltage, a second driving signal is sent to the write assist circuit; wherein the second driving signal includes a signal for driving the write assist circuit to stop working.

4. The method according to claim 1, wherein in, The method for obtaining the preset reference voltage includes: Performing a yield test on the target random access memory; The preset reference voltage is obtained according to the operating voltage of the target random access memory at which a write error occurs during the yield test.

5. The method according to claim 4, characterized in that The performing a yield test on the target random access memory includes: Get test data; Controlling the target random access memory to write the test data under a nominal operating voltage; When detecting that no error occurs in the test data written to the target random access memory at the nominal operating voltage, sequentially reducing the operating voltage of the target random access memory according to a preset voltage step size, and detecting the test data written to the target random access memory after each reduction in the operating voltage until an error is detected in the test data written to the target random access memory; Obtaining the preset reference voltage according to the operating voltage of the target random access memory at which a write error occurs during the yield test includes: The operating voltage of the target random access memory is recorded when a write error occurs for the first time when the test data written to the target random access memory is written, and the preset reference voltage is obtained.

6. A driving circuit, characterized in that: The driving circuit is used to drive the write assist circuit of the target random access memory; the driving circuit includes: a comparison control module and a signal driving module; The first input terminal of the comparison control module is used to receive the current operating voltage of the target random access memory, and the second input terminal of the comparison control module is used to receive a preset reference voltage; The output end of the comparison control module is electrically connected to the input end of the signal driving module; The output end of the signal driving module is used to be electrically connected to the write assist circuit; wherein the preset reference voltage is obtained by calibrating the operating voltage of the target random access memory in the event of a write error; The comparison control module is used to determine whether to drive the write assist circuit to operate according to the current operating voltage and the preset reference voltage.

7. The driving circuit according to claim 6, wherein: The comparison control module includes a voltage comparator; The positive input terminal of the voltage comparator is used to receive the current working voltage, the negative input terminal of the voltage comparator is used to receive the preset reference voltage, and the output terminal of the voltage comparator is electrically connected to the input terminal of the signal driving module; The voltage comparator is configured to send a first driving signal to the signal driving module when the current operating voltage is less than or equal to the preset reference voltage; wherein the first driving signal includes a signal that drives the write assist circuit to operate; The voltage comparator is further configured to send a second driving signal to the signal driving module when the current operating voltage is greater than the preset reference voltage; wherein the second driving signal includes a signal that drives the write assist circuit to stop working.

8. The driving circuit according to claim 7, wherein: The signal driving module includes a first inverter, a CMOS inverter, a second inverter and a first NAND gate; The input terminal of the first inverter is electrically connected to the output terminal of the voltage comparator; The input end of the CMOS inverter is electrically connected to the input end of the first inverter, and the output end of the CMOS inverter is electrically connected to the input end of the second inverter; The output end of the second inverter is connected to the first input end of the first NAND gate, and the second input end of the first NAND gate is used to receive an activation signal of the write assist circuit.

9. The driving circuit according to claim 6, wherein: The driving circuit further includes an isolation module; The isolation module is arranged between the signal driving module and the write assist circuit; The isolation module is used to shield the driving signal transmitted by the signal driving module to the write assist circuit when receiving the isolation signal.

10. A random access memory, characterized in that: The random access memory comprises the driving circuit and the write assist circuit according to any one of claims 6 to 9; wherein the output end of the signal driving module of the driving circuit is electrically connected to the write assist circuit.

Images