High-precision capacitor forming process and capacitor thereof

Abstract

The invention relates to the technical field of electronic functional materials, and discloses a high-precision capacitor forming process and a capacitor thereof, and the high-precision capacitor forming process comprises the following steps: (1) substrate treatment and bottom electrode preparation: depositing a metal bottom electrode with the thickness of 50-150nm on the surface of a clean substrate; (2) preparation of a gradient functionalized molecular sieve skeleton film: forming an ordered mesoporous molecular sieve film with the aperture of 2-10nm on the surface of the bottom electrode by a sol-gel method, gradient chemical modification is performed on the pore wall of the molecular sieve film, a modifier comprises a silane coupling agent, and the addition amount of the modifier is 0.5-5mol% of the molar weight of the silicon source; and (3) preparation of a functionalized nanoparticle-monomer composite solution: dispersing the functionalized nanoparticles subjected to surface modification in a low-polarity monomer according to 0.5-10vol%. By constructing a gradient interface and a confinement structure, ordered distribution and interface stability control of the nanoparticles are realized, and the electrical property consistency and environmental adaptability of the composite dielectric material are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic functional materials, and in particular to a high-precision capacitor forming process and a capacitor thereof. Background Art

[0002] In the current research on high-performance dielectric materials, composite organic-inorganic dielectrics have attracted widespread attention due to their high dielectric constant and good processability, especially showing important application prospects in miniaturized and highly integrated electronic devices. However, existing composite dielectric materials generally face key technical bottlenecks such as interface mismatch, uneven particle dispersion, and poor processing compatibility. The dispersion of traditional fillers in polymer matrices often relies on physical mixing, which easily leads to nanoparticle agglomeration and the formation of local polarization enhancement zones, seriously affecting the uniformity of the electric field distribution and breakdown stability. At the same time, the interfacial bonding force between inorganic particles and the organic matrix is ​​weak, and debonding or interface defects are easily generated in a thermal and electrical coupling environment, which in turn causes dielectric performance drift and reliability degradation.

[0003] Furthermore, in practical device applications, composite dielectric materials often require low-temperature fabrication on flexible substrates or layers with low thermal stability. However, many traditional processes still rely on high-temperature sintering or energy-intensive processing methods, which not only destroys the integrity of the underlying structure but also limits their widespread application in flexible electronics, printed circuits, and heterogeneous integrated platforms. Existing material systems still lack effective solutions for balancing dielectric performance with process adaptability. In particular, the lack of a structure-interface synergistic optimization mechanism for achieving high filler loading rates while maintaining low loss and controllable thickness is a key obstacle to the development of next-generation high-performance dielectric devices. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-precision capacitor forming process and capacitor thereof, which solves the problems in the prior art such as uneven particle dispersion in composite dielectric materials, unstable interface and poor low-temperature process compatibility that affect device performance and reliability.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: A high-precision capacitor forming process includes the following steps: (1) Substrate treatment and bottom electrode preparation: deposit a metal bottom electrode with a thickness of 50-150 nm on the surface of a clean substrate; (2) Preparation of gradient functionalized molecular sieve skeleton film: An ordered mesoporous molecular sieve film with a pore size of 2-10 nm is formed on the surface of the bottom electrode by a sol-gel method. The pore wall of the molecular sieve film is subjected to gradient chemical modification. The modifier includes a silane coupling agent, and the addition amount thereof is 0.5-5 mol% of the molar amount of the silicon source; (3) Preparation of functionalized nanoparticle-monomer composite solution: dispersing surface-modified functionalized nanoparticles in a low-polarity monomer at 0.5-10 vol%, wherein the nanoparticles are selected from barium strontium titanate quantum dots, hexagonal boron nitride nanosheets, or high-k non-ferroelectric ceramic nanoparticles, and have a particle size of 3-10 nm; (4) Composite solution infiltration and confined polymerization: the solution obtained in step (3) is filled into the molecular sieve pores, and in situ polymerization is performed at 20-250° C. to form a composite dielectric layer comprising polymer-nanoparticles@molecular sieve; (5) Top electrode deposition: Deposit a 50-200nm metal top electrode on the surface of the dielectric layer.

[0006] Preferably, the gradient chemical modification in (2) includes: modifying the pore walls near the bottom electrode area with aminosilane, and modifying the outer pore walls with a silane coupling agent containing double bonds or epoxy groups.

[0007] Preferably, the in-situ polymerization in (4) includes light curing, heat curing or catalytic curing, the curing temperature is ≤250°C, and the polymerization time is ≤4 hours.

[0008] A high-precision capacitor comprising: a bottom electrode, a composite dielectric layer, and a top electrode; The composite dielectric layer is composed of a gradient functionalized molecular sieve framework and an in-situ polymerized material filling its pores, wherein the in-situ polymerized material comprises: (a) a polymer matrix selected from fluorinated polyimide, perfluoropolyether acrylate or epoxy resin; (b) functionalized nanoparticles, uniformly dispersed in the matrix at 0.5-10 vol%, the nanoparticles having a surface modified with a silane coupling agent and a particle size of 3-10 nm; (c) The molecular sieve framework has a pore size of 2-10 nm, and the pore wall is modified by gradient chemical modification, with the content of the modifier being 0.5-5 mol% of the molar amount of the silicon source.

[0009] Preferably, the functionalized nanoparticles include barium strontium titanate quantum dots, the surface of which is grafted with a silane coupling agent containing double bonds.

[0010] Preferably, the molecular sieve framework is mesoporous silica or a metal organic framework material, and the pore depth direction thereof presents a pore size gradient distribution, and the pore size variation range is ±1-3 nm.

[0011] Preferably, the polymer matrix is ​​connected to the molecular sieve pore wall via a covalent bond, and the interface binding energy is ≥200 kJ / mol.

[0012] Preferably, the interface roughness between the top electrode and the dielectric layer is ≤5 nm, and the electrode material is platinum, copper or aluminum.

[0013] Preferably, the composite dielectric layer has a thickness of 50 nm-10 μm, and a thickness uniformity deviation of ≤±2%.

[0014] In summary, the present invention includes at least one of the following beneficial technical effects: 1. By constructing a molecular sieve structure with a gradient functionalized interface, the present invention achieves the orderly distribution and stable anchoring of nanoparticles in the composite dielectric material, effectively avoiding the dielectric inhomogeneity problem caused by particle agglomeration, significantly improving the dielectric uniformity and structural integrity of the material, and is particularly suitable for the manufacturing needs of high-performance miniaturized capacitors.

[0015] 2. The present invention introduces a gradient modification strategy with differences in internal and external chemical functional zones, which enables the interface polarization behavior to be controlled, reduces the interface instability factors induced by the electric field, fundamentally suppresses dielectric nonlinearity and capacitance drift phenomena, and improves the response stability of the composite material within a wide voltage operating range. It is particularly suitable for application scenarios in precision electrical systems with high requirements for capacitance stability.

[0016] 3. The confined filling and self-limiting growth mechanism adopted by the present invention effectively improves the density and flatness of the dielectric layer, reduces the formation of structural defects, and at the same time has excellent interface continuity, providing a stable and reliable film-forming process foundation for the construction of large-area, controllable-thickness functional dielectric films, and enhancing the integrated processing adaptability of the material system.

[0017] 4. The three-dimensional ordered confined structure constructed by the present invention, combined with the interface gradient design, can form a stress release path under the action of thermal stress, avoiding interface debonding or local cracking, and significantly improving the structural stability of the composite material under multiple working conditions. It is particularly suitable for electronic devices that need to withstand thermal and electrical coupling loads.

[0018] 5. The present invention adopts a gradient assembly method compatible with low-temperature processing. While ensuring the high dielectric properties of the composite material, it ensures its good adaptability to flexible substrates and existing integrated circuit packaging systems. This makes the present invention widely applicable to flexible electronics, wearable devices and highly integrated electronic modules, and has broad potential for process and application expansion. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the method of the present invention. DETAILED DESCRIPTION

[0020] The following is combined with Figure 1 , the present invention is described in further detail.

[0021] The present invention provides the following steps: (1) Substrate treatment and bottom electrode preparation: deposit a metal bottom electrode with a thickness of 50-150 nm on the surface of a clean substrate; (2) Preparation of gradient functionalized molecular sieve skeleton film: An ordered mesoporous molecular sieve film with a pore size of 2-10 nm is formed on the surface of the bottom electrode by a sol-gel method. The pore wall of the molecular sieve film is subjected to gradient chemical modification. The modifier includes a silane coupling agent, and the addition amount thereof is 0.5-5 mol% of the molar amount of the silicon source; (3) Preparation of functionalized nanoparticle-monomer composite solution: dispersing surface-modified functionalized nanoparticles in a low-polarity monomer at a rate of 0.5-10 vol%, wherein the nanoparticles are selected from barium strontium titanate quantum dots, hexagonal boron nitride nanosheets, or high-k non-ferroelectric ceramic nanoparticles, and have a particle size of 3-10 nm; (4) Composite solution infiltration and confined polymerization: the solution obtained in step (3) is filled into the molecular sieve pores, and in situ polymerization is performed at 20-250° C. to form a composite dielectric layer comprising polymer-nanoparticles@molecular sieve; (5) Top electrode deposition: Deposit a 50-200nm metal top electrode on the surface of the dielectric layer.

[0022] Construction of gradient functionalized molecular sieve framework The molecular sieve framework uses ordered mesoporous materials (such as MCM-41, SBA-15, or MOFs) to form a thin film with a pore size of 2-10 nm on the substrate surface through a sol-gel method. The molecular sieve pore walls are modified with gradient chemicals (such as aminosilane, silane coupling agents containing double bonds or epoxy groups) to form a gradient distribution of chemical properties from the bottom electrode to the dielectric layer surface. This gradient design not only enhances the interfacial bonding between the molecular sieve and the electrode, but also regulates the distribution of subsequent monomers and nanoparticles through the chemical guidance effect of the pore walls, laying the foundation for the uniformity and functionalization of the composite dielectric layer.

[0023] Permeation and confined polymerization of functionalized nanoparticle-monomer composite solutions Functional nanoparticles (such as BST quantum dots and h-BN nanosheets) are surface-modified and uniformly dispersed in low-polarity monomers (such as fluorinated polyimide precursors and perfluoropolyether acrylates) to form a composite solution. The solution is filled into the pores of the molecular sieve using vacuum assistance or capillary action, and in situ polymerization is carried out at low temperatures (≤250°C). The nanoconfinement effect of the molecular sieve constrains the conformation and movement of the polymer chains, inhibiting the formation of free volume. Simultaneously, the functional nanoparticles chemically bond with the polymer matrix and the molecular sieve pore walls to form a strong synergistic interface, optimizing the stability of the dielectric properties.

[0024] Low temperature liquid phase process and precise thickness control The sol-gel method is combined with a spin-coating or dip-coating process to achieve precise control of the molecular sieve film thickness (deviation ≤ ±2%) through a self-limiting growth mechanism. The low-temperature polymerization process avoids stress deformation caused by high-temperature sintering or mechanical winding, ensuring the integrity of the dielectric layer structure and interface consistency. The top electrode is deposited at low temperature using magnetron sputtering or ALD technology to further reduce thermal damage to the dielectric layer.

[0025] Synergistic effect of gradient functionalization of molecular sieves Gradient chemical modification of the molecular sieve pore walls works through the following mechanisms: Interface enhancement: The aminosilane modification layer near the bottom electrode improves the adhesion between the molecular sieve and the metal electrode and reduces interface defects.

[0026] Directional guidance: The outer layer of modified groups containing double bonds or epoxy groups pre-reacts with the monomer molecules to promote the orderly growth of the polymer, while anchoring the functional nanoparticles to prevent their agglomeration.

[0027] Electric field optimization: Gradient chemical properties can adjust the distribution of dielectric constant in the thickness direction, achieve electric field homogenization, and reduce the risk of local breakdown.

[0028] Nanoconfined polymerization and interfacial bonding mechanism The confinement effect of the nanopores of molecular sieves on polymers is reflected in: Chain conformation control: The extension of polymer chains in confined spaces is reduced, and the free volume is reduced, thereby reducing dielectric loss.

[0029] Defect suppression: The pore size limits the movement of macromolecular segments and inhibits the formation of microcracks or voids.

[0030] Strong interfacial bonding: The silane coupling agent on the surface of the functional nanoparticles forms a covalent bond or hydrogen bond network with the polymer matrix and the molecular sieve pore wall, enhancing the stress transfer efficiency and optimizing the electric field distribution around the nanoparticles.

[0031] Synergistic advantages of low temperature process and self-limiting growth The self-limiting growth of the sol-gel method achieves intrinsic control over the thickness of the zeolite film through precise regulation of precursor concentration, solvent evaporation rate, and surface energy balance. Low-temperature polymerization (such as photocuring or catalytic curing) avoids material denaturation caused by high temperatures while preserving the zeolite pore structure and the active surface of the functional nanoparticles, ensuring the microstructural integrity of the composite dielectric layer.

[0032] Example 1 Step 1: Substrate treatment and bottom electrode preparation A 4-inch P-type silicon wafer (resistivity 5Ω·cm) was selected and ultrasonically cleaned with acetone, isopropanol, and deionized water for 15 minutes each, and then subjected to argon plasma treatment (power 75W, pressure 20Pa, time 3 minutes).

[0033] Magnetron sputtering deposition of platinum bottom electrode: power 150W, argon pressure 0.5Pa, deposition rate A continuous platinum layer with a thickness of 100 nm was obtained (surface roughness Ra = 1.8 nm, measured by AFM).

[0034] Step 2: Molecular sieve film preparation Prepare SBA-15 precursor sol: TEOS:EtOH:H2O:HCl=1:30:6:0.005 (molar ratio), add 1.5 mol% APTES and 3 mol% MPTMS.

[0035] Spin coating process: 2500 rpm × 40 seconds, repeated 3 times, with intermediate drying (80°C × 5 minutes).

[0036] Gradient calcination: 350°C × 3 hours (heating rate 1.5°C / min) to obtain a molecular sieve film with a pore size of 6.2±0.3 nm and a thickness of 1.2 μm.

[0037] Step 3: Preparation of BST quantum dot composite solution Ba0.6Sr0.4TiO3 quantum dots (particle size 6±1 nm) were hydrothermally synthesized and modified with APTES (addition amount 1.5 wt%).

[0038] Dispersed in PAA solution (solid content 15%): quantum dots added in an amount of 5 vol%, and ultrasonicated in an ice bath (300 W x 30 min).

[0039] Step 4: Domain-limited aggregation After vacuum infiltration (vacuum degree 5 Pa), gradient imidization was carried out: 80°C×1h→150°C×1h→220°C×2h.

[0040] FTIR showed that the imidization degree was 93% (1780 cm -1 peak integrated intensity).

[0041] Step 5: Top electrode and packaging Magnetron sputtering aluminum top electrode: thickness 120nm, deposition rate

[0042] ParyleneC encapsulation: deposition thickness 8μm.

[0043] Example 2 Step 1: Substrate treatment and bottom electrode preparation A flexible PET film (thickness 100 μm) was selected and treated with oxygen plasma (power 30 W, time 1 minute).

[0044] Sputtering copper electrode: power 180W, argon pressure 0.3Pa, deposition rate A copper layer with a thickness of 50 nm (sheet resistance of 0.8 Ω / sq) was obtained.

[0045] Step 2: Molecular sieve film preparation Prepare MCM-41 precursor sol: CTAB / TEOS=0.1 (molar ratio), add 0.5 mol% PTES.

[0046] Dipping and pulling: rate 1mm / min, single film formation.

[0047] Low-temperature solvent extraction: ethanol / HCl (1 M) solution at 60°C for 6 hours to obtain a film with a pore size of 2.8±0.2 nm and a thickness of 300 nm.

[0048] Step 3: Preparation of h-BN nanosheet composite solution Liquid phase exfoliation of h-BN nanosheets (2-3 layers thick) modified with diazonium salt.

[0049] Dispersed in PFPE-DA monomer: adding amount 0.5 vol%, ultrasonic treatment (200W×15 minutes).

[0050] Step 4: Light-curing polymerization UV curing: wavelength 365nm, intensity 10mW / cm 2 ×1 minute.

[0051] Conversion rate detection: Real-time infrared shows that the double bond conversion rate is 88%.

[0052] Step 5: Top electrode and packaging Spray-coated PEDOT:PSS electrode: thickness 150 nm, annealed at 80°C for 20 minutes.

[0053] Epoxy resin encapsulation: thickness 1μm.

[0054] Example 3 Step 1: Substrate treatment and bottom electrode preparation Tantalum foil substrate (thickness 200 μm) was selected, and gold electrode was sputtered after acid activation: power 250W, argon pressure 0.8Pa, deposition rate A gold layer with a thickness of 200 nm was obtained.

[0055] Step 2: Molecular sieve film preparation Synthesis of ZIF-8 type MOFs membrane: 2-methylimidazole / zinc nitrate = 4:1 (molar ratio), adding 5 mol% VTES.

[0056] Liquid phase epitaxial growth: 20 cycles to obtain a thin film with a pore size of 3.4 nm and a thickness of 10 μm.

[0057] Step 3: Preparation of HfO2 nanoparticle composite solution HfO2 nanoparticles (particle size 9±1 nm) were prepared by sol-gel method and modified with MPTMS (addition amount 5 wt%).

[0058] Dispersed in epoxy resin: Addition amount 10 vol%, triple-roll milling process.

[0059] Step 4: Catalytic Curing Polymerization Anhydride curing system: MHHPA / epoxy equivalent ratio 1:1, added 2wt% DMP-30 accelerator.

[0060] Step curing: 80℃×2h→150℃×4h.

[0061] Step 5: Top electrode and packaging ALD deposition of ruthenium electrode: thickness 200nm, deposition temperature 150℃.

[0062] Ceramic package: tape-cast alumina layer, thickness 10μm.

[0063] Comparative Example 1: Compared with Example 1, the difference is that the molecular sieve film is not subjected to gradient chemical modification, but is modified with only a single APTES (addition amount 1.5 mol%), and the remaining steps and parameters are the same.

[0064] Comparative Example 2: Compared with Example 1, the difference is that the functionalized nanoparticles (BST quantum dots) are omitted, and only the pure PAA solution is filled into the molecular sieve pores. The remaining steps and parameters are the same.

[0065] Comparative Example 3: Compared with Example 1, the difference is that the pore size of the molecular sieve is enlarged to 20 nm, and the other steps and parameters are the same.

[0066] Comparative Example 4: Compared with Example 1, the difference is that the traditional high-temperature sintering process (calcination at 800° C. for 2 hours) is used instead of the low-temperature confined polymerization, and the other steps and parameters are the same.

[0067] Comparative Example 5: Compared with Example 1, the difference is that the amount of nanoparticles added is increased to 15 vol%, and the other steps and parameters are the same.

[0068] Comparative Example 6: Compared with Example 1, the difference is that the vacuum-assisted infiltration step is eliminated, and the composite solution is filled only by natural infiltration (the infiltration time is extended to 24 hours), and the other steps and parameters are the same.

[0069] Test Example 1: Capacitance Accuracy and Thickness Uniformity Test Experiment Description Experimental procedures Sample preparation According to the process of Example 1, Comparative Example 1 (no gradient modification), Comparative Example 3 (pore diameter 20nm), and Comparative Example 6 (natural infiltration), 10 capacitor samples were prepared, each sample containing 100 independent capacitor units (unit area 1mm 2 ).

[0070] Dielectric layer thickness measurement The thickness of each sample was measured at the center of 100 capacitor units using a non-contact optical film thickness meter (model Filmetrics F20, accuracy ±0.5 nm).

[0071] Randomly select 20 units from each sample and calculate the thickness standard deviation (σ) and range (Max-Min).

[0072] Capacitance test The capacitance of all capacitor units was measured using an LCR meter (Keysight E4980A, test frequency 1 kHz, voltage 1 Vrms).

[0073] Statistical analysis was performed on the 100 unit capacitance values ​​of each sample, and the standard deviation (σ) and range were calculated.

[0074] Statistics The average standard deviation and range of the 10 samples were summarized as the final comparison data.

[0075] Table 1 Comparison of dielectric layer thickness and capacitance uniformity: In Example 1, the gradient chemical modification gradient design of the pore wall of the gradient functionalized molecular sieve forms a directional chemical potential gradient from the electrode to the surface in the dielectric layer through the synergistic effect of aminosilane and double-bond silane. This gradient distribution effectively regulates the wetting dynamics of the composite solution, allowing the nanoparticle-monomer solution to be uniformly filled under the joint drive of capillary action and chemical adsorption. Due to the lack of gradient modification in Comparative Example 1, the difference in the migration rate of the solution within the pore channel leads to local enrichment, and the thickness uniformity is significantly reduced (σ=51.6nmvs24.1nm), which verifies the necessity of gradient chemical guidance for filling homogenization.

[0076] The precise control of the molecular sieve pore size (6.2 ± 0.3 nm) and the synergistic effect of nanoparticle surface modification further optimize the spatial confinement effect of the composite material. When the pore size is expanded to 20 nm in Comparative Example 3, the Brownian motion of the nanoparticles in the pores intensifies, and sedimentation and agglomeration occur in some areas, resulting in an increase in the discreteness of the capacitance value (extreme difference 14.2%). In Example 1, the confined space inhibits particle migration, and the pre-reaction anchoring effect of the surface modification group and the monomer is combined to make the nanoparticles monodisperse, and the capacitance consistency is significantly improved.

[0077] The self-limiting growth process achieves intrinsic control of the thickness of the molecular sieve film through the dynamic balance between the precursor concentration and the solvent evaporation rate. When natural infiltration was used in Comparative Example 6, the mass transfer of the solution in the pores was limited by viscous resistance, and the deep pores could not be completely filled, resulting in thickness fluctuations (extreme difference 487nm). In Example 1, vacuum-assisted infiltration was driven by pressure difference to quickly replace residual gas, combined with the shear force regulation of the spin coating process to ensure the pore filling integrity and surface flatness, and ultimately achieve precise control of the dielectric layer thickness deviation ≤±2%.

[0078] Test Example 2: Temperature / Voltage Coefficient Stability Test Experiment Description Experimental procedures Sample grouping 20 capacitors (nominal capacitance of 500 pF±5%) were selected from Example 1, Comparative Example 1 (no gradient modification), Comparative Example 2 (no nanoparticles), and Comparative Example 5 (15 vol% nanoparticles).

[0079] Temperature coefficient (TCC) test The sample was placed in a high and low temperature test chamber (ESPECT-240) and cycled according to the following program: 25°C → -55°C (hold for 30 minutes) → 25°C (recover for 1 hour) → 125°C (hold for 30 minutes) → 25°C (recover for 1 hour), for a total of 5 cycles.

[0080] Use an LCR meter (1kHz, 1Vrms) to record capacitance values ​​at -55°C, 25°C, and 125°C, and calculate the average TCC: Voltage coefficient (VCC) test At 25°C, a high voltage source (Keysight B2962A) was used to apply a 0-200 V DC bias with a step size of 20 V. The capacitance value was recorded after each voltage point stabilized for 30 seconds.

[0081] Calculate VCC: Abnormal data processing eliminates invalid data caused by breakdown or open circuit (such as the breakdown of 3 samples at 150V in Comparative Example 5).

[0082] Table 2 Temperature / voltage coefficient stability comparison: The temperature and voltage coefficient stability results shown in Test Example 2 fully verify the key role of gradient interface regulation and nano-confinement synergy in the stability of dielectric response. The multi-level chemical interface constructed in the embodiment not only provides a stable mechanical bond at room temperature through the synergistic effect of amino groups and double bond structures, but also shows good elastic matching in the stress release during heating or cooling, thereby avoiding the structural distortion of the dielectric layer during thermal cycling. This interface buffering mechanism significantly suppresses the nonlinearity of the polarization response caused by temperature, and the TCC is controlled within ±15ppm / ℃. In the comparative example, due to the lack of interface matching, the thermal strain concentration causes drastic fluctuations in capacitance.

[0083] In addition, the spatial constraint effect of the confined structure on the polarization path is also reflected in the VCC test. In the embodiment, the dispersed state of the nanoparticles forms a multiphase synergistic network with the organic matrix, which effectively curbs the local polarization agglomeration induced by the electric field enhancement. This "discontinuous polarization interface" suppresses the dielectric nonlinearity under high voltage, so that VCC is always maintained within ±20ppm / V. In the comparative example, nanoparticle agglomeration or interface debonding will form a local polarization enhancement area, causing VCC to deviate from the linear response, showing phenomena such as enhanced voltage sensitivity and increased discreteness.

[0084] Notably, the gradient construction method employed in the embodiment also serves to regulate stress gradients. Specifically, in a dual-stress environment of temperature and voltage, the gradient interface automatically shares stress by differentially responding to the materials within and outside the layer, avoiding the formation of concentrated stress points. This "stress deconcentration" mechanism fundamentally improves the stability of the dielectric system under complex operating conditions and provides a structural foundation for achieving highly reliable capacitors.

[0085] Test Example 3: High-Frequency Dielectric Loss and Breakdown Strength Test Experimental Description Experimental procedures Sample preparation Fifteen capacitor samples (with a nominal capacitance of 500 pF±5%) were prepared according to the processes of Example 1, Comparative Example 2 (without nanoparticles), and Comparative Example 4 (high-temperature sintering).

[0086] High frequency dielectric loss test An impedance analyzer (Keysight E4991A) was used to scan the frequency range of 1 MHz to 1 GHz, and the dielectric loss tangent (tan δ) at four frequency points, 1 MHz, 10 MHz, 100 MHz, and 1 GHz, was recorded.

[0087] Each sample was tested 3 times, and the median value was taken as the final result.

[0088] Breakdown field strength test The sample was placed in insulating oil and the voltage was increased at a rate of 100 V / s using a high voltage generator (Hipotronics DC-100 kV) until breakdown occurred.

[0089] Record the breakdown voltage and calculate the breakdown field strength (breakdown voltage / dielectric layer thickness).

[0090] Abnormal data caused by edge discharge (such as the breakdown of two samples at the electrode edge in Comparative Example 4) were eliminated.

[0091] Data Filtering For each group of valid data, 12 samples were retained (excluding 3 outliers) and the mean and standard deviation were calculated.

[0092] Table 3 Comparison of high frequency dielectric loss and breakdown strength: The results of Test Example 3 further confirm the synergistic mechanism of nano-confinement effect and gradient interface construction in improving high-frequency stability and dielectric strength. In the embodiment, the introduced molecular sieve pore structure not only realizes the spatially ordered distribution of nanoparticles, but also forms an effective confinement of carriers through interface modification, greatly reducing the dielectric loss at high frequency. The particles avoid interface polarization accumulation and space charge accumulation in the confined state, so that tanδ remains within 0.005 at a frequency of 1 GHz, which is much better than the high loss behavior caused by particle agglomeration or interface discontinuity in the comparative sample.

[0093] The improvement in breakdown strength comes from the multiple blocking mechanisms in the structure: the three-dimensional ordered pore network constructed by the molecular sieve makes the electric field non-uniformly distributed in the material, effectively delaying the formation of the electric breakdown channel. At the same time, the presence of the gradient interface provides a transition buffer area for the electric field distribution on a microscopic scale, avoiding the early breakdown induced by field strength concentration. Compared with the local field strength out of control caused by disordered accumulation or sintering cracks in the comparative samples, the example samples remain stable above 500V / μm, reflecting the direct effect of structural regulation on the electric strength dimension.

[0094] At the same time, the structural response under high-frequency conditions also shows that the interface construction strategy is not only effective under static conditions, but also shows its regulatory advantages when the electromagnetic response frequency increases. The gradient interface region can maintain a low dielectric relaxation under high-frequency excitation, effectively shielding the loss peak caused by the interface mismatch between the electrode and the dielectric. This composite structure with a layer-by-layer transition from the inside to the outside provides an engineering foundation for constructing a low-loss, high-voltage, and spectrally stable dielectric material system, and further highlights the application potential of interface regulation and nano-confinement in high-frequency devices.

[0095] Test Example 4: Process Compatibility and Reliability Verification Experiment Description Experimental procedures Flexible substrate deformation test Ten capacitor samples of Example 1 (low-temperature process) and Comparative Example 4 (high-temperature sintering process) were prepared on a flexible PET substrate (thickness 125 μm).

[0096] The warpage of the substrate was measured using a laser scanning profilometer (Zygo New View 9000): 5 areas (center + four corners) were selected for each sample, and the average warpage angle (unit: degree) was calculated.

[0097] Nanoparticle dispersion analysis The dielectric layer sample of Comparative Example 5 (15 vol % nanoparticles) was selected, and a cross-sectional sample was prepared by focused ion beam (FIB) cutting.

[0098] Field emission scanning electron microscopy (FE-SEM, Hitachi SU5000) combined with EDS surface scanning was used to count the proportion of nanoparticle agglomeration areas (defined as aggregation of ≥3 particles with a spacing of <50 nm) to the total area.

[0099] Data collection and processing The warpage data removes outliers caused by operational damage (such as scratched areas).

[0100] The EDS surface scan analysis of Comparative Example 5 selected three different fields of view (each field of view 50×50 μm 2 ), and calculate the average value of the proportion of agglomerated areas.

[0101] Table 4 Comparison of process compatibility and material dispersibility: Test Example 4 shows that the proposed low-temperature process and structural gradient design effectively improve the dispersibility of nanofillers and the structural integrity of the medium while ensuring process compatibility. The low-temperature polymerization strategy used in the embodiment is combined with functionalized molecular sieves to achieve stress-free film formation on a flexible substrate. Compared with the high-temperature sintering process, its thermal impact on the substrate is significantly reduced, and the warpage is controlled within 0.1°. This is attributed to the gradual cross-linking and solidification of the prepolymer components in the molecular sieve pores under the interfacial chemical action of the gradient distribution, completing dense filling without causing a sudden change in the overall volume, avoiding curling or cracking caused by thermal stress accumulation.

[0102] The dispersibility of the particles also reflects the advantages of gradient regulation. Due to the chemical modification of the pore wall to form a functional zone transition structure of "hydrophilic inside and hydrophobic outside", the functional nanoparticles can be directionally adsorbed during the precursor infiltration process to form a stable monodisperse state. In the comparative example, the lack of gradient modification resulted in the free migration of particles in the pores or matrix, and then formed a chain or agglomerated structure, which seriously affected the composite uniformity. In the embodiment, the dual mechanism of confined space and interface anchoring was used to effectively block the secondary aggregation behavior of the particles, greatly reducing the proportion of the agglomerated area and suppressing the formation of dielectric layer defects from the structural source.

[0103] Furthermore, this gradient control strategy regulates the interfacial tension and migration pathways during solution infiltration, enabling directional solution drive and coordinated component migration at the nanoscale, further improving the material's structural adaptability in complex device configurations. No obvious bubbles or surface cracks were observed during the experiment, demonstrating that the constructed interface structure is not only thermodynamically stable but also has good process tolerance in large-scale fabrication, providing reliable support for low-temperature processable, high-performance dielectric materials in flexible electronic devices.

[0104] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision capacitor forming process, characterized in that: The following steps are involved: (1) Substrate treatment and bottom electrode preparation: deposit a metal bottom electrode with a thickness of 50-150 nm on the surface of a clean substrate; (2) Preparation of gradient functionalized molecular sieve skeleton film: An ordered mesoporous molecular sieve film with a pore size of 2-10 nm is formed on the surface of the bottom electrode by a sol-gel method. The pore wall of the molecular sieve film is subjected to gradient chemical modification. The modifier includes a silane coupling agent, and the addition amount thereof is 0.5-5 mol% of the molar amount of the silicon source. (3) Preparation of functionalized nanoparticle-monomer composite solution: dispersing surface-modified functionalized nanoparticles in a low-polarity monomer at 0.5-10 vol%, wherein the nanoparticles are selected from barium strontium titanate quantum dots, hexagonal boron nitride nanosheets, or high-k non-ferroelectric ceramic nanoparticles, and have a particle size of 3-10 nm; (4) Composite solution infiltration and confined polymerization: The solution obtained in step (3) is filled into the molecular sieve pores and in situ polymerization is performed at 20-250°C to form a composite dielectric layer comprising polymer-nanoparticles@molecular sieve; (5) Top electrode deposition: Deposit a 50-200nm metal top electrode on the surface of the dielectric layer.

2. A high-precision capacitor forming process according to claim 1, characterized in that: The gradient chemical modification described in (2) includes: modifying the pore walls near the bottom electrode area with aminosilane, and modifying the outer pore walls with a silane coupling agent containing double bonds or epoxy groups.

3. The high-precision capacitor forming process according to claim 1, characterized in that: The in-situ polymerization described in (4) includes light curing, heat curing or catalytic curing, with a curing temperature of ≤250°C and a polymerization time of ≤4 hours.

4. A high-precision capacitor, prepared by the high-precision capacitor forming process according to any one of claims 1 to 3, characterized in that: include: a bottom electrode, a composite dielectric layer, and a top electrode; The composite dielectric layer is composed of a gradient functionalized molecular sieve framework and an in-situ polymerized material filling its pores, wherein the in-situ polymerized material comprises: (a) a polymer matrix selected from fluorinated polyimide, perfluoropolyether acrylate or epoxy resin; (b) functionalized nanoparticles, uniformly dispersed in the matrix at 0.5-10 vol%, the nanoparticles having a surface modified with a silane coupling agent and a particle size of 3-10 nm; (c) The pore size of the molecular sieve framework is 2-10 nm, and the pore wall is modified by gradient chemical modification, and the content of the modifier is 0.5-5 mol% of the molar amount of the silicon source.

5. A high-precision capacitor according to claim 4, characterized in that: The functionalized nanoparticles include barium strontium titanate quantum dots, the surfaces of which are grafted with a silane coupling agent containing double bonds.

6. The high-precision capacitor according to claim 4, characterized in that: The molecular sieve skeleton is mesoporous silica or metal organic framework material, and the pore depth direction thereof presents a pore size gradient distribution, and the pore size variation range is ±1-3nm.

7. The high-precision capacitor according to claim 4, characterized in that: The polymer matrix is ​​connected to the molecular sieve pore wall via a covalent bond, and the interface binding energy is ≥200 kJ / mol.

8. The high-precision capacitor according to claim 4, characterized in that: The interface roughness between the top electrode and the dielectric layer is ≤5nm, and the electrode material is platinum, copper or aluminum.

9. The high-precision capacitor according to claim 4, characterized in that: The thickness of the composite dielectric layer is 50nm-10μm, and the thickness uniformity deviation is ≤±2%.

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