Flexible base film and chip on film

Abstract

The invention provides a flexible base film and a chip on film. The flexible base film comprises a substrate, a plurality of signal wires and a first heat dissipation pattern. The substrate is provided with a chip bonding area bonded with the driving chip, the plurality of signal wires are arranged in the substrate, and the plurality of signal wires are used for being electrically connected with the driving chip. The first heat dissipation pattern is located in the substrate and used for dissipating heat for the driving chip. Wherein the ratio of the length of the first heat dissipation pattern to the width of the first heat dissipation pattern is greater than a preset length-width ratio. By adopting the flexible base film and the chip on film, the heat dissipation problem of the driving chip in the prior art can be solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a flexible base film and a chip-on-film using the flexible base film. Background Art

[0002] Chip-on-film (COF) is a die-on-film packaging technology that secures integrated circuits (ICs) to flexible circuit boards. In the display technology field, COF can be used to connect circuit boards and display panels.

[0003] Large-size, high-resolution, and high-refresh-rate displays offer a superior visual experience, leading to increasing demand for these devices. However, these devices require high-power driver ICs. This increased driver IC power significantly increases heat generation, and in severe cases, can even cause driver IC failure, preventing the display from displaying properly. Therefore, a technical solution to the heat dissipation problem associated with chip-on-film (COF) is needed. Summary of the Invention

[0004] The embodiments of the present application provide a flexible base film and a chip-on-film using the flexible base film, aiming to solve the heat dissipation problem of the chip-on-film in the prior art.

[0005] A first aspect of the present application provides a flexible base film, comprising a substrate, a plurality of signal wirings, and at least one first heat dissipation pattern. The substrate has a chip bonding area for bonding with a driver chip. The plurality of signal wirings are disposed within the substrate, the plurality of signal wirings being electrically connected to the driver chip. At least one first heat dissipation pattern is disposed within the substrate, and the at least one first heat dissipation pattern is disposed on one side of the chip bonding area. The ratio of the length of the first heat dissipation pattern to the width of the first heat dissipation pattern is greater than or equal to a predetermined aspect ratio.

[0006] As an optional implementation manner, a ratio of a length of the first heat dissipation pattern along the second direction to a width of the first heat dissipation pattern along the first direction is greater than or equal to 1.5, wherein the second direction is perpendicular to the first direction.

[0007] As an optional implementation, the flexible base film further includes a second heat dissipation pattern and a third heat dissipation pattern arranged in the substrate; along the first direction, the second heat dissipation pattern and the third heat dissipation pattern are respectively located on opposite sides of the chip bonding area.

[0008] As an optional implementation, the ratio of the length of the second heat dissipation pattern to the width of the second heat dissipation pattern is between 0.9 and 2.9; and / or the ratio of the length of the third heat dissipation pattern to the width of the third heat dissipation pattern is between 0.9 and 2.9.

[0009] As an optional implementation, the flexible base film includes a first long side and a second long side arranged opposite to each other and a first short side and a second short side arranged opposite to each other; along the first direction, the first long side is parallel to the second long side; along the second direction, the first short side is parallel to the second short side; the distance between the uppermost side of the chip bonding area in the second direction and the first long side of the flexible base film is a first distance, and the ratio of the length of the first heat dissipation pattern in the second direction to the first distance is between 0.5 and 1.

[0010] As an optional implementation manner, the ratio of the length of the first heat dissipation pattern to the width of the flexible base film is between 0.2 and 0.8.

[0011] As an optional implementation, the distance between the leftmost side of the chip bonding area in the first direction and the first short side of the flexible base film is a second distance, and the ratio of the width of the second heat dissipation pattern to the second distance is between 0.2 and 0.8.

[0012] As an optional implementation, the ratio of the length of the first heat dissipation pattern to the width of the chip bonding area is between 12 and 40.

[0013] As an optional implementation, the ratio of the width of the first heat dissipation pattern to the length of the chip bonding area is between 0.1 and 0.5.

[0014] A second aspect of the present application further provides a chip-on-film, comprising: a driver chip and the flexible base film as described above; wherein the driver chip is disposed on the flexible base film.

[0015] The flexible base film and COF provided in this application utilize a heat dissipation pattern within the flexible base film to dissipate heat generated by the driver chip during operation. Furthermore, by adjusting the aspect ratio of the heat dissipation pattern, this application effectively improves the heat dissipation effect of the heat dissipation pattern on the driver chip, resolving the heat dissipation issues associated with COF in the prior art. This effect is particularly significant for large-size, high-resolution, and high-refresh-rate display devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of an application scenario of a chip-on-film provided in one embodiment of the present application.

[0017] Figure 2 A schematic structural diagram of a chip-on-film provided in one embodiment of the present application.

[0018] Figure 3 A schematic structural diagram of a chip-on-film provided in another embodiment of the present application.

[0019] Figure 4 A schematic structural diagram of a chip-on-film provided in another embodiment of the present application.

[0020] Figure 5 A schematic structural diagram of a chip-on-film provided in another embodiment of the present application.

[0021] Figure 6 for Figure 5 Another schematic diagram of a chip-on-film according to an embodiment.

[0022] Figure 7 To adopt Figure 5 A diagram showing the relationship between the aspect ratio of the first heat dissipation pattern and temperature during chip-on-film fabrication according to an embodiment.

[0023] Figure 8 A schematic structural diagram of a chip-on-film provided in another embodiment of the present application.

[0024] Figure 9 A schematic diagram of another application scenario of the chip-on-film provided in one embodiment of the present application.

[0025] Figure 10 For the Figure 9 Cross-section along line AA.

[0026] Figure 11 Schematic diagram of the temperature of chip-on-film using different embodiments. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0028] It should be noted that when an element is considered to be “connected” to another element, it may be directly connected to the other element or there may be a centrally disposed element. When an element is considered to be “disposed on” another element, it may be directly disposed on the other element or there may be a centrally disposed element.

[0029] When a component is referred to as being “fixed to” or “disposed on” another component, it may be directly on the other component or indirectly on the other component. When a component is referred to as being “connected to” another component, it may be directly or indirectly connected to the other component. When a component is referred to as being “electrically connected to” another component, it may be an electrical connection via conductors, a wireless connection, or any other connection method capable of transmitting electrical signals.

[0030] The directions or positional relationships indicated by terms such as "upper", "lower", "left", and "right" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of description. They do not indicate or imply that the devices or elements referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on this patent. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0032] The flexible base film and chip-on-film provided by the embodiments of the present application will be described and explained in detail below with reference to the drawings.

[0033] See also Figure 1 , Figure 1 A schematic diagram of an application scenario of the chip-on-film 100 provided in one embodiment of the present application. Figure 1 Figure 1 is a top view of the chip-on-film 100 in an application scenario. It is understood that the technical solutions of the embodiments of the present application can be applied to any display technology-related scenario. For example, the chip-on-film 100 can be applied to various display-capable devices, including mobile devices such as mobile phones, wearable devices such as watches, televisions, monitors, laptop computers, or tablet computers. The following description will use the application of the chip-on-film 100 in a display as an example.

[0034] like Figure 1 As shown, in one scenario, the COF 100 is applied to a display 400. The display 400 can be used to display images. It is understood that the display 400 in this embodiment can include the COF 100, the circuit board 200, and the display panel 300.

[0035] It is understood that the COF 100 of the present application can be connected between the display panel 300 and the circuit board 200. The COF 100 may also include a bonding area for bonding with the circuit board 200 and a bonding area for bonding with the display panel 300. In some specific implementations, gold fingers (not shown) at both ends of the COF 100 can be connected to gold fingers on the display panel 300 and gold fingers on the circuit board 200, thereby enabling signal transmission between the driver chip in the COF 100, the display panel 300, and the circuit board 200.

[0036] The COF 100 may include a flexible base film 10 and a driver chip 20 , wherein the driver chip 20 may be attached to the surface of the flexible base film 10 .

[0037] It can be understood that the flexible base film 10 can provide a flexible function.

[0038] See also Figure 2 , is a schematic diagram of a chip-on-film 100 provided in one embodiment of the present application. Figure 2 FIG. 4 is a top view of the chip-on-film 100 .

[0039] In the present application, the flexible base film 10 may include a substrate 11 and a plurality of signal wiring areas (not shown in the drawings).

[0040] The substrate 11 may include an insulating polymer material. The insulating polymer material may be polyimide, poly(ethylene terephthalate) (PET), and / or poly(ethylene naphthalate) (PEN). It is understood that the substrate 11 may be a multilayer structure.

[0041] In one embodiment of the present application, the flexible base film 10 has a chip bonding area 14, and the chip bonding area 14 may be located at the center of the flexible base film 10. It is understood that in other embodiments, the chip bonding area 14 may also be located near the center of the flexible base film 10. For example, the chip bonding area 14 may also be located at a lower position (farther from the display panel 300) or at an upper position (closer to the display panel 300) of the center of the flexible base film 10.

[0042] A driver chip 20 may be disposed on the chip bonding region 14 of the flexible base film 10 to form a COF 100. Typically, the chip bonding region 14 may include a plurality of bonding pads, and the driver chip 20 may include a plurality of bumps. The driver chip 20 is disposed on the flexible base film 10 in a flip chip manner, and is bonded to the bumps via the bonding pads.

[0043] The chip bonding area 14 may include two opposite long sides b3 and b4 and two opposite short sides a3 and a4 .

[0044] Optionally, along the first direction, the long side b3 and the long side b4 may be arranged in parallel, and along the second direction, the short side a3 and the short side a4 may be arranged in parallel.

[0045] The chip bonding area 14 is approximately the same size as the driver chip 20. The long side b3 of the chip bonding area 14 may correspond to one long side of the driver chip 20, and the long side b4 of the chip bonding area 14 may correspond to the other long side of the driver chip 20. The short side a3 of the chip bonding area 14 may correspond to one short side of the driver chip, and the short side a4 of the chip bonding area 14 may correspond to the other short side of the driver chip.

[0046] As a possible example, the flexible base film 10 may include two long sides b1 and b2 arranged opposite to each other and two short sides a1 and a2 arranged opposite to each other. Optionally, along a first direction, the long sides b1 and b2 are arranged parallel to each other. Along a second direction, the short sides a1 and a2 are arranged parallel to each other. The first direction is perpendicular to the second direction, and the first direction may be Figure 2 The second direction can be the X direction shown in Figure 2 Y direction shown in .

[0047] It can be understood that, along the first direction, the chip bonding area 14 is arranged substantially parallel to the long sides b1 and b2. In some implementations of the present application, the flexible base film 10 may further include a first heat dissipation pattern 13, which may be disposed within the flexible base film 10. The first heat dissipation pattern 13 may be used to dissipate heat from the driver chip 20.

[0048] As a possible example, the first heat dissipation pattern 13 may be provided on a side of the chip bonding area 14 close to the long side b1 , that is, in the area between the driving chip and the display panel.

[0049] like Figure 2 As shown, the flexible base film 10 can have multiple signal wiring areas, and the driver chip 20 is electrically connected to the signal wiring in the multiple signal wiring areas. The multiple signal wiring areas include a first signal wiring area 101, a second signal wiring area 102, a third signal wiring area 103, a fourth signal wiring area 104, a fifth signal wiring area 105, a sixth signal wiring area 106, and a seventh signal wiring area 107.

[0050] It is understood that the first signal wiring region 101, the second signal wiring region 102, the third signal wiring region 103, the fourth signal wiring region 104, and the fifth signal wiring region 105 can all extend outward from the chip bonding area 14. Figure 2 Not shown in the figure, each signal wiring area in the flexible base film 10 of the present application can include multiple signal wirings, wherein the signal wirings can all be metal wires to transmit signals, and their materials can be made of any metal or any alloy such as copper, aluminum, molybdenum, chromium, gold, silver, titanium, nickel and neodymium.

[0051] Specifically, the first signal wiring region 101 includes signal wiring between the driver chip 20 and the circuit board 200. The second signal wiring region 102, the third signal wiring region 103, the fourth signal wiring region 104, and the fifth signal wiring region 105 include signal wiring between the driver chip 20 and the display panel 300. The sixth signal wiring region 106 and the seventh signal wiring region 107 include signal wiring between the circuit board 200 and the display panel 300.

[0052] The first signal wiring region 101 is located on the side of the chip bonding area 14 close to the long side b2. The second signal wiring region 102 and the third signal wiring region 103 are located on the side of the chip bonding area 14 close to the long side b1. The first heat dissipation pattern 13 is physically separated from the second signal wiring region 102 and the third signal wiring region 103.

[0053] The sixth signal wiring region 106 is located on the side of the flexible base film 10 close to the short side a1, and the seventh signal wiring region 107 is located on the side of the flexible base film 10 close to the short side a2. The fourth signal wiring region 104 is located between the sixth signal wiring region 106, the second signal wiring region 102, and the first signal wiring region 101. The fifth signal wiring region 105 is located between the seventh signal wiring region 107, the third signal wiring region 103, and the first signal wiring region 101.

[0054] When the display 400 starts displaying or updating an image, the driver chip 20 begins operating, generating heat that increases the chip temperature. When the flexible base film 10 is provided with the first heat dissipation pattern 13, the heat can be transferred from the driver chip 20 to the first heat dissipation pattern 13 and quickly released to the surrounding environment, causing the temperature of the driver chip 20 to drop, thereby dissipating heat from the chip on film 100.

[0055] It is understood that the first heat dissipation pattern 13 can be a pattern made of a metal material. In some optional implementations, the first heat dissipation pattern 13 can be made of any metal or any alloy selected from copper, aluminum, molybdenum, chromium, gold, silver, titanium, nickel, and neodymium. The first heat dissipation pattern 13 can include one or more metal blocks.

[0056] In an embodiment of the present application, a ratio of a length of the first heat dissipation pattern 13 along the second direction to a width of the first heat dissipation pattern 13 along the first direction is greater than or equal to a preset aspect ratio, which is, for example, 1.

[0057] It is understood that the "width of the first heat dissipation pattern 13" mentioned above refers to the distance between the leftmost side and the rightmost side of the first heat dissipation pattern 13 in the first direction. For example, the width of the first heat dissipation pattern 13 can be Figure 2 W0 shown.

[0058] It is understood that the "length of the first heat dissipation pattern 13" mentioned above refers to the distance between the uppermost side and the lowermost side of the first heat dissipation pattern 13 in the second direction. For example, the length of the first heat dissipation pattern 13 can be Figure 2 L0 shown.

[0059] See also Figure 3 , is a schematic diagram of a chip-on-film 100 provided in another embodiment of the present application. Figure 3 FIG. 4 is a top view of the chip-on-film 100 .

[0060] and Figure 2 The difference between the COF 100 shown in the embodiment is that, Figure 3 As shown, the first heat dissipation pattern 13 can be arranged on the side of the chip bonding area 14 close to the long side b1, that is, the area between the driving chip and the display panel, and the first heat dissipation pattern 13 extends from the central position on the upper side of the chip bonding area 14 along the second direction toward the long side b1, that is, toward the display panel 300.

[0061] It is understood that in the embodiment of the present application, the first heat dissipation pattern 13 may be polygonal in shape. The shape of the first heat dissipation pattern 13 may also be adjusted according to the signal wiring result in the flexible base film 10, and the present application does not impose any specific limitation on this.

[0062] In one possible example, Figure 3 As shown, the first heat dissipation pattern 13 can be a pentagonal "conical" pattern. It can be understood that in the embodiment of the present application, the ratio between the length of the first heat dissipation pattern 13 in the second direction and the width of the first heat dissipation pattern 13 along the first direction is greater than the preset aspect ratio.

[0063] In an optional implementation, the ratio of the length to the width of the first heat dissipation pattern 13 is greater than or equal to 1.5. For example, the ratio of the length to the width of the first heat dissipation pattern 13 can be approximately 2, 2.5, 3, 3.5, 4, etc.

[0064] It is understood that the "width of the first heat dissipation pattern 13" mentioned above refers to the distance between the leftmost side and the rightmost side of the first heat dissipation pattern 13 in the first direction. For example, the width of the first heat dissipation pattern 13 can be Figure 3 W1 shown.

[0065] It is understood that the "length of the first heat dissipation pattern 13" mentioned above refers to the distance between the uppermost side and the lowermost side of the first heat dissipation pattern 13 in the second direction. For example, the length of the first heat dissipation pattern 13 can be Figure 3 L1 shown.

[0066] In other words, in the flexible base film 10 provided in the embodiment of the present application, by setting the ratio of the length L1 of the first heat dissipation pattern 13 to the width W1 of the first heat dissipation pattern 13 to be greater than or equal to 1.5, the first heat dissipation pattern 13 effectively dissipates heat for the driver chip 20 .

[0067] In this embodiment, the distance between the uppermost side (i.e., the long side b3) of the chip bonding area 14 in the second direction and the first long side b1 of the flexible base film 10 is a first distance S1, and the ratio between the length L1 of the first heat dissipation pattern 13 and the first distance S1 can be between 0.5 and 1. In some possible embodiments, the ratio L1 / S1 between the length L1 of the first heat dissipation pattern 13 and the first distance S1 can be: 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0068] See also Figure 4 , is a schematic diagram of a chip-on-film 100 provided in another embodiment of the present application. Figure 4 FIG. 4 is a top view of the chip-on-film 100 .

[0069] and Figure 2 The difference of the COF 100 shown in the embodiment is that Figure 4 As shown, in this embodiment, the flexible base film 10 may further include a second heat dissipation pattern 15 and a third heat dissipation pattern 16 .

[0070] Both the second heat dissipation pattern 15 and the third heat dissipation pattern 16 may be disposed in the flexible base film 10 .

[0071] The second heat dissipation pattern 15 may be disposed on a side of the chip bonding area 14 close to the short side a1 , and the third heat dissipation pattern 16 may be disposed on a side of the chip bonding area 14 close to the short side a2 .

[0072] The second heat dissipation pattern 15 and the third heat dissipation pattern 16 are both used to dissipate heat for the driver chip 20. In the present application, the second heat dissipation pattern 15 and the third heat dissipation pattern 16 can be respectively arranged on opposite sides of the chip bonding area 14 to dissipate heat for the driver chip 20. In an optional implementation, the second heat dissipation pattern 15 and the third heat dissipation pattern 16 can also be respectively arranged on opposite sides of the first heat dissipation pattern 13. There is a physical gap between the second heat dissipation pattern 15 and the second signal wiring area 102 and the fourth signal wiring area 104. There is a physical gap between the third heat dissipation pattern 16 and the third signal wiring area 103 and the fifth signal wiring area 105.

[0073] The first heat dissipation pattern 13, the second heat dissipation pattern 15, and the third heat dissipation pattern 16 can all be patterns made of metal. In some optional implementations, the first heat dissipation pattern 13, the second heat dissipation pattern 15, and the third heat dissipation pattern 16 can be made of any metal or any alloy selected from copper, aluminum, molybdenum, chromium, gold, silver, titanium, nickel, and neodymium.

[0074] See also Figure 5 , is a schematic diagram of a chip-on-film 100 provided in another embodiment of the present application. Figure 5 FIG. 4 is a top view of the chip-on-film 100 .

[0075] and Figure 3 The difference of the COF 100 shown in the embodiment is that Figure 5 As shown, in this embodiment, the flexible base film 10 may further include a second heat dissipation pattern 15 and a third heat dissipation pattern 16 .

[0076] The second heat dissipation pattern 15 can be disposed within the flexible base film 10 and is used to dissipate heat from the driver chip 20. The second heat dissipation pattern 15 can be disposed on a side of the chip bonding area 14 that is closer to the short side a1. More specifically, the second heat dissipation pattern 15 can extend from the left side of the chip bonding area 14 along the second direction toward the long side b1, that is, toward the display panel 300.

[0077] A third heat dissipation pattern 16 can be disposed within the flexible base film 10 and is used to dissipate heat from the driver chip 20. The third heat dissipation pattern 16 can be disposed on a side of the chip bonding area 14 that is close to the short side a2. More specifically, the third heat dissipation pattern 16 can extend from a position to the right of the chip bonding area 14 along the second direction toward the long side b1.

[0078] In other words, the second heat dissipation pattern 15 and the third heat dissipation pattern 16 of the present application can be respectively disposed on two opposite sides of the chip bonding area 14 to dissipate heat from the driving chip 20 .

[0079] In this embodiment, Figure 5As shown, the flexible base film 10 may have a plurality of signal wiring areas, for example, a first signal wiring area 101, a second signal wiring area 102, a third signal wiring area 103, a fourth signal wiring area 104, a fifth signal wiring area 105, a sixth signal wiring area 106, and a seventh signal wiring area 107. Figure 5 Not shown in the figure, the first signal wiring area 101, the second signal wiring area 102, the third signal wiring area 103, the fourth signal wiring area 104, the fifth signal wiring area 105, the sixth signal wiring area 106, and the seventh signal wiring area 107 in the flexible base film 10 of the present application may include multiple signal wirings.

[0080] The first signal wiring region 101 is located on the side of the chip bonding area 14 near the long side b2. The second and third signal wiring regions 102 and 103 are located on the side of the chip bonding area 14 near the long side b1. The fourth signal wiring region 104 extends from the left side of the long side b4 of the chip bonding area 14 (the side near the short side a1), first downward toward the long side b2, then leftward toward the short side a1, and then upward toward the long side b1. The fifth signal wiring region 105 extends from the right side of the long side b4 of the chip bonding area 14 (the side near the short side a2), first downward toward the long side b2, then rightward toward the short side a2, and then upward toward the long side b1. The first heat dissipation pattern 13 is located between the second and third signal wiring regions 102 and 103, the second heat dissipation pattern 15 is located between the second and fourth signal wiring regions 102 and 104, and the third heat dissipation pattern 16 is located between the third and fifth signal wiring regions 103 and 105.

[0081] The sixth signal wiring region 106 is located on the side of the flexible base film 10 close to the short side a1, and the seventh signal wiring region 107 is located on the side of the flexible base film 10 close to the short side a2. The fourth signal wiring region 104 is located between the sixth signal wiring region 106, the second signal wiring region 102, and the first signal wiring region 101. The fifth signal wiring region 105 is located between the seventh signal wiring region 107, the third signal wiring region 103, and the first signal wiring region 101.

[0082] It is understood that, in addition to extending toward the long side b1 of the flexible base film 10, the first and third heat dissipation patterns 15 and 16 can also extend toward the short sides a1 and a2 of the flexible base film 10, respectively. This design requires some signal wiring in the fourth and fifth signal wiring areas 104 and 105 to be routed appropriately to connect the driver chip 20 to the display panel 300, but this will aid in heat dissipation from the chip-on-film. Furthermore, the increased resistance of the signal wiring due to this routing does not affect the driving function of the driver chip 20. Therefore, while meeting the electrical specifications of the signal wiring and not affecting display performance, the extension of the second and third heat dissipation patterns 15 and 16 in the first direction can be appropriately utilized to further enhance heat dissipation.

[0083] In an optional implementation, the second heat dissipation pattern 15 and the third heat dissipation pattern 16 may also be respectively arranged on two opposite sides of the first heat dissipation pattern 13 .

[0084] It is understood that in other possible implementations, the present application may only provide one heat dissipation pattern on a single side of the chip bonding area 14. For example, in one implementation, a second heat dissipation pattern 15 is provided on the side of the chip bonding area 14 close to the short side a1, while no heat dissipation pattern is provided on the side of the chip bonding area 14 close to the short side a2. In another implementation, a third heat dissipation pattern 16 is provided on the side of the chip bonding area 14 close to the short side a2, while no heat dissipation pattern is provided on the side of the chip bonding area 14 close to the short side a1. It is understood that in some possible implementations, the sizes of the second heat dissipation pattern 15 and the third heat dissipation pattern 16 may be different, and the geometric shapes of the second heat dissipation pattern 15 and the third heat dissipation pattern 16 may also be different, all depending on actual design requirements.

[0085] In the present application, the second heat dissipation pattern 15 and the third heat dissipation pattern 16 can both be patterns made of metal. For example, the second heat dissipation pattern 15 and the third heat dissipation pattern 16 can be made of any metal or alloy selected from copper, aluminum, molybdenum, chromium, gold, silver, titanium, nickel, and neodymium. In a more specific implementation, the second heat dissipation pattern 15 can also include one or more metal blocks. The third heat dissipation pattern 16 can also include one or more metal blocks.

[0086] It can be understood that in some possible embodiments, each metal block in the first heat dissipation pattern 13 , the second heat dissipation pattern 15 and the third heat dissipation pattern 16 may also be hollowed out, that is, the metal block may have a cavity or gap.

[0087] Please also refer to Figure 6The length of the flexible base film 10 is denoted as Lf, and the width of the flexible base film 10 is denoted as Wf. It is understood that the length Lf of the flexible base film 10 may refer to the distance between the short side a1 and the short side a2 of the flexible base film 10 in the first direction. The width Wf of the flexible base film 10 may refer to the distance between the long side b1 and the long side b2 of the flexible base film 10 in the second direction.

[0088] The length of the first heat dissipation pattern 13 is denoted as L1, and the width of the first heat dissipation pattern 13 is denoted as W1. It is understood that the width W1 of the first heat dissipation pattern 13 may refer to the distance between the leftmost side and the rightmost side of the first heat dissipation pattern 13 in the first direction. The length L1 of the first heat dissipation pattern 13 may refer to the distance between the uppermost side and the lowermost side of the first heat dissipation pattern 13 in the second direction.

[0089] The length of the second heat dissipation pattern 15 is denoted as L2, and the width of the second heat dissipation pattern 15 is denoted as W2. It is understood that the width W2 of the second heat dissipation pattern 15 may refer to the distance between the leftmost side and the rightmost side of the second heat dissipation pattern 15 in the first direction. The length L2 of the second heat dissipation pattern 15 may refer to the distance between the uppermost side and the lowermost side of the second heat dissipation pattern 15 in the second direction.

[0090] The width of the chip bonding area 14 is denoted as Wc, and the length of the chip bonding area 14 is denoted as Lc. It is understood that the width Wc of the chip bonding area 14 may refer to the distance between the uppermost side and the lowermost side of the chip bonding area 14 in the second direction. The length Lc of the chip bonding area 14 may refer to the distance between the leftmost side and the rightmost side of the chip bonding area 14 in the first direction.

[0091] The first distance between the uppermost side (i.e., the long side b3) of the chip bonding area 14 in the second direction and the long side b1 of the flexible base film 10 is recorded as S1. The second distance between the leftmost side (i.e., the short side a3) of the chip bonding area 14 in the first direction and the short side a1 of the flexible base film 10 is recorded as S2. It can be understood that in order to make the present application Figure 6 To be more clear, 6 does not show the signal wiring areas as described above, but it should be understood that these signal wiring areas exist on the flexible base film 10 .

[0092] In one example, the length Lf of the flexible base film 10 can be 40.66 mm, and the width Wf of the flexible base film 10 can be 28.5 mm. The length L1 of the first heat dissipation pattern 13 can be 13.78 mm, and the width W1 of the first heat dissipation pattern 13 can be 3.55 mm. The length L2 of the second heat dissipation pattern 15 can be 12.38 mm, and the width W2 of the second heat dissipation pattern 15 can be 6.9 mm. Optionally, the length of the third heat dissipation pattern 16 can be the same as the length of the second heat dissipation pattern 15, and the width of the third heat dissipation pattern 16 can be the same as the width of the second heat dissipation pattern 15. The width Wc of the chip bonding area 14 can be 0.565 mm, and the length Lc of the chip bonding area 14 can be 12.149 mm. The first distance S1 between the uppermost side of the chip bonding area 14 in the second direction and the long side b1 of the flexible base film 10 can be 16.39 mm, and the second distance S2 between the leftmost side of the chip bonding area 14 in the first direction and the short side a1 of the flexible base film 10 can be 14.84 mm.

[0093] In some embodiments, the ratio L1 / W1 of the length of the first heat dissipation pattern 13 to the width of the first heat dissipation pattern 13 may be between 1.5 and 6.5. It is understood that in some optional embodiments, the ratio L1 / W1 of the length of the first heat dissipation pattern 13 to the width of the first heat dissipation pattern 13 may be: 1.55, 1.94, 2.33, 2.72, 3.11, 3.49, 3.88, 4.27, 4.66, 5.05, 5.43, 5.82, 6.21, etc.

[0094] In this embodiment, the ratio L1 / Wf between the length of the first heat dissipation pattern 13 and the width of the flexible base film 10 may be between 0.2 and 0.8. It is understood that in some specific embodiments, the ratio L1 / Wf between the length of the first heat dissipation pattern 13 and the width of the flexible base film 10 may be 0.24, 0.29, 0.34, 0.39, 0.44, 0.48, 0.53, 0.58, 0.63, 0.68, 0.73, 0.77, etc.

[0095] In this embodiment, the ratio of the length L1 of the first heat dissipation pattern 13 to the first distance S1 between the uppermost side of the chip bonding area 14 in the second direction and the first long side b1 of the flexible base film 10 can be between 0.5 and 1. It can be understood that in some specific embodiments, the ratio L1 / S1 between the length L1 of the first heat dissipation pattern 13 and the first distance S1 can be: 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0096] The ratio L1 / Wc between the length of the first heat dissipation pattern 13 and the width of the chip bonding area 14 may be between 12 and 40. It is understood that in some specific embodiments, the ratio L1 / Wc between the length of the first heat dissipation pattern 13 and the width of the chip bonding area 14 may be 12.19, 14.63, 17.07, 19.51, 21.95, 24.39, 26.83, 29.27, 31.71, 34.15, 36.58, 39.02, etc.

[0097] The ratio W1 / Lc between the width of the first heat dissipation pattern 13 and the length of the chip bonding area 14 may be between 0.1 and 0.5. It is understood that in some possible embodiments, the ratio W1 / Lc between the width of the first heat dissipation pattern 13 and the length of the chip bonding area 14 may be 0.15, 0.18, 0.20, 0.23, 0.26, 0.29, 0.32, 0.35, 0.38, 0.41, 0.44, 0.47, etc.

[0098] The ratio L2 / W2 between the length L2 of the second heat dissipation pattern 15 and the width W2 of the second heat dissipation pattern 15 can be between 0.9 and 2.9. It is understood that in some specific embodiments, the ratio L2 / W2 between the length L2 of the second heat dissipation pattern 15 and the width W2 of the second heat dissipation pattern 15 can be 0.90, 1.08, 1.26, 1.44, 1.61, 1.79, 1.97, 2.15, 2.33, 2.51, 2.69, 2.87, etc. Alternatively, in some embodiments, the ratio between the length of the third heat dissipation pattern 16 and the width of the third heat dissipation pattern 16 can also be between 0.9 and 2.9. It can be understood that in some possible embodiments, the ratio L2 / W2 between the length of the third heat dissipation pattern 16 and the width of the third heat dissipation pattern 16 can also be: 0.90, 1.08, 1.26, 1.44, 1.61, 1.79, 1.97, 2.15, 2.33, 2.51, 2.69, 2.87, etc.

[0099] The ratio L2 / Wf between the length of the second heat dissipation pattern 15 and the width of the flexible base film 10 may be between 0.2 and 0.7. It is understood that in some possible embodiments, the ratio L2 / Wf between the length of the second heat dissipation pattern 15 and the width of the flexible base film 10 may be 0.22, 0.26, 0.30, 0.35, 0.39, 0.43, 0.48, 0.52, 0.56, 0.61, 0.65, 0.70, etc. In some embodiments, the ratio between the length of the third heat dissipation pattern 16 and the width of the flexible base film 10 may also be between 0.2 and 0.7. It can be understood that in some possible embodiments, the ratio L2 / Wf between the length of the third heat dissipation pattern 16 and the width of the flexible base film 10 can also be: 0.22, 0.26, 0.30, 0.35, 0.39, 0.43, 0.48, 0.52, 0.56, 0.61, 0.65, 0.70, etc.

[0100] The ratio (W2 / S2) of the width W2 of the second heat dissipation pattern 15 to the second distance S2 between the leftmost side of the chip bonding area 14 in the first direction (i.e., the short side a3) and the short side a1 of the flexible base film 10 can be between 0.2 and 0.8. It is understood that in some possible embodiments, the ratio (W2 / S2) of the width W2 of the second heat dissipation pattern 15 to the second distance S2 can be 0.23, 0.28, 0.33, 0.37, 0.42, 0.46, 0.51, 0.56, 0.60, 0.65, 0.70, 0.74, etc. In some embodiments, the ratio of the width of the third heat dissipation pattern 16 to the distance between the leftmost side of the chip bonding area 14 in the first direction and the short side a2 of the flexible base film 10 can also be between 0.2 and 0.8. It can be understood that in some specific embodiments, the ratio of the width of the third heat dissipation pattern 16 to the distance between the rightmost side of the chip bonding area 14 in the first direction (i.e., the short side a4) and the short side a2 of the flexible base film 10 can also be: 0.23, 0.28, 0.33, 0.37, 0.42, 0.46, 0.51, 0.56, 0.60, 0.65, 0.70, 0.74, etc.

[0101] It can be understood that the numerical values ​​shown in the above examples can be appropriately designed according to actual conditions.

[0102] like Figure 7 As shown, the Figure 5 FIG. 1 is a diagram showing a relationship between the aspect ratio L1 / W1 of the first heat dissipation pattern 13 and the temperature of the driver chip 20 when the chip on film 100 is used in accordance with an embodiment of the present invention.

[0103] from Figure 7It can be seen that when L1 / W1 is 1, the temperature of the driver chip 20 is 83.9°C. When L1 / W1 is 1.2, the temperature of the driver chip 20 is 83.3°C. When L1 / W1 is 1.5, the temperature of the driver chip 20 is 83.1°C. When L1 / W1 is 1.7, the temperature of the driver chip 20 is 82°C. When L1 / W1 is 2.0, the temperature of the driver chip 20 is 81.8°C. When L1 / W1 is 2.3, the temperature of the driver chip 20 is 82°C. When L1 / W1 is 2.6, the temperature of the driver chip 20 is 80.9°C. When L1 / W1 is 2.9, the temperature of the driver chip 20 is 80.9°C. When L1 / W1 is 3.1, the temperature of the driver chip 20 is 79.3°C. When L1 / W1 is 3.4, the temperature of the driver chip 20 is 78.6°C. When L1 / W1 is 3.7, the temperature of the driver chip 20 is 79.8° C.

[0104] From the above Figure 7 The simulated temperature graph clearly shows that the temperature of the driver chip 20 varies with the aspect ratio L1 / W1 of the first heat dissipation pattern 13. Furthermore, when the ratio of the width L2 to the length L1 of the first heat dissipation pattern 13 is greater than 1.5, the temperature of the driver chip 20 is significantly improved, resolving the technical issues of high heat generation and slow heat dissipation in conventional display devices. This effect is particularly significant for large-size, high-resolution, and high-refresh-rate display devices.

[0105] See also Figure 8 , Figure 8 A schematic diagram of a chip-on-film 100 is provided for another embodiment of the present application. Figure 8 FIG. 4 is a top view of the chip-on-film 100 .

[0106] and Figure 5 The difference between the COF 100 shown in the embodiment is that, Figure 8 As shown, in this embodiment, the chip bonding area 14 can also be provided with multiple heat dissipation patterns on one side close to the long side b1 of the flexible base film 10. It can be understood that Figure 8 Only the first heat dissipation pattern 13 and the fourth heat dissipation pattern 19 are shown as examples for description.

[0107] The first heat dissipation pattern 13 and the fourth heat dissipation pattern 19 both extend from the upper side of the chip bonding region 14 toward the long side b1 along the second direction.

[0108] Optionally, the first heat dissipation pattern 13 and the fourth heat dissipation pattern 19 have substantially the same size and shape. It is understood that in other embodiments, the first heat dissipation pattern 13 and the fourth heat dissipation pattern 19 may also have different sizes and shapes.

[0109] Based on the above Figure 8The flexible base film 10 and the chip-on-film 100 shown in the embodiment, when the display 400 starts to display or update the picture, that is, the driver chip 20 starts to work, the driver chip 20 will generate heat. The heat can be conducted from the driver chip 20 to the first heat dissipation pattern 13, the fourth heat dissipation pattern 19, the second heat dissipation pattern 15 and the third heat dissipation pattern 16, and the heat is released to the surrounding environment, thereby achieving heat dissipation of the chip-on-film 100 and reducing the temperature of the driver chip 20.

[0110] Understandably, for the sake of brevity, Figure 3 、 4 , 6, and 8 do not identify various signal wiring areas, but it should be understood that the flexible base film 10 may include these areas.

[0111] Please also refer to Figure 9 and Figure 10 , is a schematic diagram of a chip-on-film 100 provided in one embodiment of the present application.

[0112] In this embodiment, the driver chip 20 may include a plurality of bumps, which may correspond to a plurality of pins in the driver chip 20 and a plurality of signal wirings in the flexible base film 10 .

[0113] In one example, Figure 10 As shown, the driver chip 20 may include bumps 23 and 24, and the driver chip 20 may also include pins 21 and 22, but the present application is not limited thereto. The bumps 23 of the driver chip 20 correspond to the pins 21, and the bumps 24 of the driver chip 20 correspond to the pins 22.

[0114] It is understood that the driver chip 20 can be bonded to one signal wiring with the bump 23 and to another signal wiring with the bump 24 through a thermal compression process. Based on this design, the multiple pins of the driver chip 20 are electrically connected to the multiple signal wirings in the flexible base film 10 through the corresponding bumps, thereby achieving signal transmission between the driver chip in the chip-on-film 100, the display panel 300, and the circuit board 200.

[0115] Please also refer to Figure 11 , which shows the simulated temperature distribution in the vicinity of the chip bonding region in the chip on film 100 . Figure 11 (A) in the formula is Figure 2 Temperature simulation diagram of the COF of the embodiment, wherein L1 / W1 of the first heat dissipation pattern 13 is 1. Figure 11 (B) in the formula is Figure 3 Temperature simulation diagram of the COF of the embodiment, wherein L1 / W1 of the first heat dissipation pattern 13 is 3.88. Figure 11 (C) in the formula is Figure 4The temperature simulation diagram of the COF of the embodiment shows that L1 / W1 of the first heat dissipation pattern 13 is 1, and L2 / W2 of the second heat dissipation pattern 15 and the third heat dissipation pattern 16 is 2.49. Figure 11 (D) in the formula is Figure 5 The temperature simulation diagram of the chip on film of the embodiment shows that L1 / W1 of the first heat dissipation pattern 13 is 3.88, and L2 / W2 of the second heat dissipation pattern 15 and the third heat dissipation pattern 16 is 1.94.

[0116] from Figure 11 It can be seen that Figure 3 The chip-on-film of the embodiment is compared with Figure 2 For the chip-on-film of the embodiment, the temperature of the chip-on-film is improved. Figure 4 The chip-on-film of the embodiment is compared with Figure 2 For the chip-on-film of the embodiment, the temperature of the chip-on-film is further improved. Figure 5 The chip-on-film of the embodiment is compared with Figure 4 The chip-on-film of the embodiment further improves the temperature of the chip-on-film. Specific temperature values ​​can be found in Table 1 below.

[0117] From Table 1 above, we can see that Figure 5 The chip-on-film of the embodiment has the most obvious effect of improving the temperature of the chip-on-film.

[0118] The flexible base film and chip-on-film (COF) using the same are described herein. A heat dissipation pattern is provided within the flexible base film to dissipate heat generated by the driver chip during operation to the heat dissipation pattern, thereby dissipating heat from the COF. Furthermore, by adjusting the aspect ratio of the heat dissipation pattern, the heat dissipation effect of the heat dissipation pattern on the driver chip is effectively enhanced, thereby reducing the operating temperature of the driver chip. This solves the technical problem of excessively high temperatures in display devices caused by high heat generation and slow heat dissipation from the driver chip in prior art displays.

[0119] Those skilled in the art should recognize that the above embodiments are merely intended to illustrate the present application and are not intended to limit the present application. Any appropriate changes and modifications to the above embodiments are within the scope of protection claimed in the present application, as long as they are within the spirit of the present application.

Claims

1. A flexible base film, characterized in that: The flexible base film includes a substrate, a plurality of signal wirings and at least one first heat dissipation pattern; The substrate has a chip bonding area, and the chip bonding area is used to bond with the driving chip; The plurality of signal wirings are arranged in the substrate, and the plurality of signal wirings are used to be electrically connected to the driver chip; The at least one first heat dissipation pattern is located in the substrate, and the at least one first heat dissipation pattern is arranged on one side of the chip bonding area; Wherein, a ratio between the length of the first heat dissipation pattern and the width of the first heat dissipation pattern is greater than or equal to a preset aspect ratio.

2. The flexible base film according to claim 1, wherein A ratio of a length of the first heat dissipation pattern along a second direction to a width of the first heat dissipation pattern along the first direction is greater than or equal to 1.5, wherein the second direction is perpendicular to the first direction.

3. The flexible base film according to claim 1 or 2, characterized in that: The flexible base film further includes a second heat dissipation pattern and a third heat dissipation pattern disposed within the substrate; Along the first direction, the second heat dissipation pattern and the third heat dissipation pattern are respectively located on two opposite sides of the chip bonding area.

4. The flexible base film according to claim 3, wherein a ratio between the length of the second heat dissipation pattern and the width of the second heat dissipation pattern is between 0.9 and 2.9; and / or A ratio of a length of the third heat dissipation pattern to a width of the third heat dissipation pattern is between 0.9 and 2.

9.

5. The flexible base film according to claim 3, characterized in that The flexible base film comprises a first long side and a second long side arranged opposite to each other and a first short side and a second short side arranged opposite to each other; Along the first direction, the first long side is parallel to the second long side; along the second direction, the first short side is parallel to the second short side; A distance between the uppermost side of the chip bonding area in the second direction and the first long side of the flexible base film is a first distance, and a ratio of a length of the first heat dissipation pattern in the second direction to the first distance is between 0.5 and 1.

6. The flexible base film according to claim 1, characterized in that A ratio between a length of the first heat dissipation pattern and a width of the flexible base film is between 0.2 and 0.

8.

7. The flexible base film according to claim 5, characterized in that A distance between the leftmost side of the chip bonding area in the first direction and the first short side of the flexible base film is a second distance, and a ratio of a width of the second heat dissipation pattern to the second distance is between 0.2 and 0.

8.

8. The flexible base film according to claim 1, wherein A ratio between a length of the first heat dissipation pattern and a width of the chip bonding area is between 12 and 40.

9. The flexible base film according to claim 1, wherein A ratio between a width of the first heat dissipation pattern and a length of the chip bonding area is between 0.1 and 0.

5.

10. A chip-on-film, characterized in that: The chip-on-film comprises: Driver chip; The flexible base film according to any one of claims 1 to 9; Wherein, the driving chip is arranged on the chip bonding area of ​​the flexible base film.

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