Application programming interface for decryption

Abstract

The invention discloses an application programming interface for decryption. Apparatus, systems, and techniques for executing an application programming interface (API). In at least one embodiment, the API is used to cause decryption of encrypted information based at least in part on one or more encryption algorithm indicators.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present application incorporates by reference herein the entire disclosure of U.S. Patent Application No. 18 / 612,985, entitled "Application Programming Interface for Encryption," and U.S. Patent Application No. 18 / 612,992, entitled "Application Programming Interface for Decryption," for all purposes. Technical Field

[0003] At least one embodiment is directed to one or more encryption algorithms identified by one or more indicators.For example, at least one embodiment is directed to computer-executable instructions comprising one or more indicators identifying one or more encryption algorithms. Background Art

[0004] Encryption algorithms can be used to conceal information. Generally, encryption algorithms are used to convert plaintext information into ciphertext. Specifically, encryption algorithms convert plaintext information into ciphertext understandable to humans and / or machines. Encryption algorithms can convert ciphertext into plaintext information understandable to humans and / or machines. Technologies using encryption algorithms can be enhanced to improve data protection, memory usage, computer storage usage, computing resource performance, and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 An exemplary system environment for encrypting information according to at least one embodiment is shown;

[0006] Figure 2 An exemplary system environment for encrypting one or more neural network parameters according to at least one embodiment is shown;

[0007] Figure 3 An exemplary system environment for decrypting information according to at least one embodiment is shown;

[0008] Figure 4 An exemplary system environment for decrypting information according to at least one embodiment is shown;

[0009] Figure 5 An exemplary system environment including a system operable to perform cryptographic operations according to at least one embodiment is shown;

[0010] Figure 6 An exemplary system environment including a system operable to perform cryptographic operations according to at least one embodiment is shown;

[0011] Figure 7is a block diagram illustrating a driver and / or runtime including one or more libraries for providing one or more application programming interfaces (APIs) according to at least one embodiment;

[0012] Figure 8 illustrates an encryption process according to at least one embodiment;

[0013] Figure 9 illustrates an encryption process according to at least one embodiment;

[0014] Figure 10 illustrates a decryption process according to at least one embodiment;

[0015] Figure 11 illustrates a decryption process according to at least one embodiment;

[0016] Figure 12 An exemplary data center is shown in accordance with at least one embodiment;

[0017] Figure 13 A processing system according to at least one embodiment is shown;

[0018] Figure 14 A computer system according to at least one embodiment is shown;

[0019] Figure 15 A system according to at least one embodiment is shown;

[0020] Figure 16 An exemplary integrated circuit according to at least one embodiment is shown;

[0021] Figure 17 A computing system according to at least one embodiment is shown;

[0022] Figure 18 An APU is shown according to at least one embodiment;

[0023] Figure 19 A CPU according to at least one embodiment is shown;

[0024] Figure 20 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0025] Figure 21A-21B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0026] Figure 22A A graphics core according to at least one embodiment is shown;

[0027] Figure 22B GPGPU according to at least one embodiment is shown;

[0028] Figure 23A A parallel processor according to at least one embodiment is shown;

[0029] Figure 23B illustrates a processing cluster according to at least one embodiment;

[0030] Figure 23C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0031] Figure 24 A graphics processor according to at least one embodiment is shown;

[0032] Figure 25 A processor according to at least one embodiment is shown;

[0033] Figure 26 A processor according to at least one embodiment is shown;

[0034] Figure 27 illustrates a graphics processor core according to at least one embodiment;

[0035] Figure 28 illustrates a PPU according to at least one embodiment;

[0036] Figure 29 shows a GPC according to at least one embodiment;

[0037] Figure 30 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0038] Figure 31 illustrates a software stack for a programming platform according to at least one embodiment;

[0039] Figure 32 According to at least one embodiment, Figure 31 CUDA implementation of the software stack;

[0040] Figure 33 According to at least one embodiment, Figure 31 ROCm implementation of the software stack;

[0041] Figure 34 According to at least one embodiment, Figure 31 OpenCL implementation of the software stack;

[0042] Figure 35 illustrates software supported by a programming platform according to at least one embodiment;

[0043] Figure 36 According to at least one embodiment, Figures 31-34 Compiled code executed on the programming platform;

[0044] Figure 37 According to at least one embodiment, Figures 31-34 More detailed compiled code executed on the programming platform;

[0045] Figure 38 Transforming source code before compiling it according to at least one embodiment is shown;

[0046] Figure 39A A system configured to compile and execute CUDA source code using different types of processing units is shown in accordance with at least one embodiment;

[0047] Figure 39B A method configured to compile and execute a program using a CPU and a CUDA-enabled GPU according to at least one embodiment is shown. Figure 39A CUDA source code system;

[0048] Figure 39C A method configured to compile and execute using a CPU and a non-CUDA enabled GPU according to at least one embodiment is shown. Figure 39A CUDA source code system;

[0049] Figure 40 According to at least one embodiment, Figure 39C An example kernel converted by the CUDA to HIP conversion tool;

[0050] Figure 41 More details are shown according to at least one embodiment. Figure 39C A non-CUDA-enabled GPU;

[0051] Figure 42 shows how threads of an exemplary CUDA grid are mapped to Figure 41 Different computing units;

[0052] Figure 43 shows how to migrate existing CUDA code to data parallel C++ code according to at least one embodiment; and

[0053] Figure 44 Components of a system for accessing large language models in accordance with at least one embodiment are shown. DETAILED DESCRIPTION

[0054] In the following description, numerous specific details are set forth to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0055] In at least one embodiment, information is identified for encryption. In at least one embodiment, the information is data. In at least one embodiment, the information is associated with at least one neural network. In at least one embodiment, the information is generated based on training at least one neural network. In at least one embodiment, the information includes parameters of the neural network. In at least one embodiment, the information includes weights of the neural network. In at least one embodiment, the information includes parameters of a neural network model generated by training at least one neural network.

[0056] In at least one embodiment, the information identified for encryption is in a data structure. In at least one embodiment, the data structure is a file accessible by a computing system. In at least one embodiment, the data structure is an archive file. In at least one embodiment, the archive file may include one or more parameters of at least one neural network. In at least one embodiment, the archive file may include one or more weights of at least one neural network.

[0057] In at least one embodiment, the information identified for encryption is obtained by computer-executable instructions executed by at least one processor. In at least one embodiment, the described computer-executable instructions are executed by at least one processor to perform the actions and / or functions described herein. In at least one embodiment, the information identified for encryption includes at least one identifier. In at least one embodiment, the at least one identifier is associated with an encryption algorithm. In at least one embodiment, the computer-executable instructions include the encryption algorithm, and the at least one identifier can be used to locate the encryption algorithm. In at least one embodiment, the identifier is associated with a salt. In at least one embodiment, the salt is a string that can be combined with the encryption algorithm. In at least one embodiment, the salt is a random byte string generated by a string generator function.

[0058] In at least one embodiment, the computer-executable instructions use the at least one identifier to locate an associated encryption algorithm. In at least one embodiment, the computer-executable instructions use the associated encryption algorithm to encrypt information. In at least one embodiment, the at least one identifier is associated with the encrypted information. In at least one embodiment, the at least one identifier is associated with metadata of the encrypted information.

[0059] In at least one embodiment, the computer-executable instructions decrypt encrypted information. In at least one embodiment, the computer-executable instructions use at least one identifier associated with the encrypted information to locate an encryption algorithm. In at least one embodiment, the computer-executable instructions locate the encryption algorithm by referencing metadata of the encrypted information, determine that the metadata includes at least one identifier, and determine the encryption algorithm based on the at least one identifier. In at least one embodiment, the located encryption algorithm is used by the computer-executable instructions to decrypt the encrypted information.

[0060] In at least one embodiment, a computer-implemented system obtains information to be encrypted. In at least one embodiment, the computer-implemented system selects at least one encryption algorithm from a plurality of encryption algorithms to encrypt the information. In at least one embodiment, each of the plurality of encryption algorithms has an associated identifier. In at least one embodiment, the computer-implemented system randomly selects at least one encryption algorithm from the plurality of encryption algorithms to encrypt the information. In at least one embodiment, the computer-implemented system associates an identifier associated with the encryption algorithm that encrypted the information with the encrypted information. In at least one embodiment, the identifier is included in metadata of the encrypted information.

[0061] Figure 1 An exemplary system environment 100 for encrypting information according to at least one embodiment is shown. In at least one embodiment, system 102 provides information 104. In at least one embodiment, system 102 includes one or more processors and one or more computer-executable instructions executable by the one or more processors. In at least one embodiment, the one or more processors execute the one or more computer-executable instructions to generate information 104. In at least one embodiment, system 102 includes one or more neural networks for providing information 104. In at least one embodiment, the one or more computer-executable instructions are hosted by one or more computer-implemented storage devices, such as volatile and / or non-volatile computer-implemented storage devices.

[0062] In at least one embodiment, information 104 is obtained by system 106. In at least one embodiment, information 104 is transmitted from system 102 to system 106. In at least one embodiment, system 102 and system 106 are separate systems that are separated by a wired and / or wireless communication arrangement. In at least one embodiment, system 102 and system 106 are jointly incorporated into a common system environment. In at least one embodiment, system 106 includes one or more processors and one or more computer-executable instructions executed by the one or more processors.

[0063] In at least one embodiment, the system 106 includes a cryptographic engine 108. In at least one embodiment, the cryptographic engine 108 is configured to perform one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, the cryptographic engine 108 is included in the one or more computer-executable instructions of the system 106. In at least one embodiment, the cryptographic engine 108 is included in hardware and / or software, such as the hardware and / or software of the system 106.

[0064] In at least one embodiment, the cryptographic engine 108 includes an encryption algorithm lookup table 110. In at least one embodiment, the encryption algorithm lookup table 110 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 110 includes multiple encryption algorithm indicators, each of which is associated with an encryption algorithm. In at least one embodiment, the encryption algorithm indicator can be used to locate the associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 110 provides a mapping of the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, the cryptographic engine 108 maps the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, one or more APIs map the encryption algorithm indicator to the encryption algorithm.

[0065] In at least one embodiment, the system 106 includes an encryption algorithm storage device 112. In at least one embodiment, the encryption algorithm storage device 112 includes non-volatile memory, volatile memory, or a combination of non-volatile memory and volatile memory. In at least one embodiment, the encryption algorithm storage device 112 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in the encryption algorithm storage device 112 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of the encryption algorithm. In at least one embodiment, the encryption algorithm indicator is linked to the at least one encryption algorithm in the encryption algorithm storage device 112. In at least one embodiment, the encryption algorithm indicator is included in the metadata of the at least one encryption algorithm in the encryption algorithm storage device 112.

[0066] In at least one embodiment, the cryptographic engine 108 can locate an encryption algorithm in the encryption algorithm storage device 112 by referencing the encryption algorithm lookup table 110, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate the encryption algorithm in the encryption algorithm storage device 112 by matching the encryption algorithm indicator in the encryption algorithm lookup table 110 with a similar encryption algorithm indicator associated with the encryption algorithm hosted by the encryption algorithm storage device 112.

[0067] In at least one embodiment, information 104 may be received by system 106. In at least one embodiment, information 104 is encrypted by cryptographic engine 108. In at least one embodiment, cryptographic engine 108 locates an encryption algorithm indicator in encryption algorithm lookup table 110. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of an encryption algorithm. In at least one embodiment, cryptographic engine 108 randomly locates the encryption algorithm indicator in encryption algorithm lookup table 110. In at least one embodiment, cryptographic engine 108 locates the encryption algorithm indicator in encryption algorithm lookup table 110 based on the encryption algorithm indicator included in information 104. In at least one embodiment, cryptographic engine 108 uses the encryption algorithm indicator included in information 104 to locate the encryption algorithm indicator in encryption algorithm lookup table 110. In at least one embodiment, the located encryption algorithm indicator in encryption algorithm lookup table 110 is linked to an encryption algorithm hosted by encryption algorithm storage 112. In at least one embodiment, the encryption algorithm linked to the encryption algorithm indicator is used to encrypt information 104. In at least one embodiment, the information 104 is encrypted by the cryptographic engine 108 and the located encryption algorithm, generating encrypted information 114. In at least one embodiment, the encryption algorithm indicator associated with the encryption algorithm used to generate the encrypted information 114 is associated with the encrypted information 114. In at least one embodiment, the encryption algorithm indicator is associated with metadata 116 of the encrypted information 114. In at least one embodiment, the encryption algorithm indicator is associated with other information linked to the encrypted information 114.

[0068] Figure 2 An exemplary system environment 200 for encrypting one or more neural network parameters is shown in accordance with at least one embodiment. In at least one embodiment, a neural network 202 provides one or more parameters 204. In at least one embodiment, the neural network 202 can be executed by one or more processors. In at least one embodiment, the one or more processors execute the neural network 202 to generate the one or more parameters 204.

[0069] In at least one embodiment, one or more parameters 204 may include one or more weights, which may include the strength or amplitude of the connections between neurons in neural network 202. In at least one embodiment, the weights may be adjusted during the learning process to reduce the difference between the actual output of neural network 202 and the expected output. In at least one embodiment, one or more parameters 204 may include one or more biases. In at least one embodiment, a bias is a parameter that can be added to the weighted sum of the inputs to shift the activation function, which can aid neural network learning. In at least one embodiment, one or more parameters 204 may include one or more activation functions, which are mathematical equations that determine the output of a neural network. These functions are attached to one or more neurons in the network and determine whether to activate the function based on whether the inputs of the one or more neurons correlate with the model's predictions. In at least one embodiment, one or more parameters 204 may include one or more learning rates. In at least one embodiment, the learning rate is a hyperparameter that determines the step size for each iteration while moving toward the minimum value of the loss function. In at least one embodiment, one or more parameters 204 may include one or more layers and / or one or more nodes in each layer. In at least one embodiment, the number of layers in a neural network can determine how the network will learn from data.

[0070] In at least one embodiment, one or more parameters 204 are obtained by system 206. In at least one embodiment, one or more parameters 204 are transmitted to system 206 by neural network 202. In at least one embodiment, neural network 202 and system 206 are separated by a wired and / or wireless communication arrangement. In at least one embodiment, neural network 202 and system 206 are jointly incorporated into a common system environment. In at least one embodiment, system 206 includes one or more processors and one or more computer-executable instructions to be executed by the one or more processors.

[0071] In at least one embodiment, the system 206 includes a cryptographic engine 208. In at least one embodiment, the cryptographic engine 208 is configured to perform one or more cryptographic operations, such as encrypting and / or decrypting information, such as one or more parameters 204. In at least one embodiment, the cryptographic engine 208 is included in the one or more computer-executable instructions of the system 206. In at least one embodiment, the cryptographic engine 208 is included in hardware and / or software, such as the hardware and / or software of the system 206.

[0072] In at least one embodiment, the cryptographic engine 208 includes an encryption algorithm lookup table 210. In at least one embodiment, the encryption algorithm lookup table 210 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 210 includes multiple encryption algorithm indicators, each of which is associated with an encryption algorithm. In at least one embodiment, the encryption algorithm indicator can be used to locate the associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 210 provides a mapping of the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, the cryptographic engine 208 maps the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, one or more APIs map the encryption algorithm indicator to the encryption algorithm.

[0073] In at least one embodiment, the system 206 includes an encryption algorithm storage device 212. In at least one embodiment, the encryption algorithm storage device 212 includes non-volatile memory, volatile memory, or a combination of non-volatile memory and volatile memory. In at least one embodiment, the encryption algorithm storage device 212 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in the encryption algorithm storage device 212 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is linked to the at least one encryption algorithm in the encryption algorithm storage device 212. In at least one embodiment, the encryption algorithm indicator is included in the metadata of the at least one encryption algorithm in the encryption algorithm storage device 212.

[0074] In at least one embodiment, the cryptographic engine 208 can locate an encryption algorithm in the encryption algorithm storage device 212 by referencing the encryption algorithm lookup table 210, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate the encryption algorithm in the encryption algorithm storage device 212 by matching the encryption algorithm indicator in the encryption algorithm lookup table 210 with a matching encryption algorithm indicator associated with the encryption algorithm hosted by the encryption algorithm storage device 212.

[0075] In at least one embodiment, the system 206 may receive one or more parameters 204. In at least one embodiment, the one or more parameters 204 are to be encrypted by the cryptographic engine 208. In at least one embodiment, the cryptographic engine 208 locates an encryption algorithm indicator in the encryption algorithm lookup table 210. In at least one embodiment, the cryptographic engine 208 randomly locates the encryption algorithm indicator in the encryption algorithm lookup table 210. In at least one embodiment, the cryptographic engine 208 locates the encryption algorithm indicator in the encryption algorithm lookup table 210 based on the encryption algorithm indicator included in the one or more parameters 204. In at least one embodiment, the cryptographic engine 208 uses the encryption algorithm indicator included in the one or more parameters 204 to locate the encryption algorithm indicator in the encryption algorithm lookup table 210. In at least one embodiment, the located encryption algorithm indicator in the encryption algorithm lookup table 210 is linked to an encryption algorithm hosted by the encryption algorithm storage 212. In at least one embodiment, the encryption algorithm linked to the encryption algorithm indicator is used to encrypt the one or more parameters 204. In at least one embodiment, the one or more parameters 204 are encrypted by the cryptographic engine 208 and the located encryption algorithm, generating the encrypted one or more parameters 204. In at least one embodiment, the encryption algorithm indicator associated with the encryption algorithm used to generate the encrypted one or more parameters 214 is associated with the encrypted one or more parameters 214. In at least one embodiment, the encryption algorithm indicator is associated with metadata 216 of the encrypted one or more parameters 214. In at least one embodiment, the encryption algorithm indicator is associated with other information linked to the encrypted one or more parameters 214.

[0076] In at least one embodiment, the encrypted parameters 214 are further protected using a key. In at least one embodiment, the encrypted parameters 214 are protected by the cryptographic engine 208 using the key. In at least one embodiment, the key is provided by a user. In at least one embodiment, the key is generated by the cryptographic engine 208. In at least one embodiment, the key is generated by the cryptographic engine 208 and provided to the user. In at least one embodiment, the user may provide the key to the cryptographic engine 208 to further protect the encrypted parameters 214.

[0077] Figure 3An exemplary system environment 300 for decrypting information according to at least one embodiment is shown. In at least one embodiment, encrypted information 314 is obtained by a system 306. In at least one embodiment, the system 306 includes one or more processors and one or more computer-executable instructions executable by the one or more processors. In at least one embodiment, the system 306 includes a cryptographic engine 308. In at least one embodiment, the cryptographic engine 308 is configured to perform one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, the cryptographic engine 308 is included in the one or more computer-executable instructions of the system 306. In at least one embodiment, the cryptographic engine 308 is included in hardware and / or software, such as the hardware and / or software of the system 306.

[0078] In at least one embodiment, the cryptographic engine 308 includes an encryption algorithm lookup table 310. In at least one embodiment, the encryption algorithm lookup table 310 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 310 includes multiple encryption algorithm indicators, each of which is associated with an encryption algorithm. In at least one embodiment, the encryption algorithm indicator can be used to locate the associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 310 provides a mapping of the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, the cryptographic engine 308 maps the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, one or more APIs map the encryption algorithm indicator to the encryption algorithm.

[0079] In at least one embodiment, the system 306 includes an encryption algorithm storage device 312. In at least one embodiment, the encryption algorithm storage device 312 includes non-volatile memory, volatile memory, or a combination of non-volatile memory and volatile memory. In at least one embodiment, the encryption algorithm storage device 312 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in the encryption algorithm storage device 312 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of the encryption algorithm. In at least one embodiment, the encryption algorithm indicator is linked to the at least one encryption algorithm in the encryption algorithm storage device 312. In at least one embodiment, the encryption algorithm indicator is included in the metadata of the at least one encryption algorithm in the encryption algorithm storage device 312.

[0080] In at least one embodiment, the cryptographic engine 308 can locate an encryption algorithm in the encryption algorithm storage device 312 by referencing the encryption algorithm lookup table 310, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate the encryption algorithm in the encryption algorithm storage device 312 by matching the encryption algorithm indicator in the encryption algorithm lookup table 310 with a similar encryption algorithm indicator associated with the encryption algorithm hosted by the encryption algorithm storage device 312.

[0081] In at least one embodiment, system 306 may receive encrypted information 314. In at least one embodiment, encrypted information 314 is decrypted by cryptographic engine 308. In at least one embodiment, cryptographic engine 308 locates an encryption algorithm indicator in encryption algorithm lookup table 310. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of an encryption algorithm. In at least one embodiment, cryptographic engine 308 locates the encryption algorithm indicator in encryption algorithm lookup table 310 based on the encryption algorithm indicator included in encrypted information 314. In at least one embodiment, cryptographic engine 308 uses the encryption algorithm indicator included in encrypted information 314 to locate the encryption algorithm indicator in encryption algorithm lookup table 310. In at least one embodiment, the located encryption algorithm indicator in encryption algorithm lookup table 310 is linked to an encryption algorithm hosted by encryption algorithm storage 312. In at least one embodiment, the encryption algorithm linked to the encryption algorithm indicator is used to decrypt encrypted information 314 to provide information 304. In at least one embodiment, encrypted information 314 is decrypted using cryptographic engine 308 and the located encryption algorithm to generate decrypted information 304. In at least one embodiment, the encryption algorithm indicator is associated with metadata 316 of encrypted information 314. In at least one embodiment, the encryption algorithm indicator is associated with other information linked to encrypted information 314. In at least one embodiment, information 304 is provided to system 302.

[0082] Figure 4An exemplary system environment 400 for decrypting information according to at least one embodiment is shown. In at least one embodiment, a system 406 obtains one or more encrypted parameters 414. In at least one embodiment, the system 406 includes one or more processors and one or more computer-executable instructions executable by the one or more processors. In at least one embodiment, the system 406 includes a cryptographic engine 408. In at least one embodiment, the cryptographic engine 408 is configured to perform one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, the cryptographic engine 408 is included in the one or more computer-executable instructions of the system 406. In at least one embodiment, the cryptographic engine 408 is included in hardware and / or software, such as the hardware and / or software of the system 406.

[0083] In at least one embodiment, the cryptographic engine 408 includes an encryption algorithm lookup table 410. In at least one embodiment, the encryption algorithm lookup table 410 includes one or more encryption algorithm indicators associated with one or more encryption algorithms. In at least one embodiment, the encryption algorithm lookup table 410 includes multiple encryption algorithm indicators, each of which is associated with an encryption algorithm. In at least one embodiment, the encryption algorithm indicator can be used to locate the associated encryption algorithm. In at least one embodiment, the encryption algorithm lookup table 410 provides a mapping of the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, the cryptographic engine 408 maps the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, one or more APIs map the encryption algorithm indicator to the encryption algorithm.

[0084] In at least one embodiment, the system 406 includes an encryption algorithm storage device 412. In at least one embodiment, the encryption algorithm storage device 412 includes non-volatile memory, volatile memory, or a combination of non-volatile memory and volatile memory. In at least one embodiment, the encryption algorithm storage device 412 includes one or more encryption algorithms. In at least one embodiment, at least one encryption algorithm in the encryption algorithm storage device 412 includes an associated encryption algorithm indicator. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of the encryption algorithm. In at least one embodiment, the encryption algorithm indicator is linked to the at least one encryption algorithm in the encryption algorithm storage device 412. In at least one embodiment, the encryption algorithm indicator is included in the metadata of the at least one encryption algorithm in the encryption algorithm storage device 412.

[0085] In at least one embodiment, the cryptographic engine 408 can locate an encryption algorithm in the encryption algorithm storage device 412 by referencing the encryption algorithm lookup table 410, locating an encryption algorithm indicator, and using the encryption algorithm indicator to locate the encryption algorithm in the encryption algorithm storage device 412 by matching the encryption algorithm indicator in the encryption algorithm lookup table 410 with a similar encryption algorithm indicator associated with the encryption algorithm hosted by the encryption algorithm storage device 412.

[0086] In at least one embodiment, the system 406 may receive one or more encrypted parameters 414. In at least one embodiment, the encrypted one or more parameters 414 are to be decrypted by the cryptographic engine 408. In at least one embodiment, the cryptographic engine 408 locates an encryption algorithm indicator in the encryption algorithm lookup table 410. In at least one embodiment, the encryption algorithm indicator is an opaque identifier of an encryption algorithm. In at least one embodiment, the cryptographic engine 408 locates the encryption algorithm indicator in the encryption algorithm lookup table 410 based on the encryption algorithm indicator included in the encrypted one or more parameters 414. In at least one embodiment, the cryptographic engine 408 uses the encryption algorithm indicator included in the encrypted one or more parameters 414 to locate the encryption algorithm indicator in the encryption algorithm lookup table 410. In at least one embodiment, the located encryption algorithm indicator in the encryption algorithm lookup table 410 is linked to an encryption algorithm hosted by the encryption algorithm storage 412. In at least one embodiment, the encryption algorithm linked to the encryption algorithm indicator is used to decrypt the encrypted one or more parameters 414. In at least one embodiment, the encrypted parameters 414 are decrypted by the cryptographic engine 408 and the located encryption algorithm to generate the decrypted parameters 404. In at least one embodiment, the encryption algorithm indicator is associated with metadata 416 for the encrypted one or more parameters 414. In at least one embodiment, the encryption algorithm indicator is associated with other information linked to the encrypted one or more parameters 414. In at least one embodiment, the parameters 404 are provided to the system 402.

[0087] Figure 5 An exemplary system environment 500 including systems operable to perform cryptographic operations according to at least one embodiment is shown. In at least one embodiment, a system 506 is included in the system environment 500. In at least one embodiment, the system 506 can be one or more of the systems described in the system environment 100, the system environment 200, the system environment 300, and / or the system environment 400.

[0088] In at least one embodiment, the system 506 includes a cryptographic engine 508. In at least one embodiment, the cryptographic engine 508 is configured to perform one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, the cryptographic engine 508 is included in the one or more computer-executable instructions of the system 506. In at least one embodiment, the cryptographic engine 508 is included in hardware and / or software, such as the hardware and / or software of the system 506.

[0089] In at least one embodiment, the cryptographic engine 508 includes an encryption algorithm lookup table 510. In at least one embodiment, the encryption algorithm lookup table 510 includes one or more encryption algorithm indicators 1-N associated with one or more encryption algorithms 1-N. In at least one embodiment, the encryption algorithm lookup table 510 includes multiple encryption algorithm indicators 1-N, wherein each encryption algorithm indicator 1-N is associated with an encryption algorithm 1-N. In at least one embodiment, the encryption algorithm indicator 1-N can be used to locate the associated encryption algorithm 1-N. In at least one embodiment, the encryption algorithm lookup table 510 provides a mapping of encryption algorithm indicators to encryption algorithms. In at least one embodiment, the cryptographic engine 508 maps encryption algorithm indicators to encryption algorithms. In at least one embodiment, one or more APIs map encryption algorithm indicators to encryption algorithms.

[0090] In at least one embodiment, the system 506 includes an encryption algorithm storage device 512. In at least one embodiment, the encryption algorithm storage device 512 includes non-volatile memory, volatile memory, or a combination of non-volatile memory and volatile memory. In at least one embodiment, the encryption algorithm storage device 512 includes one or more encryption algorithms 1-N. In at least one embodiment, at least one encryption algorithm 1-N in the encryption algorithm storage device 512 includes an associated encryption algorithm indicator 1-N. In at least one embodiment, the encryption algorithm indicator 1-N is an opaque identifier of the encryption algorithm 1-N. In at least one embodiment, the encryption algorithm indicator 1-N is linked to the at least one encryption algorithm in the encryption algorithm storage device 512. In at least one embodiment, the encryption algorithm indicator 1-N is included in the metadata of the at least one encryption algorithm 1-N in the encryption algorithm storage device 512. In at least one embodiment, one or more of the encryption algorithm indicators 1-N is a string, such as a numeric value, an alphanumeric value, or the like.

[0091] Figure 6An exemplary system environment 600 including systems operable to perform cryptographic operations according to at least one embodiment is shown. In at least one embodiment, a system 606 is included in the system environment 600. In at least one embodiment, the system 606 can be one or more of the systems described in the system environment 100, the system environment 200, the system environment 300, and / or the system environment 400.

[0092] In at least one embodiment, the system 606 includes a cryptographic engine 608. In at least one embodiment, the cryptographic engine 608 is configured to perform one or more cryptographic operations, such as encrypting and / or decrypting information. In at least one embodiment, the cryptographic engine 608 is included in the one or more computer-executable instructions of the system 606. In at least one embodiment, the cryptographic engine 608 is included in hardware and / or software, such as the hardware and / or software of the system 606.

[0093] In at least one embodiment, the cryptographic engine 608 includes a salt lookup table 610. In at least one embodiment, the salt lookup table 610 includes one or more salt indicators 1-N that can be combined with one or more encryption algorithms. In at least one embodiment, the salt lookup table 610 includes multiple salt indicators 1-N, each salt indicator 1-N being associated with a salt 1-N. In at least one embodiment, the salt indicators 1-N can be used to locate the associated salt 1-N. In at least one embodiment, one or more of the salts 1-N are values, such as strings. In at least one embodiment, one or more of the salts 1-N are randomly generated values, such as randomly generated strings. In at least one embodiment, one or more of the salts 1-N are randomly generated by the cryptographic engine 608. In at least one embodiment, one or more of the salts 1-N can be combined with one or more encryption algorithms to generate an encryption algorithm that can be used to encrypt and / or decrypt information (such as data or neural network parameters).

[0094] In at least one embodiment, system 606 includes storage 612. In at least one embodiment, storage 612 includes non-volatile memory, volatile memory, or a combination of non-volatile and volatile memory. In at least one embodiment, storage 612 includes one or more encryption salts 614 and one or more encryption algorithms 616. In at least one embodiment, one or more encryption salts 614 include encryption salts 1-N. In at least one embodiment, storage 612 includes one or more encryption algorithms 616. In at least one embodiment, at least one encryption salt 1-N in storage 612 includes an associated encryption salt indicator 1-N. In at least one embodiment, the encryption salt indicator 1-N is an opaque identifier for the encryption salt 1-N. In at least one embodiment, the encryption salt indicator 1-N is linked to the at least one encryption salt in storage 612. In at least one embodiment, the encryption salt indicator 1-N is included in metadata for at least one encryption algorithm, such as encryption algorithm 616.

[0095] Figure 7 7 is a block diagram illustrating a driver and / or runtime 704 including one or more libraries 706 for providing one or more application programming interfaces (APIs) 710 according to at least one embodiment. In at least one embodiment, system 700 includes one or more processors for executing one or more APIs. In at least one embodiment, software program 702 is a software module. In at least one embodiment, software program 702 includes one or more software modules associated with one or more processors. In at least one embodiment, software program 702 includes one or more cryptographic engines described herein. In at least one embodiment, software program 702 is implemented by one or more systems described herein and / or one or more system environments described herein.

[0096] In at least one embodiment, one or more APIs 710 are software instruction sets that, if executed, cause one or more processors to perform one or more computing operations. In at least one embodiment, one or more APIs 710 are distributed or otherwise provided as part of one or more libraries 706, drivers / runtimes 704, and / or any other grouping of software and / or executable code as further described herein. In at least one embodiment, one or more APIs 710 perform one or more computing operations in response to a call by a software program 702. In at least one embodiment, a software program 702 is a collection of software code, commands, instructions, or other text sequences that directs a computing device to perform one or more computing operations and / or call one or more other instruction sets (such as APIs 710 or API functions 712 (e.g., to perform cryptographic operations 716, such as encrypting or decrypting data or one or more parameters)) to be executed. In at least one embodiment, the functions provided by one or more APIs 710 include software functions 712, such as software functions that can be used to perform one or more cryptographic operations 716 using one or more parallel processing units (PPUs), such as a graphics processing unit (GPU).

[0097] In at least one embodiment, the API 710 is a hardware interface to one or more circuits for performing one or more computing operations, such as cryptographic operations. In at least one embodiment, the one or more software APIs 710 described herein are implemented as one or more circuits for performing the following operations in conjunction with Figure 1-11 In at least one embodiment, one or more software programs 702 include instructions that, if executed, cause one or more hardware devices and / or circuits to perform operations in conjunction with Figures 1-11 One or more techniques further described.

[0098] In at least one embodiment, a software program 702 (e.g., a user-implemented software program) utilizes one or more APIs 710 to perform various cryptographic operations, such as encrypting data or parameters, decrypting data or parameters, encrypting data or parameters in a data structure (e.g., a file), decrypting data or parameters in a data structure (e.g., a file), or any computing operation performed by one or more processors or parallel processing units (PPUs) (e.g., a graphics processing unit (GPU)), as described herein. In at least one embodiment, the one or more APIs 710 provide a set of callable functions 712 (referred to herein as APIs, API functions, and / or functions) that respectively perform one or more functions and / or operations, such as encrypting data or parameters, decrypting data or parameters, encrypting data or parameters in a data structure (e.g., a file), decrypting data or parameters in a data structure (e.g., a file), and cryptographic operations related to encrypting and / or decrypting information. For example, in one embodiment, the one or more APIs 710 provide functions 712 for performing cryptographic operations or functions. In at least one embodiment, one or more APIs 710 may be utilized by one or more cryptographic engines (e.g., cryptographic engine modules) described herein. In at least one embodiment, one or more APIs 710 may be utilized by one or more systems and / or system environments described herein.

[0099] In at least one embodiment, one or more software programs 702 interact with or otherwise communicate with one or more APIs 710 to perform one or more computing operations (such as cryptographic operations) using one or more PPUs (such as GPUs). In at least one embodiment, the one or more computing operations using the one or more PPUs include at least one or more groups of computing operations that are to be performed at least in part by the one or more PPUs. In at least one embodiment, the one or more software programs 702 interact with the one or more APIs 710 to perform one or more cryptographic operations 716 on information, data, parameters, etc. generated by one or more systems and / or one or more neural networks.

[0100] In at least one embodiment, an interface is software instructions that, if executed, provide access to one or more functions 712 provided by one or more APIs 710. In at least one embodiment, a software program 702 uses a native interface when a software developer compiles one or more software programs 702 in conjunction with one or more libraries 706 that include or otherwise provide access to the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are statically compiled in conjunction with precompiled libraries 706 or uncompiled source code that includes instructions for executing the one or more APIs 710. In at least one embodiment, the one or more software programs 702 are dynamically compiled and linked to the one or more precompiled libraries 706 that include the one or more APIs 710 using a linker.

[0101] In at least one embodiment, a software program 702 uses a remote interface when a software developer executes a software program that utilizes a library 706 including one or more APIs 710 or otherwise communicates with a library 706 including one or more APIs 710 over a network or other remote communication medium. In at least one embodiment, the one or more libraries 706 including one or more APIs 710 are executed by a remote computing service, such as a computing resource service provider. In another embodiment, the one or more libraries 706 including one or more APIs 710 are executed by any other computing host that provides the one or more APIs 710 to the one or more software programs 702.

[0102] In at least one embodiment, a processor executing or using one or more software programs 702 calls, uses, executes, or otherwise implements one or more APIs 710 to allocate, access, and / or otherwise manage memory 714 to be used by the software programs 702. In at least one embodiment, the one or more software programs 702 utilize the one or more APIs 710 to allocate, access, and otherwise manage memory 714 to be used by one or more portions of the software programs 702 to perform one or more cryptographic operations described herein. In at least one embodiment, the software programs 702 can request a neural network and / or other described systems and / or software to perform a function 712 provided by the one or more APIs 710, in one embodiment.

[0103] In at least one embodiment, API 710 is an API for facilitating parallel computing and, in at least one embodiment, for facilitating one or more cryptographic operations. In at least one embodiment, API 710 is any other API described further herein. In at least one embodiment, API 710 is provided by a driver and / or runtime 704. In at least one embodiment, API 710 is provided by a CUDA user-mode driver. In at least one embodiment, API 710 is provided by a CUDA runtime. In at least one embodiment, a driver (e.g., driver / runtime 704) is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 712 of API 710 during the loading and execution of one or more portions of software program 702. In at least one embodiment, runtime 704 is a data value and software instruction that, if executed, performs or otherwise facilitates the operation of one or more functions 712 of API 710 during the execution of software program 702. In at least one embodiment, one or more software programs 702 utilize one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform one or more cryptographic operations 716. In at least one embodiment, one or more of the described cryptographic engines and / or modules utilize one or more APIs 710 implemented or otherwise provided by a driver and / or runtime 704 to perform one or more cryptographic operations 716, which may include encrypting and / or decrypting data, information, parameters, data structures, files, compressed files, and the like.

[0104] Figure 8 An encryption process 800 is shown according to at least one embodiment. In at least one embodiment, the encryption process 800 is performed by one or more of the described computing system environments (such as one or more of the computing system environments 100-700 and / or Figure 1-7 one or more systems) to achieve this.

[0105] In at least one embodiment, the specific implementation of the technology disclosed herein is a matter of choice depending on the performance and other requirements of one or more computing devices. Therefore, in at least one embodiment, the logical operations (also referred to as actions) described herein are referred to differently as states, operations, structural devices, or modules. In at least one embodiment, these states, operations, structural devices, actions, and modules can be implemented with hardware, software, firmware, dedicated digital logic, and any combination thereof. In at least one embodiment, it will be understood that more or less operations than those shown in the figures and described herein can be performed. In at least one embodiment, these operations can also be performed in a different order than described herein. In at least one embodiment, it will also be understood that the method described herein can end at any time and does not need to be performed in full.

[0106] In at least one embodiment, some or all of the operations of the processes / methods described herein and / or substantially equivalent operations may be performed by executing computer-readable instructions contained on a computer storage medium. In at least one embodiment, the terms "computer-readable instructions," "computer-executable instructions," and variations thereof, as used in the specification and claims, are used broadly herein to include routines, applications, application modules, program modules, system modules, programs, components, data structures, algorithms, and the like. In at least one embodiment, the computer-readable instructions may be implemented on a variety of system configurations, including single-processor or multi-processor systems, minicomputers, mainframe computers, distributed computer systems, personal computers, handheld computing devices, programmable consumer electronics, combinations thereof, and the like.

[0107] Thus, in at least one embodiment, it will be understood that the logical operations described herein are implemented as (1) a sequence of computer-implemented actions or program modules (such as one or more cryptographic engines) running on a computing system and / or (2) interconnected machine logic circuits or circuit modules within the computing system. In at least one embodiment, the implementation is a matter of choice depending on the performance and other requirements of the computing system. Thus, in at least one embodiment, the logical operations described herein are variously referred to as states, operations, structural devices, actions, or modules. In at least one embodiment, these states, operations, structural devices, actions, and modules may be implemented in software, firmware, dedicated digital logic, and any combination thereof.

[0108] In at least one embodiment, at 802, information is obtained. In at least one embodiment, the information includes data. In at least one embodiment, the information includes parameters. In at least one embodiment, the information includes parameters from at least one neural network. In at least one embodiment, the information is obtained in a data structure. In at least one embodiment, the information is obtained in a file. In at least one embodiment, the information is obtained in an archive file. In at least one embodiment, the archive file includes one or more parameters, such as one or more parameters from one or more neural networks. In at least one environment, the information includes an indicator of an encryption algorithm. In at least one embodiment, the information includes a specifier, such as a flag, binary value, or other specifier, indicating that the information is to be encrypted. In at least one embodiment, the information is obtained by the system and at least temporarily stored in volatile memory. In at least one embodiment, the information is obtained by the system and stored in protected volatile memory, such as encrypted volatile memory. In at least one embodiment, all of the volatile memory storing the information is encrypted. In at least one embodiment, only a portion of the volatile memory storing the information is encrypted.

[0109] In at least one embodiment, at 804, the information is analyzed to determine whether the information is to be encrypted. In at least one embodiment, determining whether the information is to be encrypted includes analyzing the information to determine whether the information includes a descriptor indicating that the information is to be encrypted. In at least one embodiment, when the information is not to be encrypted, the system performing encryption process 800 enters a steady state, awaiting additional information for processing. In at least one embodiment, when the information is to be encrypted, the information is analyzed to determine 806 whether the information includes an indicator of an encryption algorithm.

[0110] In at least one embodiment, when the information includes the indicator of the encryption algorithm at 806, the indicator is used to locate an encryption algorithm having an associated indicator that matches the indicator included in the information at 808. In at least one embodiment, the encryption algorithm is stored in protected storage, such as protected volatile memory or non-volatile memory. In at least one embodiment, the encryption algorithm is stored in encrypted storage, such as encrypted volatile memory or non-volatile memory.

[0111] In at least one embodiment, at 810, the encryption algorithm located using the indicator included in the information and the indicator associated with the encryption algorithm is used to encrypt the information. In at least one embodiment, protection of the encrypted information can be further enhanced by associating a key with the encrypted information. In at least one embodiment, the key is a user's key. In at least one embodiment, to decrypt the encrypted information, the encryption algorithm and the key are required to decrypt the encrypted information. In at least one embodiment, to decrypt the encrypted information, the encryption algorithm and the key are required to decrypt the encrypted information using its associated identifier.

[0112] In at least one embodiment, at 812, the encrypted information is disseminated. In at least one embodiment, the encrypted information is disseminated to a user and / or one or more systems for use after being decrypted. In at least one embodiment, the encrypted information includes metadata, the metadata including the indicator associated with the encryption algorithm used to encrypt the information. In at least one embodiment, the encryption algorithm is decryptable by software and / or hardware that has access to the encryption algorithm used to encrypt the information. The software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information by searching for the encryption algorithm having an associated indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encryption algorithm is only decryptable by software and / or hardware that has access to the encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information.

[0113] In at least one embodiment, at 814, when the information does not include an indicator for encryption, an indicator is selected. In at least one embodiment, the indicator corresponds to an encryption algorithm with an associated similar indicator. In at least one embodiment, the indicator is selected from a plurality of indicators, each indicator corresponding to an associated encryption algorithm. In at least one embodiment, the indicator is randomly selected from the plurality of indicators. In at least one embodiment, the plurality of indicators are listed in a lookup table, each indicator corresponding to an associated encryption algorithm. In at least one embodiment, the selected indicator is selected from the lookup table. In at least one embodiment, the selected indicator is randomly selected from the lookup table. In at least one embodiment, the encryption algorithm lookup table provides a mapping of encryption algorithm indicators to encryption algorithms. In at least one embodiment, a cryptographic engine maps the encryption algorithm indicator to the encryption algorithm. In at least one embodiment, one or more APIs map the encryption algorithm indicator to the encryption algorithm.

[0114] In at least one embodiment, the selected indicator is used to locate an encryption algorithm at 816. In at least one embodiment, the selected indicator is used to query system storage for an encryption algorithm having an associated indicator that matches the selected indicator.

[0115] In at least one embodiment, at 818, the encryption algorithm located using the indicator is used to encrypt the information.

[0116] In at least one embodiment, at 820, encrypted information is disseminated. In at least one embodiment, the encrypted information is disseminated to a user and / or one or more systems for use after being decrypted. In at least one embodiment, the encrypted information includes metadata, including the indicator associated with the encryption algorithm used to encrypt the information. In at least one embodiment, the encrypted information is decryptable by software and / or hardware that has access to the encryption algorithm used to encrypt the information. The software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information by searching for the encryption algorithm having an associated indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encrypted information is decryptable only by software and / or hardware that has access to the encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the encryption algorithm used to encrypt the information.

[0117] Figure 9An encryption process 900 is shown according to at least one embodiment. In at least one embodiment, the encryption process 900 is implemented by one or more of the described computing system environments, such as one or more of the computing system environments 100-700 and / or Figure 1-7 One or more systems.

[0118] In at least one embodiment, at 902, information is obtained. In at least one embodiment, the information includes data. In at least one embodiment, the information includes parameters. In at least one embodiment, the information includes parameters from at least one neural network. In at least one embodiment, the information is obtained in a data structure. In at least one embodiment, the information is obtained in a file. In at least one embodiment, the information is obtained in an archive file. In at least one embodiment, the archive file includes one or more parameters, such as one or more parameters from one or more neural networks. In at least one environment, the information includes an indicator of a salt. In at least one embodiment, the information includes a descriptor, such as a flag, binary value, or other descriptor, indicating that the information is to be encrypted. In at least one embodiment, the information is obtained by the system and at least temporarily stored in volatile memory. In at least one embodiment, the information is obtained by the system and stored in protected volatile memory, such as encrypted volatile memory. In at least one embodiment, the entire volatile memory storing the information is encrypted. In at least one embodiment, only a portion of the volatile memory storing the information is encrypted.

[0119] In at least one embodiment, at 904, the information is analyzed to determine whether the information is to be encrypted. In at least one embodiment, determining whether the information is to be encrypted includes analyzing the information to determine whether the information includes a descriptor indicating that the information is to be encrypted. In at least one embodiment, when the information is not to be encrypted, the system performing the encryption process 900 enters a steady state, awaiting additional information for processing. In at least one embodiment, when the information is to be encrypted, the information is analyzed to determine 906 whether the information includes an indicator of a salt.

[0120] In at least one embodiment, at 906, when the information includes the indicator of the salt, the indicator is used to locate a salt having an associated indicator that matches the indicator included in the information. In at least one embodiment, the salt is stored in protected storage, such as protected volatile memory or non-volatile memory. In at least one embodiment, the salt is stored in encrypted storage, such as encrypted volatile memory or non-volatile memory. In at least one embodiment, multiple salts can be stored, and each of the multiple salts includes an associated indicator.

[0121] In at least one embodiment, at 910, the salt located using the indicator included in the information and the indicator associated with the salt is combined with an encryption algorithm to generate an encryption algorithm modified by the salt. In at least one embodiment, the salt is random data. In at least one embodiment, the salt is an input to the encryption algorithm. In at least one embodiment, the salt is used to increase the effort required to perform a brute force attack on information encrypted using the encryption algorithm, which processes the salt as input. In at least one embodiment, the information is encrypted using the encryption algorithm modified by the salt to generate encrypted information. In at least one embodiment, protection of the encrypted information is further enhanced by associating a key with the encrypted information. In at least one embodiment, the key is a user's key. In at least one embodiment, to decrypt the encrypted information, the encryption algorithm, the salt, and the key are required to decrypt the encrypted information. In at least one embodiment, to decrypt the encrypted information, the encryption algorithm modified by the salt and the key are required to decrypt the encrypted information.

[0122] In at least one embodiment, at 912, the encrypted information is disseminated. In at least one embodiment, the encrypted information is disseminated to a user and / or one or more systems for use after decryption. In at least one embodiment, the encrypted information includes metadata, including an indicator associated with the salt, which is used to modify the encryption algorithm used to encrypt the information. In at least one embodiment, the encrypted information is decryptable by software and / or hardware that has access to the encryption algorithm and salt used to encrypt the information. The software and / or hardware uses the indicator associated with the encrypted information to locate the salt by searching for a salt with an associated indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encrypted information is decryptable only by software and / or hardware that has access to the salt and encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the salt and use it to encrypt the information.

[0123] In at least one embodiment, at 914, when the information does not include an indicator for encryption, an indicator is selected. In at least one embodiment, the indicator corresponds to a salt with an associated similar indicator. In at least one embodiment, the indicator is selected from a plurality of indicators, each indicator corresponding to an associated salt. In at least one embodiment, the indicator is randomly selected from the plurality of indicators. In at least one embodiment, the plurality of indicators are listed in a lookup table, each indicator corresponding to an associated salt. In at least one embodiment, the selected indicator is selected from the lookup table. In at least one embodiment, the selected indicator is randomly selected from the lookup table.

[0124] In at least one embodiment, the selected indicator is used to locate a salt at 916. In at least one embodiment, the selected indicator is used to query system storage for a salt having an associated indicator that matches the selected indicator.

[0125] In at least one embodiment, at 918, the salt located using the indicator is used with an encryption algorithm to encrypt information.

[0126] In at least one embodiment, at 920, the encrypted information is disseminated. In at least one embodiment, the encrypted information is disseminated to a user and / or one or more systems for use after decryption. In at least one embodiment, the encrypted information includes metadata, including an indicator associated with the salt used to modify the encryption algorithm used to encrypt the information. In at least one embodiment, the encrypted information is decryptable by software and / or hardware that has access to the encryption algorithm and salt used to encrypt the information. The software and / or hardware uses the indicator associated with the encrypted information to locate the salt by searching for a salt with an associated indicator that matches the indicator associated with the encrypted information. In at least one embodiment, the encrypted information is decryptable only by software and / or hardware that has access to the salt and encryption algorithm used to encrypt the information. In at least one embodiment, the software and / or hardware uses the indicator associated with the encrypted information to locate the salt and use it to encrypt the information.

[0127] Figure 10 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the decryption process 1000 is implemented by one or more of the described computing system environments, such as one or more of the computing system environments 100-700 and / or Figure 1-7 One or more systems.

[0128] In at least one embodiment, at 1002, encrypted information is obtained. In at least one embodiment, the encrypted information comprises encrypted data. In at least one embodiment, the encrypted information comprises encrypted parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters of a trained neural network model. In at least one embodiment, the encrypted information comprises encrypted neural network parameters that are confidential neural network parameters of the trained neural network model. In at least one embodiment, the confidential neural network parameters will remain encrypted and hidden from a system and / or user of a neural network using the confidential neural network parameters.

[0129] In at least one embodiment, at 1004, an indicator associated with the encrypted information is determined. In at least one embodiment, the indicator associated with the encrypted information is determined from metadata of the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information that is separate from the encrypted information. In at least one embodiment, the other information is obtained separately from the encrypted information.

[0130] In at least one embodiment, at 1006, an encryption algorithm is located. In at least one embodiment, the encryption algorithm is located using the indicator associated with the encrypted information. In at least one embodiment, the encryption algorithm is located by referencing a lookup table comprising one or more indicators. In at least one embodiment, each of the one or more indicators of the lookup table comprises an associated reference to an encryption algorithm. In at least one embodiment, the encryption algorithm can be retrieved from a computer-implemented storage device based on locating the encryption algorithm using the indicator associated with the encrypted information.

[0131] In at least one embodiment, at 1008, a user key is obtained. In at least one embodiment, the user key is used in conjunction with an encryption algorithm to encrypt the encrypted information. In at least one embodiment, the user key is obtained from a user. In at least one embodiment, the user key is obtained from a system, software, and / or hardware that provides the encrypted information.

[0132] In at least one embodiment, at 1010, the located encryption algorithm is used to decrypt the encrypted information. In at least one embodiment, the located encryption algorithm and the user key are used to decrypt the encrypted information. In at least one embodiment, a system that uses the located encryption algorithm to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users. In at least one embodiment, a system that uses the located encryption algorithm and the user key to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users. In at least one embodiment, the decrypted information is disclosed only to the system that uses the decrypted information. In at least one embodiment, the decrypted information is disclosed only to the neural network that uses the decrypted information. In at least one embodiment, the decrypted information is stored in a protected computer-implemented storage device, such as encrypted volatile memory and / or non-volatile memory.

[0133] Figure 11 1. Decryption process 1100 is shown in accordance with at least one embodiment. In at least one embodiment, decryption process 1100 is implemented by one or more of the described computing system environments, such as one or more of computing system environments 100-700 and / or Figure 1-7 One or more systems.

[0134] In at least one embodiment, at 1102, encrypted information is obtained. In at least one embodiment, the encrypted information comprises encrypted data. In at least one embodiment, the encrypted information comprises encrypted parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters. In at least one embodiment, the encrypted information comprises encrypted neural network parameters of a trained neural network model. In at least one embodiment, the encrypted information comprises encrypted neural network parameters that are confidential neural network parameters of the trained neural network model. In at least one embodiment, the confidential neural network parameters will remain encrypted and hidden from a system and / or user of a neural network that utilizes the confidential neural network parameters.

[0135] In at least one embodiment, at 1104, an indicator associated with the encrypted information is determined. In at least one embodiment, the indicator associated with the encrypted information is determined from metadata of the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information. In at least one embodiment, the indicator associated with the encrypted information is determined from other information associated with the encrypted information that is separate from the encrypted information. In at least one embodiment, the other information is obtained separately from the encrypted information.

[0136] In at least one embodiment, at 1106, a salt is located. In at least one embodiment, the salt is located using the indicator associated with the encrypted information. In at least one embodiment, the salt is located by referencing a lookup table comprising one or more indicators. In at least one embodiment, each of the one or more indicators of the lookup table comprises an associated reference to a salt. In at least one embodiment, the salt can be retrieved from a computer-implemented storage device based on locating the salt using the indicator associated with the salt.

[0137] In at least one embodiment, at 1108, a user key is obtained. In at least one embodiment, the user key is used in conjunction with an encryption algorithm to encrypt the encrypted information. In at least one embodiment, the user key is obtained from a user. In at least one embodiment, the user key is obtained from a system, software, and / or hardware that provides the encrypted information.

[0138] In at least one embodiment, at 1110, the located salt is combined with an encryption algorithm to decrypt the encrypted information. In at least one embodiment, the located salt is combined with the encryption algorithm and the user key to decrypt the encrypted information. In at least one embodiment, a system that uses the located salt in combination with the encryption algorithm to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users. In at least one embodiment, a system that uses the located salt in combination with the encryption algorithm and the user key to decrypt the encrypted information does not disclose the decrypted information to unauthorized systems and / or users. In at least one embodiment, the decrypted information is disclosed only to the system that uses the decrypted information. In at least one embodiment, the decrypted information is disclosed only to the neural network that uses the decrypted information. In at least one embodiment, the decrypted information is stored in a protected computer-implemented storage device, such as encrypted volatile memory and / or non-volatile memory.

[0139] Data Center

[0140] Figure 12 An example data center 1200 is shown in accordance with at least one embodiment. In at least one embodiment, the data center 1200 includes, but is not limited to, a data center infrastructure layer 1210, a framework layer 1220, a software layer 1230, and an application layer 1240.

[0141] In at least one embodiment, Figure 12 As shown, the data center infrastructure layer 1210 may include a resource coordinator 1212, grouped computing resources 1214, and node computing resources ("node CRs") 1216(1)-1216(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 1216(1)-1216(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), data processing units ("DPUs") in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NWI / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 1216(1)-1216(N) may be servers having one or more of the above-mentioned computing resources.

[0142] In at least one embodiment, the grouped computing resources 1214 may include separate groups of node CRs housed in one or more racks (not shown), or many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 1214 may include computing, networking, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including CPUs or processors may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0143] In at least one embodiment, resource coordinator 1212 may configure or otherwise control one or more nodes CR 1216(1)-1216(N) and / or grouped computing resources 1214. In at least one embodiment, resource coordinator 1212 may comprise a software design infrastructure ("SDI") management entity for data center 1200. In at least one embodiment, resource coordinator 1212 may comprise hardware, software, or some combination thereof.

[0144] In at least one embodiment, Figure 12As shown, framework layer 1220 includes, but is not limited to, a job scheduler 1232, a configuration manager 1234, a resource manager 1236, and a distributed file system 1238. In at least one embodiment, framework layer 1220 may include a framework that supports software 1252 of software layer 1230 and / or one or more applications 1242 of application layer 1240. In at least one embodiment, software 1252 or applications 1242 may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1220 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which may utilize distributed file system 1238 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 1232 may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center 1200. In at least one embodiment, a configuration manager 1234 can be capable of configuring different layers, such as a software layer 1230 and a framework layer 1220 including Spark and a distributed file system 1238 for supporting large-scale data processing. In at least one embodiment, a resource manager 1236 can manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 1238 and the job scheduler 1232. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 1214 on the data center infrastructure layer 1210. In at least one embodiment, the resource manager 1236 can coordinate with the resource coordinator 1212 to manage these mapped or allocated computing resources.

[0145] In at least one embodiment, the software 1252 included in the software layer 1230 may include software used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0146] In at least one embodiment, the one or more applications 1242 included in the application layer 1240 may include one or more types of applications used by at least a portion of the node CRs 1216(1)-1216(N), the grouped computing resources 1214, and / or the distributed file system 1238 of the framework layer 1220. The one or more types of applications may include, but are not limited to, CUDA applications.

[0147] In at least one embodiment, any of configuration manager 1234, resource manager 1236, and resource coordinator 1212 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 1200 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0148] In at least one embodiment, Figure 12 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 12 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0149] Computer-based systems

[0150] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0151] Figure 13 A processing system 1300 is shown according to at least one embodiment. In at least one embodiment, system 1300 includes one or more processors 1302 and one or more graphics processors 1308, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 1302 or processor cores 1307. In at least one embodiment, processing system 1300 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. In at least one embodiment, processor cores 1307 are referred to as computational units or arithmetic units.

[0152] In at least one embodiment, the processing system 1300 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the processing system 1300 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 1300 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 1300 is a television or set-top box device having one or more processors 1302 and a graphical interface generated by one or more graphics processors 1308.

[0153] In at least one embodiment, each of the one or more processors 1302 includes one or more processor cores 1307 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 1307 is configured to process a specific instruction set 1309. In at least one embodiment, the instruction set 1309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 1307 can each process a different instruction set 1309, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 1307 can also include other processing devices, such as a digital signal processor (DSP).

[0154] In at least one embodiment, processor 1302 includes cache memory 1304. In at least one embodiment, processor 1302 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 1302. In at least one embodiment, processor 1302 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share this logic among processor cores 1307 using known cache coherence techniques. In at least one embodiment, processor 1302 also includes a register file 1306. Processor 1302 can include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 1306 can include general purpose registers or other registers.

[0155] In at least one embodiment, one or more processors 1302 are coupled to one or more interface buses 1310 to transmit communication signals, such as address, data, or control signals, between the processors 1302 and other components in the system 1300. In at least one embodiment, the interface bus 1310 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 1310 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 1302 includes an integrated memory controller 1316 and a platform controller hub 1330. In at least one embodiment, the memory controller 1316 facilitates communication between memory devices and other components of the processing system 1300, while the platform controller hub (PCH) 1330 provides connectivity to input / output (I / O) devices via a local I / O bus. In at least one embodiment, the one or more peripheral component interconnect buses include PCIe Gen 5, which provides an interface for the processors.

[0156] In at least one embodiment, the storage device 1320 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the storage device 1320 can be used as system memory for the processing system 1300 to store data 1322 and instructions 1321 for use when one or more processors 1302 execute applications or processes. In at least one embodiment, the memory controller 1316 is also coupled to an optional external graphics processor 1312, which can communicate with one or more graphics processors 1308 in the processor 1302 to perform graphics and media operations. In at least one embodiment, a display device 1311 can be connected to the processor 1302. In at least one embodiment, the display device 1311 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (such as a DisplayPort). In at least one embodiment, the display device 1311 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0157] In at least one embodiment, the platform controller hub 1330 enables peripheral devices to connect to the storage device 1320 and the processor 1302 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 1346, a network controller 1334, a firmware interface 1328, a wireless transceiver 1326, a touch sensor 1325, and a data storage device 1324 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 1324 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 1325 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 1326 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 1328 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 1334 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 1310. In at least one embodiment, the audio controller 1346 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 1300 includes an optional legacy I / O controller 1340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 1300. In at least one embodiment, the platform controller hub 1330 can also be connected to one or more universal serial bus (USB) controllers 1342, which connect input devices such as a keyboard and mouse 1343 combination, a camera 1344, or other USB input devices.

[0158] In at least one embodiment, instances of memory controller 1316 and platform controller hub 1330 may be integrated into a discrete external graphics processor, such as external graphics processor 1312. In at least one embodiment, platform controller hub 1330 and / or memory controller 1316 may be external to one or more processors 1302. For example, in at least one embodiment, processing system 1300 may include external memory controller 1316 and platform controller hub 1330, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 1302.

[0159] In at least one embodiment, Figure 13One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 13 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0160] Figure 14 A computer system 1400 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1400 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 1400 is formed by a processor 1402, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 1400 can include, but is not limited to, components such as the processor 1402, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 1400 can include a processor such as the Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 1400 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0161] In at least one embodiment, the computer system 1400 can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include microcontrollers, digital signal processors ("DSPs"), SoCs, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system that can execute one or more instructions according to at least one embodiment.

[0162] In at least one embodiment, computer system 1400 may include, but is not limited to, a processor 1402, which may include, but is not limited to, one or more execution units 1408, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 1400 is a single-processor desktop or server system. In at least one embodiment, computer system 1400 may be a multi-processor system. In at least one embodiment, processor 1402 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1402 may be coupled to a processor bus 1410 that may transmit data signals between processor 1402 and other components in computer system 1400.

[0163] In at least one embodiment, processor 1402 may include, but is not limited to, level 1 ("L1") internal cache memory ("cache") 1404. In at least one embodiment, processor 1402 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor 1402. In at least one embodiment, processor 1402 may include a combination of internal and external caches. In at least one embodiment, register file 1406 may store different types of data in various registers, including but not limited to integer registers, floating point registers, status registers, and an instruction pointer register.

[0164] In at least one embodiment, an execution unit 1408, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 1402. The processor 1402 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 1408 may include logic for processing a packed instruction set 1409. In at least one embodiment, by including the packed instruction set 1409 in the instruction set of the general-purpose processor 1402, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 1402. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0165] In at least one embodiment, execution unit 1408 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 1400 may include, but is not limited to, memory 1420. In at least one embodiment, memory 1420 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 1420 may store instructions 1419 and / or data 1421 represented by data signals that may be executed by processor 1402.

[0166] In at least one embodiment, a system logic chip can be coupled to the processor bus 1410 and the memory 1420. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 1416, and the processor 1402 can communicate with the MCH 1416 via the processor bus 1410. In at least one embodiment, the MCH 1416 can provide a high-bandwidth memory path 1418 to the memory 1420 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1416 can initiate data signals between the processor 1402, the memory 1420, and other components in the computer system 1400, and bridge data signals between the processor bus 1410, the memory 1420, and the system I / O 1422. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1416 may be coupled to the memory 1420 via a high-bandwidth memory path 1418 , and the graphics / video card 1412 may be coupled to the MCH 1416 via an Accelerated Graphics Port (“AGP”) interconnect 1414 .

[0167] In at least one embodiment, computer system 1400 may use system I / O 1422 as a proprietary hub interface bus to couple MCH 1416 to I / O controller hub ("ICH") 1430. In at least one embodiment, ICH 1430 may provide direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to memory 1420, chipset, and processor 1402. Examples may include, but are not limited to, an audio controller 1429, a firmware hub ("FlashBIOS") 1428, a wireless transceiver 1426, a data store 1424, a traditional I / O controller 1423 including user input 1425 and a keyboard interface, a serial expansion port 1427 (e.g., USB), and a network controller 1434. Data store 1424 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0168] In at least one embodiment, Figure 14 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 14 An exemplary SoC may be shown. In at least one embodiment, Figure 14The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 1400 are interconnected using a Compute Express Link (CXL) interconnect.

[0169] In at least one embodiment, Figure 14 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 14 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0170] Figure 15 A system 1500 is shown in accordance with at least one embodiment. In at least one embodiment, the system 1500 is an electronic device that utilizes a processor 1510. In at least one embodiment, the system 1500 can be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-site or cloud service providers, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0171] In at least one embodiment, system 1500 may include, but is not limited to, a processor 1510 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1510 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 15 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 15 An exemplary SoC may be shown. In at least one embodiment, Figure 15 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 15One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0172] In at least one embodiment, Figure 15 The system may include a display 1524, a touch screen 1525, a touchpad 1530, a near field communication unit ("NFC") 1545, a sensor hub 1540, a thermal sensor 1546, a fast chipset ("EC") 1535, a trusted platform module ("TPM") 1538, a BIOS / firmware / flash memory ("BIOS, FWFlash") 1522, a DSP 1560, a solid-state disk ("SSD") or a hard disk drive ("HDD") 1520, a wireless local area network unit ("WLAN") 1550, a Bluetooth unit 1552, a wireless wide area network unit ("WWAN") 1556, a global positioning system (GPS) 1555, a camera ("USB 3.0 camera") 1554 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 1515 implemented using, for example, the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0173] In at least one embodiment, other components may be communicatively coupled to processor 1510 through the components discussed above. In at least one embodiment, accelerometer 1541, ambient light sensor (“ALS”) 1542, compass 1543, and gyroscope 1544 may be communicatively coupled to sensor hub 1540. In at least one embodiment, thermal sensor 1539, fan 1537, keyboard 1536, and touchpad 1530 may be communicatively coupled to EC 1535. In at least one embodiment, speaker 1563, earphone 1564, and microphone (“mic”) 1565 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1562, which in turn may be communicatively coupled to DSP 1560. In at least one embodiment, audio unit 1562 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1557 may be communicatively coupled to WWAN unit 1556. In at least one embodiment, components such as the WLAN unit 1550 and the Bluetooth unit 1552 and the WWAN unit 1556 may be implemented as a next generation form factor (NGFF).

[0174] In at least one embodiment, Figure 15 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 15 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0175] Figure 16 An exemplary integrated circuit 1600 according to at least one embodiment is shown. In at least one embodiment, exemplary integrated circuit 1600 is a SoC, which can be manufactured using one or more IP cores. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., CPU, DPU), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1600 includes peripheral or bus logic, including a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I2S / I2C controller 1640. In at least one embodiment, integrated circuit 1600 can include a display device 1645 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1650 and a Mobile Industry Processor Interface (MIPI) display interface 1655. In at least one embodiment, storage can be provided by a flash memory subsystem 1660, including flash memory and a flash memory controller. In at least one embodiment, a memory interface for accessing SDRAM or SRAM memory devices may be provided via memory controller 1665. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0176] In at least one embodiment, Figure 16 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 16 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0177] Figure 17A computing system 1700 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 1700 includes a processing subsystem 1701 having one or more processors 1702 and system memory 1704 communicating via an interconnect path that may include a memory hub 1705. In at least one embodiment, memory hub 1705 may be a separate component within a chipset assembly or integrated within one or more processors 1702. In at least one embodiment, memory hub 1705 is coupled to an I / O subsystem 1711 via a communication link 1706. In at least one embodiment, I / O subsystem 1711 includes an I / O hub 1707, which enables computing system 1700 to receive input from one or more input devices 1708. In at least one embodiment, I / O hub 1707 may enable a display controller, included in one or more processors 1702, to provide output to one or more display devices 1710A. In at least one embodiment, the one or more display devices 1710A coupled to I / O hub 1707 may include local, internal, or embedded display devices.

[0178] In at least one embodiment, the processing subsystem 1701 includes one or more parallel processors 1712 coupled to the memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, the communication link 1713 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1712 form a parallel or vector processing system in a computational cluster that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor or compute unit. In at least one embodiment, the one or more parallel processors 1712 form a graphics processing subsystem that can output pixels to one of one or more display devices 1710A coupled via the I / O hub 1707. In at least one embodiment, the one or more parallel processors 1712 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1710B.

[0179] In at least one embodiment, system storage unit 1714 can be connected to I / O hub 1707 to provide a storage mechanism for computing system 1700. In at least one embodiment, I / O switch 1716 can be used to provide an interface mechanism to enable connections between I / O hub 1707 and other components, such as network adapter 1718 and / or wireless network adapter 1719, which can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 1720. In at least one embodiment, network adapter 1718 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1719 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0180] In at least one embodiment, computing system 1700 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1707. Figure 17 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0181] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing (including, for example, video output circuitry) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1712, memory hub 1705, processor 1702, and I / O hub 1707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 1700 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system. In at least one embodiment, I / O subsystem 1711 and display device 1710B are omitted from computing system 1700. In at least one embodiment, one or more parallel processors 1712 include one or more tensor memory accelerator (TMA) units that can transfer blocks of data between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa.

[0182] In at least one embodiment, Figure 17 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 17 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0183] Processing system

[0184] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0185] Figure 18An accelerated processing unit ("APU") 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 1800 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 1800 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 1800 includes, but is not limited to, a core complex 1810, a graphics complex 1840, a fabric 1860, an I / O interface 1870, a memory controller 1880, a display controller 1892, and a multimedia engine 1894. In at least one embodiment, the APU 1800 can include, but is not limited to, any combination of any number of core complexes 1810, any number of graphics complexes 1840, any number of display controllers 1892, and any number of multimedia engines 1894. For purposes of illustration, multiple instances of similar objects are denoted herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0186] In at least one embodiment, core complex 1810 is a CPU, graphics complex 1840 is a GPU, and APU 1800 is a processing unit that is not limited to integrating 1810 and 1840 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 1810, while other tasks may be assigned to graphics complex 1840. In at least one embodiment, core complex 1810 is configured to execute primary control software associated with APU 1800, such as an operating system. In at least one embodiment, core complex 1810 is the main processor of APU 1800, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 1810 issues commands that control the operations of graphics complex 1840. In at least one embodiment, core complex 1810 may be configured to execute host executable code derived from CUDA source code, and graphics complex 1840 may be configured to execute device executable code derived from CUDA source code.

[0187] In at least one embodiment, core complex 1810 includes, but is not limited to, cores 1820(1)-1820(4) and L3 cache 1830. In at least one embodiment, core complex 1810 may include, but is not limited to, any number of cores 1820 and any combination of any number and type of caches. In at least one embodiment, cores 1820 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1820 is a CPU core. In at least one embodiment, cores 1820 are referred to as computational units or arithmetic units.

[0188] In at least one embodiment, each core 1820 includes, but is not limited to, a fetch / decode unit 1822, an integer execution engine 1824, a floating-point execution engine 1826, and an L2 cache 1828. In at least one embodiment, the fetch / decode unit 1822 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1824 and the floating-point execution engine 1826. In at least one embodiment, the fetch / decode unit 1822 can simultaneously dispatch one micro-op to the integer execution engine 1824 and another micro-op to the floating-point execution engine 1826. In at least one embodiment, the integer execution engine 1824 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1826 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1822 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1824 and the floating-point execution engine 1826.

[0189] In at least one embodiment, each core 1820(i) can access an L2 cache 1828(i) included in the core 1820(i), where i is an integer representing a specific instance of the core 1820. In at least one embodiment, each core 1820 included in a core complex 1810(j) is connected to the other cores 1820 included in the core complex 1810(j) via an L3 cache 1830(j) included in the core complex 1810(j), where j is an integer representing a specific instance of the core complex 1810. In at least one embodiment, a core 1820 included in a core complex 1810(j) can access all L3 caches 1830(j) included in the core complex 1810(j), where j is an integer representing a specific instance of the core complex 1810. In at least one embodiment, the L3 cache 1830 can include, but is not limited to, any number of slices.

[0190] In at least one embodiment, graphics complex 1840 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 1840 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 1840 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 1840 is configured to perform both graphics-related operations and graphics-independent operations.

[0191] In at least one embodiment, graphics complex 1840 includes, but is not limited to, any number of compute units 1850 and L2 cache 1842. In at least one embodiment, compute units 1850 share L2 cache 1842. In at least one embodiment, L2 cache 1842 is partitioned. In at least one embodiment, graphics complex 1840 includes, but is not limited to, any number of compute units 1850 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 1840 includes, but is not limited to, any amount of dedicated graphics hardware.

[0192] In at least one embodiment, each compute unit 1850 includes, but is not limited to, any number of SIMD units 1852 and shared memory 1854. In at least one embodiment, each SIMD unit 1852 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 1850 can execute any number of thread blocks, but each thread block executes on a single compute unit 1850. In at least one embodiment, a thread block includes, but is not limited to, any number of threads of execution. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1852 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 1854. In at least one embodiment, each compute unit 1850 includes one or more thread block clusters, where a thread block cluster can implement programmatic control of locality at a finer granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, a thread block cluster (also referred to as a "cluster") enables multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0193] In at least one embodiment, fabric 1860 is a system interconnect that facilitates data and control transfers across core complex 1810, graphics complex 1840, I / O interface 1870, memory controller 1880, display controller 1892, and multimedia engine 1894. In at least one embodiment, APU 1800 may include, but is not limited to, any number and type of system interconnects in addition to or in lieu of fabric 1860 that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 1800. In at least one embodiment, I / O interface 1870 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1870. In at least one embodiment, peripheral devices coupled to I / O interface 1870 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0194] In at least one embodiment, display controller 1892 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 1894 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 1880 facilitates data transfer between APU 1800 and unified system memory 1890. In at least one embodiment, core complex 1810 and graphics complex 1840 share unified system memory 1890.

[0195] In at least one embodiment, the APU 1800 implements a memory subsystem including, but not limited to, any number and type of memory controllers 1880 and memory devices that can be dedicated to a component or shared among multiple components (e.g., shared memory 1854). In at least one embodiment, the APU 1800 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 1928, L3 cache 1830, and L2 cache 1842), each of which can be private to a component or shared among any number of components (e.g., core 1820, core complex 1810, SIMD units 1852, compute units 1850, and graphics complex 1840).

[0196] In at least one embodiment, Figure 18One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 18 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0197] Figure 19 A CPU 1900 is shown according to at least one embodiment. In at least one embodiment, the CPU 1900 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 1900 can be configured to execute application programs. In at least one embodiment, the CPU 1900 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 1900 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1900 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1900 includes, but is not limited to, any number of core complexes 1910, fabric 1960, I / O interfaces 1970, and memory controller 1980.

[0198] In at least one embodiment, core complex 1910 includes, but is not limited to, cores 1920(1)-1920(4) and L3 cache 1930. In at least one embodiment, core complex 1910 may include, but is not limited to, any number of cores 1920 and any combination of any number and type of caches. In at least one embodiment, cores 1920 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 1920 is a CPU core.

[0199] In at least one embodiment, each core 1920 includes, but is not limited to, a fetch / decode unit 1922, an integer execution engine 1924, a floating-point execution engine 1926, and an L2 cache 1928. In at least one embodiment, the fetch / decode unit 1922 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 1924 and the floating-point execution engine 1926. In at least one embodiment, the fetch / decode unit 1922 can simultaneously dispatch one micro-op to the integer execution engine 1924 and another micro-op to the floating-point execution engine 1926. In at least one embodiment, the integer execution engine 1924 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1926 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 1922 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 1924 and the floating-point execution engine 1926.

[0200] In at least one embodiment, each core 1920(i) can access an L2 cache 1928(i) included in the core 1920(i), where i is an integer representing a specific instance of the core 1920. In at least one embodiment, each core 1920 included in a core complex 1910(j) is connected to the other cores 1920 in the core complex 1910(j) via an L3 cache 1930(j) included in the core complex 1910(j), where j is an integer representing a specific instance of the core complex 1910. In at least one embodiment, a core 1920 included in a core complex 1910(j) can access all L3 caches 1930(j) included in the core complex 1910(j), where j is an integer representing a specific instance of the core complex 1910. In at least one embodiment, the L3 cache 1930 can include, but is not limited to, any number of slices.

[0201] In at least one embodiment, fabric 1960 is a system interconnect that facilitates data and control transfers across core complexes 1910(1)-1910(N) (where N is an integer greater than zero), I / O interface 1970, and memory controller 1980. In at least one embodiment, CPU 1900 may include, in addition to or in lieu of fabric 1960, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 1900. In at least one embodiment, I / O interface 1970 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1970. In at least one embodiment, peripheral devices coupled to I / O interface 1970 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0202] In at least one embodiment, memory controller 1980 facilitates data transfers between CPU 1900 and system memory 1990. In at least one embodiment, core complex 1910 and graphics complex 1940 share system memory 1990. In at least one embodiment, CPU 1900 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 1980 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 1900 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 1928 and L3 cache 1930), each of which can be private to a component or shared among any number of components (e.g., core 1920 and core complex 1910).

[0203] In at least one embodiment, Figure 19 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 19 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0204] Figure 20 An exemplary accelerator integrated slice 2090 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0205] The application effective address space 2082 within system memory 2014 stores a process element 2083. In one embodiment, the process element 2083 is stored in response to a GPU call 2081 from an application 2080 executing on processor 2007. The process element 2083 contains the processing state of the corresponding application 2080. The work descriptor (WD) 2084 contained in the process element 2083 can be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 2084 is a pointer to a job request queue in the application effective address space 2082.

[0206] Graphics acceleration module 2046 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 2084 to graphics acceleration module 2046 to start a job in a virtualized environment can be included.

[0207] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 2046 or individual graphics processing engine. Because the graphics acceleration module 2046 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 2046 is allocated.

[0208] In operation, the WD fetch unit 2091 in the accelerator integrated slice 2090 fetches the next WD 2084, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 2046. Data from the WD 2084 can be stored in registers 2045 for use by the memory management unit (MMU) 2039, the interrupt management circuit 2047, and / or the context management circuit 2048, as shown. For example, one embodiment of the MMU 2039 includes segment / page roaming circuitry for accessing the segment / page tables 2086 within the OS virtual address space 2085. The interrupt management circuit 2047 can process interrupt events (INT) 2092 received from the graphics acceleration module 2046. When executing graph operations, the effective address 2093 generated by the graphics processing engine is converted into a real address by the MMU 2039.

[0209] In one embodiment, the same register set 2045 is replicated for each graphics processing engine and / or graphics acceleration module 2046 and can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 2090. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0210] Table 1 - Registers initialized by the hypervisor

[0211] 1 Slice Control Register 2 Process area pointer assigned by real address (RA) 3 Permission mask override register 4 Interrupt vector table input offset 5 Interrupt vector table entry restriction 6 Status Register 7 Logical partition ID 8 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 9 Storage Description Register

[0212] Example registers that may be initialized by the operating system are shown in Table 2.

[0213] Table 2 - Operating System Initialization Registers

[0214]

[0215]

[0216] In one embodiment, each WD 2084 is specific to a particular graphics acceleration module 2046 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0217] In at least one embodiment, Figure 20 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 20One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0218] Figure 21A-21B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0219] Figure 21A An exemplary graphics processor 2110 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 21B An additional exemplary graphics processor 2140 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 21A The graphics processor 2110 is a low power graphics processor core. In at least one embodiment, Figure 21B The graphics processor 2140 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 2110, 2140 can be Figure 16 A variant of the graphics processor 1610.

[0220] In at least one embodiment, the graphics processor 2110 includes a vertex processor 2105 and one or more fragment processors 2115A-2115N (e.g., 2115A, 2115B, 2115C, 2115D through 2115N-1 and 2115N). In at least one embodiment, the graphics processor 2110 can execute different shader programs via separate logic, such that the vertex processor 2105 is optimized to perform operations for the vertex shader program, while one or more fragment processors 2115A-2115N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 2105 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 2115A-2115N use the primitives and vertex data generated by the vertex processor 2105 to generate a frame buffer for display on a display device. In at least one embodiment, fragment processors 2115A-2115N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct3D API.

[0221] In at least one embodiment, the graphics processor 2110 additionally includes one or more MMUs 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B. In at least one embodiment, the one or more MMUs 2120A-2120B provide a mapping of virtual to physical addresses for the graphics processor 2110, including for the vertex processor 2105 and / or the fragment processors 2115A-2115N, which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 2125A-2125B. In at least one embodiment, the one or more MMUs 2120A-2120B may synchronize with other MMUs within the system, including with the one or more MMUs 2120A-2120B. Figure 16 One or more MMUs associated with one or more application processors 1605, graphics processor 1615, and / or video processor 1620 enable each processor 1605-1620 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2130A-2130B enable the graphics processor 2110 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0222] In at least one embodiment, graphics processor 2140 includes Figure 21AOne or more MMUs 2120A-2120B, caches 2125A-2125B, and circuit interconnects 2130A-2130B of the graphics processor 2110. In at least one embodiment, the graphics processor 2140 includes one or more shader cores 2155A-2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F, through 2155N-1 and 2155N), which provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 2140 includes an inter-core task manager 2145 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2155A-2155N and a tiling unit 2158 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0223] In at least one embodiment, Figure 21A-21B One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 21A-21B One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0224] Figure 22A FIG2 shows a graphics core 2200 according to at least one embodiment. In at least one embodiment, the graphics core 2200 may include Figure 16 In at least one embodiment, the graphics core 2200 may be Figure 21B2155N. In at least one embodiment, the graphics core 2200 includes a shared instruction cache 2202, texture units 2218, and cache / shared memory 2220, which are common to execution resources within the graphics core 2200. In at least one embodiment, the graphics core 2200 may include multiple slices 2201A-2201N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 2200. The slices 2201A-2201N may include support logic including local instruction caches 2204A-2204N, thread schedulers 2206A-2206N, thread dispatchers 2208A-2208N, and a set of registers 2210A-2210N. In at least one embodiment, slices 2201A-2201N may include a set of additional function units (AFUs) 2212A-2212N, floating point units (FPUs) 2214A-2214N, integer arithmetic logic units (ALUs) 2216A-2216N, address calculation units (ACUs) 2213A-2213N, double precision floating point units (DPFPUs) 2215A-2215N, and matrix processing units (MPUs) 2217A-2217N. In at least one embodiment, graphics core 2200 is referred to as a compute unit or operation unit.

[0225] In one embodiment, the FPUs 2214A-2214N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 2215A-2215N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 2216A-2216N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 2217A-2217N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 2217A-2217N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 2212A-2212N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0226] Figure 22BA general purpose graphics processing unit (GPGPU) 2230 is shown in at least one embodiment. In at least one embodiment, GPGPU 2230 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 2230 can be configured to enable highly parallel computational operations to be performed by a GPU array. In at least one embodiment, GPGPU 2230 can be directly linked to other instances of GPGPU 2230 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 2230 includes a host interface 2232 to enable connection to a host processor. In at least one embodiment, host interface 2232 is a PCIe interface. In at least one embodiment, host interface 2232 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 2230 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 2236A-2236H using a global scheduler 2234. In at least one embodiment, the compute clusters 2236A-2236H share a cache memory 2238. In at least one embodiment, the cache memory 2238 can serve as a higher level cache for the cache memories within the compute clusters 2236A-2236H.

[0227] In at least one embodiment, GPGPU 2230 includes memory 2244A-2244B coupled to compute cluster 2236A-2236H via a set of memory controllers 2242A-2242B. In at least one embodiment, memory 2244A-2244B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0228] In at least one embodiment, computing clusters 2236A-2236H each include a set of graphics cores, such as Figure 22A The graphics core 2200, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. For example, in at least one embodiment, at least a subset of the floating-point units in each compute cluster 2236A-2236H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0229] In at least one embodiment, multiple instances of GPGPU 2230 can be configured to operate as a compute cluster. Compute clusters 2236A-2236H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 2230 communicate via host interface 2232. In at least one embodiment, GPGPU 2230 includes an I / O hub 2239 that couples GPGPU 2230 to GPU link 2240, enabling direct connection to other instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2230 are located in separate data processing systems and communicate via a network device accessible via host interface 2232. In at least one embodiment, GPU link 2240 may be configured to connect to a host processor, in addition to or in place of host interface 2232. In at least one embodiment, GPGPU 2230 may be configured to execute CUDA programs.

[0230] In at least one embodiment, Figures 22A-22B One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figures 22A-22B One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0231] Figure 23A A parallel processor 2300 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 2300 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0232] In at least one embodiment, parallel processor 2300 includes parallel processing unit 2302. In at least one embodiment, parallel processing unit 2302 includes an I / O unit 2304 that enables communication with other devices, including other instances of parallel processing unit 2302. In at least one embodiment, I / O unit 2304 can be directly connected to other devices. In at least one embodiment, I / O unit 2304 connects to other devices using a hub or switch interface (e.g., memory hub 2305). In at least one embodiment, the connection between memory hub 2305 and I / O unit 2304 forms a communication link. In at least one embodiment, I / O unit 2304 is connected to a host interface 2306 and a memory crossbar switch 2316, where host interface 2306 receives commands for performing processing operations and memory crossbar switch 2316 receives commands for performing memory operations.

[0233] In at least one embodiment, when host interface 2306 receives command buffers via I / O unit 2304, host interface 2306 can direct work operations to execute those commands to front end 2308. In at least one embodiment, front end 2308 is coupled to scheduler 2310, which is configured to dispatch commands or other work items to processing array 2312. In at least one embodiment, scheduler 2310 ensures that processing array 2312 is properly configured and in a valid state before dispatching tasks to processing array 2312. In at least one embodiment, scheduler 2310 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, a microcontroller-implemented scheduler 2310 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling rapid preemption and context switching of threads executing on processing array 2312. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 2312 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 2312 by scheduler 2310 logic within a microcontroller that includes scheduler 2310 .

[0234] In at least one embodiment, the processing array 2312 can include up to "N" processing clusters (e.g., cluster 2314A, cluster 2314B, through cluster 2314N). In at least one embodiment, each cluster 2314A-2314N of the processing array 2312 can execute a large number of concurrent threads. In at least one embodiment, the scheduler 2310 can allocate work to the clusters 2314A-2314N of the processing array 2312 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by the scheduler 2310 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing array 2312. In at least one embodiment, different clusters 2314A-2314N of the processing array 2312 can be assigned to process different types of programs or to perform different types of computations.

[0235] In at least one embodiment, the processing array 2312 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 2312 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing array 2312 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0236] In at least one embodiment, the processing array 2312 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 2312 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 2312 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing units 2302 may transfer data from system memory via the I / O units 2304 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2322) during processing and then written back to the system memory.

[0237] In at least one embodiment, when parallel processing unit 2302 is used to perform graph processing, scheduler 2310 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 2314A-2314N of processing array 2312. In at least one embodiment, portions of processing array 2312 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2314A-2314N can be stored in a buffer to allow the intermediate data to be transferred between clusters 2314A-2314N for further processing.

[0238] In at least one embodiment, the processing array 2312 can receive processing tasks to be executed via the scheduler 2310, which receives commands defining the processing tasks from the front end 2308. In at least one embodiment, the processing tasks can include an index of data to be processed, which can include surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2310 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 2308. In at least one embodiment, the front end 2308 can be configured to ensure that the processing array 2312 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0239] In at least one embodiment, each of the one or more instances of parallel processing unit 2302 can be coupled to parallel processor memory 2322. In at least one embodiment, parallel processor memory 2322 can be accessed via memory crossbar 2316, which can receive memory requests from processing array 2312 and I / O unit 2304. In at least one embodiment, memory crossbar 2316 can access parallel processor memory 2322 via memory interface 2318. In at least one embodiment, memory interface 2318 can include multiple partition units (e.g., partition unit 2320A, partition unit 2320B, through partition unit 2320N), which can each be coupled to a portion of parallel processor memory 2322 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 2320A-2320N are configured to be equal to the number of memory cells, such that the first partition unit 2320A has a corresponding first memory cell 2324A, the second partition unit 2320B has a corresponding memory cell 2324B, and the Nth partition unit 2320N has a corresponding Nth memory cell 2324N. In at least one embodiment, the number of partition units 2320A-2320N may not be equal to the number of memory devices.

[0240] In at least one embodiment, memory units 2324A-2324N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 2324A-2324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 2324A-2324N, allowing partition units 2320A-2320N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 2322. In at least one embodiment, local instances of parallel processor memory 2322 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0241] In at least one embodiment, any of the clusters 2314A-2314N of the processing array 2312 can process data to be written to any memory unit 2324A-2324N within the parallel processor memory 2322. In at least one embodiment, the memory crossbar 2316 can be configured to transmit the output of each cluster 2314A-2314N to any partition unit 2320A-2320N or to another cluster 2314A-2314N, which can perform other processing operations on the output. In at least one embodiment, each cluster 2314A-2314N can communicate with a memory interface 2318 via the memory crossbar 2316 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 2316 has connections to memory interface 2318 for communicating with I / O unit 2304, as well as connections to local instances of parallel processor memory 2322, thereby enabling processing units within different processing clusters 2314A-2314N to communicate with system memory or other memory that is not local to parallel processing unit 2302. In at least one embodiment, memory crossbar switch 2316 can use virtual channels to separate traffic flows between clusters 2314A-2314N and partition units 2320A-2320N.

[0242] In at least one embodiment, multiple instances of parallel processing unit 2302 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 2302 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2302 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 2302 or parallel processor 2300 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0243] Figure 23B FIG2 shows a processing cluster 2394 according to at least one embodiment. In at least one embodiment, the processing cluster 2394 is included within a parallel processing unit. In at least one embodiment, the processing cluster 2394 is Figure 23AIn at least one embodiment, a processing cluster 2394 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster 2394.

[0244] In at least one embodiment, the operation of the processing cluster 2394 can be controlled by a pipeline manager 2332 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 2332 Figure 23A The scheduler 2310 receives instructions and manages the execution of these instructions through the graphics multiprocessor 2334 and / or the texture unit 2336. In at least one embodiment, the graphics multiprocessor 2334 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 2394. In at least one embodiment, one or more instances of the graphics multiprocessor 2334 may be included within the processing cluster 2394. In at least one embodiment, the graphics multiprocessor 2334 may process data, and the data crossbar 2340 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2332 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 2340.

[0245] In at least one embodiment, each graphics multiprocessor 2334 within a processing cluster 2394 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0246] In at least one embodiment, instructions transmitted to the processing cluster 2394 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 2334. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop by the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 2334. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 2334, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 2334.

[0247] In at least one embodiment, the graphics multiprocessor 2334 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 2334 can abandon the internal cache and use cache memory within the processing cluster 2394 (e.g., L1 cache 2348). In at least one embodiment, each graphics multiprocessor 2334 can also access a partition unit (e.g., Figure 23A L2 cache within partition units 2320A-2320N) of the graphics multiprocessor 2334 is shared across all processing clusters 2394 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 2334 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2302 can be used as global memory. In at least one embodiment, processing cluster 2394 includes multiple instances of graphics multiprocessor 2334, which can share common instructions and data, which can be stored in L1 cache 2348.

[0248] In at least one embodiment, each processing cluster 2394 may include an MMU 2345 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2345 may reside in Figure 23A2348 or a cache line index.

[0249] In at least one embodiment, the processing clusters 2394 can be configured such that each graphics multiprocessor 2334 is coupled to a texture unit 2336 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2334, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2334 outputs processed tasks to a data crossbar 2340 to provide the processed tasks to another processing cluster 2394 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 2316. In at least one embodiment, a pre-raster operations unit (preROP) 2342 is configured to receive data from the graphics multiprocessor 2334 and direct the data to a ROP unit, which can communicate with a partitioning unit (e.g., a partitioning unit) as described herein. Figure 23A In at least one embodiment, the PreROP 2342 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0250] Figure 23C A graphics multiprocessor 2396 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 2396 is Figure 23B2366. The graphics multiprocessor 2396 is coupled to the pipeline manager 2332 of the processing cluster 2394. In at least one embodiment, the graphics multiprocessor 2396 has an execution pipeline that includes, but is not limited to, an instruction cache 2352, an instruction unit 2354, an address mapping unit 2356, a register file 2358, one or more GPGPU cores 2362, and one or more LSUs 2366. The GPGPU cores 2362 and the LSUs 2366 are coupled to the cache memory 2372 and the shared memory 2370 via a memory and cache interconnect 2368.

[0251] In at least one embodiment, the instruction cache 2352 receives a stream of instructions to be executed from the pipeline manager 2332. In at least one embodiment, the instructions are cached in the instruction cache 2352 and dispatched for execution by the instruction unit 2354. In one embodiment, the instruction unit 2354 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 2362. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 2356 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 2366.

[0252] In at least one embodiment, register file 2358 provides a set of registers for the functional units of graphics multiprocessor 2396. In at least one embodiment, register file 2358 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 2362, LSU 2366) connected to graphics multiprocessor 2396. In at least one embodiment, register file 2358 is divided between each functional unit such that a dedicated portion of register file 2358 is allocated to each functional unit. In at least one embodiment, register file 2358 is divided between the different thread groups being executed by graphics multiprocessor 2396.

[0253] In at least one embodiment, the GPGPU cores 2362 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 2396. The GPGPU cores 2362 may be architecturally similar or the architectures may differ. In at least one embodiment, a first portion of the GPGPU core 2362 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2308 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 2396 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 2362 may also include fixed-function or special-function logic.

[0254] In at least one embodiment, the GPGPU core 2362 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2362 can physically execute SIMD4, SIMD8, and SIMD9 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0255] In at least one embodiment, the memory and cache interconnect 2368 is an interconnect network that connects each functional unit of the graphics multiprocessor 2396 to the register file 2358 and the shared memory 2370. In at least one embodiment, the memory and cache interconnect 2368 is a crossbar interconnect that allows the LSU 2366 to implement load and store operations between the shared memory 2370 and the register file 2358. In at least one embodiment, the register file 2358 can operate at the same frequency as the GPGPU core 2362, resulting in very low latency for data transfers between the GPGPU core 2362 and the register file 2358. In at least one embodiment, the shared memory 2370 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2396. In at least one embodiment, the cache memory 2372 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 2336. In at least one embodiment, the shared memory 2370 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 2372, threads executing on GPGPU core 2362 may also programmatically store data in shared memory.

[0256] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0257] In at least one embodiment, Figures 23A-23C One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figures 23A-23COne or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0258] Figure 24 A graphics processor 2400 is shown in accordance with at least one embodiment. In at least one embodiment, graphics processor 2400 includes a ring interconnect 2402, a pipeline front end 2404, a media engine 2437, and graphics cores 2480A-2480N. In at least one embodiment, ring interconnect 2402 couples graphics processor 2400 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2400 is one of many processors integrated within a multi-core processing system.

[0259] In at least one embodiment, the graphics processor 2400 receives batches of commands via a ring interconnect 2402. In at least one embodiment, the input commands are interpreted by a command streamer 2403 in a pipeline front end 2404. In at least one embodiment, the graphics processor 2400 includes scalable execution logic to perform 3D geometry processing and media processing via graphics cores 2480A-2480N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2403 provides the commands to a geometry pipeline 2436. In at least one embodiment, for at least some media processing commands, the command streamer 2403 provides the commands to a video front end 2434, which is coupled to a media engine 2437. In at least one embodiment, the media engine 2437 includes a video quality engine (VQE) 2430 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2433 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2436 and the media engine 2437 each generate execution threads for thread execution resources provided by at least one graphics core 2480A.

[0260] In at least one embodiment, the graphics processor 2400 includes scalable thread execution resources featuring modular graphics cores 2480A-2480N (sometimes referred to as core slices), each of which has multiple sub-cores 2450A-2450N, 2460A-2460N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2400 can have any number of graphics cores 2480A-2480N. In at least one embodiment, the graphics processor 2400 includes a graphics core 2480A having at least a first sub-core 2450A and a second sub-core 2460A. In at least one embodiment, the graphics processor 2400 is a low-power processor having a single sub-core (e.g., 2450A). In at least one embodiment, the graphics processor 2400 includes multiple graphics cores 2480A-2480N, each of which includes a set of first sub-cores 2450A-2450N and a set of second sub-cores 2460A-2460N. In at least one embodiment, each of the first sub-cores 2450A-2450N includes at least a first set of execution units (EUs) 2452A-2452N and media / texture samplers 2454A-2454N. In at least one embodiment, each of the second sub-cores 2460A-2460N includes at least a second set of execution units 2462A-2462N and samplers 2464A-2464N. In at least one embodiment, each of the sub-cores 2450A-2450N, 2460A-2460N shares a set of shared resources 2470A-2470N. In at least one embodiment, the shared resources 2470 include a shared cache and pixel operation logic.

[0261] In at least one embodiment, Figure 24 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 24 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0262] Figure 25A processor 2500 is shown for use in accordance with at least one embodiment. In at least one embodiment, the processor 2500 may include, but is not limited to, logic circuitry for executing instructions. In at least one embodiment, the processor 2500 may execute instructions including x86 instructions, ARM instructions, specialized instructions for ASICs, and the like. In at least one embodiment, the processor 2510 may include registers for storing packed data, such as the 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. In at least one embodiment, the MMX registers, available in integer and floating-point form, may operate with packed data elements associated with SIMD and Streaming SIMD Extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as "SSEx") technology may store such packed data operands. In at least one embodiment, the processor 2510 may execute instructions to accelerate CUAD programs.

[0263] In at least one embodiment, processor 2500 includes an in-order front end ("Front End") 2501 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, Front End 2501 may include several units. In at least one embodiment, instruction prefetcher 2526 retrieves instructions from memory and provides them to instruction decoder 2528, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2528 decodes received instructions into one or more operations called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") for execution. In at least one embodiment, instruction decoder 2528 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform the operations. In at least one embodiment, trace cache 2530 can assemble the decoded microinstructions into a program-ordered sequence or trace in microinstruction queue 2534 for execution. In at least one embodiment, when trace cache 2530 encounters a complex instruction, microcode ROM 2532 provides the microinstructions necessary to complete the operation.

[0264] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2528 may access the microcode ROM 2532 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2528. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2532. In at least one embodiment, the trace cache 2530 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2532 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2532 completes the micro-op sequencing for the instruction, the front end 2501 of the machine may resume fetching micro-ops from the trace cache 2530.

[0265] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2503 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2503 includes, but is not limited to, an allocator / register renamer 2540, a memory microinstruction queue 2542, an integer / floating-point microinstruction queue 2544, a memory scheduler 2546, a fast scheduler 2502, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2504, and a simple floating-point scheduler ("simple FP scheduler") 2506. In at least one embodiment, the fast scheduler 2502, the slow / general purpose floating-point scheduler 2504, and the simple floating-point scheduler 2506 are also collectively referred to as "microinstruction schedulers 2502, 2504, 2506." The allocator / register renamer 2540 allocates the machine buffers and resources required for each microinstruction to execute in order. In at least one embodiment, the allocator / register renamer 2540 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2540 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2542 for memory operations and an integer / floating point microinstruction queue 2544 for non-memory operations, preceding the memory scheduler 2546 and the microinstruction schedulers 2502, 2504, 2506. In at least one embodiment, the microinstruction schedulers 2502, 2504, 2506 determine when a microinstruction is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2502 of at least one embodiment can schedule on every half of the main clock cycle, while the slow / general floating point scheduler 2504 and the simple floating point scheduler 2506 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2502, 2504, 2506 arbitrate on dispatch ports to schedule microinstructions for execution.

[0266] In at least one embodiment, execution block 2511 includes, but is not limited to, integer register file / branch network 2508, floating point register file / branch network ("FP register file / branch network") 2510, address generation units ("AGUs") 2512 and 2514, fast arithmetic logic units ("fast ALUs") 2516 and 2518, slow ALU 2520, floating point ALU ("FP") 2522, and floating point move unit ("FP move") 2524. In at least one embodiment, integer register file / branch network 2508 and floating point register file / bypass network 2510 are also referred to herein as "register files 2508, 2510." In at least one embodiment, ALUs 2512 and 2514, fast ALUs 2516 and 2518, slow ALU 2520, floating-point ALU 2522, and floating-point move unit 2524 are also referred to herein as "execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524." In at least one embodiment, an execution block may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

[0267] In at least one embodiment, register files 2508 and 2510 may be arranged between microinstruction schedulers 2502, 2504, and 2506 and execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524. In at least one embodiment, integer register file / bypass network 2508 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2510 performs floating-point operations. In at least one embodiment, each of register files 2508 and 2510 may include, but is not limited to, a bypass network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2508 and 2510 can communicate data with each other. In at least one embodiment, integer register file / bypass network 2508 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / bypass network 2510 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0268] In at least one embodiment, execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524 can execute instructions. In at least one embodiment, register files 2508 and 2510 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2500 can include, but is not limited to, any number of execution units 2512, 2514, 2516, 2518, 2520, 2522, and 2524, and combinations thereof. In at least one embodiment, floating-point ALU 2522 and floating-point move unit 2524 can execute floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2522 can include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 2516 and 2518. In at least one embodiment, the fast ALUs 2516 and 2518 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to the slow ALU 2520, as the slow ALU 2520 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by the AGUs 2512 and 2514. In at least one embodiment, the fast ALUs 2516, 2518, and slow ALUs 2520 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALUs 2516, 2518, and slow ALUs 2520 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2522 and floating point shift unit 2524 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2522 and floating point shift unit 2524 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0269] In at least one embodiment, the microinstruction schedulers 2502, 2504, and 2506 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2500, processor 2500 can also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline that temporarily prevent the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0270] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0271] In at least one embodiment, Figure 25 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 25 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0272] Figure 26A processor 2600 is shown in accordance with at least one embodiment. In at least one embodiment, processor 2600 includes, but is not limited to, one or more processor cores ("cores") 2602A-2602N, an integrated memory controller 2614, and an integrated graphics processor 2608. In at least one embodiment, processor 2600 may include additional cores, up to and including the additional processor core 2602N represented by the dashed box. In at least one embodiment, each processor core 2602A-2602N includes one or more internal cache units 2604A-2604N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2606. In at least one embodiment, one or more processor cores 2602A-2602N are referred to as computational units or operational units.

[0273] In at least one embodiment, the internal cache units 2604A-2604N and the shared cache unit 2606 represent a cache memory hierarchy within the processor 2600. In at least one embodiment, the cache memory units 2604A-2604N may include at least one level of instruction and data within each processor core and one or more levels of cache in a shared mid-level cache, such as an L2, L3, level 4 (L4), or other level of cache, with the highest level of cache being categorized as LLC before external memory. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2606 and 2604A-2604N.

[0274] In at least one embodiment, the processor 2600 may also include a set of one or more bus controller units 2616 and a system agent core 2610. In at least one embodiment, the one or more bus controller units 2616 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2610 provides management functions for various processor components. In at least one embodiment, the system agent core 2610 includes one or more integrated memory controllers 2614 to manage access to various external memory devices (not shown).

[0275] In at least one embodiment, one or more processor cores 2602A-2602N include support for simultaneous multithreading. In at least one embodiment, system agent core 2610 includes components for coordinating and operating processor cores 2602A-2602N during multithreaded processing. In at least one embodiment, system agent core 2610 may additionally include a power control unit (PCU) that includes logic and components to regulate one or more power states of processor cores 2602A-2602N and graphics processor 2608.

[0276] In at least one embodiment, processor 2600 further includes a graphics processor 2608 to perform graphics processing operations. In at least one embodiment, graphics processor 2608 is coupled to a shared cache unit 2606 and a system agent core 2610 including one or more integrated memory controllers 2614. In at least one embodiment, system agent core 2610 also includes a display controller 2611 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, display controller 2611 may also be a separate module coupled to graphics processor 2608 via at least one interconnect, or may be integrated within graphics processor 2608.

[0277] In at least one embodiment, a ring-based interconnect 2612 is used to couple the internal components of the processor 2600. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2608 is coupled to the ring interconnect 2612 via I / O links 2613.

[0278] In at least one embodiment, I / O link 2613 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2618 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2602A-2602N and graphics processor 2608 uses embedded memory module 2618 as a shared LLC.

[0279] In at least one embodiment, the processor cores 2602A-2602N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2602A-2602N are heterogeneous in terms of ISA, where one or more processor cores 2602A-2602N execute a common instruction set, while one or more other processor cores 2602A-2602N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2602A-2602N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2600 can be implemented on one or more chips or as a SoC integrated circuit.

[0280] In at least one embodiment, Figure 26 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 26 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0281] Figure 27 A graphics processor core 2700 is shown in accordance with at least one described embodiment. In at least one embodiment, graphics processor core 2700 is included within a graphics core array. In at least one embodiment, graphics processor core 2700 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2700 is an example of a graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2700 can include fixed function blocks 2730 coupled to multiple sub-cores 2701A-2701F, also referred to as sub-slices, which include modular blocks of general purpose and fixed function logic.

[0282] In at least one embodiment, fixed function block 2730 includes a geometry / fixed function pipeline 2736, which may be shared by all sub-cores in graphics processor 2700, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 2736 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0283] In at least one embodiment, fixed function block 2730 also includes a graphics SoC interface 2737, a graphics microcontroller 2738, and a media pipeline 2739. Graphics SoC interface 2737 provides an interface between graphics core 2700 and other processor cores in the SoC integrated circuit system. In at least one embodiment, graphics microcontroller 2738 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2700, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2739 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2739 implements media operations via requests to computational or sampling logic within sub-cores 2701A-2701F.

[0284] In at least one embodiment, the SoC interface 2737 enables the graphics core 2700 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2737 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2700 and the CPU within the SoC. In at least one embodiment, the SoC interface 2737 may also implement power management controls for the graphics core 2700 and enable interfaces between the clock domain of the graphics core 2700 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2737 enables receiving command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2739 when media operations are to be performed, or may be assigned to the geometry and fixed function pipelines (e.g., the geometry and fixed function pipeline 2736, the geometry and fixed function pipeline 2714) when graph processing operations are to be performed.

[0285] In at least one embodiment, the graphics microcontroller 2738 can be configured to perform various scheduling and management tasks for the graphics core 2700. In at least one embodiment, the graphics microcontroller 2738 can perform graph and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2702A-2702F, 2704A-2704F in the sub-cores 2701A-2701F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2700 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2738 may also facilitate a low power or idle state for the graphics core 2700, thereby providing the graphics core 2700 with the ability to save and restore registers across low power state transitions within the graphics core 2700 independent of the operating system and / or graphics driver software on the system.

[0286] In at least one embodiment, graphics core 2700 may have more or fewer sub-cores than the sub-cores 2701A-2701F shown, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core 2700 may also include shared function logic 2710, shared and / or cache memory 2712, geometry / fixed function pipelines 2714, and additional fixed function logic 2716 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2710 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2700. Shared and / or cache memory 2712 may be LLC for the N sub-cores 2701A-2701F within graphics core 2700 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2714 may be included in place of geometry / fixed function pipeline 2736 within fixed function block 2730 and may include the same or similar logic units.

[0287] In at least one embodiment, graphics core 2700 includes additional fixed-function logic 2716, which may include various fixed-function acceleration logic for use by graphics core 2700. In at least one embodiment, additional fixed-function logic 2716 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, a full geometry pipeline and a culling pipeline within geometry / fixed-function pipelines 2716, 2736, which are additional geometry pipelines that may be included in additional fixed-function logic 2716. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2716 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0288] In at least one embodiment, the additional fixed function logic 2716 may also include general purpose processing acceleration logic, such as fixed function matrix multiplication logic, for implementing slowed down CUAD routines.

[0289] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2701A-2701F that can be used to execute graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2701A-2701F includes multiple EU arrays 2702A-2702F, 2704A-2704F, thread dispatch and inter-thread communication (TD / IC) logic 2703A-2703F, 3D (e.g., texture) samplers 2705A-2705F, media samplers 2706A-2706F, shader processors 2707A-2707F, and shared local memory (SLM) 2708A-2708F. Each EU array 2702A-2702F, 2704A-2704F includes multiple execution units, which are GU GPUs capable of servicing graphics, media, or compute operations, executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2703A-2703F performs local thread dispatch and thread control operations for the execution units within the sub-core and facilitates communication between threads executing on the execution units of the sub-core. In at least one embodiment, 3D samplers 2705A-2705F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2706A-2706F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2701A-2701F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2701A-2701F may utilize shared local memory 2708A-2708F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0290] In at least one embodiment, Figure 27 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 27 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0291] Figure 28 A parallel processing unit ("PPU") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, PPU 2800 is configured with machine-readable code that, if executed by PPU 2800, causes PPU 2800 to perform some or all of the processes and techniques described herein. In at least one embodiment, PPU 2800 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by PPU 2800. In at least one embodiment, PPU 2800 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as an LCD device. In at least one embodiment, PPU 2800 is configured to perform computations, such as linear algebra operations and machine learning operations. Figure 28 The example parallel processor is shown for illustrative purposes only and should be construed as a non-limiting example of a processor architecture implemented in at least one embodiment.

[0292] In at least one embodiment, one or more PPUs 2800 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2800 are configured to accelerate CUDA programs. In at least one embodiment, a PPU 2800 includes, but is not limited to, an I / O unit 2806, a front-end unit 2810, a scheduler unit 2812, a work distribution unit 2814, a hub 2816, a crossbar switch ("Xbar") 2820, one or more general processing clusters ("GPCs") 2818, and one or more partitioning units ("memory partitioning units") 2822. In at least one embodiment, a PPU 2800 is connected to a host processor or other PPUs 2800 via one or more high-speed GPU interconnects ("GPU interconnects") 2808. In at least one embodiment, a PPU 2800 is connected to a host processor or other peripheral devices via a system bus or interconnect 2802. In one embodiment, the PPU 2800 is connected to local memory including one or more memory devices ("memory") 2804. In at least one embodiment, the memory devices 2804 include, but are not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, the one or more DRAM devices are configured and / or configurable as a high-bandwidth memory ("HBM") subsystem, with multiple DRAM dies stacked within each device.

[0293] In at least one embodiment, the high-speed GPU interconnect 2808 may refer to a wire-based, multi-lane communication link that a system uses to scale and includes one or more PPUs 2800 ("CPUs") in conjunction with one or more CPUs, supporting cache coherency between the PPU 2800 and the CPUs and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2808 transmits data and / or commands to other units of the PPU 2800, such as one or more copy engines, video encoders, video decoders, power management units, and / or other processors, via a hub 2816. Figure 28 Other components that may not be explicitly shown.

[0294] In at least one embodiment, the I / O unit 2806 is configured to receive data from the host processor ( Figure 282806). In at least one embodiment, the I / O unit 2806 communicates with the host processor directly via the system bus 2802 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2806 can communicate with one or more other processors (e.g., one or more PPUs 2800) via the system bus 2802. In at least one embodiment, the I / O unit 2806 implements a PCIe interface for communicating over the PCIe bus. In at least one embodiment, the I / O unit 2806 implements an interface for communicating with external devices.

[0295] In at least one embodiment, the I / O unit 2806 decodes packets received via the system bus 2802. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2800 to perform various operations. In at least one embodiment, the I / O unit 2806 sends the decoded commands to various other units of the PPU 2800 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2810 and / or to the hub 2816 or other units of the PPU 2800, such as one or more copy engines, video encoders, video decoders, power management units, etc. ( Figure 28 In at least one embodiment, I / O unit 2806 is configured to route communications between the various logical units of PPU 2800.

[0296] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2800 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2800—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2802 via memory requests transmitted via the I / O unit 2806 over the system bus 2802. In at least one embodiment, the host processor writes a command stream into the buffer and then sends a pointer indicating the beginning of the command stream to the PPU 2800, so that the front end unit 2810 receives pointers to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to the various units of the PPU 2800.

[0297] In at least one embodiment, the front end unit 2810 is coupled to a scheduler unit 2812 that configures the various GPCs 2818 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2812 is configured to track state information related to the various tasks managed by the scheduler unit 2812, where the state information may indicate which GPC 2818 the task is assigned to, whether the task is active or inactive, a priority associated with the task, and the like. In at least one embodiment, the scheduler unit 2812 manages multiple tasks that execute on one or more GPCs 2818.

[0298] In at least one embodiment, the scheduler unit 2812 is coupled to a work distribution unit 2814, which is configured to dispatch tasks for execution on the GPCs 2818. In at least one embodiment, the work distribution unit 2814 tracks a plurality of scheduled tasks received from the scheduler unit 2812 and manages a pending task pool and an active task pool for each GPC 2818. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2818; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively being processed by the GPC 2818, such that as a task in a GPC 2818 completes execution, the task is evicted from the active task pool of the GPC 2818, and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2818. In at least one embodiment, if an active task is idle on a GPC 2818, such as while waiting for data dependencies to be resolved, the active task is evicted from the GPC 2818 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on the GPC 2818.

[0299] In at least one embodiment, work distribution unit 2814 communicates with one or more GPCs 2818 via XBar 2820. In at least one embodiment, XBar 2820 is an interconnect network that couples many units of PPU 2800 to other units of PPU 2800 and can be configured to couple work distribution unit 2814 to a specific GPC 2818. In at least one embodiment, one or more other units of PPU 2800 can also be connected to XBar 2820 through hub 2816.

[0300] In at least one embodiment, tasks are managed by a scheduler unit 2812 and assigned to one of the GPCs 2818 by a work distribution unit 2814. The GPC 2818 is configured to process tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2818, routed to a different GPC 2818 via an XBar 2820, or stored in memory 2804. In at least one embodiment, the results can be written to memory 2804 via a partition unit 2822, which implements a memory interface for writing data to or reading data from memory 2804. In at least one embodiment, the results can be transferred to another PPU 2800 or CPU via a high-speed GPU interconnect 2808. In at least one embodiment, the PPU 2800 includes, but is not limited to, U partition units 2822, which equal the number of separate and distinct memory devices 2804 coupled to the PPU 2800.

[0301] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2800. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2800, and the PPU 2800 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2800, and the driver core outputs the tasks to one or more streams processed by the PPU 2800. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for executing tasks and exchanging data through shared memory.

[0302] In at least one embodiment, Figure 28 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 28 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0303] Figure 29 FIG2 shows a GPC 2900 according to at least one embodiment. In at least one embodiment, the GPC 2900 is Figure 28 2818. In at least one embodiment, each GPC 2900 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2900 includes, but is not limited to, a pipeline manager 2902, a pre-raster operations unit ("PROP") 2904, a raster engine 2908, a work distribution crossbar ("WDX") 2916, a memory management unit ("MMU") 2918, one or more data processing clusters ("DPCs") 2906, and any suitable combination of components.

[0304] In at least one embodiment, the operation of the GPC 2900 is controlled by a pipeline manager 2902. In at least one embodiment, the pipeline manager 2902 manages the configuration of one or more DPCs 2906 to process tasks assigned to the GPC 2900. In at least one embodiment, the pipeline manager 2902 configures at least one of the one or more DPCs 2906 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, a DPC 2906 is configured to execute vertex shader programs on a programmable streaming multiprocessor ("SM") 2914. In at least one embodiment, the pipeline manager 2902 is configured to route packets received from a work distribution unit to appropriate logic within the GPC 2900, and in at least one embodiment, some packets may be routed to fixed-function hardware units in the PROP 2904 and / or raster engine 2908, while other packets may be routed to a DPC 2906 for processing by a primitive engine 2912 or an SM 2914. In at least one embodiment, pipeline manager 2902 configures at least one of DPCs 2906 to implement a neural network model and / or a computational pipeline. In at least one embodiment, pipeline manager 2902 configures at least one of DPCs 2906 to execute at least a portion of a CUDA program.

[0305] In at least one embodiment, PROP unit 2904 is configured to route data generated by raster engine 2908 and DPC 2906 to a raster operations ("ROP") unit in a partition unit, such as described above in conjunction with Figure 28Memory partitioning unit 2822, etc., described in more detail. In at least one embodiment, PROP unit 2904 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, raster engine 2908 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2908 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for the primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is passed to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where fragments outside the viewing frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to a fine raster engine to generate properties for the pixel fragments based on a plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2908 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2906).

[0306] In at least one embodiment, each DPC 2906 included in a GPC 2900 includes, but is not limited to, an M-pipeline controller ("MPC") 2910; a primitive engine 2912; one or more SMs 2914; and any suitable combination thereof. In at least one embodiment, the MPC 2910 controls the operation of the DPC 2906, routing packets received from the pipeline manager 2902 to appropriate units within the DPC 2906. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2912, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2914.

[0307] In at least one embodiment, SM 2914 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2914 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2914 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different set of data based on the same instruction set, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. Figure 30 At least one embodiment of SM 2914 is described in more detail.

[0308] In at least one embodiment, the MMU 2918 provides a communication channel between the GPC 2900 and the memory partition unit (e.g., Figure 28 The MMU 2918 provides an interface between the memory and the partition unit 2822, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2918 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0309] In at least one embodiment, Figure 29 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 29 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0310] Figure 30 Streaming Multiprocessor ("SM") 3000 is shown in accordance with at least one embodiment. In at least one embodiment, SM 3000 is Figure 29 SM 2914. In at least one embodiment, SM 3000 includes, but is not limited to, an instruction cache 3002; one or more scheduler units 3004; a register file 3008; one or more processing cores ("cores") 3010; one or more special function units ("SFUs") 3012; one or more load / store units ("LSUs") 3014; an interconnect network 3016; a shared memory / level 1 ("L1") cache 3018; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), with each task being assigned to a specific data processing cluster ("DPC") within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 3000. In at least one embodiment, scheduler unit 3004 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 3000. In at least one embodiment, the scheduler unit 3004 schedules thread blocks for execution as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 3004 manages multiple different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 3010, SFU 3012, and LSU 3014) during each clock cycle. In at least one embodiment, the SM 3000 includes one or more thread block clusters, where thread block clusters can implement local programmatic control at a finer granularity than a single thread block of a single streaming multiprocessor (SM). In at least one embodiment, thread block clusters (also referred to as "clusters") enable multiple thread blocks running concurrently across a streaming multiprocessor to synchronously and cooperatively acquire, exchange, or otherwise use data.

[0311] In at least one embodiment, "cooperative groups" may refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling the expression of richer, more efficient decompositions of parallelism. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, conventional programming model APIs provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., the syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide function interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block and multi-block granularity and perform collective operations, such as synchronizing threads within a cooperative group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, allowing libraries and utility functions to safely synchronize within their local environment without making assumptions about convergence. In at least one embodiment, the cooperation group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks.

[0312] In at least one embodiment, the dispatch unit 3006 is configured to send instructions to one or more of the functional units, and the scheduler unit 3004 includes, but is not limited to, two dispatch units 3006 that enable two different instructions from the same warp to be dispatched per clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0313] In at least one embodiment, each SM 3000 includes, but is not limited to, a register file 3008 that provides a set of registers for the functional units of SM 3000. In at least one embodiment, register file 3008 is partitioned between each functional unit, allocating a dedicated portion of register file 3008 to each functional unit. In at least one embodiment, register file 3008 is partitioned between the different warps executed by SM 3000, and register file 3008 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM 3000 includes, but is not limited to, a plurality of L processing cores 3010. In at least one embodiment, SM 3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3010. In at least one embodiment, each processing core 3010 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3010 includes, but is not limited to, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0314] In at least one embodiment, the tensor cores are configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 3010. In at least one embodiment, the tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0315] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the accumulation matrices C and D are 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the tensor core performs a 32-bit floating-point accumulation operation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA-C++ API) exposes specialized matrix load, matrix multiplication and accumulation, and matrix store operations to efficiently use the tensor cores from a CUDA-C++ program. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16×16 matrix size across all 32 warp threads.

[0316] In at least one embodiment, each SM 3000 includes, but is not limited to, M SFUs 3012 that perform specialized functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 3012 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 3012 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texels) from memory and sample the texture maps to generate sampled texture values ​​for use by shader programs executed by the SM 3000. In at least one embodiment, the texture maps are stored in shared memory / L1 cache 3018. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM 3000 includes, but is not limited to, two texture units.

[0317] In at least one embodiment, each SM 3000 includes, but is not limited to, N LSUs 3014 that implement load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM 3000 includes, but is not limited to, an interconnection network 3016 that connects each functional unit to the register file 3008, and the LSUs 3014 connect to the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnection network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3008, and to connect the LSUs 3014 to memory locations in the register file 3008 and the shared memory / L1 cache 3018.

[0318] In at least one embodiment, shared memory / L1 cache 3018 is an array of on-chip memory that, in at least one embodiment, allows for data storage and communication between the SM 3000 and the primitive engines, as well as between threads within the SM 3000. In at least one embodiment, shared memory / L1 cache 3018 includes, but is not limited to, 128KB of storage capacity and is located in the path from the SM 3000 to the partition unit. In at least one embodiment, shared memory / L1 cache 3018 is used, in at least one embodiment, to cache reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 3018, L2 cache, and memory is a backing store.

[0319] In at least one embodiment, data cache and shared memory functionality are combined into a single memory block, providing improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use the shared memory or as a cache. For example, if the shared memory is configured to use half of its capacity, texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to function as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, when configured for general-purpose parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function GPU is bypassed, creating a simpler programming model. In at least one embodiment, in a general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 3000 to execute the program and perform computations, use shared memory / L1 cache 3018 to communicate between threads, and use LSU 3014 to read and write global memory through shared memory / L1 cache 3018 and a memory partitioning unit. In at least one embodiment, when configured for general-purpose parallel computation, SM 3000 writes commands to scheduler unit 3004 that can be used to start new work on a DPC. In at least one embodiment, SM 3000 includes one or more distributed shared memories (or distributed shared memories) that enable direct SM-to-SM operations, such as load, store, and execute atomic operations, of memory blocks shared across multiple SMs.

[0320] In at least one embodiment, the SM 3000 includes one or more asynchronous execution functions, including a Tensor Memory Accelerator (TMA) unit that can transfer data blocks between global memory and shared memory. In at least one embodiment, one or more processors use or access one or more TMAs to perform bidirectional copy operations, such as from global memory to shared memory and vice versa. In at least one embodiment, the SM 3000 includes one or more TMAs for asynchronously copying between thread blocks in the cluster. In at least one embodiment, the SM 3000 includes one or more asynchronous transaction barriers for performing atomic data movement and synchronization. In at least one embodiment, the SM 3000 includes a Tensor Core Converter Engine, which includes software and one or more cores for accelerating converter model training and inference. In at least one embodiment, one or more processor cores executing one or more Tensor Core Converter Engines manage and dynamically select between FP8 and 16-bit computations by recasting and scaling between FP8 and 16-bit in each layer of one or more neural networks.

[0321] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a RISC CPU, an MMU, a digital-to-analog converter ("DAC"), etc.).

[0322] In at least one embodiment, the PPU can be included on a graphics card that includes one or more storage devices. The graphics card can be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU can be an integrated GPU ("iGPU") included in a chipset on the motherboard.

[0323] In at least one embodiment, Figure 30 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 30 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0324] Software Construction for General Computing

[0325] The following figures illustrate, but are not limited to, exemplary software architectures for implementing at least one embodiment.

[0326] Figure 31 A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL or IntelOneAPI.

[0327] In at least one embodiment, the programming platform's software stack 3100 provides an execution environment for applications 3101. In at least one embodiment, applications 3101 may include any computer software capable of being launched on the software stack 3100. In at least one embodiment, applications 3101 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0328] In at least one embodiment, the application 3101 and software stack 3100 run on hardware 3107. In at least one embodiment, the hardware 3107 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support a programming platform. In at least one embodiment, for example, using CUDA, the software stack 3100 may be vendor-specific and only compatible with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, the software stack 3100 can be used with devices from different vendors. In at least one embodiment, the hardware 3107 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within the hardware 3107, which may include but is not limited to a CPU (but may also include a computing device) and its memory, the devices within the hardware 3107 may include but are not limited to a GPU, FPGA, AI engine, or other computing device (but may also include a CPU) and its memory.

[0329] In at least one embodiment, the programming platform's software stack 3100 includes, but is not limited to, multiple libraries 3103, a runtime 3105, and device kernel drivers 3106. In at least one embodiment, each of the libraries 3103 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 3103 may include, but are not limited to, prewritten code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 3103 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 3103 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 2903 are associated with corresponding APIs 3102, which may include one or more APIs that expose the functions implemented in the libraries 3103. In at least one embodiment, a processor (e.g., a CPU, a GPU) executes, calls, or otherwise uses one or more APIs to prioritize kernels. For example, a first kernel (e.g., a parent kernel) can launch a second kernel (e.g., a child kernel), and the second kernel can be used by the processor to launch an additional kernel (e.g., a grandchild kernel) independent of the first kernel. In at least one embodiment, the processor executes an API or calls an API to be executed from memory to support dynamic stream priorities (e.g., updating priorities as streams are used to perform operations). For example, when the processor executes the API, it allows a programmer to copy stream priorities from one stream to one or more other streams.

[0330] In at least one embodiment, the software stack 3100 includes an API to support dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows a programmer to set the priority of a stream at any time after creation. In at least one embodiment, the software stack 3100 includes an API to support dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows a programmer to obtain the current priority of a stream, where the priority is one of multiple attributes of a stream. In at least one embodiment, the software stack 3100 includes an API to support dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows a programmer to obtain the current priority of a stream as a single attribute. In at least one embodiment, the software stack 3100 includes an API to support dynamic stream priorities (e.g., updating the priority when a stream is used to perform an operation), which allows a programmer to launch the kernel to perform an operation on a stream at a set priority (which may be different from the stream priority). In at least one embodiment, the software stack 3100 includes an API that indicates whether an object (e.g., a thread synchronization object such as a barrier) that tracks whether all data movement operations for a set of threads operating on the GPU complete with a specified state after a specified time period, where the specified state can be a state indicating that the data has been moved and is ready for use, and is specified using an expected parity value as input to the API.

[0331] In at least one embodiment, the software stack 3100 includes one or more APIs for updating the kernel. In at least one embodiment, the processor executes the API or calls the API to be executed from the memory to update to the existing API to support context-free kernels, which allows the programmer to add kernel nodes to the graph without a graphics context so that the graphics context can be dynamically associated with the kernel at runtime. In at least one embodiment, the software stack 3100 includes one or more APIs for allowing the programmer to obtain the kernel identifier and the graphics context as separate parameters from the kernel node, thereby obtaining parameters from the kernel and the context-free kernel. In at least one embodiment, the software stack 3100 includes one or more APIs for launching a task graph (e.g., a task graph) and executing one or more task graphs (e.g., including one or more programs) using a parallel processor (such as, one or more graphics processing units).

[0332] In at least one embodiment, the software stack 3100 includes one or more APIs for associating one or more instructions with one or more memory ordering operations (e.g., fence or bank operations). In at least one embodiment, instructions are associated with one or more domains so that memory ordering operations are performed in association with one or more specific domains without interfering with instructions from other domains. The software stack 3100 includes an API for indicating that a thread has reached (e.g., at a thread synchronization barrier) or has completed a phase of work associated with an asynchronous data movement operation on the GPU. In at least one embodiment, the software stack 3100 includes one or more APIs for allowing a programmer to manually indicate an expected transaction count when a thread has completed a phase of work, which count is used to update an object that tracks whether all data movement operations for a group of threads are complete.

[0333] In at least one embodiment, the application 3101 is written as source code that is compiled into executable code as follows: Figures 36-38 3101. In at least one embodiment, the executable code of application 3101 can run at least in part on an execution environment provided by software stack 3100. In at least one embodiment, during the execution of application 3101, code that needs to run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 3105 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 3105 can include any technically feasible runtime system capable of supporting the execution of application 3101.

[0334] In at least one embodiment, runtime 3105 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 3104). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0335] In at least one embodiment, the runtime library and corresponding API 3104 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0336] In at least one embodiment, one or more processors disclosed in the "processing system" may execute, access, or otherwise use the software stack 3100. For example, the APU 1800, the CPU 1900, Figures 21A-21B The exemplary graphics processor, general-purpose graphics processing unit (“GPGPU”) 2230, parallel processor 2300, processing cluster 2394, graphics multiprocessor 2334, graphics multiprocessor 2396, graphics processor 2400, processor 2500, processor 2600, parallel processing unit (“PPU”) 2800, GPC 2900 and / or streaming multiprocessor (“SM”) 3000 in the software stack 3100 can execute, use, call or otherwise implement (e.g., by accessing memory) one or more APIs included in the software stack 3100.

[0337] In at least one embodiment, the device kernel driver 3106 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 3106 can provide APIs such as API 3104 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 3106 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3106 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without requiring the device kernel driver 3106 to compile the IR code at runtime.

[0338] In at least one embodiment, Figure 31One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 31 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0339] Figure 32 According to at least one embodiment, Figure 31 3201. In at least one embodiment, the CUDA software stack 3200, on which the application 3201 can be launched, includes a CUDA library 3203, a CUDA runtime 3205, a CUDA driver 3207, and a device kernel driver 3208. In at least one embodiment, the CUDA software stack 3200 executes on hardware 3209, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0340] In at least one embodiment, the application 3201, the CUDA runtime 3205, and the device kernel driver 3208 can perform similar functions as the application 3101, the runtime 3105, and the device kernel driver 3106, respectively. Figure 313206 . In at least one embodiment, the CUDA driver 3207 includes a library (libcuda.so) that implements the CUDA driver API 3206. In at least one embodiment, similar to the CUDA runtime API 3204 implemented by the CUDA runtime library (cudart), the CUDA driver API 3206 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3206 differs from the CUDA runtime API 3204 in that the CUDA runtime API 3204 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3204, in at least one embodiment, the CUDA driver API 3206 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3206 may expose functions for context management that are not exposed by the CUDA runtime API 3204. In at least one embodiment, the CUDA driver API 3206 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 3204. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 3205, can be considered separate from the driver components, including the user-mode CUDA driver 3207 and the kernel-mode device driver 3208 (sometimes also referred to as a "display" driver).

[0341] In at least one embodiment, the CUDA libraries 3203 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 3201). In at least one embodiment, the CUDA libraries 3203 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers. In at least one embodiment, the CUDA libraries 3203 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference.

[0342] In at least one embodiment, Figure 32One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 32 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0343] Figure 33 According to at least one embodiment, Figure 31 3300 . In at least one embodiment, the ROCm software stack 3300 , on which an application 3301 can be launched, includes a language runtime 3303 , a system runtime 3305 , thunks 3307 , and a ROCm kernel driver 3308 . In at least one embodiment, the ROCm software stack 3300 executes on hardware 3309 , which may include a ROCm-enabled GPU developed by AMD, Inc. of Santa Clara, California.

[0344] In at least one embodiment, application 3301 may execute a combination of the above Figure 31 In addition, in at least one embodiment, the language runtime 3303 and the system runtime 3305 can perform functions similar to those described above in conjunction with the application 3101. Figure 31The language runtime 3303 and the system runtime 3305 have similar functionality to the runtime 3105 discussed above. In at least one embodiment, the language runtime 3303 differs from the system runtime 3305 in that the system runtime 3305 is a language-agnostic runtime that implements the ROCr system runtime API 3304 and leverages the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3305, the language runtime 3303 is an implementation of a language-specific runtime API 3302 layered on top of the ROCr system runtime API 3304. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 32 Similar functions to the CUDA runtime API 3204 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0345] In at least one embodiment, thunk (ROCt) 3307 is an interface that can be used to interact with the underlying ROCm driver 3308. In at least one embodiment, the ROCm driver 3308 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 31 The HSA kernel driver 3106 may function similarly to the discussed device kernel driver 3106. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0346] In at least one embodiment, Figure 33 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 33One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0347] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3300 above the language runtime 3303 and provide Figure 32 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDAcuBLAS, a rocFFT library similar to CUDAcuFFT for computing FFTs, and the like.

[0348] Figure 34 According to at least one embodiment, Figure 31 3400. In at least one embodiment, the OpenCL software stack 3400, on which an application 3401 can be launched, includes an OpenCL framework 3410, an OpenCL runtime 3406, and a driver 3407. In at least one embodiment, the OpenCL software stack 3400 executes on hardware 3209 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0349] In at least one embodiment, the application 3401, the OpenCL runtime 3406, the device kernel driver 3407 and the hardware 3408 can each execute in conjunction with the above Figure 31 Similar functionality is discussed for application 3101, runtime 3105, device kernel driver 3106, and hardware 3107. In at least one embodiment, application 3401 also includes an OpenCL kernel 3402 having code to be executed on the device.

[0350] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 3403 and runtime API 3405. In at least one embodiment, runtime API 3405 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 3405 can use to manage the device's command queue, program and kernel objects, shared memory objects, and the like. In at least one embodiment, platform API 3403 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. Additionally, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, and the like.

[0351] In at least one embodiment, a compiler 3404 is also included in the OpenCL framework 3410. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the application. In contrast to CUDA and ROCm, OpenCL applications in at least one embodiment can be compiled online by compiler 3404, which is included to represent any number of compilers that can be used to compile source code and / or IR code (e.g., Standard Portable Intermediate Representation ("SPIR-V") code) into binary code. Alternatively, in at least one embodiment, OpenCL applications can be compiled offline before executing such applications.

[0352] In at least one embodiment, Figure 34 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 34 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0353] Figure 35Software supported by a programming platform according to at least one embodiment is shown. In at least one embodiment, programming platform 3504 is configured to support various programming models 3503, middleware and / or libraries 3502, and frameworks 3501 that applications 3500 can rely on. In at least one embodiment, application 3500 can be an AI / ML application implemented using, for example, a deep learning framework (e.g., MXNet, PyTorch, or TensorFlow), which can rely on libraries such as cuDNN, NVIDIA Collective Communications Library ("NCCL"), and / or NVIDIA Developer Data Loading Library ("DALI") CUDA libraries to provide accelerated computation on the underlying hardware.

[0354] In at least one embodiment, the programming platform 3504 can be a combination of the above Figure 32 、 Figure 33 and Figure 34 In at least one embodiment, the programming platform 3504 supports one of the CUDA, ROCm, or OpenCL platforms described herein. In at least one embodiment, the programming platform 3504 supports multiple programming models 3503, which are abstractions of the underlying computing system that allow the expression of algorithms and data structures. In at least one embodiment, the programming model 3503 can expose features of the underlying hardware to improve performance. In at least one embodiment, the programming model 3503 can include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multiprocessing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute (VulcanCompute).

[0355] In at least one embodiment, the library and / or middleware 3502 provides an abstract implementation of the programming model 3504. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, in addition to those that can be obtained from the programming platform 3504, such middleware also includes software that provides services to the application. In at least one embodiment, the library and / or middleware 3502 may include but is not limited to cuBLAS, cuFFT, cuRAND and other CUDA libraries, or rocBLAS, rocFFT, rocRAND and other ROCm libraries. In addition, in at least one embodiment, the library and / or middleware 3502 may include NCCL and ROCm communication collection libraries ("RCCL") libraries that provide communication routines for GPUs, MIOpen libraries for deep learning acceleration and / or intrinsic libraries for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms.

[0356] In at least one embodiment, application framework 3501 relies on libraries and / or middleware 3502. In at least one embodiment, each application framework 3501 is a software framework for implementing a standard structure for application software. Returning to the AI / ML example discussed above, in at least one embodiment, AI / ML applications can be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or MxNet deep learning framework.

[0357] In at least one embodiment, Figure 35 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 35 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0358] Figure 36 Compiled code is shown in accordance with at least one embodiment to Figures 31-34 In at least one embodiment, compiler 3601 receives source code 3600, which includes both host code and device code. In at least one embodiment, compiler 3601 is configured to convert source code 3600 into host executable code 3602 for execution on the host and device executable code 3603 for execution on the device. In at least one embodiment, source code 3600 can be compiled offline before executing the application, or compiled online during execution of the application. In at least one embodiment, compiler 3601 includes or has access to one or more libraries to identify API call sequences to execute a single fused API, where the single fused API is a combined API of two or more APIs.

[0359] In at least one embodiment, source code 3600 may include code in any programming language supported by compiler 3601, such as C++, C, Fortran, etc. In at least one embodiment, source code 3600 may be included in a single-source file that has a mix of host code and device code and indicates the location of the device code. In at least one embodiment, the single-source file may be a .cu file that includes CUDA code or a .hip.cpp file that includes HIP code. Alternatively, in at least one embodiment, source code 3600 may include multiple source code files rather than a single source file in which the host code and device code are separated.

[0360] In at least one embodiment, compiler 3601 is configured to compile source code 3600 into host executable code 3602 for execution on a host and device executable code 3603 for execution on a device. In at least one embodiment, compiler 3601 performs operations including parsing source code 3600 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment where source code 3600 comprises a single source file, compiler 3601 may separate device code from host code in such a single source file, compile the device code and host code into device executable code 3603 and host executable code 3602, respectively, and link device executable code 3603 and host executable code 3602 together in a single file, as described below with respect to Figure 37 discussed in more detail.

[0361] In at least one embodiment, host executable code 3602 and device executable code 3603 may be in any suitable format, such as binary code and / or IR code. In the case of CUDA, in at least one embodiment, host executable code 3602 may include native object code, while device executable code 3603 may include code in a PTX intermediate representation. In at least one embodiment, in the case of ROCm, both host executable code 3602 and device executable code 3603 may include target binary code.

[0362] In at least one embodiment, Figure 36 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 36 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0363] Figure 37 is compiled code according to at least one embodiment to Figures 31-34 3701 is a more detailed illustration of the execution of the program on one of the programming platforms of FIG. In at least one embodiment, the compiler 3701 is configured to receive the source code 3700, compile the source code 3700, and output an executable file 3710. In at least one embodiment, the source code 3700 is a single source file, such as a .cu file, a .hip.cpp file, or a file in another format, which includes both host code and device code. In at least one embodiment, the compiler 3701 can be, but is not limited to, the NVIDIA CUDA compiler ("NVCC") for compiling CUDA code in .cu files, or the HCC compiler for compiling HIP code in .hip.cpp files.

[0364] In at least one embodiment, compiler 3701 includes a compiler front end 3702, a host compiler 3705, a device compiler 3706, and a linker 3709. In at least one embodiment, compiler front end 3702 is configured to separate device code 3704 from host code 3703 in source code 3700. In at least one embodiment, device code 3704 is compiled by device compiler 3706 into device executable code 3708, which, as described, may include binary code or IR code. In at least one embodiment, host code 3703 is separately compiled by host compiler 3705 into host executable code 3707. In at least one embodiment, for NVCC, host compiler 3705 may be, but is not limited to, a general-purpose C / C++ compiler that outputs native object code, while device compiler 3706 may be, but is not limited to, a Low-Level Virtual Machine ("LLVM")-based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code. In at least one embodiment, for HCC, both the host compiler 3705 and the device compiler 3706 can be, but are not limited to, LLVM-based compilers that output target binary code.

[0365] In at least one embodiment, after source code 3700 is compiled into host executable code 3707 and device executable code 3708, linker 3709 links host and device executable code 3707 and 3708 together in executable file 3710. In at least one embodiment, native object code for the host and PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format for storing object code.

[0366] In at least one embodiment, Figure 37 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 37 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0367] Figure 38 3802. Figure 36 discussed.

[0368] In at least one embodiment, the conversion performed by the conversion tool 3801 is used to port the source code 3800 for execution in an environment different from that on which it was originally intended to run. In at least one embodiment, the conversion tool 3801 may include, but is not limited to, a HIP converter for "hipifying" CUDA code for a CUDA platform into HIP code that can be compiled and executed on a ROCm platform. In at least one embodiment, the conversion of the source code 3800 may include parsing the source code 3800 and converting calls to APIs provided by one programming model (e.g., CUDA) to corresponding calls to APIs provided by another programming model (e.g., HIP), as described below in conjunction with Figures 39A-40 Returning to the example of porting CUDA code, in at least one embodiment, calls to the CUDA runtime API, the CUDA driver API, and / or the CUDA library can be converted to corresponding HIP API calls. In at least one embodiment, the automatic conversion performed by the conversion tool 3801 may sometimes be incomplete, requiring additional manual effort to fully port the source code 3800.

[0369] In at least one embodiment, Figure 38 One or more systems and / or other hardware / software depicted in the foregoing are used to implement, for example, an application programming interface (API) for one or more neural networks having various algorithms, formulas, and processes (e.g., in conjunction with Figure 7 those described herein), and / or otherwise perform the operations described herein. In at least one embodiment, Figure 38 One or more systems depicted in the are used to implement one or more systems and / or processes (e.g., in conjunction with Figure 1-11 those described herein), and / or implement an application programming interface (API) to perform one or more cryptographic operations / functions and / or otherwise perform the operations described herein.

[0370] Configuring GPUs for general computing

[0371] The following figures illustrate, but are not limited to, exemplary architectures for compiling and executing computing source code in accordance with at least one embodiment.

[0372] Figure 39A A system 3900 is shown configured to compile and execute CUDA source code 3910 using different types of processing units in accordance with at least one embodiment. In at least one embodiment, the system 3900 includes, but is not limited to, CUDA source code 3910, a CUDA compiler 3950, a host executable 3970(1), a host executable 3970(2), a CUDA device executable 3984, a CPU 3990, a CUDA-enabled GPU 3994, a GPU 3992, a CUDA to HIP conversion tool 3920, HIP source code 3930, a HIP compiler driver 3940, an HCC 3960, and an HCC device executable 3982.

[0373] In at least one embodiment, CUDA source code 3910 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device can be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3990, GPU 3992, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU 3990.

[0374] In at least one embodiment, CUDA source code 3910 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, global functions 3912, device functions 3914, host functions 3916, and host / device functions 3918 can be intermixed within CUDA source code 3910. In at least one embodiment, each global function 3912 is executable on the device and callable from the host. Thus, in at least one embodiment, one or more of the global functions 3912 can serve as an entry point for the device. In at least one embodiment, each global function 3912 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more global functions 3912 define a kernel that is executable on and callable from a device. In at least one embodiment, the kernel is executed N times (where N is any positive integer) in parallel by N different threads on the device during execution.

[0375] In at least one embodiment, each device function 3914 executes on a device and can only be called from such a device. In at least one embodiment, each host function 3916 executes on a host and can only be called from such a host. In at least one embodiment, each host / device function 3916 defines both a host version of the function that is executable on the host and can only be called from such a host, and a device version of the function that is executable on a device and can only be called from such a device.

[0376] In at least one embodiment, CUDA source code 3910 may also include, but is not limited to, any number of calls to any number of functions defined by the CUDA Runtime API 3902. In at least one embodiment, the CUDA Runtime API 3902 may include, but is not limited to, any number of functions executed on the host for allocating and deallocating device memory, transferring data between host and device memory, managing systems with multiple devices, and the like. In at least one embodiment, CUDA source code 3910 may also include, but is not limited to, any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API may be any API designed for use by CUDA code. In at least one embodiment, CUDA APIs include, but are not limited to, the CUDA Runtime API 3902, the CUDA Driver API, APIs for any number of CUDA libraries, and the like. In at least one embodiment, and relative to the CUDA Runtime API 3902, the CUDA Driver API is a lower-level API that provides finer-grained control over the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, and the like.

[0377] In at least one embodiment, the CUDA compiler 3950 compiles input CUDA code (e.g., CUDA source code 3910) to generate host executable code 3970(1) and CUDA device executable code 3984. In at least one embodiment, the CUDA compiler 3950 is NVCC. In at least one embodiment, the host executable code 3970(1) is a compiled version of the host code included in the input source code that is executable on the CPU 3990. In at least one embodiment, the CPU 3990 can be any processor optimized for sequential instruction processing.

[0378] In at least one embodiment, the CUDA device executable code 3984 is a compiled version of the device code included in the input source code that is executable on the CUDA-enabled GPU 3994. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, IR code, such as PTX code, which is further compiled by a device driver at runtime into binary code for a specific target device (e.g., a CUDA-enabled GPU 3994). In at least one embodiment, the CUDA-enabled GPU 3994 can be any processor optimized for parallel instruction processing and that supports CUDA. In at least one embodiment, the CUDA-enabled GPU 3994 was developed by NVIDIA Corporation of Santa Clara, California.

[0379] In at least one embodiment, the CUDA to HIP conversion tool 3920 is configured to convert CUDA source code 3910 into functionally similar HIP source code 3930. In at least one embodiment, the HIP source code 3930 is a collection of human-readable code in the HIP programming language. In at least one embodiment, the HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language and includes, but is not limited to, a functionally similar version of the CUDA mechanisms for defining device code and distinguishing between device code and host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, the HIP programming language includes, but is not limited to, mechanisms for defining global functions 3912. However, such a HIP programming language may lack support for dynamic parallelism, and therefore, global functions 3912 defined in the HIP code are only callable from the host.

[0380] In at least one embodiment, HIP source code 3930 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916, and any number (including zero) of host / device functions 3918. In at least one embodiment, HIP source code 3930 may also include any number of calls to any number of functions specified in the HIP runtime API 3932. In one embodiment, the HIP runtime API 3932 includes, but is not limited to, functionally similar versions of a subset of the functions included in the CUDA runtime API 3902. In at least one embodiment, HIP source code 3930 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API may be any API designed for use by HIP code and / or ROCm. In at least one embodiment, a HIP API includes, but is not limited to, the HIP runtime API 3932, a HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and the like.

[0381] In at least one embodiment, the CUDA to HIP conversion tool 3920 converts each kernel call in the CUDA code from CUDA syntax to HIP syntax and converts any number of other CUDA calls in the CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA to HIP conversion tool 3920 converts any number of calls to functions specified in the CUDA runtime API 3902 to any number of calls to functions specified in the HIP runtime API 3932.

[0382] In at least one embodiment, the CUDA to HIP conversion tool 3920 is a tool called hipify-perl, which performs a text-based conversion process. In at least one embodiment, the CUDA to HIP conversion tool 3920 is a tool called hipify-clang, which performs a more complex and robust conversion process than hipify-perl, which involves parsing the CUDA code using clang (a compiler front end) and then converting the resulting symbols. In at least one embodiment, in addition to those modifications performed by the CUDA to HIP conversion tool 3920, correctly converting the CUDA code to HIP code may require modifications (e.g., manual editing).

[0383] In at least one embodiment, HIP compiler driver 3940 is a front end that determines target device 3946 and then configures a compiler compatible with target device 3946 to compile HIP source code 3930. In at least one embodiment, target device 3946 is a processor optimized for parallel instruction processing. In at least one embodiment, HIP compiler driver 3940 can determine target device 3946 in any technically feasible manner.

[0384] In at least one embodiment, if the target device 3946 is CUDA compatible (e.g., a CUDA-enabled GPU 3994), the HIP compiler driver 3940 generates HIP / NVCC compile commands 3942. In at least one embodiment and in conjunction with Figure 39B As described in more detail, HIP / NVCC compile command 3942 configures CUDA compiler 3950 to use, but not limited to, HIP to CUDA translation headers and CUDA runtime libraries to compile HIP source code 3930. In at least one embodiment and in response to HIP / NVCC compile command 3942, CUDA compiler 3950 generates host executable code 3970(1) and CUDA device executable code 3984.

[0385] In at least one embodiment, if the target device 3946 is not CUDA compatible, the HIP compiler driver 3940 generates HIP / HCC compilation commands 3944. In at least one embodiment and as in conjunction with Figure 39C As described in more detail, HIP / HCC compile command 3944 configures HCC 3960 to compile HIP source code 3930 using the HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3944, HCC 3960 generates host executable code 3970(2) and HCC device executable code 3982. In at least one embodiment, HCC device executable code 3982 is a compiled version of the device code contained in HIP source code 3930 that can be executed on GPU 3992. In at least one embodiment, GPU 3992 can be any processor optimized for parallel instruction processing that is not CUDA-compatible and is compatible with HCC. In at least one embodiment, GPU 3992 is developed by AMD, Inc. of Santa Clara, California. In at least one embodiment, GPU 3992 is a non-CUDA-enabled GPU 3992.

[0386] For illustrative purposes only, Figure 39A39. In at least one embodiment, three different flows that can be implemented to compile CUDA source code 3910 for execution on a CPU 3990 and different devices are depicted. In at least one embodiment, the direct CUDA flow compiles CUDA source code 3910 for execution on the CPU 3990 and a CUDA-enabled GPU 3994 without converting the CUDA source code 3910 into HIP source code 3930. In at least one embodiment, the indirect CUDA flow converts CUDA source code 3910 into HIP source code 3930 and then compiles the HIP source code 3930 for execution on the CPU 3990 and a CUDA-enabled GPU 3994. In at least one embodiment, the CUDA / HCC flow converts CUDA source code 3910 into HIP source code 3930 and then compiles the HIP source code 3930 for execution on the CPU 3990 and a GPU 3992.

[0387] A direct CUDA flow that can be implemented in at least one embodiment can be depicted by a dashed line and a series of bubble annotations A1-A3. In at least one embodiment, and as indicated by bubble annotation A1, a CUDA compiler 3950 receives a CUDA source code 3910 and a CUDA compile command 3948 that configures the CUDA compiler 3950 to compile the CUDA source code 3910. In at least one embodiment, the CUDA source code 3910 used in the direct CUDA flow is written in the CUDA programming language, which is based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3948, the CUDA compiler 3950 generates a host executable code 3970 (1) and a CUDA device executable code 3984 (indicated by bubble annotation A2). In at least one embodiment and as indicated by bubble annotation A3, the host executable code 3970 (1) and the CUDA device executable code 3984 can be executed on a CPU 3990 and a CUDA-enabled GPU 3994, respectively. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0388] The indirect CUDA flow that can be implemented in at least one embodiment can be depicted by the dashed line and a series of bubble notes B1-B6. In at least one embodiment and as indicated by bubble note B1, a CUDA to HIP conversion tool 3920 receives CUDA source code 3910. In at least one embodiment and as indicated by bubble note B2, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 into HIP source code 3930. In at least one embodiment and as indicated by bubble note B3, a HIP compiler driver 3940 receives the HIP source code 3930 and determines whether the target device 3946 is CUDA-enabled.

[0389] In at least one embodiment and as indicated by bubble note B4, the HIP compiler driver 3940 generates HIP / NVCC compile commands 3942 and sends both the HIP / NVCC compile commands 3942 and the HIP source code 3930 to the CUDA compiler 3950. Figure 39B As described in more detail, the HIP / NVCC compile command 3942 configures the CUDA compiler 3950 to compile the HIP source code 3930 using, but not limited to, the HIP to CUDA translation header and the CUDA runtime library. In at least one embodiment and in response to the HIP / NVCC compile command 3942, the CUDA compiler 3950 generates a host executable code 3970 (1) and a CUDA device executable code 3984 (indicated by bubble note B5). In at least one embodiment and as indicated by bubble note B6, the host executable code 3970 (1) and the CUDA device executable code 3984 can be executed on a CPU 3990 and a CUDA-enabled GPU 3994, respectively. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3984 includes, but is not limited to, PTX code and is further compiled into binary code for a specific target device at runtime.

[0390] The CUDA / HCC process that can be implemented in at least one embodiment can be described by a solid line and a series of bubble comments C1-C6. In at least one embodiment and as indicated by bubble comment C1, a CUDA to HIP conversion tool 3920 receives CUDA source code 3910. In at least one embodiment and as indicated by bubble comment C2, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 into HIP source code 3930. In at least one embodiment and as indicated by bubble comment C3, a HIP compiler driver 3940 receives the HIP source code 3930 and determines that the target device 3946 is not CUDA-enabled.

[0391] In at least one embodiment, the HIP compiler driver 3940 generates HIP / HCC compile commands 3944 and sends both the HIP / HCC compile commands 3944 and the HIP source code 3930 to the HCC 3960 (indicated by bubble comment C4). Figure 39C As described in more detail, HIP / HCC compile command 3964 configures HCC 3960 to compile HIP source code 3930 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment and in response to HIP / HCC compile command 3944, HCC 3960 generates host executable code 3970(2) and HCC device executable code 3982 (indicated by bubble comment C5). In at least one embodiment and as indicated by bubble comment C6, host executable code 3970(2) and HCC device executable code 3982 can be executed on CPU 3990 and GPU 3992, respectively.

[0392] In at least one embodiment, after converting the CUDA source code 3910 to the HIP source code 3930, the HIP compiler driver 3940 can then be used to generate executable code for the CUDA-enabled GPU 3994 or GPU 3992 without having to re-implement the CUDA to HIP conversion tool 3920. In at least one embodiment, the CUDA to HIP conversion tool 3920 converts the CUDA source code 3910 to the HIP source code 3930, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3940 then configures the HCC 3960 to generate a host executable code 3970 (2) and an HCC device executable code 3982 based on the HIP source code 3930. In at least one embodiment, the HIP compiler driver 3940 then configures the CUDA compiler 3950 to generate a host executable code 3970 (1) and a CUDA device executable code 3984 based on the stored HIP source code 3930.

[0393] Figure 39B 3990 and a CUDA-enabled GPU 3994 configured to compile and execute Figure 39A In at least one embodiment, the system 3904 includes, but is not limited to, CUDA source code 3910, a CUDA to HIP conversion tool 3920, HIP source code 3930, a HIP compiler driver 3940, a CUDA compiler 3950, a host executable 3970(1), a CUDA device executable 3984, a CPU 3990, and a CUDA-enabled GPU 3994.

[0394] In at least one embodiment and as previously incorporated herein Figure 39A As depicted, CUDA source code 3910 includes, but is not limited to, any number (including zero) of global functions 3912, any number (including zero) of device functions 3914, any number (including zero) of host functions 3916,...

Claims

1. A processor, comprising: One or more circuits for executing an application programming interface (API) to enable decryption of encrypted information based at least in part on one or more encryption algorithm indicators. 2 . The processor of claim 1 , wherein the one or more encryption algorithm indicators are used to identify one or more salts. 3 . The processor of claim 1 , wherein executing the API further causes a mapping of encryption algorithm identifiers to salts to be generated. 4 . The processor of claim 1 , wherein the one or more encryption algorithm indicators comprise one or more opaque identifiers associated with one or more encryption algorithms. 5 . The processor of claim 1 , wherein the one or more encryption algorithm indicators identify one or more salts that can be used to decrypt the encrypted information.

6. The processor of claim 1, wherein the one or more encryption algorithm indicators identify cryptographic information that can be used to decrypt the encrypted information to provide information, and wherein the cryptographic information is inaccessible outside of software using the information.

7. The processor of claim 1 , wherein executing the API causes the encrypted information to be decrypted to provide decrypted information, whereby to decrypt the encrypted information, at least both cryptographic information accessible to a user and cryptographic information inaccessible outside of software using the decrypted information are used.

8. The processor of claim 1, wherein executing the API further causes decryption of the encrypted information using at least both a user's key and the encryption algorithm identified by the one or more encryption algorithm indicators.

9. A method comprising: An application programming interface (API) is executed to cause information to be decrypted based at least in part on the one or more encryption algorithm indicators.

10. The method of claim 9, wherein the one or more encryption algorithm indicators are used to identify one or more salts.

11. The method of claim 9, wherein executing the API further causes a mapping of encryption algorithm identifiers to salts to be generated.

12. The method of claim 9, wherein the one or more encryption algorithm indicators comprise one or more opaque identifiers associated with one or more encryption algorithms.

13. The method of claim 9, wherein the one or more encryption algorithm indicators identify one or more salts that can be used to decrypt the information.

14. The method of claim 9, wherein the one or more encryption algorithm indicators identify cryptographic information that can be used to decrypt the encrypted information to provide decrypted information, and wherein the cryptographic information is inaccessible outside of software using the information.

15. A system comprising: One or more processors for executing an application programming interface (API) to enable decryption of information based at least in part on one or more encryption algorithm indicators.

16. The system of claim 15, wherein the one or more encryption algorithm indicators are used to identify one or more salts.

17. The system of claim 15, wherein executing the API further causes a mapping of encryption algorithm identifiers to salts to be generated.

18. The system of claim 15, wherein the one or more encryption algorithm indicators comprise one or more opaque identifiers associated with one or more encryption algorithms.

19. The system of claim 15, wherein the one or more encryption algorithm indicators identify one or more salts that can be used to decrypt the information.

20. The system of claim 15, wherein executing the API causes the information to be decrypted, whereby at least both cryptographic information accessible to the user and cryptographic information inaccessible outside of the software are used to decrypt the information.

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