Semiconductor test data transmission method and device and semiconductor test equipment

Abstract

The invention is suitable for the technical field of semiconductor testing, and provides a semiconductor test data transmission method and device and semiconductor test equipment. The semiconductor test data transmission method comprises the following steps: receiving test response data; splicing the test response data with the remaining test response data reserved in the previous clock period, and if the bit number of the spliced data is smaller than the bit width of the output data, performing zero padding to obtain intermediate data; according to a preset output data bit width, fixed-width cutting is carried out on the intermediate data, and output data used for current transmission and updated remaining test response data are obtained; and outputting the output data for the current transmission. According to the scheme, the test response data and the remaining test response data are spliced, cut and output, low-delay bit width conversion and protocol adaptation of the test response data in the semiconductor test process are achieved, and then the test efficiency and test reliability of semiconductor test equipment are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing technology, and in particular relates to a semiconductor test data transmission method, device and semiconductor testing equipment. Background Art

[0002] With the continuous development of information technology, especially its growing applications in fields such as communications, artificial intelligence, image processing, and embedded systems, the functions of system modules are becoming increasingly complex, and the demand for data exchange between different modules is constantly increasing. In system architectures such as SoC (System on Chip), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or ATE (Automatic Test Equipment), multiple functional modules often transmit data via internal buses or streaming interfaces.

[0003] For example, when testing chips, ATE systems typically need to perform high-speed data communication verification on the chip's interface, including data acquisition, protocol verification, functional testing, and timing testing. The test data format often suffers from bit-width mismatches due to varying chip interface widths. For example, the internal test bus used by the ATE equipment itself typically has a fixed bit width (e.g., 64bit / 128bit), but the chip under test (DUT) may use a different I / O bit width (e.g., 8bit, 12bit, 20bit, etc.). If this bit-width mismatch is not addressed, direct communication will result in data truncation, misalignment, or even communication failure, which in turn will cause the ATE system to fail to perform high-speed communication verification on the chip's interface, reducing reliability and test efficiency. Summary of the Invention

[0004] In view of this, an embodiment of the present application provides a semiconductor test data transmission method, which realizes low-latency bit width conversion and protocol adaptation of test response data during semiconductor testing by splicing test response data with remaining test response data and cropping and outputting them, thereby improving the test efficiency and test reliability of semiconductor testing equipment.

[0005] A first aspect of an embodiment of the present application provides a semiconductor test data transmission method, the semiconductor test data transmission method comprising:

[0006] receiving test response data from the device under test;

[0007] Splicing the test response data with the remaining test response data retained in the previous clock cycle, and if the number of bits of the spliced ​​data is less than the output data bit width, padding with zeros to obtain intermediate data;

[0008] According to the preset output data bit width, the intermediate data is clipped to a fixed width to obtain the output data for this transmission and the remaining test response data after the update;

[0009] The output data used for this transmission is output.

[0010] The semiconductor test data transmission method provided in the embodiment of the present application receives test response data from the device under test and splices it with the remaining test response data retained in the previous clock cycle, automatically pads zeros when the splicing result is not sufficient to meet the output data bit width, and generates intermediate data; secondly, the intermediate data is fixed-width cropped according to the preset output data bit width, the output data of this cycle is obtained and the remaining test response data is updated, thereby achieving continuous and stable data transmission. This method can effectively solve the alignment problem caused by the inconsistent bit widths used by semiconductor test equipment and the device under test during the semiconductor test process, and realizes low-latency bit width conversion and protocol adaptation of test response data during the semiconductor test process, thereby improving the test efficiency and test reliability of semiconductor test equipment.

[0011] In a possible implementation manner, before concatenating the test response data with the remaining test response data retained in the previous clock cycle, the method further includes:

[0012] Determining whether the number of valid bits of the test response data is greater than or equal to a preset output data bit width;

[0013] The step of splicing the test response data with the remaining test response data retained in the previous clock cycle includes:

[0014] When the number of valid bits of the test response data is smaller than the output data bit width, the test response data is concatenated with remaining test response data retained in the previous clock cycle.

[0015] In a possible implementation, the semiconductor test data transmission method further includes:

[0016] Acquire a data transmission arrangement mode, wherein the arrangement mode includes one of a big endian mode and a little endian mode;

[0017] The test response data is concatenated with the remaining test response data retained in the previous clock cycle, and if the number of bits of the concatenated data is less than the output data bit width, zero padding is performed to obtain intermediate data, including:

[0018] According to the arrangement, the test response data is spliced ​​with the remaining test response data retained in the previous clock cycle. If the number of bits of the spliced ​​data is less than the output data bit width, zeros are padded according to the arrangement to obtain intermediate data.

[0019] In one possible implementation, the test response data is concatenated with the remaining test response data retained in the previous clock cycle according to the arrangement, and if the number of bits of the concatenated data is less than the output data bit width, zero padding is performed according to the arrangement to obtain intermediate data, including:

[0020] When the arrangement mode is big-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, the remaining test response data is placed in the high position of the spliced ​​data, the test response data is placed in the middle position of the spliced ​​data, and the zero-padding data is placed in the low position of the spliced ​​data to generate the intermediate data;

[0021] When the arrangement mode is little-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, the zero-padding data is placed in the high position of the spliced ​​data, the test response data is placed in the middle position of the spliced ​​data, and the remaining test response data is placed in the low position of the spliced ​​data to generate the intermediate data.

[0022] In a possible implementation, the semiconductor test data transmission method further includes:

[0023] Based on the arrangement and the size relationship between the test response data bit width and the output data bit width, performing a shift operation on the intermediate data to obtain target intermediate data;

[0024] The step of clipping the intermediate data to a fixed width according to a preset output data bit width to obtain the output data for this transmission and the updated remaining test response data includes:

[0025] According to the preset output data bit width, the target intermediate data is clipped to a fixed width to obtain the output data for this transmission and the remaining test response data after update.

[0026] In a possible implementation, performing a shift operation on the intermediate data based on the arrangement and the relationship between the test response data bit width and the output data bit width to obtain target intermediate data includes:

[0027] When the arrangement mode is big-endian mode, if the test response data bit width is greater than the output data bit width, a right shift operation is performed on the intermediate data based on a previous cycle margin latch value, where the previous cycle margin latch value is the number of remaining bits of the previous clock cycle latched by a rising edge of the clock in the previous clock cycle;

[0028] When the arrangement mode is big-endian mode, if the test response data bit width is smaller than the output data bit width, a right shift operation is performed on the intermediate data based on a current cycle margin latch value, where the current cycle margin latch value is the number of remaining bits of the current clock cycle latched by a rising edge of the clock in the current clock cycle;

[0029] When the arrangement mode is a little-endian mode, if the test response data bit width is greater than the output data bit width, performing a left shift operation on the intermediate data based on the previous cycle margin latch value;

[0030] When the arrangement mode is the little endian mode, if the bit width of the test response data is smaller than the bit width of the output data, a left shift operation is performed on the intermediate data based on the current cycle margin latch value.

[0031] In a possible implementation, the step of clipping the target intermediate data to a fixed width according to a preset output data bit width to obtain the output data for this transmission and the updated remaining test response data includes:

[0032] When the arrangement mode is big-endian mode, extracting a middle and high-order portion of the target intermediate data as the output data, and extracting a low-order portion as the updated remaining test response data, wherein the bit width of the middle and high-order portion is determined based on the output data bit width and a maximum bit width, and the maximum bit width is the maximum value between the output data bit width and the test response data bit width;

[0033] When the arrangement mode is little-endian mode, the middle and low-order parts of the target intermediate data are extracted as the output data, and the high-order part is extracted as the updated remaining test response data, and the bit width of the middle and low-order parts is determined based on the output data bit width and the test response data bit width.

[0034] In a possible implementation, the semiconductor test data transmission method further includes acquiring a current cycle margin latch value and a previous cycle margin latch value through a margin recorder.

[0035] In a possible implementation, the semiconductor test data transmission method further includes:

[0036] When the test response data bit width is greater than or equal to the output data bit width, if the previous cycle margin latch value is greater than or equal to the output data bit width, outputting a valid signal as a high level to determine that the output data is valid data;

[0037] When the test response data bit width is smaller than the output data bit width, if the previous cycle margin latch value plus the test response data bit width is greater than or equal to the output data bit width, a valid signal is output as a high level to determine that the output data is valid data.

[0038] In a possible implementation manner, after outputting the output data for current transmission, the method further includes:

[0039] After the output data is transmitted, the updated remaining test response data is shifted in a direction-variable manner at the rising edge of the clock cycle, and the updated remaining test response data is latched for a splicing operation in the next clock cycle.

[0040] A second aspect of an embodiment of the present application provides a semiconductor test data transmission device, the semiconductor test data transmission device comprising:

[0041] A receiving module, configured to receive test response data from a device under test;

[0042] a splicing module, configured to splice the test response data with the remaining test response data retained in the previous clock cycle, and if the number of bits of the spliced ​​data is less than the output data bit width, padding with zeros to obtain intermediate data;

[0043] A cropping module is used to crop the intermediate data to a fixed width according to a preset output data bit width, and obtain the output data for this transmission and the remaining test response data after update;

[0044] The output module is used to output the output data used for this transmission.

[0045] In a possible implementation manner, the semiconductor test data transmission device further includes:

[0046] A judging module, configured to judge whether the number of valid bits of the test response data is greater than or equal to a preset output data bit width;

[0047] Correspondingly, the splicing module further includes:

[0048] The valid splicing submodule is configured to splice the test response data with the remaining test response data retained in the previous clock cycle when the number of valid bits of the test response data is smaller than the output data bit width.

[0049] In a possible implementation manner, the semiconductor test data transmission device further includes:

[0050] an arrangement mode acquisition module, configured to acquire an arrangement mode for data transmission, wherein the arrangement mode includes one of a big endian mode and a little endian mode;

[0051] Correspondingly, the splicing module further includes:

[0052] The arrangement and splicing submodule is used to splice the test response data with the remaining test response data retained in the previous clock cycle according to the arrangement method. If the number of bits of the spliced ​​data is less than the output data bit width, zero is padded according to the arrangement method to obtain intermediate data.

[0053] In one possible implementation, the arrangement and splicing submodule includes:

[0054] a big-endian splicing unit, configured to place the remaining test response data in the high order of the spliced ​​data, the test response data in the middle of the spliced ​​data, and zero-padding data in the low order of the spliced ​​data, to generate the intermediate data when the arrangement mode is the big-endian mode and the number of bits of the spliced ​​data is less than the output data bit width;

[0055] A little-endian splicing unit is used to place the zero-padding data in the high position of the spliced ​​data, the test response data in the middle position of the spliced ​​data, and the remaining test response data in the low position of the spliced ​​data when the arrangement mode is the little-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, so as to generate the intermediate data.

[0056] In a possible implementation manner, the semiconductor test data transmission device further includes:

[0057] a shift module, configured to perform a shift operation on the intermediate data based on the arrangement and the size relationship between the test response data bit width and the output data bit width to obtain target intermediate data;

[0058] Correspondingly, the cropping module includes:

[0059] The target clipping submodule is used to perform fixed-width clipping on the target intermediate data according to a preset output data bit width, and obtain the output data for this transmission and the remaining test response data after update.

[0060] In a possible implementation, the shift module includes:

[0061] a first shift submodule, configured to, when the arrangement mode is big-endian mode, perform a right shift operation on the intermediate data based on a previous cycle margin latch value if the test response data bit width is greater than the output data bit width, wherein the previous cycle margin latch value is a number of remaining bits of the previous clock cycle latched by a rising edge of the clock in the previous clock cycle;

[0062] a second shift submodule, configured to, when the arrangement mode is big-endian mode, perform a right shift operation on the intermediate data based on a current cycle margin latch value if the test response data bit width is smaller than the output data bit width, wherein the current cycle margin latch value is a remaining number of bits of the current clock cycle latched by a rising edge of the clock in the current clock cycle;

[0063] a third shift submodule, configured to, when the arrangement mode is a little-endian mode, perform a left shift operation on the intermediate data based on the previous cycle margin latch value if the test response data bit width is greater than the output data bit width;

[0064] A fourth shift submodule is configured to, when the arrangement is in little-endian mode, perform a left shift operation on the intermediate data based on the current cycle margin latch value if the test response data bit width is smaller than the output data bit width.

[0065] In a possible implementation, the target clipping submodule includes:

[0066] a big-endian clipping unit, configured to extract, when the arrangement mode is big-endian mode, a middle and high-order portion of the target intermediate data as the output data, and extract a low-order portion as the updated remaining test response data, wherein the bit width of the middle and high-order portion is determined based on the output data bit width and a maximum bit width, wherein the maximum bit width is the maximum value between the output data bit width and the test response data bit width;

[0067] A little-endian clipping unit is used to extract the middle and low-order parts of the target intermediate data as the output data and extract the high-order part as the updated remaining test response data when the arrangement mode is the little-endian mode, and the bit width of the middle and low-order parts is determined based on the output data bit width and the test response data bit width.

[0068] In a possible implementation manner, the semiconductor test data transmission device further includes:

[0069] The margin recorder is used to obtain the margin latch value of this cycle and the margin latch value of the previous cycle.

[0070] In a possible implementation manner, the semiconductor test data transmission device further includes:

[0071] a first validity judgment module, configured to output a valid signal of a high level when the test response data bit width is greater than or equal to the output data bit width and if the previous cycle margin latch value is greater than or equal to the output data bit width, so as to determine that the output data is valid data;

[0072] The second validity judgment module is used to output a valid signal of a high level when the test response data bit width is smaller than the output data bit width and if the previous cycle margin latch value plus the test response data bit width is greater than or equal to the output data bit width, so as to determine that the output data is valid data.

[0073] In a possible implementation manner, the semiconductor test data transmission device further includes:

[0074] The update latch module is used to shift the updated remaining test response data in a variable direction at the rising edge of the clock cycle after the output data is transmitted, and latch the updated remaining test response data for splicing operation in the next clock cycle.

[0075] A third aspect of an embodiment of the present application provides a semiconductor testing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the semiconductor test data transmission method described in the first aspect when executing the computer program.

[0076] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the semiconductor test data transmission method described in the first aspect is implemented.

[0077] A fifth aspect of the embodiments of the present application provides a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device executes the semiconductor test data transmission method described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0078] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0079] Figure 1 This is a flow chart of a semiconductor test data transmission method provided in Example 1 of the present application;

[0080] Figure 2This is a flow chart of another semiconductor test data transmission method provided in the second embodiment of the present application;

[0081] Figure 3 This is a timing diagram of each signal in the big-endian mode when the test response data width is greater than the output data width;

[0082] Figure 4 This is the timing diagram of each signal when the test response data width is greater than the output data width and in little-endian mode;

[0083] Figure 5 This is a timing diagram of each signal when the test response data width is smaller than the output data width and in big-endian mode;

[0084] Figure 6 This is the timing diagram of each signal when the test response data width is smaller than the output data width and in little-endian mode;

[0085] Figure 7 This is a flowchart of another semiconductor test data transmission method provided in the third embodiment of the present application;

[0086] Figure 8 This is a structural diagram of a semiconductor test data transmission device provided in the fourth embodiment of the present application;

[0087] Figure 9 This is a structural diagram of a semiconductor testing device provided in Example 5 of the present application. DETAILED DESCRIPTION

[0088] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0089] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0090] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0091] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0092] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0093] It should be understood that the size of the serial numbers of each step in this embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of this application.

[0094] With the continuous development of information technology, especially its growing applications in fields such as communications, artificial intelligence, image processing, and embedded systems, the functions of system modules are becoming increasingly complex, and the demand for data exchange between different modules is constantly increasing. In system architectures such as SoC (System on Chip), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or ATE (Automatic Test Equipment), multiple functional modules often transmit data via internal buses or streaming interfaces.

[0095] For example, when testing chips, ATE systems typically need to perform high-speed data communication verification on the chip's interface, including data acquisition, protocol verification, functional testing, and timing testing. The test data format often suffers from bit-width mismatches due to varying chip interface widths. For example, the internal test bus used by the ATE equipment itself typically has a fixed bit width (e.g., 64bit / 128bit), but the chip under test (DUT) may use a different I / O bit width (e.g., 8bit, 12bit, 20bit, etc.). If this bit-width mismatch is not addressed, direct communication will result in data truncation, misalignment, or even communication failure, which in turn will cause the ATE system to fail to perform high-speed communication verification on the chip's interface, reducing reliability and test efficiency.

[0096] In order to solve the above problems, an embodiment of the present application provides a semiconductor test data transmission method, which receives test response data from the device under test and splices it with the remaining test response data retained in the previous clock cycle, and automatically fills zeros when the splicing result is not enough to meet the output data bit width to generate intermediate data; secondly, the intermediate data is fixed-width cropped according to the preset output data bit width, the output data of this cycle is obtained and the remaining test response data is updated, thereby achieving continuous and stable data transmission. This method can effectively solve the alignment problem caused by the inconsistent bit width used by the semiconductor test equipment and the device under test during the semiconductor testing process, and realizes low-latency bit width conversion and protocol adaptation of the test response data during the semiconductor testing process, thereby improving the test efficiency and test reliability of the semiconductor testing equipment.

[0097] The semiconductor test data transmission method, apparatus, semiconductor test equipment, storage medium, and computer program provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0098] Figure 1 FIG1 shows a flow chart of a semiconductor test data transmission method provided in the first embodiment of the present application. Figure 1 As shown, the method may include the following steps:

[0099] Step 101: Receive test response data.

[0100] Among them, test response data refers to the data flow entering the current data transmission device from the upstream module (such as the data source interface, sensor or other computing unit, etc.) during the system operation. When the semiconductor testing equipment tests the device under test, the test response data comes from the device under test.

[0101] In the embodiments of the present application, the device under test can be various types of semiconductor chips, such as: digital signal processors (DSPs); memory chips (such as NAND Flash, DDR DRAM); analog / mixed signal chips (such as ADC / DAC, power management chips); communication interface chips (such as USB transceivers, Ethernet PHY, CAN transceivers, etc.).

[0102] In the embodiments of the present application, test response data refers to the response signal generated by the device under test to a test stimulus signal or test command during the test process. For example, when the device under test is an ADC chip, the test response data is a digital sample value; when the device under test is a SoC chip, the test response data can be a bus transmission frame, data compression encoding results, or register readback information; when the device under test is an image sensor chip, the test response data is a data frame sampled and output by the pixel array; when the device under test is a communication chip, the test response data may be bit error rate statistics, signal feedback data, etc.

[0103] Specifically, the test response data usually has the following properties: bit width, that is, the bit width of the test response data, such as 8 bits, 12 bits, 16 bits, etc.; validity, that is, whether it is data available in the current cycle, usually accompanied by an in_valid signal indication; timing synchronization, that is, the clock receiving the test response data is aligned with the system clock clk and collected in beats; arrangement method, such as big endian (high bit arrives first) or little endian (low bit arrives first).

[0104] Receiving test response data means that the system reads a set of test response data from the data bus or interface on the rising edge of the clock after certain handshake conditions are met (for example, in_valid is high and in_ready is high). In this case, in_valid = 1 indicates that the data source is ready for data, and in_ready = 1 indicates that the receiving end can receive data. Data sampling is then triggered on the rising edge of clk, indicating that the test response data is received.

[0105] Step 102 : concatenate the test response data with the remaining test response data retained in the previous clock cycle. If the number of bits of the concatenated data is less than the output data bit width, zero padding is performed to obtain intermediate data.

[0106] The remaining test response data refers to the data segment that failed to be output in the previous clock cycle. This is usually because the length of the data segment is insufficient to meet the output data bit width and needs to be temporarily stored for splicing in the next clock cycle.

[0107] Here, splicing refers to splicing the test response data and the remaining test response data of the previous clock cycle into a new data sequence according to the bit width in a specific arrangement order (such as big endian mode, little endian mode or default mode).

[0108] Among them, when the total number of bits after splicing is less than the output bit width, zeros are inserted in the high or low bits of the spliced ​​data to make up the required width, which facilitates subsequent alignment processing.

[0109] For example, assuming that the test response data bit width IW = 8, the output data bit width OW = 12, the test response data in_data = 0x12, and the remaining test response data shiftB retained in the previous clock cycle = 0x345; after splicing, stit_dat = {shiftB, in_data, {OW{1'b0}}} = 0x34512000, or stit_dat = {{OW{1'b0}}, in_data, shiftB} = 0x00012345, where {OW{1'b0}} represents a value of 0, and the bit width of the value is equal to OW. The spliced ​​intermediate data can be specifically determined according to the order of data transmission, and the order of data transmission can be determined according to the arrangement mode of the test response data or by default or by reading the configuration register, which is not limited in this application.

[0110] Step 103 : Cut the intermediate data to a fixed width according to the preset output data bit width to obtain the output data for this transmission and the remaining test response data after update.

[0111] Among them, fixed-width cropping refers to cutting out a section of data equal to the preset output bit width from the intermediate data formed by splicing and zero padding.

[0112] The output data used for this transmission refers to the data segment formed after trimming within this cycle and to be sent or output to the next link.

[0113] The updated remaining test response data refers to the remaining data in the intermediate data after the output data is clipped, and is stored and used for the splicing operation of the next cycle.

[0114] Specifically, the intermediate data is clipped in a fixed-width manner, that is, according to the output data bit width, the valid data of the corresponding bits are intercepted from the middle and high-bit segments or the middle and low-bit segments of the intermediate data. The clipped data is the output data, and the other bit segments that are not clipped are stored as the updated remaining test response data for data splicing in the next clock cycle.

[0115] For example, assuming that the intermediate data is 0x0034120, the preset output data width is 12 bits, and the default mode of data splicing is little endian mode; then the cropped output data is out_data=0x412, and the updated remaining test response data is rem_data=0x003.

[0116] In a possible implementation, the number of bits of the remaining test response data may be recorded by a margin recorder.

[0117] Specifically, the number of bits of the remaining test response data can be recorded based on the bit width IW of the test response data, the bit width OW of the output data, the input ready signal (in_ready), the input valid signal (in_valid), the output ready signal (out_ready), the output valid signal (out_valid) and the clock signal (clk).

[0118] For example, two variables are set inside the remaining_cnt module: the previous cycle remaining value latch (rem_cnt_1d), which is a clock-triggered variable. That is, when the rising edge of the clock signal (clk) is triggered, the current value of the real-time remaining variable (rem_cnt) is assigned to the latched remaining variable (rem_cnt_1d); the current cycle remaining value latch (rem_cnt), which is dynamically updated according to the following four real-time situations:

[0119] (1) If the input ready signal (in_ready), input valid signal (in_valid), output ready signal (out_ready) and output valid signal (out_valid) are valid at the same time, that is, they are all at a high level (logic "1"), the update method of the margin latch value in this cycle is: rem_cnt = rem_cnt_1d + IW - OW.

[0120] (2) If the above signals are not valid at the same time, only the input ready signal (in_ready) and the input valid signal (in_valid) are valid (high level), and the update method of the margin latch value in this cycle is: rem_cnt=rem_cnt_1d+IW.

[0121] (3) If the above signals are not valid at the same time, only the output ready signal (out_ready) and the output valid signal (out_valid) are valid (high level), and the update method of the margin latch value in this cycle is: rem_cnt=rem_cnt_1d-OW.

[0122] (4) If none of the above conditions are met, the margin latch value of this cycle remains unchanged, that is, rem_cnt = rem_cnt_1d.

[0123] Step 104: Output data for this transmission.

[0124] In the embodiment of the present application, the output condition of the output data is usually determined by the two signals out_valid and out_ready, that is, when out_valid=1 and out_ready=1, the output data out_data for this transmission is output at the rising edge of the clock.

[0125] Among them, out_valid=1 indicates that the output data is ready, and out_ready=1 indicates that the next level module is ready to receive the output data.

[0126] In a possible implementation, the output of the output ready signal and the output valid signal is determined based on the relationship between the test response data bit width and the output data bit width, and the relationship between the previous cycle margin latch value and the output data bit width.

[0127] Specifically, the semiconductor test data transmission method further includes:

[0128] When the test response data bit width is greater than or equal to the output data bit width, if the previous cycle margin latch value is greater than or equal to the output data bit width, the output valid signal is high to confirm that the output data is valid data;

[0129] When the test response data bit width is smaller than the output data bit width, if the previous cycle margin latch value plus the test response data bit width is greater than or equal to the output data bit width, the output valid signal is high to determine that the output data is valid data.

[0130] For example, in an application scenario where the test response data bit width is 64 bits and the output data bit width is 32 bits, the margin recorder maintains the previous cycle margin latch value as 32 bits. When the test response data arrives, because the test response data bit width is greater than the output data bit width, it is determined whether the previous cycle margin latch value is greater than or equal to 32 bits. At this time, the previous cycle margin latch value is equal to 32 bits, and the output valid signal is set to a high level, indicating that the current output data is valid. In another application scenario, the test response data bit width is 8 bits and the output data bit width is 16 bits, and the previous cycle margin latch value recorded by the margin recorder is 10 bits. When new test response data arrives, the sum of the previous cycle margin latch value and the test response data bit width is 18 bits, which exceeds the output data bit width by 16 bits. The output valid signal is set to a high level, and the current output data is marked as valid.

[0131] This application dynamically determines the triggering conditions for outputting valid signals, precisely controlling the timing of generating valid data states and avoiding invalid or redundant output data transmission. During the conversion process where the bit width of semiconductor test equipment and the device under test do not match, the valid signal generation mechanism ensures the integrity and timing accuracy of the output data, significantly reducing the risk of data loss, while also reducing bandwidth waste caused by invalid operations and improving the overall transmission efficiency of the system.

[0132] In a possible implementation, after the output data for this transmission is output, the margin recorder is updated and the remaining test response data is buffered to prepare for processing in the next clock cycle.

[0133] Specifically, after outputting the output data for this transmission, the method further includes:

[0134] After the output data is transmitted, at the rising edge of the clock cycle, the updated remaining test response data is shifted in a variable direction and latched for the splicing operation of the next clock cycle.

[0135] For example, after completing the output data transmission of the current clock cycle, when the clock signal enters the rising edge stage, the bit width of the updated remaining test response data is adjusted through the shift register. The shift direction is determined by the arrangement of the system configuration. When in big-endian mode, a right shift operation is performed to align the high-order valid data with the high-order area of ​​the next cycle splicing; when in little-endian mode, a left shift operation is performed to align the low-order valid data with the low-order area of ​​the next cycle splicing. The remaining test response data after the shift is latched into a dedicated register unit and spliced ​​with the new test response data in the next clock cycle. The latching process is controlled by the clock synchronization circuit to ensure that the remaining test response data is in a stable state when splicing.

[0136] This application effectively solves the data splicing misalignment problem caused by fixed shift directions in traditional bit width conversion. By dynamically adjusting the shift direction of the remaining test response data, valid data in different arrangement modes can be accurately aligned with the target bit width, avoiding the waste of clock cycles caused by repeated shift operations.

[0137] The semiconductor test data transmission method provided in the first embodiment of the present application receives test response data and splices it with the remaining test response data retained in the previous clock cycle, automatically pads zeros when the splicing result is not sufficient to meet the output data bit width, and generates intermediate data; secondly, the intermediate data is fixed-width cropped according to the preset output data bit width, the output data of this cycle is obtained and the remaining test response data is updated, thereby achieving continuous and stable data transmission. This method can effectively solve the alignment problem caused by the inconsistent bit widths used by semiconductor test equipment and the device under test during semiconductor testing, and realizes low-latency bit width conversion and protocol adaptation of test response data during semiconductor testing, thereby improving the test efficiency and test reliability of semiconductor test equipment.

[0138] Figure 2 FIG. 1 is a flow chart showing another semiconductor test data transmission method provided in the second embodiment of the present application. Figure 2 As shown, the method may include the following steps:

[0139] Step 201: Receive test response data.

[0140] Step 201 of the embodiment of the present application is similar to step 101 of the aforementioned embodiment, and they can refer to each other and will not be described in detail here.

[0141] Step 202: Acquire the data transmission arrangement.

[0142] The data transmission arrangement refers to the order in which bits are organized during data transmission or storage. Specifically, it can include: Big Endian mode, also known as Big Endian mode, where the high-order byte or bit of data is transmitted or stored first. For example, the value 0x1234 is stored as 0x12 0x34 in big-endian order, meaning the high-order bit 0x12 comes first. Little Endian mode, also known as Little Endian mode, where the low-order byte or bit of data is transmitted or stored first. For example, the value 0x1234 is stored as 0x34 0x12 in little-endian order, meaning the low-order bit 0x34 comes first.

[0143] Specifically, the data transmission arrangement can be obtained by reading and identifying the arrangement mode (big endian mode or little endian mode) currently used for data transmission from a configuration register, a status register, or other system configuration units.

[0144] The method of reading from the configuration register is: when the system is initialized, the arrangement mode is pre-set through the configuration register, and the register is read in subsequent steps to determine the arrangement mode.

[0145] The arrangement can also be modified in real time through an external interface or software command, and the system dynamically reads it at the beginning of each data processing cycle. Alternatively, the transmission protocol used by the system itself specifies the data arrangement, and the system determines the arrangement based on the protocol type. All of the above methods can obtain the arrangement of data transmission, and users can set it specifically according to the actual scenario. This application does not limit this.

[0146] Step 203: splice the test response data with the remaining test response data retained in the previous clock cycle according to the arrangement mode. If the number of bits of the spliced ​​data is less than the output data bit width, zero is padded according to the arrangement mode to obtain intermediate data.

[0147] In an embodiment of the present application, during the splicing operation, the positional relationship between the remaining test response data and the test response data is dynamically adjusted by the arrangement mode, and the zero-padding position selects the high or low bit filling according to the endian mode. For example, when the arrangement mode is big endian, the remaining test response data occupies the high bit after splicing, the test response data occupies the middle bit, and the zero-padding fills the low bit; when the arrangement mode is little endian, the zero-padding occupies the high bit, the test response data occupies the middle bit, and the remaining test response data occupies the low bit. The data bit width calculation is monitored in real time by a counter. When the total bit width after splicing is less than the output data bit width, the zero-padding operation is triggered, and the number of zero-padding bits is equal to the difference between the output data bit width and the splicing data bit width.

[0148] Specifically, after receiving the test response data, the arrangement mode is first obtained. If the arrangement mode is big-endian mode, the remaining test response data of the previous cycle is used as the high-order part, and the test response data is used as the middle part. The two are spliced ​​together to calculate the total number of bits. When the total number of bits is less than the output data bit width, zero values ​​are padded in the low order to generate intermediate data. For example, if the test response data bit width is 12 bits, the remaining test response data is 8 bits, and the output data bit width is 32 bits, the total number of bits after splicing is 20 bits, and 12 bits of zero values ​​need to be padded in the low order. If the current mode is little-endian mode, the remaining test response data is used as the low-order part, and the test response data is used as the middle part, and zero values ​​are padded in the high order. After the intermediate data is generated, it is fixed-width cropped according to the output data bit width, retaining the valid data part, and the remaining part is stored in the register for use in the next cycle. By dynamically adapting the arrangement mode, it is ensured that the data splicing and zero-padding logic in different endian scenarios comply with the protocol specifications, avoiding data bit misalignment or invalid padding.

[0149] That is, according to the arrangement mode, the test response data is spliced ​​with the remaining test response data retained in the previous clock cycle. If the number of bits of the spliced ​​data is less than the output data bit width, zeros are padded according to the arrangement mode to obtain intermediate data, including:

[0150] When the arrangement mode is big-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, the remaining test response data is placed in the high position of the spliced ​​data, the test response data is placed in the middle position of the spliced ​​data, and the zero-filled data is placed in the low position of the spliced ​​data to generate intermediate data;

[0151] When the arrangement mode is little-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, the zero-padding data is placed in the high position of the spliced ​​data, the test response data is placed in the middle position of the spliced ​​data, and the remaining test response data is placed in the low position of the spliced ​​data to generate intermediate data.

[0152] For example, assuming that the test response data bit width IW = 8, the output data bit width OW = 12, the test response data in_data = 0x12, and the remaining test response data shiftB retained in the previous clock cycle = 0x345; in big endian mode, the spliced ​​stit_dat = {shiftB, in_data, {OW{1'b0}}} = 0x34512000, and in little endian mode, the spliced ​​intermediate data stit_dat = {{OW{1'b0}}, in_data, shiftB} = 0x00012345.

[0153] Step 204 : Based on the arrangement mode and the relationship between the test response data bit width and the output data bit width, perform a shift operation on the intermediate data to obtain target intermediate data.

[0154] In the embodiment of the present application, the test response data and the remaining test response data are concatenated and zero-padded to generate intermediate data. However, when the test response data bit width is inconsistent with the output data bit width, the valid portion of the intermediate data may not be aligned with the output data bit width, resulting in bit errors or invalid padding in the output data after fixed-width cropping, affecting transmission accuracy and the update logic of the remaining test response data. Therefore, before fixed-width cropping, the intermediate data is shifted to obtain the target intermediate data.

[0155] Specifically, the above step 204 may include:

[0156] When the arrangement mode is big-endian mode, if the test response data bit width is larger than the output data bit width, a right shift operation is performed on the intermediate data based on the previous cycle margin latch value, where the previous cycle margin latch value is the number of remaining bits of the previous clock cycle latched by the rising edge of the clock in the previous clock cycle;

[0157] When the arrangement mode is big-endian mode, if the test response data bit width is smaller than the output data bit width, the intermediate data is right-shifted based on the current cycle margin latch value, which is the number of remaining bits in the current clock cycle latched by the rising edge of the clock in the current clock cycle;

[0158] When the arrangement mode is little endian mode, if the test response data bit width is larger than the output data bit width, a left shift operation is performed on the intermediate data based on the previous cycle margin latch value;

[0159] When the arrangement mode is little endian mode, if the test response data bit width is smaller than the output data bit width, a left shift operation is performed on the intermediate data based on the margin latch value of this cycle.

[0160] Specifically, the purpose of the shift operation is to adjust the position of the intermediate data so that the output data and the remaining test response data can be accurately divided during fixed-width trimming. For example, in big-endian mode, if the test response data bit width is 64 bits, the output data bit width is 32 bits, and the remaining test response data of the previous cycle is 16 bits, the intermediate data consists of the remaining test response data high bit, the test response data middle bit, and the zero-filled low bit. At this time, the previous cycle margin latch value is 16. After the intermediate data is right-shifted by 16 bits, the lower 32 bits of the test response data and the upper 16 bits of the remaining test response data form a continuous valid data segment, which is convenient for trimming and output. In little-endian mode, if the test response data bit width is 8 bits and the output data bit width is 16 bits, the current cycle margin latch value is 8, and the intermediate data is left-shifted by 8 bits, so that the test response data and the remaining test response data are aligned at the low bit, and the high bit is padded with zeros to ensure that the valid data is at the target position during trimming. Through the shift operation, the valid part of the intermediate data is accurately adjusted to the position corresponding to the output data bit width, thereby avoiding data misalignment or invalid truncation, ensuring the integrity of the output data and the correct update of the remaining test response data.

[0161] Step 205 : Cut the target intermediate data to a fixed width according to the preset output data bit width, and obtain the output data for this transmission and the updated remaining test response data.

[0162] Specifically, the target intermediate data is clipped with a fixed width, that is, according to the output data bit width, the valid data of the corresponding bits are intercepted from the middle and high bit segments or the middle and low bit segments of the target intermediate data. The clipped data is the output data, and the other bit segments that are not clipped are stored as the updated remaining test response data for data splicing in the next clock cycle.

[0163] In a possible implementation, step 205 may specifically include:

[0164] When the arrangement mode is big-endian mode, the middle and high-order parts of the target intermediate data are extracted as output data, and the low-order parts are extracted as the updated remaining test response data. The bit width of the middle and high-order parts is determined based on the output data bit width and the maximum bit width. The maximum bit width is the maximum value of the output data bit width and the test response data bit width.

[0165] When the arrangement mode is little endian mode, the middle and low-order parts of the target intermediate data are extracted as output data, and the high-order part is extracted as the updated remaining test response data. The bit width of the middle and low-order parts is determined based on the output data bit width and the test response data bit width.

[0166] Specifically, after the intermediate data undergoes a shift operation, the high and low bit distribution of the target intermediate data is adjusted according to the arrangement. In big-endian mode, the valid data after the shift is concentrated in the high-order area. At this time, the mid-high-order portion that matches the output data bit width is intercepted from the high-order to the low-order as the output data, and the remaining portion is retained as the low-order data. In little-endian mode, the valid data is concentrated in the low-order area. At this time, the mid-low-order portion that matches the output data bit width is intercepted from the low-order to the high-order as the output data, and the remaining portion is retained as the high-order data. The relationship between the output data bit width and the test response data bit width affects the maximum bit width, which in turn determines the specific interception range of the mid-high-order portion.

[0167] For example, when the test response data bit width is larger than the output data bit width, the maximum bit width is the test response data bit width, and at this time the middle and high-order part of the bit width in the big-endian mode is equal to the output data bit width; when the test response data bit width is smaller than the output data bit width, the maximum bit width is the output data bit width, and at this time the middle and high-order part of the bit width still remains as the output data bit width.

[0168] The dynamic adjustment method of the embodiment of the present application ensures the correct interception of output data under different arrangement modes, avoids valid data from being cut or mixed into the remaining test response data, and ensures the integrity and continuity of data transmission.

[0169] Step 206: Output the output data for this transmission.

[0170] Step 206 of the embodiment of the present application is similar to step 104 of the aforementioned embodiment, and they can refer to each other and will not be described in detail here.

[0171] Reference below Figures 3 to 6 The implementation of the second embodiment is described in detail.

[0172] like Figure 3 Shown is the timing diagram of each signal when the test response data width is larger than the output data width and in big-endian mode.

[0173] Specifically, when the test response data width is larger than the output data width and big-endian mode is used, the splicing and cropping operations include:

[0174] The remaining test response data retained in the previous cycle is placed in the high position of the splicing data, the test response data received in the current cycle is placed in the middle position, and zero is added to the low position of the splicing data to form intermediate data; the intermediate data is shifted right by the preset offset value to complete data alignment; the middle bit segment is extracted from the right-shifted intermediate data as the current output data, and the low-bit segment is used as the updated remaining test response data; in the next clock cycle, the updated remaining test response data is prepared for position by right shifting for use in the next splicing.

[0175] like Figure 3 As shown, the test response data bit width is 12 bits, in_data[11:0]; the output data bit width is 8 bits, out_data[7:0]; the target intermediate data stit_dat bit width is 32 bits, the data arrangement is big endian mode, and the internal signals include rem_cnt (residual latch value of this cycle), rem_cnt_1d (residual latch value of the previous cycle), sftB_dat (remaining test response data), sftA_dat (target intermediate data), etc.

[0176] The high bit of the middle data is the remaining test response data retained in the previous clock cycle, the middle is the test response data, and the low bit is padded with zero. Take the first valid input cycle as an example:

[0177] in_data=0x123, sftB_dat=0x000 (initial), intermediate data stit_dat={sftB_dat, in_data, zero padding}=0x00012300.

[0178] In the second cycle, the test response data is 0x456, the remainder of the previous cycle sftB_dat=0x003 (obtained from the rem_dat of the previous cycle), and the intermediate data is updated to stit_dat=0x00345600.

[0179] After the splicing is completed, the system performs right shift processing (big endian) on the spliced ​​data according to rem_cnt or rem_cnt_1d. The right shift bit is equal to the previous cycle margin latch value rem_cnt_1d to ensure that the output data is in the correct position. The data after shifting is sftA_dat, and then the cropping is performed. Figure 3 As shown:

[0180] sftA_dat=stit_dat>>rem_cnt_1d;

[0181] After the first cycle is right-shifted, sftA_dat = 0x00012300, and the middle segment out_data = 0x12 is intercepted. The low-order bit 0x300 is used as the remaining test response data. The low-order portion of sftA_dat is extracted as rem_dat for the next cycle splicing. For example, in the first cycle, rem_dat = 0x300 is latched into sftB_dat on the rising edge of the clock and continues to be placed in the high-order splicing data during the next cycle splicing.

[0182] By continuously shifting right and extracting and cropping, the system achieves the orderly generation of multiple small blocks of output data, ensuring high-order priority and big-endian alignment.

[0183] like Figure 4Shown is the timing diagram of each signal when the test response data width is larger than the output data width and in little-endian mode.

[0184] Specifically, when the test response data bit width is larger than the output data bit width and the little endian mode is adopted, the splicing and cropping operations include: filling the high bits of the spliced ​​data with zeros, placing the test response data received in the current cycle in the middle position, and placing the remaining test response data retained in the previous cycle in the low bits of the spliced ​​data to form intermediate data; shifting the intermediate data left by a preset offset value to complete data alignment; extracting the middle bit segment from the left-shifted intermediate data as the current output data, and extracting the updated remaining test response data from the high-bit segment at the same time; in the next clock cycle, preparing the position of the updated remaining test response data by left shifting for use in the next splicing.

[0185] like Figure 4 As shown, the test response data bit width is 12 bits, in_data[11:0]; the output data bit width is 8 bits, out_data[7:0]; the target intermediate data stit_dat bit width is 32 bits, and the data arrangement is in little-endian mode. The internal signals include rem_cnt (residual latch value of this cycle), rem_cnt_1d (residual latch value of the previous cycle), sftB_dat (remaining test response data), sftA_dat (target intermediate data), stit_dat (intermediate data), etc.

[0186] The high bit of the spliced ​​data is padded with zeros, the test response data is placed in the middle position, and the remaining test response data of the previous cycle is placed in the low bit to form the middle data. Take the first valid input cycle as an example:

[0187] in_data=0x123, sftB_dat=0x000 (initial), intermediate data stit_dat={fill with zeros, in_data, sftB_dat}=0x00123000.

[0188] In the second cycle, the test response data is 0x456, the remainder of the previous cycle sftB_dat=0x100 (obtained from the rem_dat of the previous cycle), and the intermediate data is updated to stit_dat=0x00456100.

[0189] After stitching is completed, the stit_dat needs to perform a left shift operation according to the current remaining amount rem_cnt. For example, sftA_dat = stit_dat << rem_cnt_1d; In the first cycle: rem_cnt = 0x0, left shift = 0, left shift result: sftA_dat = 0x00123000; In the second cycle: rem_cnt = 0x4, left shift = 4; The left shift result is: sftA_dat = 0x04561000; Finally, extract the middle 8 bits from sftA_dat, output out_data, and retain the rem_dat for the next cycle from the high bit.

[0190] Figure 4 It fully shows the update of the test response data in_data per cycle, the formation rule of the intermediate data stit_dat, the target intermediate data sftA_dat after shifting, the output result of out_data per cycle, and the retention update logic of rem_dat.

[0191] Such as Figure 5 shown is the timing diagram of each signal in the case where the bit width of the test response data is less than the bit width of the output data and in the big-endian mode.

[0192] Specifically, when the bit width of the test response data is less than the bit width of the output data and the big-endian mode is adopted, the stitching and cropping operations include: placing the remaining test response data retained in the previous cycle at the high bit of the stitched data, placing the test response data received in the current cycle in the middle position, filling zeros at the low bit of the stitched data to form the intermediate data; shifting the intermediate data to the right by a preset offset value to complete data alignment; extracting the middle bit segment from the right-shifted intermediate data as the current output data, and at the same time taking the low segment as the updated remaining test response data; in the next clock cycle, prepare the position of the updated remaining test response data by shifting to the right for the next stitching.

[0193] Such as Figure 5 shown, the bit width of the test response data is 8bit, in_data[7:0]; the bit width of the output data is 12bit, out_data[11:0]; the bit width of the target intermediate data stit_dat is 32bit, and the data arrangement is in the big-endian mode. The internal signals include rem_cnt (the latch value of the remaining amount in this cycle), rem_cnt_1d (the latch value of the remaining amount in the previous cycle), sftB_dat (the remaining test response data), sftA_dat (the target intermediate data), etc.

[0194] The high bit of the intermediate data is the remaining test response data retained in the previous clock cycle, the middle is the test response data, and zeros are filled at the low bit. Taking the first valid input cycle as an example:

[0195] in_data=0x12, sftB_dat=0x000 (initial), intermediate data stit_dat={sftB_dat, in_data, zero padding}=0x00001200.

[0196] In the second cycle, the test response data is 0x34, the remainder of the previous cycle sftB_dat=0x012 (obtained from the rem_dat of the previous cycle), and the intermediate data is updated to stit_dat=0x01234000.

[0197] After the splicing is completed, stit_dat will be shifted right by the preset offset value (by rem_cnt) to complete the data alignment:

[0198] sftA_dat=stit_dat>>rem_cnt;

[0199] Extract the middle segment as out_data, which is 12 bits long, and extract the low-order segment as rem_dat for the next cycle splicing. Figure 5 As shown, in the third cycle: stit_dat=0x00456000; rem_cnt=0; sftA_dat=0x00456000; out_data=0x456; rem_dat=0x000.

[0200] like Figure 5 As shown in the figure, the right-shifted rem_dat is latched as sftB_dat on the rising edge of clk for use in the next cycle splicing. Current cycle: rem_dat = sftA_dat[11:0]; Next cycle: sftB_dat <= rem_dat(@posedgeclk). As can be seen in the signal in the figure, rem_dat is correctly updated to sftB_dat in each cycle, achieving seamless data splicing.

[0201] like Figure 6 The figure shows the timing diagram of each signal when the test response data width is smaller than the output data width and in little-endian mode.

[0202] Specifically, when the test response data bit width is smaller than the output data bit width and the little-endian mode is adopted, the splicing and cropping operations include: filling the high bits of the spliced ​​data with zeros, placing the test response data received in the current cycle in the middle position, and placing the remaining test response data retained in the previous cycle in the low bits of the spliced ​​data to form intermediate data; shifting the intermediate data left by a preset offset value to complete data alignment; extracting the middle bit segment from the left-shifted intermediate data as the current output data, and extracting the updated remaining test response data from the high-bit segment at the same time; in the next clock cycle, preparing the position of the updated remaining test response data by left shifting for use in the next splicing.

[0203] like Figure 6 As shown, the test response data bit width is 8 bits, in_data[7:0]; the output data bit width is 12 bits, out_data[11:0]; the target intermediate data stit_dat bit width is 32 bits, the data arrangement is little endian mode, and the internal signals include rem_cnt (residual latch value of this cycle), rem_cnt_1d (residual latch value of the previous cycle), sftB_dat (remaining test response data), sftA_dat (target intermediate data), etc.

[0204] The high bit of the intermediate data is padded with zeros, the middle bit is the test response data, and the low bit is the remaining test response data retained in the previous clock cycle. Take the first valid input cycle as an example:

[0205] in_data=0x12, sftB_dat=0x000 (initial), intermediate data stit_dat={fill with zeros, in_data, sftB_dat}=0x0012000.

[0206] In the second cycle, the test response data is 0x34, the remainder of the previous cycle sftB_dat=0x120 (obtained by latching the rising edge of rem_dat), and the intermediate data is updated to stit_dat=0x0034120.

[0207] After the splicing is completed, stit_dat is shifted left according to the previous cycle margin rem_cnt:

[0208] sftA_dat=stit_dat< <rem_cnt;

[0209] To achieve the alignment of output data and output bit width; intercept the middle segment from sftA_dat as out_data, and intercept the high-order part as rem_dat. Figure 6 As shown in the figure, in the third cycle: stit_dat = 0x00056300; rem_cnt = 0; sftA_dat = 0x00056300; out_data = 0x563; rem_dat = 0x000. As can be seen from the signal in the figure, rem_dat in each cycle is correctly updated to sftB_dat, achieving seamless data splicing.

[0210] The semiconductor test data transmission method provided in Example 2 of the present application introduces big-endian and little-endian arrangements, enabling splicing and zero-padding operations to adapt to systems with different data arrangement rules, thereby enhancing the method's versatility and platform compatibility, and enabling stable adaptation and use in a variety of bus protocols or processing architectures. At the same time, the introduction of shift operations based on the relationship between arrangement and bit width optimizes the structure of intermediate data before entering the clipping phase, improving the alignment accuracy of the output data, laying an accurate foundation for subsequent fixed-width clipping, and enhancing the flexibility of the module.

[0211] Figure 7 FIG. 1 is a flow chart showing another method for transmitting semiconductor test data provided in the third embodiment of the present application. Figure 7 As shown, the method may include the following steps:

[0212] Step 701: Receive test response data.

[0213] Step 701 of the embodiment of the present application is similar to step 101 of the aforementioned embodiment, and they can refer to each other and will not be described in detail here.

[0214] Step 702, determining whether the number of valid bits of the test response data is greater than or equal to a preset output data bit width;

[0215] In some of the above-mentioned schemes of the present application, when splicing the test response data with the remaining test response data retained in the previous clock cycle, there is a situation where the splicing operation is performed regardless of whether the test response data meets the output data bit width requirements, resulting in redundant calculations in the intermediate links of data processing, increasing logic resource consumption and timing delays.

[0216] Therefore, before splicing the test response data with the remaining test response data retained in the previous clock cycle, this embodiment first determines whether the number of valid bits of the test response data is greater than or equal to the preset output data bit width; when the number of valid bits of the test response data is less than the output data bit width, the splicing operation is triggered.

[0217] Step 703: When the number of valid bits of the test response data is less than the output data bit width, the test response data is concatenated with the remaining test response data retained in the previous clock cycle. If the number of bits of the concatenated data is less than the output data bit width, zeros are padded to obtain intermediate data.

[0218] Step 704 : Cut the intermediate data to a fixed width according to the preset output data bit width to obtain the output data for this transmission and the remaining updated test response data.

[0219] Step 705: Output data for this transmission.

[0220] Steps 703 to 705 of the embodiment of the present application are similar to steps 102 and 104 of the aforementioned embodiment, and can be referred to each other, and will not be repeated here.

[0221] The semiconductor test data transmission method provided in Example 3 of the present application further ensures that the splicing operation is performed only when necessary by judging the number of valid bits of the test response data before splicing. This can improve the logical judgment efficiency of the transmission process, avoid unnecessary splicing operations, save system resources and optimize data path scheduling.

[0222] See also Figure 8 , shows a structural schematic diagram of a semiconductor test data transmission device provided in Example 4 of the present application. For the sake of convenience, only the parts related to the embodiment of the present application are shown.

[0223] The semiconductor test data transmission device 800 includes:

[0224] The receiving module 801 is used to receive test response data from the device under test;

[0225] The splicing module 802 is used to splice the test response data with the remaining test response data retained in the previous clock cycle. If the number of bits of the spliced ​​data is less than the output data bit width, zero padding is performed to obtain intermediate data;

[0226] The cropping module 803 is used to crop the intermediate data to a fixed width according to the preset output data bit width, and obtain the output data for this transmission and the remaining test response data after the update;

[0227] The output module 804 is used to output the output data used for this transmission.

[0228] In the embodiment of the present application, the semiconductor test data transmission device 800 further includes:

[0229] A judging module, configured to judge whether the number of valid bits of the test response data is greater than or equal to a preset output data bit width;

[0230] Correspondingly, the splicing module 802 further includes:

[0231] The valid splicing submodule is used to splice the test response data with the remaining test response data retained in the previous clock cycle when the number of valid bits of the test response data is less than the output data bit width.

[0232] In the embodiment of the present application, the semiconductor test data transmission device 800 further includes:

[0233] an arrangement mode acquisition module, for acquiring an arrangement mode of data transmission, wherein the arrangement mode includes one of a big endian mode and a little endian mode;

[0234] Correspondingly, the splicing module 802 further includes:

[0235] The arrangement and splicing submodule is used to splice the test response data with the remaining test response data retained in the previous clock cycle according to the arrangement method. If the number of bits of the spliced ​​data is less than the output data bit width, zeros are added according to the arrangement method to obtain intermediate data.

[0236] In the embodiment of the present application, the arrangement and splicing submodule includes:

[0237] a big-endian splicing unit, configured to place the remaining test response data in the high order of the spliced ​​data, the test response data in the middle of the spliced ​​data, and the zero-filled data in the low order of the spliced ​​data, when the arrangement mode is the big-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, thereby generating intermediate data;

[0238] The little-endian splicing unit is used to place the zero-padding data in the high position of the spliced ​​data, the test response data in the middle position of the spliced ​​data, and the remaining test response data in the low position of the spliced ​​data when the arrangement mode is little-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, so as to generate intermediate data.

[0239] In the embodiment of the present application, the semiconductor test data transmission device 800 further includes:

[0240] A shift module is used to perform a shift operation on the intermediate data based on the arrangement mode and the relationship between the bit width of the test response data and the bit width of the output data to obtain the target intermediate data;

[0241] Correspondingly, the cropping module 803 includes:

[0242] The target clipping submodule is used to clip the target intermediate data to a fixed width according to the preset output data bit width, and obtain the output data for this transmission and the remaining test response data after update.

[0243] In an embodiment of the present application, the shift module includes:

[0244] a first shift submodule, configured to, when the arrangement mode is big-endian mode, perform a right shift operation on the intermediate data based on a previous cycle margin latch value if the test response data bit width is greater than the output data bit width, where the previous cycle margin latch value is the number of remaining bits of the previous clock cycle latched by the rising edge of the clock in the previous clock cycle;

[0245] a second shift submodule, configured to, when the arrangement mode is big-endian mode, perform a right shift operation on the intermediate data based on a current cycle margin latch value if the test response data bit width is smaller than the output data bit width, where the current cycle margin latch value is the number of remaining bits of the current clock cycle latched by the rising edge of the clock in the current clock cycle;

[0246] A third shift submodule is configured to, when the arrangement mode is little endian mode, perform a left shift operation on the intermediate data based on the previous cycle margin latch value if the test response data bit width is greater than the output data bit width;

[0247] The fourth shift submodule is configured to, when the arrangement is in little endian mode, perform a left shift operation on the intermediate data based on the margin latch value of this cycle if the test response data bit width is smaller than the output data bit width.

[0248] In this embodiment of the present application, the target clipping submodule includes:

[0249] a big-endian cropping unit, configured to extract, when the arrangement mode is big-endian mode, a middle and high-order portion of the target intermediate data as output data and a low-order portion as updated remaining test response data, wherein the bit width of the middle and high-order portion is determined based on the output data bit width and the maximum bit width, and the maximum bit width is the maximum value between the output data bit width and the test response data bit width;

[0250] The little endian clipping unit is used to extract the middle and low-order parts of the target intermediate data as output data and extract the high-order part as the updated remaining test response data when the arrangement mode is little endian mode. The bit width of the middle and low-order parts is determined based on the output data bit width and the test response data bit width.

[0251] In the embodiment of the present application, the semiconductor test data transmission device 800 further includes:

[0252] The margin recorder is used to obtain the margin latch value of this cycle and the margin latch value of the previous cycle.

[0253] In the embodiment of the present application, the semiconductor test data transmission device 800 further includes:

[0254] A first validity judgment module is configured to output a valid signal of high level when the test response data bit width is greater than or equal to the output data bit width and if the previous cycle margin latch value is greater than or equal to the output data bit width, so as to determine that the output data is valid data;

[0255] The second validity judgment module is used to output a valid signal of high level when the test response data bit width is smaller than the output data bit width, if the previous cycle margin latch value plus the test response data bit width is greater than or equal to the output data bit width, to determine that the output data is valid data.

[0256] In the embodiment of the present application, the semiconductor test data transmission device 800 further includes:

[0257] The update latch module is used to shift the updated remaining test response data in a variable direction at the rising edge of the clock cycle after the output data is transmitted, and latch the updated remaining test response data for splicing operation in the next clock cycle.

[0258] The semiconductor test data transmission device 800 provided in the embodiment of the present application can be applied to the semiconductor test data transmission method provided in the aforementioned embodiment. For details, please refer to the description of the semiconductor test data transmission method provided in the aforementioned embodiment, which will not be repeated here.

[0259] Figure 9 Schematic diagram of the structure of the semiconductor testing equipment provided by the embodiment of the present application. Figure 9 As shown, the semiconductor testing device 900 of this embodiment includes: at least one processor 910 ( Figure 9 Only one is shown in the figure) a processor, a memory 920, and a computer program 921 stored in the memory 920 and executable on the at least one processor 910, wherein the processor 910 implements the steps in the above-mentioned semiconductor test data transmission method embodiment when executing the computer program 921.

[0260] The semiconductor testing device 900 may be a server, a physical server, a computing device, etc. The semiconductor testing device may include, but is not limited to, a processor 910 and a memory 920. It will be understood by those skilled in the art that Figure 9 It is only an example of the semiconductor test device 900 and does not constitute a limitation of the semiconductor test device 900. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include a receiving module for receiving test response data; a splicing module for splicing the test response data with the remaining test response data retained in the previous clock cycle, and if the number of bits of the spliced ​​data is less than the output data bit width, padding with zeros to obtain intermediate data; a cropping module for cropping the intermediate data to a fixed width according to a preset output data bit width to obtain the output data for this transmission and the updated remaining test response data; an output module for outputting the output data for this transmission, etc.

[0261] The processor 910 may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or any conventional processor.

[0262] In some embodiments, the memory 920 may be an internal storage unit of the semiconductor test device 900, such as a hard disk or memory of the semiconductor test device 900. In other embodiments, the memory 920 may also be an external storage device of the semiconductor test device 900, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the semiconductor test device 900. Furthermore, the memory 920 may also include both an internal storage unit of the semiconductor test device 900 and an external storage device. The memory 920 is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as the program code of the computer program. The memory 920 may also be used to temporarily store data that has been output or is about to be output.

[0263] In a specific implementation, the processor 910, memory 920, and computer program 921 described in the embodiments of the present application can execute the embodiments of the semiconductor test data transmission method of the present application, which will not be repeated here.

[0264] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0265] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0266] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0267] In the embodiments provided in this application, it should be understood that the disclosed devices / semiconductor testing equipment and methods can be implemented in other ways. For example, the device / semiconductor testing equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0268] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0269] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0270] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the process in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by the processor, it can implement the steps of the above-mentioned various method embodiments. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0271] The present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed through a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the above-mentioned method embodiments when executed.

[0272] The above embodiments are intended only to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application and should be included within the scope of protection of the present application.

Claims

1. A semiconductor test data transmission method, applied to semiconductor test equipment, characterized in that: The data transmission method includes: receiving test response data from the device under test; Splicing the test response data with the remaining test response data retained in the previous clock cycle, and if the number of bits of the spliced ​​data is less than the output data bit width, padding with zeros to obtain intermediate data; According to the preset output data bit width, the intermediate data is clipped to a fixed width to obtain the output data for this transmission and the remaining test response data after the update; The output data used for this transmission is output.

2. The semiconductor test data transmission method according to claim 1, wherein: Before the step of splicing the test response data with the remaining test response data retained in the previous clock cycle, the method further includes: Determining whether the number of valid bits of the test response data is greater than or equal to a preset output data bit width; The step of splicing the test response data with the remaining test response data retained in the previous clock cycle includes: When the number of valid bits of the test response data is smaller than the output data bit width, the test response data is concatenated with remaining test response data retained in the previous clock cycle.

3. The semiconductor test data transmission method according to claim 1, wherein: The data transmission method further includes: Acquire a data transmission arrangement mode, wherein the arrangement mode includes one of a big endian mode and a little endian mode; The test response data is concatenated with the remaining test response data retained in the previous clock cycle, and if the number of bits of the concatenated data is less than the output data bit width, zero padding is performed to obtain intermediate data, including: According to the arrangement, the test response data is spliced ​​with the remaining test response data retained in the previous clock cycle. If the number of bits of the spliced ​​data is less than the output data bit width, zeros are padded according to the arrangement to obtain intermediate data.

4. The semiconductor test data transmission method according to claim 3, wherein: The test response data is spliced ​​with the remaining test response data retained in the previous clock cycle according to the arrangement, and if the number of bits of the spliced ​​data is less than the output data bit width, zero padding is performed according to the arrangement to obtain intermediate data, including: When the arrangement mode is big-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, the remaining test response data is placed in the high position of the spliced ​​data, the test response data is placed in the middle position of the spliced ​​data, and the zero-padding data is placed in the low position of the spliced ​​data to generate the intermediate data; When the arrangement mode is little-endian mode and the number of bits of the spliced ​​data is less than the output data bit width, the zero-padding data is placed in the high position of the spliced ​​data, the test response data is placed in the middle position of the spliced ​​data, and the remaining test response data is placed in the low position of the spliced ​​data to generate the intermediate data.

5. The semiconductor test data transmission method according to claim 3, wherein: The data transmission method further includes: Based on the arrangement and the size relationship between the test response data bit width and the output data bit width, performing a shift operation on the intermediate data to obtain target intermediate data; The step of clipping the intermediate data to a fixed width according to a preset output data bit width to obtain the output data for this transmission and the updated remaining test response data includes: According to the preset output data bit width, the target intermediate data is clipped to a fixed width to obtain the output data for this transmission and the remaining test response data after update.

6. The semiconductor test data transmission method according to claim 5, wherein: The step of performing a shift operation on the intermediate data based on the arrangement mode and the size relationship between the test response data bit width and the output data bit width to obtain target intermediate data includes: When the arrangement mode is big-endian mode, if the test response data bit width is greater than the output data bit width, a right shift operation is performed on the intermediate data based on a previous cycle margin latch value, where the previous cycle margin latch value is the number of remaining bits of the previous clock cycle latched by a rising edge of the clock in the previous clock cycle; When the arrangement mode is big-endian mode, if the test response data bit width is smaller than the output data bit width, a right shift operation is performed on the intermediate data based on a current cycle margin latch value, where the current cycle margin latch value is the number of remaining bits of the current clock cycle latched by a rising edge of the clock in the current clock cycle; When the arrangement mode is a little-endian mode, if the test response data bit width is greater than the output data bit width, performing a left shift operation on the intermediate data based on the previous cycle margin latch value; When the arrangement mode is the little endian mode, if the bit width of the test response data is smaller than the bit width of the output data, a left shift operation is performed on the intermediate data based on the current cycle margin latch value.

7. The semiconductor test data transmission method according to claim 5, wherein: The step of clipping the target intermediate data to a fixed width according to a preset output data bit width to obtain the output data for this transmission and the updated remaining test response data includes: When the arrangement mode is big-endian mode, extracting a middle and high-order portion of the target intermediate data as the output data, and extracting a low-order portion as the updated remaining test response data, wherein the bit width of the middle and high-order portion is determined based on the output data bit width and a maximum bit width, and the maximum bit width is the maximum value between the output data bit width and the test response data bit width; When the arrangement mode is little-endian mode, the middle and low-order parts of the target intermediate data are extracted as the output data, and the high-order part is extracted as the updated remaining test response data, and the bit width of the middle and low-order parts is determined based on the output data bit width and the test response data bit width.

8. The semiconductor test data transmission method according to any one of claims 1 to 7, wherein: After outputting the output data for this transmission, the method further includes: After the output data is transmitted, the updated remaining test response data is shifted in a direction-variable manner at the rising edge of the clock cycle, and the updated remaining test response data is latched for a splicing operation in the next clock cycle.

9. A semiconductor test data transmission device, characterized in that: The semiconductor test data transmission device comprises: A receiving module, configured to receive test response data from a device under test; a splicing module, configured to splice the test response data with the remaining test response data retained in the previous clock cycle, and if the number of bits of the spliced ​​data is less than the output data bit width, padding with zeros to obtain intermediate data; A cropping module is used to crop the intermediate data to a fixed width according to a preset output data bit width, and obtain the output data for this transmission and the remaining test response data after update; The output module is used to output the output data used for this transmission.

10. A semiconductor testing device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

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